[PATCH 0/2] spi: fsl-lpspi: Option to prevent FIFO under/overrun

[PATCH 0/2] spi: fsl-lpspi: Option to prevent FIFO under/overrun

[Hieu Tran Dang]

Certain devices don't work well when a transmit FIFO underrun or
receive FIFO overrun occurs. Example is the SAF400x radio chip when
running at high speed which leads to garbage being sent to/received from
the chip. In which case, it should stall waiting for further data to be
available before proceeding. This patch add option to configure the SPI
controller to allow stalling (unset NOSTALL bit in CFGR1).

Hieu Tran Dang (2):
  dt-bindings: spi: fsl-lpspi: Option to allow stalling
  spi: fsl-lpspi: Option to prevent FIFO under/overrun

 .../devicetree/bindings/spi/spi-fsl-lpspi.txt          |  2 ++
 drivers/spi/spi-fsl-lpspi.c                            | 10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH 1/2] dt-bindings: spi: fsl-lpspi: Option to allow stalling

[Hieu Tran Dang]

This patch add fsl,allow-stalling property documentation for fsl-lpspi

Signed-off-by: Hieu Tran Dang <dangtranhieu2012@gmail.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
index 4af132606b37..2b012b8cb05e 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
@@ -6,6 +6,8 @@ Required properties:
 - reg : address and length of the lpspi master registers
 - interrupts : lpspi interrupt
 - clocks : lpspi clock specifier
+- fsl,allow-stall : allow stalling of transfers when the transmit FIFO is empty
+  or when the receive FIFO is full
 
 Examples:
 
-- 
2.17.1

Re: [PATCH 1/2] dt-bindings: spi: fsl-lpspi: Option to allow stalling

[Rob Herring]

DT bindings should be sent to DT list.

On Tue, Sep 25, 2018 at 3:37 PM Hieu Tran Dang
<dangtranhieu2012@gmail.com> wrote:
>
> This patch add fsl,allow-stalling property documentation for fsl-lpspi
>
> Signed-off-by: Hieu Tran Dang <dangtranhieu2012@gmail.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> index 4af132606b37..2b012b8cb05e 100644
> --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> @@ -6,6 +6,8 @@ Required properties:
>  - reg : address and length of the lpspi master registers
>  - interrupts : lpspi interrupt
>  - clocks : lpspi clock specifier
> +- fsl,allow-stall : allow stalling of transfers when the transmit FIFO is empty
> +  or when the receive FIFO is full

This seems odd. That seems like what normal behavior should be.

Rob

Re: [PATCH 1/2] dt-bindings: spi: fsl-lpspi: Option to allow stalling

[Đặng Trần Hiếu]

>
> DT bindings should be sent to DT list.
>

DT bindings already sent to DT list, included here for completeness
sake. Of course, this is my first patch to the kernel so I might have
completely been wrong about the process. I can create another patch
set to send to correct list if necessary.

> On Tue, Sep 25, 2018 at 3:37 PM Hieu Tran Dang
> <dangtranhieu2012@gmail.com> wrote:
> >
> > This patch add fsl,allow-stalling property documentation for fsl-lpspi
> >
> > Signed-off-by: Hieu Tran Dang <dangtranhieu2012@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> > index 4af132606b37..2b012b8cb05e 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt
> > @@ -6,6 +6,8 @@ Required properties:
> >  - reg : address and length of the lpspi master registers
> >  - interrupts : lpspi interrupt
> >  - clocks : lpspi clock specifier
> > +- fsl,allow-stall : allow stalling of transfers when the transmit FIFO is empty
> > +  or when the receive FIFO is full
>
> This seems odd. That seems like what normal behavior should be.
>
> Rob

Default value of the register is to allow stalling (NOSTALL bit not
set) but the spi-fsl-lpspi driver defaults to setting the NOSTALL bit
in CFGR1. To me, it's more logical to leave the NOSTALL bit off with
fsl,nostall binding to set the bit but as I am not sure if there are
other drivers depending on the NOSTALL bit being set and not wanting
to break other drivers hence introduction of this binding to keep the
current default behavior.

Re: [PATCH 1/2] dt-bindings: spi: fsl-lpspi: Option to allow stalling

[Mark Brown]

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On Wed, Sep 26, 2018 at 09:37:39PM +0700, Đặng Trần Hiếu wrote:

> Default value of the register is to allow stalling (NOSTALL bit not
> set) but the spi-fsl-lpspi driver defaults to setting the NOSTALL bit
> in CFGR1. To me, it's more logical to leave the NOSTALL bit off with
> fsl,nostall binding to set the bit but as I am not sure if there are
> other drivers depending on the NOSTALL bit being set and not wanting
> to break other drivers hence introduction of this binding to keep the
> current default behavior.

I can't see a situation where you'd actively want to report an error
rather than stall, stalling allows us to handle things gracefully by
restarting things.  Even if it's a timeout situation it sounds like we
can unblock by reading/writing the stalled FIFO, and normally you'd be
resetting the entire IP anyway.  I'd imagine the driver is this way
either through an oversight or because there's some bug on some silicon
which means that stalling breaks.

Probably best to just always enable stalling unless I'm misreading
things, if it is silicon bugs on some versions then either a whitelist
or blacklist of SoCs to enable on (depending on how common the bug is)
would be the way forwards - that way SoCs where it works get the benefit.

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Re: [PATCH 1/2] dt-bindings: spi: fsl-lpspi: Option to allow stalling

[Hieu Tran Dang]

Agree. I will create new patch which will just allow stalling by default.

Vào Th 6, 28 thg 9, 2018 vào lúc 05:47 Mark Brown <broonie@kernel.org> đã viết:
>
> On Wed, Sep 26, 2018 at 09:37:39PM +0700, Đặng Trần Hiếu wrote:
>
> > Default value of the register is to allow stalling (NOSTALL bit not
> > set) but the spi-fsl-lpspi driver defaults to setting the NOSTALL bit
> > in CFGR1. To me, it's more logical to leave the NOSTALL bit off with
> > fsl,nostall binding to set the bit but as I am not sure if there are
> > other drivers depending on the NOSTALL bit being set and not wanting
> > to break other drivers hence introduction of this binding to keep the
> > current default behavior.
>
> I can't see a situation where you'd actively want to report an error
> rather than stall, stalling allows us to handle things gracefully by
> restarting things.  Even if it's a timeout situation it sounds like we
> can unblock by reading/writing the stalled FIFO, and normally you'd be
> resetting the entire IP anyway.  I'd imagine the driver is this way
> either through an oversight or because there's some bug on some silicon
> which means that stalling breaks.
>
> Probably best to just always enable stalling unless I'm misreading
> things, if it is silicon bugs on some versions then either a whitelist
> or blacklist of SoCs to enable on (depending on how common the bug is)
> would be the way forwards - that way SoCs where it works get the benefit.

[PATCH 2/2] spi: fsl-lpspi: Option to prevent FIFO under/overrun

[Hieu Tran Dang]

Certain devices don't work well when a transmit FIFO underrun or
receive FIFO overrun occurs. Example is the SAF400x radio chip when
running at high speed which leads to garbage being sent to/received from
the chip. In which case, it should stall waiting for further data to be
available before proceeding. This patch add option to configure the SPI
controller to allow stalling (unset NOSTALL bit in CFGR1).

Signed-off-by: Hieu Tran Dang <dangtranhieu2012@gmail.com>
---
 drivers/spi/spi-fsl-lpspi.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index e6d5cc6ab108..7588b62ef08b 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -73,6 +73,7 @@ struct lpspi_config {
 	u8 prescale;
 	u16 mode;
 	u32 speed_hz;
+	bool nostall;
 };
 
 struct fsl_lpspi_data {
@@ -276,7 +277,11 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
 
 	fsl_lpspi_set_watermark(fsl_lpspi);
 
-	temp = CFGR1_PCSCFG | CFGR1_MASTER | CFGR1_NOSTALL;
+	temp = CFGR1_PCSCFG | CFGR1_MASTER;
+
+	if (fsl_lpspi->config.nostall)
+		temp |= CFGR1_NOSTALL;
+
 	if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 		temp |= CFGR1_PCSPOL;
 	writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
@@ -475,6 +480,9 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
 
 	clk_disable_unprepare(fsl_lpspi->clk);
 
+	fsl_lpspi->config.nostall =
+		!of_get_property(pdev->dev.of_node, "fsl,allow-stall", NULL);
+
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "spi_register_master error.\n");
-- 
2.17.1