* [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask
@ 2018-09-26 19:24 José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL José Roberto de Souza
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx
Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 34 ++++++++++++--------------------
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..358bbcd3b5f3 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -575,28 +575,20 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
else
chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
- } else {
- /*
- * Per Spec: Avoid continuous PSR exit by masking MEMUP
- * and HPD. also mask LPSP to avoid dependency on other
- * drivers that might block runtime_pm besides
- * preventing other hw tracking issues now we can rely
- * on frontbuffer tracking.
- */
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP);
}
+
+ /*
+ * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
+ * mask LPSP to avoid dependency on other drivers that might block
+ * runtime_pm besides preventing other hw tracking issues now we
+ * can rely on frontbuffer tracking.
+ */
+ I915_WRITE(EDP_PSR_DEBUG,
+ EDP_PSR_DEBUG_MASK_MEMUP |
+ EDP_PSR_DEBUG_MASK_HPD |
+ EDP_PSR_DEBUG_MASK_LPSP |
+ EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
+ EDP_PSR_DEBUG_MASK_MAX_SLEEP);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
--
2.19.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch José Roberto de Souza
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx
ICL spec states that this bit is now reserved.
Bspec: 7722
v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++------
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 27e650fe591b..8f436c73f184 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,7 +4195,7 @@ enum {
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
#define EDP_PSR_DEBUG_MASK_HPD (1 << 25)
-#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16)
+#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
#define EDP_PSR2_CTL _MMIO(0x6f900)
@@ -4232,7 +4232,7 @@ enum {
#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
-#define PSR_EVENT_REGISTER_UPDATE (1 << 5)
+#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */
#define PSR_EVENT_HDCP_ENABLE (1 << 4)
#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
#define PSR_EVENT_VBI_ENABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 358bbcd3b5f3..5af22e3522f8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -558,6 +558,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 mask;
/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
* use hardcoded values PSR AUX transactions
@@ -583,12 +584,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
* runtime_pm besides preventing other hw tracking issues now we
* can rely on frontbuffer tracking.
*/
- I915_WRITE(EDP_PSR_DEBUG,
- EDP_PSR_DEBUG_MASK_MEMUP |
- EDP_PSR_DEBUG_MASK_HPD |
- EDP_PSR_DEBUG_MASK_LPSP |
- EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
- EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+ mask = EDP_PSR_DEBUG_MASK_MEMUP |
+ EDP_PSR_DEBUG_MASK_HPD |
+ EDP_PSR_DEBUG_MASK_LPSP |
+ EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+ if (INTEL_GEN(dev_priv) < 11)
+ mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+ I915_WRITE(EDP_PSR_DEBUG, mask);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
--
2.19.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-27 22:38 ` Dhinakaran Pandiyan
2018-09-27 22:44 ` Dhinakaran Pandiyan
2018-09-26 19:24 ` [PATCH v2 4/7] drm/i915/psr: Remove PSR2 TODO error handling José Roberto de Souza
` (5 subsequent siblings)
7 siblings, 2 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
v2(Dhinakaran): Using else of dev_priv->psr.psr2_enabled to set
DP_PSR_CRC_VERIFICATION
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5af22e3522f8..fadcc29e7518 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -340,13 +340,12 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
if (dev_priv->psr.psr2_enabled) {
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
- dpcd_val |= DP_PSR_ENABLE_PSR2;
- }
+ dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
+ } else if (INTEL_GEN(dev_priv) >= 8)
+ dpcd_val |= DP_PSR_CRC_VERIFICATION;
if (dev_priv->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
- if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 4/7] drm/i915/psr: Remove PSR2 TODO error handling
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 5/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2 José Roberto de Souza
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx
We are already handling all PSR2 errors, so we can drop this TODO.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index fadcc29e7518..73f72b5b2307 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1125,8 +1125,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
intel_psr_disable_locked(intel_dp);
/* clear status register */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
-
- /* TODO: handle PSR2 errors */
exit:
mutex_unlock(&psr->lock);
}
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 5/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
` (2 preceding siblings ...)
2018-09-26 19:24 ` [PATCH v2 4/7] drm/i915/psr: Remove PSR2 TODO error handling José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 José Roberto de Souza
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx
This WA also works fine for PSR2, triggering a selective update when
possible.
Acked-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 73f72b5b2307..cf18586459ec 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1021,20 +1021,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
/* By definition flush = invalidate + flush */
if (frontbuffer_bits) {
- if (dev_priv->psr.psr2_enabled) {
- intel_psr_exit(dev_priv);
- } else {
- /*
- * Display WA #0884: all
- * This documented WA for bxt can be safely applied
- * broadly so we can force HW tracking to exit PSR
- * instead of disabling and re-enabling.
- * Workaround tells us to write 0 to CUR_SURFLIVE_A,
- * but it makes more sense write to the current active
- * pipe.
- */
- I915_WRITE(CURSURFLIVE(pipe), 0);
- }
+ /*
+ * Display WA #0884: all
+ * This documented WA for bxt can be safely applied
+ * broadly so we can force HW tracking to exit PSR
+ * instead of disabling and re-enabling.
+ * Workaround tells us to write 0 to CUR_SURFLIVE_A,
+ * but it makes more sense write to the current active
+ * pipe.
+ */
+ I915_WRITE(CURSURFLIVE(pipe), 0);
}
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
` (3 preceding siblings ...)
2018-09-26 19:24 ` [PATCH v2 5/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2 José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-27 22:36 ` Dhinakaran Pandiyan
2018-09-26 19:24 ` [PATCH v2 7/7] drm/i915/psr: Remove alpm from i915_psr José Roberto de Souza
` (2 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
wrong value.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index cf18586459ec..9104cf8700dc 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -341,11 +341,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE);
dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
- } else if (INTEL_GEN(dev_priv) >= 8)
- dpcd_val |= DP_PSR_CRC_VERIFICATION;
+ } else {
+ if (INTEL_GEN(dev_priv) >= 8)
+ dpcd_val |= DP_PSR_CRC_VERIFICATION;
+
+ if (dev_priv->psr.link_standby)
+ dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+ }
- if (dev_priv->psr.link_standby)
- dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
--
2.19.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 7/7] drm/i915/psr: Remove alpm from i915_psr
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
` (4 preceding siblings ...)
2018-09-26 19:24 ` [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 José Roberto de Souza
@ 2018-09-26 19:24 ` José Roberto de Souza
2018-09-26 19:55 ` ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask Patchwork
2018-09-26 20:12 ` ✗ Fi.CI.BAT: failure " Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2018-09-26 19:24 UTC (permalink / raw)
To: intel-gfx
ALPM is a requirement and we don't need to keep it's cached, what
were done in commit 97c9de66ca80
("drm/i915/psr: Fix ALPM cap check for PSR2") but the alpm was not
removed from i915_psr.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8624b4bdc242..9e410e3d0219 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -630,7 +630,6 @@ struct i915_psr {
bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
- bool alpm;
bool psr2_enabled;
u8 sink_sync_latency;
ktime_t last_entry_attempt;
--
2.19.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
` (5 preceding siblings ...)
2018-09-26 19:24 ` [PATCH v2 7/7] drm/i915/psr: Remove alpm from i915_psr José Roberto de Souza
@ 2018-09-26 19:55 ` Patchwork
2018-09-26 20:12 ` ✗ Fi.CI.BAT: failure " Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-09-26 19:55 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL : https://patchwork.freedesktop.org/series/50236/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Share PSR and PSR2 exit mask
Okay!
Commit: drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
Okay!
Commit: drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
Okay!
Commit: drm/i915/psr: Remove PSR2 TODO error handling
Okay!
Commit: drm/i915/psr: Use WA to force HW tracking to exit PSR2
Okay!
Commit: drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
Okay!
Commit: drm/i915/psr: Remove alpm from i915_psr
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3717:16: warning: expression using sizeof(void)
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
` (6 preceding siblings ...)
2018-09-26 19:55 ` ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask Patchwork
@ 2018-09-26 20:12 ` Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-09-26 20:12 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL : https://patchwork.freedesktop.org/series/50236/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4883 -> Patchwork_10287 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10287 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10287, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/50236/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10287:
=== IGT changes ===
==== Possible regressions ====
igt@debugfs_test@read_all_entries:
fi-icl-u: PASS -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_10287 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_module_reload@basic-reload:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@drv_selftest@live_sanitycheck:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#107726)
igt@gem_exec_suspend@basic-s3:
fi-bdw-samus: PASS -> INCOMPLETE (fdo#107773)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-skl-caroline: PASS -> INCOMPLETE (fdo#107556, fdo#104108, fdo#107773)
igt@pm_rpm@basic-pci-d3-state:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106238, fdo#106097)
igt@pm_rpm@module-reload:
fi-glk-j4005: PASS -> DMESG-FAIL (fdo#104767)
==== Possible fixes ====
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS +1
igt@kms_psr@primary_page_flip:
fi-cfl-s3: FAIL (fdo#107336) -> PASS
fi-kbl-r: FAIL (fdo#107336) -> PASS
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104767 https://bugs.freedesktop.org/show_bug.cgi?id=104767
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238
fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107726 https://bugs.freedesktop.org/show_bug.cgi?id=107726
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
== Participating hosts (47 -> 41) ==
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-u2
== Build changes ==
* Linux: CI_DRM_4883 -> Patchwork_10287
CI_DRM_4883: fe61f770c6bb80e924efb5c822440d265df3dc7f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4650: a6e21812d100dce68450727e79fc09e0c0033683 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10287: 02dd623b730e6e24dba0120ba405e6064232a5fe @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
02dd623b730e drm/i915/psr: Remove alpm from i915_psr
a0419239ad01 drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
53f513a3add2 drm/i915/psr: Use WA to force HW tracking to exit PSR2
d29fe4dced8b drm/i915/psr: Remove PSR2 TODO error handling
bff2f5aa2e17 drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
8a64fcdac36d drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
5efee2316607 drm/i915/psr: Share PSR and PSR2 exit mask
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10287/issues.html
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
2018-09-26 19:24 ` [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 José Roberto de Souza
@ 2018-09-27 22:36 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 12+ messages in thread
From: Dhinakaran Pandiyan @ 2018-09-27 22:36 UTC (permalink / raw)
To: intel-gfx
On Wednesday, September 26, 2018 12:24:26 PM PDT José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
> while PSR2 is active, so don't configure sink DPCD with a
> wrong value.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index cf18586459ec..9104cf8700dc 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -341,11 +341,14 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> - } else if (INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
> + } else {
> + if (INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
> +
> + if (dev_priv->psr.link_standby)
Given that this value is exposed in debugfs, I think it makes sense to update
it to the correct state instead of ignoring it. Something along the lines of
+ if (dev_priv->psr.psr2_enabled)
+ dev_priv->psr.link_standby = false;
before psr_enable_sink is called
> + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + }
>
> - if (dev_priv->psr.link_standby)
> - dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
2018-09-26 19:24 ` [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch José Roberto de Souza
@ 2018-09-27 22:38 ` Dhinakaran Pandiyan
2018-09-27 22:44 ` Dhinakaran Pandiyan
1 sibling, 0 replies; 12+ messages in thread
From: Dhinakaran Pandiyan @ 2018-09-27 22:38 UTC (permalink / raw)
To: intel-gfx
On Wednesday, September 26, 2018 12:24:23 PM PDT José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
I'd be more comfortable with this patch if you confirm that that we aren't
hitting the intel_dp_needs_link_train() condition in intel_dp_short_pulse()
-DK
>
> v2(Dhinakaran): Using else of dev_priv->psr.psr2_enabled to set
> DP_PSR_CRC_VERIFICATION
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 5af22e3522f8..fadcc29e7518 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -340,13 +340,12 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp) if (dev_priv->psr.psr2_enabled) {
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> - dpcd_val |= DP_PSR_ENABLE_PSR2;
> - }
> + dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> + } else if (INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
>
> if (dev_priv->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch
2018-09-26 19:24 ` [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch José Roberto de Souza
2018-09-27 22:38 ` Dhinakaran Pandiyan
@ 2018-09-27 22:44 ` Dhinakaran Pandiyan
1 sibling, 0 replies; 12+ messages in thread
From: Dhinakaran Pandiyan @ 2018-09-27 22:44 UTC (permalink / raw)
To: intel-gfx
On Wednesday, September 26, 2018 12:24:23 PM PDT José Roberto de Souza wrote:
> eDP spec states 2 different bits to enable sink to trigger a
> interruption when there is a CRC mismatch.
> DP_PSR_CRC_VERIFICATION is for PSR only and
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
>
> v2(Dhinakaran): Using else of dev_priv->psr.psr2_enabled to set
> DP_PSR_CRC_VERIFICATION
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 5af22e3522f8..fadcc29e7518 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -340,13 +340,12 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp) if (dev_priv->psr.psr2_enabled) {
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE);
> - dpcd_val |= DP_PSR_ENABLE_PSR2;
> - }
> + dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> + } else if (INTEL_GEN(dev_priv) >= 8)
nit: kernel coding style expects braces here
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
>
> if (dev_priv->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> - dpcd_val |= DP_PSR_CRC_VERIFICATION;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-09-27 22:45 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-26 19:24 [PATCH v2 1/7] drm/i915/psr: Share PSR and PSR2 exit mask José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 3/7] drm/i915/psr: Enable sink to trigger a interruption on PSR2 CRC mismatch José Roberto de Souza
2018-09-27 22:38 ` Dhinakaran Pandiyan
2018-09-27 22:44 ` Dhinakaran Pandiyan
2018-09-26 19:24 ` [PATCH v2 4/7] drm/i915/psr: Remove PSR2 TODO error handling José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 5/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2 José Roberto de Souza
2018-09-26 19:24 ` [PATCH v2 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 José Roberto de Souza
2018-09-27 22:36 ` Dhinakaran Pandiyan
2018-09-26 19:24 ` [PATCH v2 7/7] drm/i915/psr: Remove alpm from i915_psr José Roberto de Souza
2018-09-26 19:55 ` ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/7] drm/i915/psr: Share PSR and PSR2 exit mask Patchwork
2018-09-26 20:12 ` ✗ Fi.CI.BAT: failure " Patchwork
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