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* [PATCH V2] clk: tegra: Fixes for MBIST work around
@ 2018-09-27  2:32 ` Joseph Lo
  0 siblings, 0 replies; 4+ messages in thread
From: Joseph Lo @ 2018-09-27  2:32 UTC (permalink / raw)
  To: Thierry Reding, Jon Hunter
  Cc: linux-tegra, linux-clk, Joseph Lo, Peter De Schrijver

Fix some incorrect data in LVL2 offset and bit mask.

Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210")
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
V2:
Add "Fixes" tag.
---
 drivers/clk/tegra/clk-tegra210.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra=
210.c
index 9eb1cb14fce1..290f7cb6a051 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2603,7 +2603,7 @@ static struct tegra210_domain_mbist_war tegra210_pg_m=
bist_war[] =3D {
 	[TEGRA_POWERGATE_MPE] =3D {
 		.handle_lvl2_ovr =3D tegra210_generic_mbist_war,
 		.lvl2_offset =3D LVL2_CLK_GATE_OVRE,
-		.lvl2_mask =3D BIT(2),
+		.lvl2_mask =3D BIT(29),
 	},
 	[TEGRA_POWERGATE_SOR] =3D {
 		.handle_lvl2_ovr =3D tegra210_generic_mbist_war,
@@ -2654,14 +2654,14 @@ static struct tegra210_domain_mbist_war tegra210_pg=
_mbist_war[] =3D {
 		.num_clks =3D ARRAY_SIZE(nvdec_slcg_clkids),
 		.clk_init_data =3D nvdec_slcg_clkids,
 		.handle_lvl2_ovr =3D tegra210_generic_mbist_war,
-		.lvl2_offset =3D LVL2_CLK_GATE_OVRC,
+		.lvl2_offset =3D LVL2_CLK_GATE_OVRE,
 		.lvl2_mask =3D BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_NVJPG] =3D {
 		.num_clks =3D ARRAY_SIZE(nvjpg_slcg_clkids),
 		.clk_init_data =3D nvjpg_slcg_clkids,
 		.handle_lvl2_ovr =3D tegra210_generic_mbist_war,
-		.lvl2_offset =3D LVL2_CLK_GATE_OVRC,
+		.lvl2_offset =3D LVL2_CLK_GATE_OVRE,
 		.lvl2_mask =3D BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_AUD] =3D {
--=20
2.19.0

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH V2] clk: tegra: Fixes for MBIST work around
@ 2018-09-27  2:32 ` Joseph Lo
  0 siblings, 0 replies; 4+ messages in thread
From: Joseph Lo @ 2018-09-27  2:32 UTC (permalink / raw)
  To: Thierry Reding, Jon Hunter
  Cc: linux-tegra, linux-clk, Joseph Lo, Peter De Schrijver

Fix some incorrect data in LVL2 offset and bit mask.

Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210")
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
V2:
Add "Fixes" tag.
---
 drivers/clk/tegra/clk-tegra210.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9eb1cb14fce1..290f7cb6a051 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2603,7 +2603,7 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
 	[TEGRA_POWERGATE_MPE] = {
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
 		.lvl2_offset = LVL2_CLK_GATE_OVRE,
-		.lvl2_mask = BIT(2),
+		.lvl2_mask = BIT(29),
 	},
 	[TEGRA_POWERGATE_SOR] = {
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
@@ -2654,14 +2654,14 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
 		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
 		.clk_init_data = nvdec_slcg_clkids,
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
-		.lvl2_offset = LVL2_CLK_GATE_OVRC,
+		.lvl2_offset = LVL2_CLK_GATE_OVRE,
 		.lvl2_mask = BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_NVJPG] = {
 		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
 		.clk_init_data = nvjpg_slcg_clkids,
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
-		.lvl2_offset = LVL2_CLK_GATE_OVRC,
+		.lvl2_offset = LVL2_CLK_GATE_OVRE,
 		.lvl2_mask = BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_AUD] = {
-- 
2.19.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH V2] clk: tegra: Fixes for MBIST work around
  2018-09-27  2:32 ` Joseph Lo
  (?)
@ 2018-09-27  8:22 ` Peter De Schrijver
  -1 siblings, 0 replies; 4+ messages in thread
From: Peter De Schrijver @ 2018-09-27  8:22 UTC (permalink / raw)
  To: Joseph Lo; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-clk

On Thu, Sep 27, 2018 at 10:32:03AM +0800, Joseph Lo wrote:
> Fix some incorrect data in LVL2 offset and bit mask.
> 
> Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210")
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>

> ---
> V2:
> Add "Fixes" tag.
> ---
>  drivers/clk/tegra/clk-tegra210.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 9eb1cb14fce1..290f7cb6a051 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2603,7 +2603,7 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
>  	[TEGRA_POWERGATE_MPE] = {
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
>  		.lvl2_offset = LVL2_CLK_GATE_OVRE,
> -		.lvl2_mask = BIT(2),
> +		.lvl2_mask = BIT(29),
>  	},
>  	[TEGRA_POWERGATE_SOR] = {
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> @@ -2654,14 +2654,14 @@ static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
>  		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
>  		.clk_init_data = nvdec_slcg_clkids,
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> -		.lvl2_offset = LVL2_CLK_GATE_OVRC,
> +		.lvl2_offset = LVL2_CLK_GATE_OVRE,
>  		.lvl2_mask = BIT(9) | BIT(31),
>  	},
>  	[TEGRA_POWERGATE_NVJPG] = {
>  		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
>  		.clk_init_data = nvjpg_slcg_clkids,
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> -		.lvl2_offset = LVL2_CLK_GATE_OVRC,
> +		.lvl2_offset = LVL2_CLK_GATE_OVRE,
>  		.lvl2_mask = BIT(9) | BIT(31),
>  	},
>  	[TEGRA_POWERGATE_AUD] = {
> -- 
> 2.19.0
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH V2] clk: tegra: Fixes for MBIST work around
  2018-09-27  2:32 ` Joseph Lo
  (?)
  (?)
@ 2018-10-16 22:30 ` Stephen Boyd
  -1 siblings, 0 replies; 4+ messages in thread
From: Stephen Boyd @ 2018-10-16 22:30 UTC (permalink / raw)
  To: Jon Hunter, Joseph Lo, Thierry Reding
  Cc: linux-tegra, linux-clk, Joseph Lo, Peter De Schrijver

Quoting Joseph Lo (2018-09-26 19:32:03)
> Fix some incorrect data in LVL2 offset and bit mask.
> 
> Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210")
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-16 22:30 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2018-09-27  2:32 [PATCH V2] clk: tegra: Fixes for MBIST work around Joseph Lo
2018-09-27  2:32 ` Joseph Lo
2018-09-27  8:22 ` Peter De Schrijver
2018-10-16 22:30 ` Stephen Boyd

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