[PATCH v4 1/7] drm/i915/psr: Share PSR and PSR2 exit mask

[PATCH v4 1/7] drm/i915/psr: Share PSR and PSR2 exit mask

[José Roberto de Souza]

Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 34 ++++++++++++--------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 83528647b40b..102da7aae9d8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -580,28 +580,20 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		else
 			chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
-		I915_WRITE(EDP_PSR_DEBUG,
-			   EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD |
-			   EDP_PSR_DEBUG_MASK_LPSP |
-			   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
-			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
-	} else {
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP
-		 * and HPD. also mask LPSP to avoid dependency on other
-		 * drivers that might block runtime_pm besides
-		 * preventing  other hw tracking issues now we can rely
-		 * on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG,
-			   EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD |
-			   EDP_PSR_DEBUG_MASK_LPSP |
-			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-			   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
 	}
+
+	/*
+	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
+	 * mask LPSP to avoid dependency on other drivers that might block
+	 * runtime_pm besides preventing  other hw tracking issues now we
+	 * can rely on frontbuffer tracking.
+	 */
+	I915_WRITE(EDP_PSR_DEBUG,
+		   EDP_PSR_DEBUG_MASK_MEMUP |
+		   EDP_PSR_DEBUG_MASK_HPD |
+		   EDP_PSR_DEBUG_MASK_LPSP |
+		   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
+		   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-- 
2.19.0

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[PATCH v4 2/7] drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL

[José Roberto de Souza]

ICL spec states that this bit is now reserved.

Bspec: 7722

v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++--
 drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++------
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507cfb9b..aff6f6754d79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,7 +4195,7 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
-#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
@@ -4232,7 +4232,7 @@ enum {
 #define  PSR_EVENT_FRONT_BUFFER_MODIFY		(1 << 9)
 #define  PSR_EVENT_WD_TIMER_EXPIRE		(1 << 8)
 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE	(1 << 6)
-#define  PSR_EVENT_REGISTER_UPDATE		(1 << 5)
+#define  PSR_EVENT_REGISTER_UPDATE		(1 << 5) /* Reserved in ICL+ */
 #define  PSR_EVENT_HDCP_ENABLE			(1 << 4)
 #define  PSR_EVENT_KVMR_SESSION_ENABLE		(1 << 3)
 #define  PSR_EVENT_VBI_ENABLE			(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 102da7aae9d8..5006b30b848d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -563,6 +563,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 mask;
 
 	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 	 * use hardcoded values PSR AUX transactions
@@ -588,12 +589,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	 * runtime_pm besides preventing  other hw tracking issues now we
 	 * can rely on frontbuffer tracking.
 	 */
-	I915_WRITE(EDP_PSR_DEBUG,
-		   EDP_PSR_DEBUG_MASK_MEMUP |
-		   EDP_PSR_DEBUG_MASK_HPD |
-		   EDP_PSR_DEBUG_MASK_LPSP |
-		   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-		   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+	mask = EDP_PSR_DEBUG_MASK_MEMUP |
+	       EDP_PSR_DEBUG_MASK_HPD |
+	       EDP_PSR_DEBUG_MASK_LPSP |
+	       EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+	if (INTEL_GEN(dev_priv) < 11)
+		mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+	I915_WRITE(EDP_PSR_DEBUG, mask);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
-- 
2.19.0

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[PATCH v4 3/7] drm/i915/psr: Remove PSR2 TODO error handling

[José Roberto de Souza]

We are already handling all PSR2 errors, so we can drop this TODO.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5006b30b848d..1c4beaca1c0f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1128,8 +1128,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 		intel_psr_disable_locked(intel_dp);
 	/* clear status register */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
-
-	/* TODO: handle PSR2 errors */
 exit:
 	mutex_unlock(&psr->lock);
 }
-- 
2.19.0

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[PATCH v4 4/7] drm/i915/psr: Use WA to force HW tracking to exit PSR2

[José Roberto de Souza]

This WA also works fine for PSR2, triggering a selective update when
possible.

Acked-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 1c4beaca1c0f..423cdf84059c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1027,20 +1027,16 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 
 	/* By definition flush = invalidate + flush */
 	if (frontbuffer_bits) {
-		if (dev_priv->psr.psr2_enabled) {
-			intel_psr_exit(dev_priv);
-		} else {
-			/*
-			 * Display WA #0884: all
-			 * This documented WA for bxt can be safely applied
-			 * broadly so we can force HW tracking to exit PSR
-			 * instead of disabling and re-enabling.
-			 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
-			 * but it makes more sense write to the current active
-			 * pipe.
-			 */
-			I915_WRITE(CURSURFLIVE(pipe), 0);
-		}
+		/*
+		 * Display WA #0884: all
+		 * This documented WA for bxt can be safely applied
+		 * broadly so we can force HW tracking to exit PSR
+		 * instead of disabling and re-enabling.
+		 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
+		 * but it makes more sense write to the current active
+		 * pipe.
+		 */
+		I915_WRITE(CURSURFLIVE(pipe), 0);
 	}
 
 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
-- 
2.19.0

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[PATCH v4 5/7] drm/i915/psr: Remove main link standby mode from debugfs

[José Roberto de Souza]

Main link stand by is only valid for PSR1 as it is not possible to
enable PSR2 and keep main link on but even for PSR1 it is not useful
information and it can be removed without any drawbacks.
But if someone still wants to check that this patch is providing the
full PSR_CTL register value so user can check if bit 27 is set, this
will also expose more information about how PSR1 and PSR2 was
configured in source.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Suggested-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f42e93b71e67..48e65becd035 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2712,8 +2712,8 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	u32 psrperf = 0;
-	bool enabled = false;
+	u32 val;
+	bool enabled;
 	bool sink_support;
 
 	if (!HAS_PSR(dev_priv))
@@ -2733,24 +2733,23 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
 		   dev_priv->psr.busy_frontbuffer_bits);
 
-	if (dev_priv->psr.psr2_enabled)
-		enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
-	else
-		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
-
-	seq_printf(m, "Main link in standby mode: %s\n",
-		   yesno(dev_priv->psr.link_standby));
+	if (dev_priv->psr.psr2_enabled) {
+		val = I915_READ(EDP_PSR2_CTL);
+		enabled = val & EDP_PSR2_ENABLE;
+	} else {
+		val = I915_READ(EDP_PSR_CTL);
+		enabled = val & EDP_PSR_ENABLE;
+	}
 
-	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
+	seq_printf(m, "HW enabled: %s [0x%x]\n", yesno(enabled), val);
 
 	/*
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
 	 */
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
-			EDP_PSR_PERF_CNT_MASK;
+		val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK;
 
-		seq_printf(m, "Performance_Counter: %u\n", psrperf);
+		seq_printf(m, "Performance_Counter: %u\n", val);
 	}
 
 	psr_source_status(dev_priv, m);
-- 
2.19.0

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[PATCH v4 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

[José Roberto de Souza]

For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
wrong value.

v4: rebased on top of the patch removing link standby from debugfs

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 423cdf84059c..26317a4e03d2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -346,12 +346,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE);
 		dpcd_val |= DP_PSR_ENABLE_PSR2;
+	} else {
+		if (dev_priv->psr.link_standby)
+			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+
+		if (INTEL_GEN(dev_priv) >= 8)
+			dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	}
 
-	if (dev_priv->psr.link_standby)
-		dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
-	if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
-		dpcd_val |= DP_PSR_CRC_VERIFICATION;
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
-- 
2.19.0

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[PATCH v4 7/7] drm/i915/psr: Remove alpm from i915_psr

[José Roberto de Souza]

ALPM is a requirement and we don't need to keep it's cached, what
were done in commit 97c9de66ca80
("drm/i915/psr: Fix ALPM cap check for PSR2") but the alpm was not
removed from i915_psr.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2264b30ce51a..7ddbb7f460c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -634,7 +634,6 @@ struct i915_psr {
 	bool sink_psr2_support;
 	bool link_standby;
 	bool colorimetry_support;
-	bool alpm;
 	bool psr2_enabled;
 	u8 sink_sync_latency;
 	ktime_t last_entry_attempt;
-- 
2.19.0

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✗ Fi.CI.SPARSE: warning for series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL   : https://patchwork.freedesktop.org/series/50526/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Share PSR and PSR2 exit mask
Okay!

Commit: drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
Okay!

Commit: drm/i915/psr: Remove PSR2 TODO error handling
Okay!

Commit: drm/i915/psr: Use WA to force HW tracking to exit PSR2
Okay!

Commit: drm/i915/psr: Remove main link standby mode from debugfs
Okay!

Commit: drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
Okay!

Commit: drm/i915/psr: Remove alpm from i915_psr
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3726:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void)

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Re: [PATCH v4 5/7] drm/i915/psr: Remove main link standby mode from debugfs

[Dhinakaran Pandiyan]

On Wednesday, October 3, 2018 1:50:29 PM PDT José Roberto de Souza wrote:
> Main link stand by is only valid for PSR1 as it is not possible to
> enable PSR2 and keep main link on but even for PSR1 it is not useful
> information and it can be removed without any drawbacks.
> But if someone still wants to check that this patch is providing the
> full PSR_CTL register value so user can check if bit 27 is set, this
> will also expose more information about how PSR1 and PSR2 was
> configured in source.
Yes, knowing the full configuration (idle frames, training pattern )  is very 
useful for debug. 

> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Suggested-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 25 ++++++++++++-------------
>  1 file changed, 12 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c index f42e93b71e67..48e65becd035
> 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2712,8 +2712,8 @@ psr_source_status(struct drm_i915_private *dev_priv,
> struct seq_file *m) static int i915_edp_psr_status(struct seq_file *m, void
> *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	u32 psrperf = 0;
> -	bool enabled = false;
> +	u32 val;
> +	bool enabled;
>  	bool sink_support;
> 
>  	if (!HAS_PSR(dev_priv))
> @@ -2733,24 +2733,23 @@ static int i915_edp_psr_status(struct seq_file *m,
> void *data) seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
>  		   dev_priv->psr.busy_frontbuffer_bits);
> 
> -	if (dev_priv->psr.psr2_enabled)
> -		enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
> -	else
> -		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> -
> -	seq_printf(m, "Main link in standby mode: %s\n",
> -		   yesno(dev_priv->psr.link_standby));
> +	if (dev_priv->psr.psr2_enabled) {
> +		val = I915_READ(EDP_PSR2_CTL);
> +		enabled = val & EDP_PSR2_ENABLE;
> +	} else {
> +		val = I915_READ(EDP_PSR_CTL);
> +		enabled = val & EDP_PSR_ENABLE;
> +	}
> 
> -	seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
> +	seq_printf(m, "HW enabled: %s [0x%x]\n", yesno(enabled), val);

The status register is printed as <hex reg value>[<mapped string>].  Can we 
please keep this interface consistent? Also, this change will need changes in 
IGTs.

With the print format changed
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> 
>  	/*
>  	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
>  	 */
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
> -			EDP_PSR_PERF_CNT_MASK;
> +		val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK;
> 
> -		seq_printf(m, "Performance_Counter: %u\n", psrperf);
> +		seq_printf(m, "Performance_Counter: %u\n", val);
>  	}
> 
>  	psr_source_status(dev_priv, m);




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Re: [PATCH v4 6/7] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

[Dhinakaran Pandiyan]

On Wednesday, October 3, 2018 1:50:30 PM PDT José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
> while PSR2 is active, so don't configure sink DPCD with a
> wrong value.
> 
> v4: rebased on top of the patch removing link standby from debugfs

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index 423cdf84059c..26317a4e03d2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -346,12 +346,14 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
>  				   DP_ALPM_ENABLE);
>  		dpcd_val |= DP_PSR_ENABLE_PSR2;
> +	} else {
> +		if (dev_priv->psr.link_standby)
> +			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> +
> +		if (INTEL_GEN(dev_priv) >= 8)
> +			dpcd_val |= DP_PSR_CRC_VERIFICATION;
>  	}
> 
> -	if (dev_priv->psr.link_standby)
> -		dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> -	if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> -		dpcd_val |= DP_PSR_CRC_VERIFICATION;
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> 
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);




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✓ Fi.CI.BAT: success for series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL   : https://patchwork.freedesktop.org/series/50526/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4925 -> Patchwork_10351 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50526/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10351 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ctx_switch@basic-default-heavy:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#105719)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191)

    igt@kms_psr@cursor_plane_move:
      fi-kbl-r:           PASS -> FAIL (fdo#107383) +3
      fi-whl-u:           PASS -> FAIL (fdo#107383) +3

    igt@kms_psr@primary_mmap_gtt:
      fi-kbl-7560u:       NOTRUN -> FAIL (fdo#107383) +3
      fi-cnl-u:           PASS -> FAIL (fdo#107383) +3

    igt@kms_psr@primary_page_flip:
      fi-skl-6600u:       PASS -> FAIL (fdo#107383) +3

    
    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-modeset:
      fi-glk-j4005:       DMESG-WARN (fdo#106000) -> PASS

    igt@kms_flip@basic-plain-flip:
      fi-glk-j4005:       DMESG-WARN (fdo#106097) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (48 -> 38) ==

  Additional (1): fi-kbl-7560u 
  Missing    (11): fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-skl-guc fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-cfl-s3 fi-icl-u fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4925 -> Patchwork_10351

  CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10351: 514e604a2b9a7a2422d760c87651585b6896a1c5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

514e604a2b9a drm/i915/psr: Remove alpm from i915_psr
665311b03a29 drm/i915/psr: Don't tell sink that main link will be active while is active PSR2
1537843c8c69 drm/i915/psr: Remove main link standby mode from debugfs
bfceeb76d06e drm/i915/psr: Use WA to force HW tracking to exit PSR2
5fa7ea20efba drm/i915/psr: Remove PSR2 TODO error handling
357c03ffd698 drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL
f91c986fb9b7 drm/i915/psr: Share PSR and PSR2 exit mask

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10351/issues.html
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✓ Fi.CI.IGT: success for series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/7] drm/i915/psr: Share PSR and PSR2 exit mask
URL   : https://patchwork.freedesktop.org/series/50526/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4925_full -> Patchwork_10351_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10351_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-apl:          PASS -> INCOMPLETE (fdo#106886, fdo#103927)

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-skl:          NOTRUN -> TIMEOUT (fdo#108039, fdo#108130)

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-skl:          NOTRUN -> FAIL (fdo#106641)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_crc@cursor-128x42-sliding:
      shard-apl:          PASS -> FAIL (fdo#103232) +2

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#103191)

    igt@kms_fbcon_fbt@psr-suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#103833)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          PASS -> FAIL (fdo#105682, fdo#103167)

    igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
      shard-skl:          PASS -> FAIL (fdo#107719) +43

    igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
      shard-skl:          NOTRUN -> FAIL (fdo#105682, fdo#107719)

    igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
      shard-skl:          SKIP -> FAIL (fdo#107719)

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
      shard-skl:          NOTRUN -> FAIL (fdo#107719) +19

    {igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +1

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-apl:          PASS -> FAIL (fdo#103166) +1

    igt@kms_psr@cursor_mmap_cpu:
      shard-skl:          PASS -> FAIL (fdo#107383) +4

    igt@kms_psr@sprite_blt:
      shard-skl:          NOTRUN -> FAIL (fdo#107383) +3

    igt@kms_setmode@basic:
      shard-snb:          NOTRUN -> FAIL (fdo#99912)

    igt@kms_sysfs_edid_timing:
      shard-skl:          NOTRUN -> FAIL (fdo#100047)

    
    ==== Possible fixes ====

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS
      shard-kbl:          FAIL (fdo#99912) -> PASS

    igt@kms_universal_plane@universal-plane-pipe-a-functional:
      shard-apl:          FAIL (fdo#103166) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103833 https://bugs.freedesktop.org/show_bug.cgi?id=103833
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
  fdo#107719 https://bugs.freedesktop.org/show_bug.cgi?id=107719
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
  fdo#108130 https://bugs.freedesktop.org/show_bug.cgi?id=108130
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing    (2): shard-glk shard-hsw 


== Build changes ==

    * Linux: CI_DRM_4925 -> Patchwork_10351

  CI_DRM_4925: b652f33e63e1aafb7fc1cb2a9648a14d66f0d35f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4665: 267870165d9ef66b4ab423e4efe7bacba023d75e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10351: 514e604a2b9a7a2422d760c87651585b6896a1c5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10351/shards.html
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