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From: Gabriel Paubert <paubert@iram.es>
To: Raz <raziebe@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: Looking for architecture papers
Date: Thu, 4 Oct 2018 12:16:40 +0200	[thread overview]
Message-ID: <20181004101640.t3o7v73fcipsjg3k@lt-gp.iram.es> (raw)
In-Reply-To: <CAPB=Z-pLCkXcsAXD5YWt5pwPzFzJrdZsdDye_bZjE0-ea-Ur6A@mail.gmail.com>

On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> Frankly, the more I read the more perplexed I get. For example,
> according to BOOK III-S, chapter 3,
> the MSR bits are differ from the ones described in
> arch/powerpc/include/asm/reg.h.
> Bit zero, is LE, but in the book it is 64-bit mode.

Just a problem of bit order definitions: IBM hardware definitions use
big-endian bit ordering, where bit 0 is the most significant bit.

> 
> Would someone be kind to explain what I do not understand?
> 
> Thank you

	Gabriel

  parent reply	other threads:[~2018-10-04 10:31 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-29 21:24 Looking for architecture papers Raz
2018-09-29 22:13 ` Segher Boessenkool
2018-09-30  7:05   ` Raz
2018-09-30  8:56     ` Segher Boessenkool
2018-10-03  4:07 ` Michael Ellerman
2018-10-04  7:41   ` Raz
2018-10-04  8:46     ` Segher Boessenkool
2018-10-04 10:16     ` Gabriel Paubert [this message]
2018-10-06  9:19       ` Raz
2018-10-06 12:27         ` Segher Boessenkool
2018-10-08 16:44           ` Raz
2018-10-08 19:29             ` Segher Boessenkool
2018-10-08 19:59     ` Gustavo Romero
2018-10-13  0:27       ` Raz

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