From: Raz <raziebe@gmail.com>
To: paubert@iram.es
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: Looking for architecture papers
Date: Sat, 6 Oct 2018 12:19:45 +0300 [thread overview]
Message-ID: <CAPB=Z-pW6FWEp=0PgphCo-mAh9pPgt0frjz_MkPp6YHuhX3-pQ@mail.gmail.com> (raw)
In-Reply-To: <20181004101640.t3o7v73fcipsjg3k@lt-gp.iram.es>
Hey
How does HVSC works ?
I looked in the code and LoPAR documentation. It looks like there is
vector called
system_call_pSeries ( at 0xc00 ) that is supposed to be called when we
invoke HVSC from kernel
mode.
Now, I wrote a NULL call HSVC and patched the exceptions-64s.S to
return RFID immediately.
This does not work.
Would you be so kind to explain how HVSC works ?
thank you
On Thu, Oct 4, 2018 at 1:16 PM Gabriel Paubert <paubert@iram.es> wrote:
>
> On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> > Frankly, the more I read the more perplexed I get. For example,
> > according to BOOK III-S, chapter 3,
> > the MSR bits are differ from the ones described in
> > arch/powerpc/include/asm/reg.h.
> > Bit zero, is LE, but in the book it is 64-bit mode.
>
> Just a problem of bit order definitions: IBM hardware definitions use
> big-endian bit ordering, where bit 0 is the most significant bit.
>
> >
> > Would someone be kind to explain what I do not understand?
> >
> > Thank you
>
> Gabriel
next prev parent reply other threads:[~2018-10-06 9:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-29 21:24 Looking for architecture papers Raz
2018-09-29 22:13 ` Segher Boessenkool
2018-09-30 7:05 ` Raz
2018-09-30 8:56 ` Segher Boessenkool
2018-10-03 4:07 ` Michael Ellerman
2018-10-04 7:41 ` Raz
2018-10-04 8:46 ` Segher Boessenkool
2018-10-04 10:16 ` Gabriel Paubert
2018-10-06 9:19 ` Raz [this message]
2018-10-06 12:27 ` Segher Boessenkool
2018-10-08 16:44 ` Raz
2018-10-08 19:29 ` Segher Boessenkool
2018-10-08 19:59 ` Gustavo Romero
2018-10-13 0:27 ` Raz
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