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diff for duplicates of <20181005085505.29024-2-pankaj.bansal@nxp.com>

diff --git a/a/1.txt b/N1/1.txt
index a6a05c9..45f7805 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,9 +1,9 @@
-an FPGA-based system controller, called “Qixis”, which
+an FPGA-based system controller, called ?Qixis?, which
 manages several critical system features, including:
-• Reset sequencing
-• Power supply configuration
-• Board configuration
-• hardware configuration
+? Reset sequencing
+? Power supply configuration
+? Board configuration
+? hardware configuration
 
 The qixis registers are accessible over one or more system-specific
 interfaces, typically I2C, JTAG or an embedded processor.
@@ -21,19 +21,19 @@ index 000000000000..bc2950cab71d
 @@ -0,0 +1,33 @@
 +* QIXIS FPGA block
 +
-+an FPGA-based system controller, called “Qixis”, which
++an FPGA-based system controller, called ?Qixis?, which
 +manages several critical system features, including:
-+• Configuration switch monitoring
-+• Power on/off sequencing
-+• Reset sequencing
-+• Power supply configuration
-+• Board configuration
-+• hardware configuration
-+• Background power data collection (DCM)
-+• Fault monitoring
-+• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
-+• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
-+• I2C master for remote board control even with no DUT available
++? Configuration switch monitoring
++? Power on/off sequencing
++? Reset sequencing
++? Power supply configuration
++? Board configuration
++? hardware configuration
++? Background power data collection (DCM)
++? Fault monitoring
++? RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
++? Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
++? I2C master for remote board control even with no DUT available
 +
 +The qixis registers are accessible over one or more system-specific interfaces,
 +typically I2C, JTAG or an embedded processor.
@@ -45,7 +45,7 @@ index 000000000000..bc2950cab71d
 +
 +Examples:
 +	/* The FPGA node */
-+        fpga@66 {
++        fpga at 66 {
 +		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
 +		reg = <0x66>;
 +		#address-cells = <1>;
diff --git a/a/content_digest b/N1/content_digest
index 5a80b25..a24c74d 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
   "ref\00020181005085505.29024-1-pankaj.bansal\@nxp.com\0"
 ]
 [
-  "From\0Pankaj Bansal <pankaj.bansal\@nxp.com>\0"
+  "From\0pankaj.bansal\@nxp.com (Pankaj Bansal)\0"
 ]
 [
   "Subject\0[PATCH 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage\0"
@@ -11,13 +11,7 @@
   "Date\0Fri,  5 Oct 2018 14:25:04 +0530\0"
 ]
 [
-  "To\0Leo Li <leoyang.li\@nxp.com>\0"
-]
-[
-  "Cc\0Alexandru Marginean <alexandru.marginean\@nxp.com>",
-  " Pankaj Bansal <pankaj.bansal\@nxp.com>",
-  " linuxppc-dev\@lists.ozlabs.org",
-  " linux-arm-kernel\@lists.infradead.org\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -26,12 +20,12 @@
   "b\0"
 ]
 [
-  "an FPGA-based system controller, called \342\200\234Qixis\342\200\235, which\n",
+  "an FPGA-based system controller, called ?Qixis?, which\n",
   "manages several critical system features, including:\n",
-  "\342\200\242 Reset sequencing\n",
-  "\342\200\242 Power supply configuration\n",
-  "\342\200\242 Board configuration\n",
-  "\342\200\242 hardware configuration\n",
+  "? Reset sequencing\n",
+  "? Power supply configuration\n",
+  "? Board configuration\n",
+  "? hardware configuration\n",
   "\n",
   "The qixis registers are accessible over one or more system-specific\n",
   "interfaces, typically I2C, JTAG or an embedded processor.\n",
@@ -49,19 +43,19 @@
   "\@\@ -0,0 +1,33 \@\@\n",
   "+* QIXIS FPGA block\n",
   "+\n",
-  "+an FPGA-based system controller, called \342\200\234Qixis\342\200\235, which\n",
+  "+an FPGA-based system controller, called ?Qixis?, which\n",
   "+manages several critical system features, including:\n",
-  "+\342\200\242 Configuration switch monitoring\n",
-  "+\342\200\242 Power on/off sequencing\n",
-  "+\342\200\242 Reset sequencing\n",
-  "+\342\200\242 Power supply configuration\n",
-  "+\342\200\242 Board configuration\n",
-  "+\342\200\242 hardware configuration\n",
-  "+\342\200\242 Background power data collection (DCM)\n",
-  "+\342\200\242 Fault monitoring\n",
-  "+\342\200\242 RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)\n",
-  "+\342\200\242 Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)\n",
-  "+\342\200\242 I2C master for remote board control even with no DUT available\n",
+  "+? Configuration switch monitoring\n",
+  "+? Power on/off sequencing\n",
+  "+? Reset sequencing\n",
+  "+? Power supply configuration\n",
+  "+? Board configuration\n",
+  "+? hardware configuration\n",
+  "+? Background power data collection (DCM)\n",
+  "+? Fault monitoring\n",
+  "+? RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)\n",
+  "+? Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)\n",
+  "+? I2C master for remote board control even with no DUT available\n",
   "+\n",
   "+The qixis registers are accessible over one or more system-specific interfaces,\n",
   "+typically I2C, JTAG or an embedded processor.\n",
@@ -73,7 +67,7 @@
   "+\n",
   "+Examples:\n",
   "+\t/* The FPGA node */\n",
-  "+        fpga\@66 {\n",
+  "+        fpga at 66 {\n",
   "+\t\tcompatible = \"fsl,lx2160aqds-fpga\", \"fsl,fpga-qixis-i2c\";\n",
   "+\t\treg = <0x66>;\n",
   "+\t\t#address-cells = <1>;\n",
@@ -84,4 +78,4 @@
   "2.17.1"
 ]
 
-a3aae2abf28793517df2ae4bde3ebb397e9dc106ca989476712e53fc58d4db18
+1948f25a3a4be4683b08a2c935dd60e7e78c470f78fc47a147887367aa9025aa
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