[igt-dev] [PATCH i-g-t v2 0/3] Data Port Cache Coherency test.

[igt-dev] [PATCH i-g-t v2 0/3] Data Port Cache Coherency test.

[Tomasz Lis]

This adds a new test binary, containing test for the Data Port Coherency
option. The tests check whether the option has real effect on execution,
by submitting gpgpu fill job with and without the coherency.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>

Lis, Tomasz (3):
  lib: Separated emit part of gpgpu_fill.
  lib: Update surface state to set MOCS and coherency.
  igt: Add a test for Data Port Coherency.

 include/drm-uapi/i915_drm.h     |   7 +
 lib/gpgpu_fill.c                |  59 +++-----
 lib/gpgpu_fill.h                |   8 +-
 lib/gpu_cmds.c                  |   3 +
 lib/intel_batchbuffer.c         |  12 +-
 lib/intel_batchbuffer.h         |   2 +-
 tests/Makefile.sources          |   1 +
 tests/gem_gpgpu_fill.c          |  19 ++-
 tests/gem_gpgpu_fill_coherent.c | 296 ++++++++++++++++++++++++++++++++++++++++
 9 files changed, 352 insertions(+), 55 deletions(-)
 create mode 100644 tests/gem_gpgpu_fill_coherent.c

-- 
2.7.4

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[igt-dev] [PATCH i-g-t v2 1/3] lib: Separated emit part of gpgpu_fill.

[Tomasz Lis]

From: "Lis, Tomasz" <tomasz.lis@intel.com>

Having emitting and sumbission in one function was restricting
possible use cases of the code. Now it is possible to emit
the gpgpu_fill to a batchbuffer with something already there,
or add more commands after.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
---
 lib/gpgpu_fill.c        | 59 ++++++++++++++++---------------------------------
 lib/gpgpu_fill.h        |  8 +++----
 lib/intel_batchbuffer.c | 12 +++++-----
 lib/intel_batchbuffer.h |  2 +-
 tests/gem_gpgpu_fill.c  | 19 ++++++++++++----
 5 files changed, 45 insertions(+), 55 deletions(-)

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 003f461..654b791 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -117,18 +117,17 @@ static const uint32_t gen11_gpgpu_kernel[][4] = {
 #define GEN7_VFE_STATE_GPGPU_MODE 1
 
 void
-gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen7_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color)
 {
 	uint32_t curbe_buffer, interface_descriptor;
-	uint32_t batch_end;
-
-	intel_batchbuffer_flush(batch);
+	uint8_t *prev_ptr;
 
 	/* setup states */
+	prev_ptr = batch->ptr;
 	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
 
 	/*
@@ -143,7 +142,7 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 
 	igt_assert(batch->ptr < &batch->buffer[4095]);
 
-	batch->ptr = batch->buffer;
+	batch->ptr = prev_ptr;
 
 	/* GPGPU pipeline */
 	OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
@@ -156,28 +155,21 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	gen7_emit_interface_descriptor_load(batch, interface_descriptor);
 	gen7_emit_gpgpu_walk(batch, x, y, width, height);
 
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-
-	batch_end = intel_batchbuffer_align(batch, 8);
-	igt_assert(batch_end < BATCH_STATE_SPLIT);
-
-	gen7_render_flush(batch, batch_end);
-	intel_batchbuffer_reset(batch);
+	igt_assert(batch->ptr + 8 < batch->buffer + BATCH_STATE_SPLIT);
 }
 
 void
-gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen8_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color)
 {
 	uint32_t curbe_buffer, interface_descriptor;
-	uint32_t batch_end;
-
-	intel_batchbuffer_flush(batch);
+	uint8_t *prev_ptr;
 
 	/* setup states */
+	prev_ptr = batch->ptr;
 	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
 
 	/*
@@ -192,7 +184,7 @@ gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 
 	igt_assert(batch->ptr < &batch->buffer[4095]);
 
-	batch->ptr = batch->buffer;
+	batch->ptr = prev_ptr;
 
 	/* GPGPU pipeline */
 	OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
@@ -204,17 +196,11 @@ gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	gen7_emit_interface_descriptor_load(batch, interface_descriptor);
 	gen8_emit_gpgpu_walk(batch, x, y, width, height);
 
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-
-	batch_end = intel_batchbuffer_align(batch, 8);
-	igt_assert(batch_end < BATCH_STATE_SPLIT);
-
-	gen7_render_flush(batch, batch_end);
-	intel_batchbuffer_reset(batch);
+	igt_assert(batch->ptr + 8 < batch->buffer + BATCH_STATE_SPLIT);
 }
 
 static void
-__gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+__gen9_emit_gpgpu_fill(struct intel_batchbuffer *batch,
 		      const struct igt_buf *dst,
 		      unsigned int x, unsigned int y,
 		      unsigned int width, unsigned int height,
@@ -222,11 +208,10 @@ __gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		      size_t kernel_size)
 {
 	uint32_t curbe_buffer, interface_descriptor;
-	uint32_t batch_end;
-
-	intel_batchbuffer_flush(batch);
+	uint8_t *prev_ptr;
 
 	/* setup states */
+	prev_ptr = batch->ptr;
 	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
 
 	/*
@@ -241,7 +226,7 @@ __gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 
 	igt_assert(batch->ptr < &batch->buffer[4095]);
 
-	batch->ptr = batch->buffer;
+	batch->ptr = prev_ptr;
 
 	/* GPGPU pipeline */
 	OUT_BATCH(GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
@@ -254,31 +239,25 @@ __gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	gen7_emit_interface_descriptor_load(batch, interface_descriptor);
 	gen8_emit_gpgpu_walk(batch, x, y, width, height);
 
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-
-	batch_end = intel_batchbuffer_align(batch, 8);
-	igt_assert(batch_end < BATCH_STATE_SPLIT);
-
-	gen7_render_flush(batch, batch_end);
-	intel_batchbuffer_reset(batch);
+	igt_assert(batch->ptr + 8 < batch->buffer + BATCH_STATE_SPLIT);
 }
 
-void gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+void gen9_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			 const struct igt_buf *dst,
 			 unsigned int x, unsigned int y,
 			 unsigned int width, unsigned int height,
 			 uint8_t color)
 {
-	__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
+	__gen9_emit_gpgpu_fill(batch, dst, x, y, width, height, color,
 			      gen9_gpgpu_kernel, sizeof(gen9_gpgpu_kernel));
 }
 
-void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+void gen11_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 			  const struct igt_buf *dst,
 			  unsigned int x, unsigned int y,
 			  unsigned int width, unsigned int height,
 			  uint8_t color)
 {
-	__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
+	__gen9_emit_gpgpu_fill(batch, dst, x, y, width, height, color,
 			      gen11_gpgpu_kernel, sizeof(gen11_gpgpu_kernel));
 }
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index e405df3..1901b1e 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -30,28 +30,28 @@
 #include "intel_batchbuffer.h"
 
 void
-gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen7_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
 void
-gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen8_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
 void
-gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen9_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
 		    unsigned int x, unsigned int y,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
 void
-gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
+gen11_emit_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		     const struct igt_buf *dst,
 		     unsigned int x, unsigned int y,
 		     unsigned int width, unsigned int height,
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 387404f..dc1e6f2 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -871,7 +871,7 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
 }
 
 /**
- * igt_get_gpgpu_fillfunc:
+ * igt_get_emit_gpgpu_fill:
  * @devid: pci device id
  *
  * Returns:
@@ -879,18 +879,18 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
  * The platform-specific gpgpu fill function pointer for the device specified
  * with @devid. Will return NULL when no gpgpu fill function is implemented.
  */
-igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
+igt_fillfunc_t igt_get_emit_gpgpu_fillfunc(int devid)
 {
 	igt_fillfunc_t fill = NULL;
 
 	if (IS_GEN7(devid))
-		fill = gen7_gpgpu_fillfunc;
+		fill = gen7_emit_gpgpu_fillfunc;
 	else if (IS_BROADWELL(devid))
-		fill = gen8_gpgpu_fillfunc;
+		fill = gen8_emit_gpgpu_fillfunc;
 	else if (IS_GEN9(devid) || IS_GEN10(devid))
-		fill = gen9_gpgpu_fillfunc;
+		fill = gen9_emit_gpgpu_fillfunc;
 	else if (IS_GEN11(devid))
-		fill = gen11_gpgpu_fillfunc;
+		fill = gen11_emit_gpgpu_fillfunc;
 
 	return fill;
 }
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 2dcb09c..21babff 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -321,7 +321,7 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
 			       uint8_t color);
 
 igt_fillfunc_t igt_get_media_fillfunc(int devid);
-igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+igt_fillfunc_t igt_get_emit_gpgpu_fillfunc(int devid);
 
 /**
  * igt_media_spinfunc_t:
diff --git a/tests/gem_gpgpu_fill.c b/tests/gem_gpgpu_fill.c
index dfb5816..d79f747 100644
--- a/tests/gem_gpgpu_fill.c
+++ b/tests/gem_gpgpu_fill.c
@@ -44,6 +44,7 @@
 #include <sys/time.h>
 #include "drm.h"
 #include "intel_bufmgr.h"
+#include "gpu_cmds.h"
 
 #define WIDTH 64
 #define HEIGHT 64
@@ -99,7 +100,8 @@ igt_simple_main
 	data_t data = {0, };
 	struct intel_batchbuffer *batch = NULL;
 	struct igt_buf dst;
-	igt_fillfunc_t gpgpu_fill = NULL;
+	igt_fillfunc_t emit_gpgpu_fill = NULL;
+        uint32_t batch_end;
 	int i, j;
 
 	data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
@@ -109,9 +111,9 @@ igt_simple_main
 	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
 	igt_assert(data.bufmgr);
 
-	gpgpu_fill = igt_get_gpgpu_fillfunc(data.devid);
+	emit_gpgpu_fill = igt_get_emit_gpgpu_fillfunc(data.devid);
 
-	igt_require_f(gpgpu_fill,
+	igt_require_f(emit_gpgpu_fill,
 		      "no gpgpu-fill function\n");
 
 	batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
@@ -125,10 +127,19 @@ igt_simple_main
 		}
 	}
 
-	gpgpu_fill(batch,
+        intel_batchbuffer_flush(batch);
+
+	emit_gpgpu_fill(batch,
 		   &dst, 0, 0, WIDTH / 2, HEIGHT / 2,
 		   COLOR_4C);
 
+        OUT_BATCH(MI_BATCH_BUFFER_END);
+
+        batch_end = intel_batchbuffer_align(batch, 8);
+
+        gen7_render_flush(batch, batch_end);
+        intel_batchbuffer_reset(batch);
+
 	for (i = 0; i < WIDTH; i++) {
 		for (j = 0; j < HEIGHT; j++) {
 			if (i < WIDTH / 2 && j < HEIGHT / 2)
-- 
2.7.4

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[igt-dev] [PATCH i-g-t v2 2/3] lib: Update surface state to set MOCS and coherency.

[Tomasz Lis]

From: "Lis, Tomasz" <tomasz.lis@intel.com>

Having LLC cache enabled by MOCS is required to perform coherency tests.
Surface coherency type needs to be set as well for that test.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
---
 lib/gpu_cmds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c..d9c6fa1 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -376,6 +376,9 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
 	ss->ss2.width  = igt_buf_width(buf) - 1;
 	ss->ss3.pitch  = buf->stride - 1;
 
+	ss->ss1.memory_object_control = 2;
+	ss->ss5.coherency_type = 1;
+
 	ss->ss7.shader_chanel_select_r = 4;
 	ss->ss7.shader_chanel_select_g = 5;
 	ss->ss7.shader_chanel_select_b = 6;
-- 
2.7.4

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[igt-dev] [PATCH i-g-t v2 3/3] igt: Add a test for Data Port Coherency.

[Tomasz Lis]

From: "Lis, Tomasz" <tomasz.lis@intel.com>

This new test performs a gpgpu fill operation with spin buffer at end.
When Data Port Coherency is enabled, all the memory writes are required
to be visible on CPU side, even though the batch buffer did not finished
yet. Without the coherency enabled, memory writes made on GPU side are
not fully visible on CPU side until the spin buffer is released and the
execution of that buffer is finished.

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Winiarski <michal.winiarski@intel.com>

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
---
 include/drm-uapi/i915_drm.h     |   7 +
 tests/Makefile.sources          |   1 +
 tests/gem_gpgpu_fill_coherent.c | 299 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 307 insertions(+)
 create mode 100644 tests/gem_gpgpu_fill_coherent.c

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 16e452a..86bfac4 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1456,6 +1456,13 @@ struct drm_i915_gem_context_param {
 #define   I915_CONTEXT_MAX_USER_PRIORITY	1023 /* inclusive */
 #define   I915_CONTEXT_DEFAULT_PRIORITY		0
 #define   I915_CONTEXT_MIN_USER_PRIORITY	-1023 /* inclusive */
+/*
+ * When data port level coherency is enabled, the GPU will update memory
+ * buffers shared with CPU, by forcing internal cache units to send memory
+ * writes to higher level caches faster. Enabling data port coherency has
+ * a performance cost.
+ */
+#define I915_CONTEXT_PARAM_DATA_PORT_COHERENCY 0x7
 	__u64 value;
 };
 
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 001f1a2..b33d2d5 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -93,6 +93,7 @@ TESTS_progs = \
 	gem_flink_basic \
 	gem_flink_race \
 	gem_gpgpu_fill \
+	gem_gpgpu_fill_coherent \
 	gem_gtt_cpu_tlb \
 	gem_gtt_hog \
 	gem_gtt_speed \
diff --git a/tests/gem_gpgpu_fill_coherent.c b/tests/gem_gpgpu_fill_coherent.c
new file mode 100644
index 0000000..bf867c3
--- /dev/null
+++ b/tests/gem_gpgpu_fill_coherent.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Damien Lespiau <damien.lespiau@intel.com>
+ *    Xiang, Haihao <haihao.xiang@intel.com>
+ */
+
+/** @file gem_gpgpu_fill_coherent.c
+ *
+ * Check that the Data port coherency option han an effect on workload
+ * execution. Performs gpgpu_fill() with a spin buffer at end, expects
+ * coherent writes to be visible from CPU and non-coherent ones to not be
+ * visible within specific time frame.
+ */
+
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+#include "gpu_cmds.h"
+
+#define WIDTH 64
+#define HEIGHT 64
+#define SIZE (HEIGHT*WIDTH)
+
+#define COLOR_C4	0xc4
+#define COLOR_4C	0x4c
+
+#define DEFAULT_CONTEXT_IDX	0
+
+typedef struct {
+	int drm_fd;
+	uint32_t devid;
+	drm_intel_bufmgr *bufmgr;
+} data_t;
+
+/**
+ * __gem_context_set_coherency:
+ * @fd: open i915 drm file descriptor
+ * @ctx_id: i915 context id
+ * @enable: desired context coherency state
+ *
+ * This function modifies Data port coherency property of the context.
+ *
+ * Returns: An integer equal to zero for success and negative for failure
+ */
+static int
+__gem_context_set_coherency(int fd, uint32_t ctx_id, int enable)
+{
+	struct drm_i915_gem_context_param p;
+
+	memset(&p, 0, sizeof(p));
+	p.ctx_id = ctx_id;
+	p.size = 0;
+	p.param = I915_CONTEXT_PARAM_DATA_PORT_COHERENCY;
+	p.value = enable;
+
+	return __gem_context_set_param(fd, &p);
+}
+
+/**
+ * gem_context_set_coherency:
+ * @fd: open i915 drm file descriptor
+ * @ctx_id: i915 context id
+ * @enable: desired context coherency state
+ *
+ * Like __gem_context_set_coherency(), except we assert on failure.
+ */
+static void
+gem_context_set_coherency(int fd, uint32_t ctx_id, int enable)
+{
+	igt_assert(__gem_context_set_coherency(fd, ctx_id, enable) == 0);
+}
+
+/**
+ * gem_context_get_coherency:
+ * @fd: open i915 drm file descriptor
+ * @ctx_id: i915 context id
+ *
+ * Retrieves current value of the data port coherency param.
+ */
+static int
+gem_context_get_coherency(int fd, uint32_t ctx_id)
+{
+	struct drm_i915_gem_context_param p;
+	memset(&p, 0, sizeof(p));
+	p.ctx_id = ctx_id;
+	p.size = 0;
+	p.param = I915_CONTEXT_PARAM_DATA_PORT_COHERENCY;
+
+	igt_assert(__gem_context_get_param(fd, &p) == 0);
+
+	return p.value;
+}
+
+static void
+scratch_buf_init(data_t *data, struct igt_buf *buf,
+		 int width, int height, uint8_t color)
+{
+	memset(buf, 0, sizeof(*buf));
+
+	buf->stride = width;
+	buf->tiling = I915_TILING_NONE;
+	buf->size = width*height;
+	buf->bo = drm_intel_bo_alloc(data->bufmgr, "", buf->size, 4096);
+
+	buf->data = drm_intel_gem_bo_map__wc(buf->bo);
+	if (!buf->data)
+		buf->data = drm_intel_gem_bo_map__gtt(buf->bo);
+
+	memset(buf->data, color, buf->size);
+}
+
+/**
+ * scratch_buf_check_plain:
+ * @buf: structure containing the buffer to check
+ * @width: width dimension of the 2D buffer, equal to stride
+ * @height: height dimension of the 2D buffer
+ *
+ * This function verifies whether the buffer is completely filled with given color.
+ *
+ * Returns: void; asserts if verification failed
+ */
+static void
+scratch_buf_check_plain(struct igt_buf *buf, int width, int height, uint8_t color)
+{
+	int i, j;
+        uint8_t val;
+        uint8_t *linear;
+
+	linear = (uint8_t *)buf->data;
+	for (i = 0; i < width; i++) {
+		for (j = 0; j < height; j++) {
+			val = linear[j * width + i];
+	                igt_assert_f(val == color,
+				"Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+				color, val, i, j);
+		}
+	}
+}
+
+/**
+ * scratch_buf_check_vstripes:
+ * @buf: structure containing the buffer to check
+ * @width: width dimension of the 2D buffer, equal to stride
+ * @height: height dimension of the 2D buffer
+ *
+ * This function verifies content of the buffer while it is being filled by the GPU.
+ * The buffer should contain 2 vertical stripes of different color.
+ *
+ * Returns: True if left stripe is filled, false on timeout; asserts if right stripe is not filled
+ */
+static bool
+scratch_buf_check_vstripes(struct igt_buf *buf, int width, int height,
+			   uint8_t colorl, uint8_t colorr)
+{
+	int i, j;
+	uint8_t val;
+	uint8_t *linear;
+
+	linear = (uint8_t *)buf->data;
+	for (i = 0; i < WIDTH; i++) {
+		for (j = 0; j < HEIGHT; j++) {
+			val = linear[j * width + i];
+			if (j < HEIGHT / 2) {
+				if (val != colorl) return false;
+			} else {
+				igt_assert_f(val == colorr,
+					"Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+					colorr, val, i, j);
+			}
+		}
+	}
+	return true;
+}
+
+static uint32_t
+igt_batchbuffer_spin_emit(struct intel_batchbuffer *batch)
+{
+	uint32_t spin_offset;
+	spin_offset = intel_batchbuffer_subdata_offset(batch, batch->ptr);
+	OUT_BATCH(MI_NOOP);
+	/* recurse */
+	OUT_BATCH(MI_BATCH_BUFFER_START | 1 << 8 | 1);
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_COMMAND, 0, spin_offset);
+	return spin_offset;
+}
+
+static void
+igt_batchbuffer_spin_finish(struct intel_batchbuffer *batch, uint32_t spin_offset)
+{
+	uint8_t * mmbuffer;
+	mmbuffer = drm_intel_gem_bo_map__wc(batch->bo);
+	if (!mmbuffer)
+		mmbuffer = drm_intel_gem_bo_map__gtt(batch->bo);
+
+	*((uint32_t *)(mmbuffer + spin_offset)) = MI_BATCH_BUFFER_END;
+
+	drm_intel_bo_unmap(batch->bo);
+}
+
+static void
+igt_batchbuffer_coherency_test(data_t *data, struct intel_batchbuffer *batch,
+			       igt_fillfunc_t emit_gpgpu_fill, bool coherent)
+{
+	struct igt_buf dst;
+        uint32_t batch_end, spin_offset;
+	bool res;
+
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, COLOR_C4);
+	scratch_buf_check_plain(&dst, WIDTH, HEIGHT, COLOR_C4);
+
+        intel_batchbuffer_flush(batch);
+	gem_context_set_coherency(data->drm_fd, DEFAULT_CONTEXT_IDX, coherent);
+
+	emit_gpgpu_fill(batch,
+		   &dst, 0, 0, WIDTH, HEIGHT / 2,
+		   COLOR_4C);
+
+	spin_offset = igt_batchbuffer_spin_emit(batch);
+
+        OUT_BATCH(MI_BATCH_BUFFER_END);
+        batch_end = intel_batchbuffer_align(batch, 8);
+
+        gen7_render_flush(batch, batch_end);
+
+	res = igt_wait(scratch_buf_check_vstripes(&dst, WIDTH, HEIGHT, COLOR_4C, COLOR_C4), 100, 1);
+
+	igt_batchbuffer_spin_finish(batch, spin_offset);
+
+        intel_batchbuffer_reset(batch);
+
+	if (coherent)
+		igt_assert_f(res,
+			"coherent buffer fill not visible on CPU side after 100ms");
+	else
+		igt_assert_f(!res,
+			"non-coherent buffer fill visible on CPU side within 100ms");
+}
+
+igt_simple_main
+{
+	data_t data = {0, };
+	struct intel_batchbuffer *batch = NULL;
+	igt_fillfunc_t emit_gpgpu_fill = NULL;
+
+	data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
+	data.devid = intel_get_drm_devid(data.drm_fd);
+	igt_require_gem(data.drm_fd);
+
+	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
+	igt_assert(data.bufmgr);
+
+	emit_gpgpu_fill = igt_get_emit_gpgpu_fillfunc(data.devid);
+
+	igt_require_f(emit_gpgpu_fill,
+		      "no gpgpu-fill function\n");
+	igt_require_f(gem_context_get_coherency(data.drm_fd, 0) >= 0,
+		"Data Port Coherency not supported by kernel\n");
+
+	batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
+	igt_assert(batch);
+
+	/* Test without coherency */
+	igt_batchbuffer_coherency_test(&data, batch, emit_gpgpu_fill, 0);
+
+	/* Now test with Data Port coherency */
+	igt_batchbuffer_coherency_test(&data, batch, emit_gpgpu_fill, 1);
+}
-- 
2.7.4

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[igt-dev] ✓ Fi.CI.BAT: success for Data Port Cache Coherency test.

[Patchwork]

== Series Details ==

Series: Data Port Cache Coherency test.
URL   : https://patchwork.freedesktop.org/series/50631/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4933 -> IGTPW_1919 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50631/revisions/1/mbox/

== Known issues ==

  Here are the changes found in IGTPW_1919 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-bdw-samus:       NOTRUN -> INCOMPLETE (fdo#107773)

    
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773


== Participating hosts (44 -> 40) ==

  Additional (3): fi-glk-j4005 fi-bdw-samus fi-snb-2520m 
  Missing    (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-byt-clapper fi-kbl-r 


== Build changes ==

    * IGT: IGT_4669 -> IGTPW_1919

  CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1919: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1919/
  IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1919/issues.html
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[igt-dev] ✗ Fi.CI.IGT: failure for Data Port Cache Coherency test.

[Patchwork]

== Series Details ==

Series: Data Port Cache Coherency test.
URL   : https://patchwork.freedesktop.org/series/50631/
State : failure

== Summary ==

= CI Bug Log - changes from IGT_4669_full -> IGTPW_1919_full =

== Summary - FAILURE ==

  Serious unknown changes coming with IGTPW_1919_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1919_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50631/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1919_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_color@pipe-b-ctm-max:
      shard-kbl:          PASS -> FAIL

    
== Known issues ==

  Here are the changes found in IGTPW_1919_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_color@pipe-b-ctm-max:
      shard-apl:          PASS -> FAIL (fdo#108147)

    igt@kms_cursor_crc@cursor-128x128-sliding:
      shard-apl:          PASS -> FAIL (fdo#103232) +1

    igt@kms_cursor_crc@cursor-64x64-random:
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359) +1

    igt@kms_cursor_crc@cursor-64x64-sliding:
      shard-glk:          PASS -> FAIL (fdo#103232) +2

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          PASS -> DMESG-WARN (fdo#105763, fdo#106538)

    igt@kms_flip@2x-absolute-wf_vblank:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
      shard-glk:          PASS -> FAIL (fdo#103167) +1

    {igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb}:
      shard-apl:          PASS -> FAIL (fdo#108145)
      shard-glk:          PASS -> FAIL (fdo#108145) +1

    igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
      shard-glk:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          PASS -> FAIL (fdo#103166) +3

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@gem_eio@in-flight-internal-10ms:
      shard-glk:          FAIL (fdo#105957) -> PASS

    igt@gem_eio@reset-stress:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          FAIL (fdo#108147) -> PASS

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          FAIL (fdo#103232) -> PASS +5
      shard-kbl:          FAIL (fdo#103232) -> PASS +1

    igt@kms_cursor_crc@cursor-64x64-onscreen:
      shard-glk:          FAIL (fdo#103232) -> PASS +2

    igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
      shard-glk:          DMESG-WARN (fdo#105763, fdo#106538) -> PASS +3

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-apl:          FAIL (fdo#103167) -> PASS +3

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +13

    igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
      shard-glk:          FAIL (fdo#103166) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS +2

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 5) ==

  Missing    (1): shard-skl 


== Build changes ==

    * IGT: IGT_4669 -> IGTPW_1919
    * Linux: CI_DRM_4931 -> CI_DRM_4933

  CI_DRM_4931: 826702bf60ae2b37841c051ed769b44af194fbb1 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4933: 6b7a44d1597791524f46d7ea17620db54dffdc8c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1919: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1919/
  IGT_4669: 5f40e617cd9c1e089f4a2d79c53a417d891e3e3c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1919/shards.html
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Re: [igt-dev] [PATCH i-g-t v2 1/3] lib: Separated emit part of gpgpu_fill.

[Kalamarz, Lukasz]

On Fri, 2018-10-05 at 20:04 +0200, Tomasz Lis wrote:
> From: "Lis, Tomasz" <tomasz.lis@intel.com>
> 
> Having emitting and sumbission in one function was restricting
> possible use cases of the code. Now it is possible to emit
> the gpgpu_fill to a batchbuffer with something already there,
> or add more commands after.

Some other libs are using same approach (i.e. rendercopy, media_fill).
Maybe it will be a good idea to do this also for those libs

> 
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Winiarski <michal.winiarski@intel.com>
> 
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> ---
>  lib/gpgpu_fill.c        | 59 ++++++++++++++++-----------------------
> ----------
>  lib/gpgpu_fill.h        |  8 +++----
>  lib/intel_batchbuffer.c | 12 +++++-----
>  lib/intel_batchbuffer.h |  2 +-
>  tests/gem_gpgpu_fill.c  | 19 ++++++++++++----
>  5 files changed, 45 insertions(+), 55 deletions(-)
> 

<SNIP>

> diff --git a/tests/gem_gpgpu_fill.c b/tests/gem_gpgpu_fill.c
> index dfb5816..d79f747 100644
> --- a/tests/gem_gpgpu_fill.c
> +++ b/tests/gem_gpgpu_fill.c
> @@ -44,6 +44,7 @@
>  #include <sys/time.h>
>  #include "drm.h"
>  #include "intel_bufmgr.h"
> +#include "gpu_cmds.h"
>  
>  #define WIDTH 64
>  #define HEIGHT 64
> @@ -99,7 +100,8 @@ igt_simple_main
>  	data_t data = {0, };
>  	struct intel_batchbuffer *batch = NULL;
>  	struct igt_buf dst;
> -	igt_fillfunc_t gpgpu_fill = NULL;
> +	igt_fillfunc_t emit_gpgpu_fill = NULL;
> +        uint32_t batch_end;

Whitespace

>  	int i, j;
>  
>  	data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
> @@ -109,9 +111,9 @@ igt_simple_main
>  	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
>  	igt_assert(data.bufmgr);
>  
> -	gpgpu_fill = igt_get_gpgpu_fillfunc(data.devid);
> +	emit_gpgpu_fill = igt_get_emit_gpgpu_fillfunc(data.devid);
>  
> -	igt_require_f(gpgpu_fill,
> +	igt_require_f(emit_gpgpu_fill,
>  		      "no gpgpu-fill function\n");
>  
>  	batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
> @@ -125,10 +127,19 @@ igt_simple_main
>  		}
>  	}
>  
> -	gpgpu_fill(batch,
> +        intel_batchbuffer_flush(batch);
> +
> +	emit_gpgpu_fill(batch,
>  		   &dst, 0, 0, WIDTH / 2, HEIGHT / 2,
>  		   COLOR_4C);
>  
> +        OUT_BATCH(MI_BATCH_BUFFER_END);
> +
> +        batch_end = intel_batchbuffer_align(batch, 8);
> +
> +        gen7_render_flush(batch, batch_end);
> +        intel_batchbuffer_reset(batch);
> +

Maybe move this part to lib as a new function (submit_gpgpu_fill)?
------
Lukasz

>  	for (i = 0; i < WIDTH; i++) {
>  		for (j = 0; j < HEIGHT; j++) {
>  			if (i < WIDTH / 2 && j < HEIGHT / 2)
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