[PATCH 00/25] reserve RM resources in CRTC state

[PATCH 00/25] reserve RM resources in CRTC state

[Jeykumar Sankaran]

Submitting series of patches to clean up DPU resource manager (RM)
of complicated hw iterations, redundant data maintenence and eventually
modifying the DPU to reserve display HW blocks only in atomic check
and caching the assigned HW blocks in atomic CRTC state.

Thanks,
Jeykumar S.

Jeykumar Sankaran (25):
  drm/msm/dpu: fix hw ctl retrieval for mixer muxing
  drm/msm/dpu: avoid tracking reservations in RM
  drm/msm/dpu: remove dev from RM
  drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration
  drm/msm/dpu: remove encoder from crtc mixer struct
  drm/msm/dpu: clean up redundant hw type
  drm/msm/dpu: reserve using crtc state
  drm/msm/dpu: release reservation using crtc state
  drm/msm/dpu: make RM iterator static
  drm/msm/dpu: maintain hw_mdp in kms
  drm/msm/dpu: remove reserve in encoder mode_set
  drm/msm/dpu: remove mode_set_complete
  drm/msm/dpu: make RM iterator hw type specific
  drm/msm/dpu: remove enc_id tagging for hw blocks
  drm/msm/dpu: avoid redundant hw blk reference
  drm/msm/dpu: clean up test_only flag for RM reservation
  drm/msm/dpu: remove RM HW block list iterator
  drm/msm/dpu: merge RM interface reservation helpers
  drm/msm/dpu: remove msm_display_topology
  drm/msm/dpu: refine layer mixer reservations
  drm/msm/dpu: merge RM reservation helpers
  drm/msm/dpu: make crtc and encoder specific HW reservation
  drm/msm/dpu: remove max_width from RM
  drm/msm/dpu: remove mutex locking for RM interfaces
  drm/msm/dpu: maintain RM init check internally

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  98 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |  16 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  96 +--
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  20 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |  16 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 728 ++++++---------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 107 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h          |  28 +-
 drivers/gpu/drm/msm/msm_drv.h                      |  12 -
 10 files changed, 322 insertions(+), 800 deletions(-)

-- 
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a Linux Foundation Collaborative Project

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[PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Jeykumar Sankaran]

Layer mixer/pingpong block counts and hw ctl block counts
will not be same for all the topologies (e.g. layer
mixer muxing to single interface)

Use the encoder's split_role info to retrieve the
respective control path for programming.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 96cdf06..d12f896 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+		int ctl_index;
 
 		if (phys) {
 			if (!dpu_enc->hw_pp[i]) {
@@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 				return;
 			}
 
-			if (!hw_ctl[i]) {
+			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
+
+			if (!hw_ctl[ctl_index]) {
 				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
-					     "at idx: %d\n", i);
+					     "at idx: %d\n", ctl_index);
 				return;
 			}
 
 			phys->hw_pp = dpu_enc->hw_pp[i];
-			phys->hw_ctl = hw_ctl[i];
+			phys->hw_ctl = hw_ctl[ctl_index];
 
 			phys->connector = conn->state->connector;
 			if (phys->ops.mode_set)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 02/25] drm/msm/dpu: avoid tracking reservations in RM

[Jeykumar Sankaran]

RM was equipped with reservation tracking structure RSVP
to cache HW reservation of displays for certain clients
where atomic_checks (atomic commit with TEST_ONLY) for all
the displays are called before their respective atomic_commits.
Since DPU doesn't support the sequence anymore, clean up
the support from RM. Replace rsvp with the corresponding
encoder id to tag the HW blocks reserved.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 284 +++++----------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   4 -
 2 files changed, 43 insertions(+), 245 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bdb1177..36a929b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -21,8 +21,8 @@
 #include "dpu_encoder.h"
 #include "dpu_trace.h"
 
-#define RESERVED_BY_OTHER(h, r) \
-	((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
+#define RESERVED_BY_OTHER(h, r)  \
+		((h)->enc_id && (h)->enc_id != r)
 
 /**
  * struct dpu_rm_requirements - Reservation requirements parameter bundle
@@ -34,85 +34,23 @@ struct dpu_rm_requirements {
 	struct dpu_encoder_hw_resources hw_res;
 };
 
-/**
- * struct dpu_rm_rsvp - Use Case Reservation tagging structure
- *	Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
- *	By using as a tag, rather than lists of pointers to HW blocks used
- *	we can avoid some list management since we don't know how many blocks
- *	of each type a given use case may require.
- * @list:	List head for list of all reservations
- * @seq:	Global RSVP sequence number for debugging, especially for
- *		differentiating differenct allocations for same encoder.
- * @enc_id:	Reservations are tracked by Encoder DRM object ID.
- *		CRTCs may be connected to multiple Encoders.
- *		An encoder or connector id identifies the display path.
- */
-struct dpu_rm_rsvp {
-	struct list_head list;
-	uint32_t seq;
-	uint32_t enc_id;
-};
 
 /**
  * struct dpu_rm_hw_blk - hardware block tracking list member
  * @list:	List head for list of all hardware blocks tracking items
- * @rsvp:	Pointer to use case reservation if reserved by a client
- * @rsvp_nxt:	Temporary pointer used during reservation to the incoming
- *		request. Will be swapped into rsvp if proposal is accepted
  * @type:	Type of hardware block this structure tracks
  * @id:		Hardware ID number, within it's own space, ie. LM_X
- * @catalog:	Pointer to the hardware catalog entry for this block
+ * @enc_id:	Encoder id to which this blk is binded
  * @hw:		Pointer to the hardware register access object for this block
  */
 struct dpu_rm_hw_blk {
 	struct list_head list;
-	struct dpu_rm_rsvp *rsvp;
-	struct dpu_rm_rsvp *rsvp_nxt;
 	enum dpu_hw_blk_type type;
 	uint32_t id;
+	uint32_t enc_id;
 	struct dpu_hw_blk *hw;
 };
 
-/**
- * dpu_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
- */
-enum dpu_rm_dbg_rsvp_stage {
-	DPU_RM_STAGE_BEGIN,
-	DPU_RM_STAGE_AFTER_CLEAR,
-	DPU_RM_STAGE_AFTER_RSVPNEXT,
-	DPU_RM_STAGE_FINAL
-};
-
-static void _dpu_rm_print_rsvps(
-		struct dpu_rm *rm,
-		enum dpu_rm_dbg_rsvp_stage stage)
-{
-	struct dpu_rm_rsvp *rsvp;
-	struct dpu_rm_hw_blk *blk;
-	enum dpu_hw_blk_type type;
-
-	DPU_DEBUG("%d\n", stage);
-
-	list_for_each_entry(rsvp, &rm->rsvps, list) {
-		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
-			      rsvp->enc_id);
-	}
-
-	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
-		list_for_each_entry(blk, &rm->hw_blks[type], list) {
-			if (!blk->rsvp && !blk->rsvp_nxt)
-				continue;
-
-			DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
-				(blk->rsvp) ? blk->rsvp->seq : 0,
-				(blk->rsvp) ? blk->rsvp->enc_id : 0,
-				(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
-				(blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
-				blk->type, blk->id);
-		}
-	}
-}
-
 struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
 {
 	return rm->hw_mdp;
@@ -148,15 +86,13 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 	i->blk = list_prepare_entry(i->blk, blk_list, list);
 
 	list_for_each_entry_continue(i->blk, blk_list, list) {
-		struct dpu_rm_rsvp *rsvp = i->blk->rsvp;
-
 		if (i->blk->type != i->type) {
 			DPU_ERROR("found incorrect block type %d on %d list\n",
 					i->blk->type, i->type);
 			return false;
 		}
 
-		if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
+		if (i->enc_id == i->blk->enc_id) {
 			i->hw = i->blk->hw;
 			DPU_DEBUG("found type %d id %d for enc %d\n",
 					i->type, i->blk->id, i->enc_id);
@@ -208,22 +144,9 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
 
 int dpu_rm_destroy(struct dpu_rm *rm)
 {
-
-	struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt;
 	struct dpu_rm_hw_blk *hw_cur, *hw_nxt;
 	enum dpu_hw_blk_type type;
 
-	if (!rm) {
-		DPU_ERROR("invalid rm\n");
-		return -EINVAL;
-	}
-
-	list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
-		list_del(&rsvp_cur->list);
-		kfree(rsvp_cur);
-	}
-
-
 	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
 		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
 				list) {
@@ -293,6 +216,7 @@ static int _dpu_rm_hw_blk_create(
 	blk->type = type;
 	blk->id = id;
 	blk->hw = hw;
+	blk->enc_id = 0;
 	list_add_tail(&blk->list, &rm->hw_blks[type]);
 
 	return 0;
@@ -316,7 +240,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 
 	mutex_init(&rm->rm_lock);
 
-	INIT_LIST_HEAD(&rm->rsvps);
 	for (type = 0; type < DPU_HW_BLK_MAX; type++)
 		INIT_LIST_HEAD(&rm->hw_blks[type]);
 
@@ -410,7 +333,7 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  *	proposed use case requirements, incl. hardwired dependent blocks like
  *	pingpong
  * @rm: dpu resource manager handle
- * @rsvp: reservation currently being created
+ * @enc_id: encoder id requesting for allocation
  * @reqs: proposed use case requirements
  * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  *      blocks connected to the lm (pp) is available and appropriate
@@ -422,7 +345,7 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  */
 static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
+		uint32_t enc_id,
 		struct dpu_rm_requirements *reqs,
 		struct dpu_rm_hw_blk *lm,
 		struct dpu_rm_hw_blk **pp,
@@ -449,7 +372,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 	}
 
 	/* Already reserved? */
-	if (RESERVED_BY_OTHER(lm, rsvp)) {
+	if (RESERVED_BY_OTHER(lm, enc_id)) {
 		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
 		return false;
 	}
@@ -467,7 +390,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	if (RESERVED_BY_OTHER(*pp, rsvp)) {
+	if (RESERVED_BY_OTHER(*pp, enc_id)) {
 		DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
 				(*pp)->id);
 		return false;
@@ -476,10 +399,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 	return true;
 }
 
-static int _dpu_rm_reserve_lms(
-		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
-		struct dpu_rm_requirements *reqs)
+static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
+			       struct dpu_rm_requirements *reqs)
 
 {
 	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
@@ -504,7 +425,7 @@ static int _dpu_rm_reserve_lms(
 		lm[lm_count] = iter_i.blk;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, rsvp, reqs, lm[lm_count],
+				rm, enc_id, reqs, lm[lm_count],
 				&pp[lm_count], NULL))
 			continue;
 
@@ -519,7 +440,7 @@ static int _dpu_rm_reserve_lms(
 				continue;
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, rsvp, reqs, iter_j.blk,
+					rm, enc_id, reqs, iter_j.blk,
 					&pp[lm_count], iter_i.blk))
 				continue;
 
@@ -537,10 +458,10 @@ static int _dpu_rm_reserve_lms(
 		if (!lm[i])
 			break;
 
-		lm[i]->rsvp_nxt = rsvp;
-		pp[i]->rsvp_nxt = rsvp;
+		lm[i]->enc_id = enc_id;
+		pp[i]->enc_id = enc_id;
 
-		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id,
+		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, enc_id,
 					 pp[i]->id);
 	}
 
@@ -549,7 +470,7 @@ static int _dpu_rm_reserve_lms(
 
 static int _dpu_rm_reserve_ctls(
 		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
+		uint32_t enc_id,
 		const struct msm_display_topology *top)
 {
 	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
@@ -570,7 +491,7 @@ static int _dpu_rm_reserve_ctls(
 		unsigned long features = ctl->caps->features;
 		bool has_split_display;
 
-		if (RESERVED_BY_OTHER(iter.blk, rsvp))
+		if (RESERVED_BY_OTHER(iter.blk, enc_id))
 			continue;
 
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
@@ -591,9 +512,9 @@ static int _dpu_rm_reserve_ctls(
 		return -ENAVAIL;
 
 	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
-		ctls[i]->rsvp_nxt = rsvp;
+		ctls[i]->enc_id = enc_id;
 		trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
-					  rsvp->enc_id);
+					  enc_id);
 	}
 
 	return 0;
@@ -601,7 +522,7 @@ static int _dpu_rm_reserve_ctls(
 
 static int _dpu_rm_reserve_intf(
 		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
+		uint32_t enc_id,
 		uint32_t id,
 		enum dpu_hw_blk_type type)
 {
@@ -614,14 +535,14 @@ static int _dpu_rm_reserve_intf(
 		if (iter.blk->id != id)
 			continue;
 
-		if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
+		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
 			DPU_ERROR("type %d id %d already reserved\n", type, id);
 			return -ENAVAIL;
 		}
 
-		iter.blk->rsvp_nxt = rsvp;
+		iter.blk->enc_id = enc_id;
 		trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
-					  rsvp->enc_id);
+					  enc_id);
 		break;
 	}
 
@@ -636,7 +557,7 @@ static int _dpu_rm_reserve_intf(
 
 static int _dpu_rm_reserve_intf_related_hw(
 		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
+		uint32_t enc_id,
 		struct dpu_encoder_hw_resources *hw_res)
 {
 	int i, ret = 0;
@@ -646,7 +567,7 @@ static int _dpu_rm_reserve_intf_related_hw(
 		if (hw_res->intfs[i] == INTF_MODE_NONE)
 			continue;
 		id = i + INTF_0;
-		ret = _dpu_rm_reserve_intf(rm, rsvp, id,
+		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
 				DPU_HW_BLK_INTF);
 		if (ret)
 			return ret;
@@ -655,33 +576,27 @@ static int _dpu_rm_reserve_intf_related_hw(
 	return ret;
 }
 
-static int _dpu_rm_make_next_rsvp(
+static int _dpu_rm_make_reservation(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
 		struct drm_crtc_state *crtc_state,
-		struct dpu_rm_rsvp *rsvp,
 		struct dpu_rm_requirements *reqs)
 {
 	int ret;
 
-	/* Create reservation info, tag reserved blocks with it as we go */
-	rsvp->seq = ++rm->rsvp_next_seq;
-	rsvp->enc_id = enc->base.id;
-	list_add_tail(&rsvp->list, &rm->rsvps);
-
-	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
+	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_ctls(rm, rsvp, &reqs->topology);
+	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate CTL\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
+	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, &reqs->hw_res);
 	if (ret)
 		return ret;
 
@@ -706,108 +621,31 @@ static int _dpu_rm_populate_requirements(
 	return 0;
 }
 
-static struct dpu_rm_rsvp *_dpu_rm_get_rsvp(
-		struct dpu_rm *rm,
-		struct drm_encoder *enc)
+static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
 {
-	struct dpu_rm_rsvp *i;
-
-	if (!rm || !enc) {
-		DPU_ERROR("invalid params\n");
-		return NULL;
-	}
-
-	if (list_empty(&rm->rsvps))
-		return NULL;
-
-	list_for_each_entry(i, &rm->rsvps, list)
-		if (i->enc_id == enc->base.id)
-			return i;
-
-	return NULL;
-}
-
-/**
- * _dpu_rm_release_rsvp - release resources and release a reservation
- * @rm:	KMS handle
- * @rsvp:	RSVP pointer to release and release resources for
- */
-static void _dpu_rm_release_rsvp(struct dpu_rm *rm, struct dpu_rm_rsvp *rsvp)
-{
-	struct dpu_rm_rsvp *rsvp_c, *rsvp_n;
 	struct dpu_rm_hw_blk *blk;
 	enum dpu_hw_blk_type type;
 
-	if (!rsvp)
-		return;
-
-	DPU_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
-
-	list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
-		if (rsvp == rsvp_c) {
-			list_del(&rsvp_c->list);
-			break;
-		}
-	}
-
 	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
 		list_for_each_entry(blk, &rm->hw_blks[type], list) {
-			if (blk->rsvp == rsvp) {
-				blk->rsvp = NULL;
-				DPU_DEBUG("rel rsvp %d enc %d %d %d\n",
-						rsvp->seq, rsvp->enc_id,
-						blk->type, blk->id);
-			}
-			if (blk->rsvp_nxt == rsvp) {
-				blk->rsvp_nxt = NULL;
-				DPU_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
-						rsvp->seq, rsvp->enc_id,
-						blk->type, blk->id);
+			if (blk->enc_id == enc_id) {
+				blk->enc_id = 0;
+				DPU_DEBUG("rel enc %d %d %d\n", enc_id,
+					  blk->type, blk->id);
 			}
 		}
 	}
-
-	kfree(rsvp);
 }
 
 void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc)
 {
-	struct dpu_rm_rsvp *rsvp;
-
-	if (!rm || !enc) {
-		DPU_ERROR("invalid params\n");
-		return;
-	}
-
 	mutex_lock(&rm->rm_lock);
 
-	rsvp = _dpu_rm_get_rsvp(rm, enc);
-	if (!rsvp) {
-		DPU_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
-		goto end;
-	}
+	_dpu_rm_release_reservation(rm, enc->base.id);
 
-	_dpu_rm_release_rsvp(rm, rsvp);
-end:
 	mutex_unlock(&rm->rm_lock);
 }
 
-static void _dpu_rm_commit_rsvp(struct dpu_rm *rm, struct dpu_rm_rsvp *rsvp)
-{
-	struct dpu_rm_hw_blk *blk;
-	enum dpu_hw_blk_type type;
-
-	/* Swap next rsvp to be the active */
-	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
-		list_for_each_entry(blk, &rm->hw_blks[type], list) {
-			if (blk->rsvp_nxt) {
-				blk->rsvp = blk->rsvp_nxt;
-				blk->rsvp_nxt = NULL;
-			}
-		}
-	}
-}
-
 int dpu_rm_reserve(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
@@ -815,7 +653,6 @@ int dpu_rm_reserve(
 		struct msm_display_topology topology,
 		bool test_only)
 {
-	struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt;
 	struct dpu_rm_requirements reqs;
 	int ret;
 
@@ -828,8 +665,6 @@ int dpu_rm_reserve(
 
 	mutex_lock(&rm->rm_lock);
 
-	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_BEGIN);
-
 	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
 					    topology);
 	if (ret) {
@@ -837,50 +672,17 @@ int dpu_rm_reserve(
 		goto end;
 	}
 
-	/*
-	 * We only support one active reservation per-hw-block. But to implement
-	 * transactional semantics for test-only, and for allowing failure while
-	 * modifying your existing reservation, over the course of this
-	 * function we can have two reservations:
-	 * Current: Existing reservation
-	 * Next: Proposed reservation. The proposed reservation may fail, or may
-	 *       be discarded if in test-only mode.
-	 * If reservation is successful, and we're not in test-only, then we
-	 * replace the current with the next.
-	 */
-	rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
-	if (!rsvp_nxt) {
-		ret = -ENOMEM;
-		goto end;
-	}
-
-	rsvp_cur = _dpu_rm_get_rsvp(rm, enc);
-
-	/* Check the proposed reservation, store it in hw's "next" field */
-	ret = _dpu_rm_make_next_rsvp(rm, enc, crtc_state, rsvp_nxt, &reqs);
-
-	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_AFTER_RSVPNEXT);
-
+	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
-		_dpu_rm_release_rsvp(rm, rsvp_nxt);
+		_dpu_rm_release_reservation(rm, enc->base.id);
 	} else if (test_only) {
-		/*
-		 * Normally, if test_only, test the reservation and then undo
-		 * However, if the user requests LOCK, then keep the reservation
-		 * made during the atomic_check phase.
-		 */
-		DPU_DEBUG("test_only: discard test rsvp[s%de%d]\n",
-				rsvp_nxt->seq, rsvp_nxt->enc_id);
-		_dpu_rm_release_rsvp(rm, rsvp_nxt);
-	} else {
-		_dpu_rm_release_rsvp(rm, rsvp_cur);
-
-		_dpu_rm_commit_rsvp(rm, rsvp_nxt);
+		 /* test_only: test the reservation and then undo */
+		DPU_DEBUG("test_only: discard test [enc: %d]\n",
+				enc->base.id);
+		_dpu_rm_release_reservation(rm, enc->base.id);
 	}
 
-	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_FINAL);
-
 end:
 	mutex_unlock(&rm->rm_lock);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index b8273bd..0dd3c21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -23,21 +23,17 @@
 /**
  * struct dpu_rm - DPU dynamic hardware resource manager
  * @dev: device handle for event logging purposes
- * @rsvps: list of hardware reservations by each crtc->encoder->connector
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
  * @hw_mdp: hardware object for mdp_top
  * @lm_max_width: cached layer mixer maximum width
- * @rsvp_next_seq: sequence number for next reservation for debugging purposes
  * @rm_lock: resource manager mutex
  */
 struct dpu_rm {
 	struct drm_device *dev;
-	struct list_head rsvps;
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
 	struct dpu_hw_mdp *hw_mdp;
 	uint32_t lm_max_width;
-	uint32_t rsvp_next_seq;
 	struct mutex rm_lock;
 };
 
-- 
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[PATCH 03/25] drm/msm/dpu: remove dev from RM

[Jeykumar Sankaran]

Not used. Remove from RM.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 7 ++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  | 6 +-----
 3 files changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0a683e6..8309850 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1075,8 +1075,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 		goto power_error;
 	}
 
-	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio,
-			dpu_kms->dev);
+	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
 	if (rc) {
 		DPU_ERROR("rm init failed: %d\n", rc);
 		goto power_error;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 36a929b..5ce89b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -224,13 +224,12 @@ static int _dpu_rm_hw_blk_create(
 
 int dpu_rm_init(struct dpu_rm *rm,
 		struct dpu_mdss_cfg *cat,
-		void __iomem *mmio,
-		struct drm_device *dev)
+		void __iomem *mmio)
 {
 	int rc, i;
 	enum dpu_hw_blk_type type;
 
-	if (!rm || !cat || !mmio || !dev) {
+	if (!rm || !cat || !mmio) {
 		DPU_ERROR("invalid kms\n");
 		return -EINVAL;
 	}
@@ -243,8 +242,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 	for (type = 0; type < DPU_HW_BLK_MAX; type++)
 		INIT_LIST_HEAD(&rm->hw_blks[type]);
 
-	rm->dev = dev;
-
 	/* Some of the sub-blocks require an mdptop to be created */
 	rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
 	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 0dd3c21..f41fd19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -22,7 +22,6 @@
 
 /**
  * struct dpu_rm - DPU dynamic hardware resource manager
- * @dev: device handle for event logging purposes
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
  * @hw_mdp: hardware object for mdp_top
@@ -30,7 +29,6 @@
  * @rm_lock: resource manager mutex
  */
 struct dpu_rm {
-	struct drm_device *dev;
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
 	struct dpu_hw_mdp *hw_mdp;
 	uint32_t lm_max_width;
@@ -63,13 +61,11 @@ struct dpu_rm_hw_iter {
  * @rm: DPU Resource Manager handle
  * @cat: Pointer to hardware catalog
  * @mmio: mapped register io address of MDP
- * @dev: device handle for event logging purposes
  * @Return: 0 on Success otherwise -ERROR
  */
 int dpu_rm_init(struct dpu_rm *rm,
 		struct dpu_mdss_cfg *cat,
-		void __iomem *mmio,
-		struct drm_device *dev);
+		void __iomem *mmio);
 
 /**
  * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
-- 
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[PATCH 04/25] drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration

[Jeykumar Sankaran]

Definition was removed already. Clean up header declaration.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index f41fd19..eb6a6ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -136,12 +136,4 @@ void dpu_rm_init_hw_iter(
  * @Return: true on match found, false on no match found
  */
 bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter);
-
-/**
- * dpu_rm_check_property_topctl - validate property bitmask before it is set
- * @val: user's proposed topology control bitmask
- * @Return: 0 on success or error
- */
-int dpu_rm_check_property_topctl(uint64_t val);
-
 #endif /* __DPU_RM_H__ */
-- 
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[PATCH 05/25] drm/msm/dpu: remove encoder from crtc mixer struct

[Jeykumar Sankaran]

Not actively used. Clean up the crtc mixer struct.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4530d6..4960641 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -461,8 +461,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 			return;
 		}
 
-		mixer->encoder = enc;
-
 		cstate->num_mixers++;
 		DPU_DEBUG("setup mixer %d: lm %d\n",
 				i, mixer->hw_lm->idx - LM_0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 3723b48..75fdd3c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -84,14 +84,12 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
  * @lm_ctl:	CTL Path HW driver context
- * @encoder:	Encoder attached to this lm & ctl
  * @mixer_op_mode:	mixer blending operation mode
  * @flush_mask:	mixer flush mask for ctl, mixer and pipe
  */
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
 	struct dpu_hw_ctl *lm_ctl;
-	struct drm_encoder *encoder;
 	u32 mixer_op_mode;
 	u32 flush_mask;
 };
-- 
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[PATCH 06/25] drm/msm/dpu: clean up redundant hw type

[Jeykumar Sankaran]

struct dpu_hw_blk has hw block type info. Remove duplicate
type tracking in struct dpu_rm_hw_blk.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5ce89b9..377def7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -38,14 +38,12 @@ struct dpu_rm_requirements {
 /**
  * struct dpu_rm_hw_blk - hardware block tracking list member
  * @list:	List head for list of all hardware blocks tracking items
- * @type:	Type of hardware block this structure tracks
  * @id:		Hardware ID number, within it's own space, ie. LM_X
  * @enc_id:	Encoder id to which this blk is binded
  * @hw:		Pointer to the hardware register access object for this block
  */
 struct dpu_rm_hw_blk {
 	struct list_head list;
-	enum dpu_hw_blk_type type;
 	uint32_t id;
 	uint32_t enc_id;
 	struct dpu_hw_blk *hw;
@@ -86,12 +84,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 	i->blk = list_prepare_entry(i->blk, blk_list, list);
 
 	list_for_each_entry_continue(i->blk, blk_list, list) {
-		if (i->blk->type != i->type) {
-			DPU_ERROR("found incorrect block type %d on %d list\n",
-					i->blk->type, i->type);
-			return false;
-		}
-
 		if (i->enc_id == i->blk->enc_id) {
 			i->hw = i->blk->hw;
 			DPU_DEBUG("found type %d id %d for enc %d\n",
@@ -151,7 +143,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
 				list) {
 			list_del(&hw_cur->list);
-			_dpu_rm_hw_destroy(hw_cur->type, hw_cur->hw);
+			_dpu_rm_hw_destroy(type, hw_cur->hw);
 			kfree(hw_cur);
 		}
 	}
@@ -213,7 +205,6 @@ static int _dpu_rm_hw_blk_create(
 		return -ENOMEM;
 	}
 
-	blk->type = type;
 	blk->id = id;
 	blk->hw = hw;
 	blk->enc_id = 0;
@@ -458,7 +449,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		lm[i]->enc_id = enc_id;
 		pp[i]->enc_id = enc_id;
 
-		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, enc_id,
+		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
 					 pp[i]->id);
 	}
 
@@ -510,7 +501,7 @@ static int _dpu_rm_reserve_ctls(
 
 	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
 		ctls[i]->enc_id = enc_id;
-		trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
+		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
 					  enc_id);
 	}
 
@@ -538,7 +529,7 @@ static int _dpu_rm_reserve_intf(
 		}
 
 		iter.blk->enc_id = enc_id;
-		trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
+		trace_dpu_rm_reserve_intf(iter.blk->id, DPU_HW_BLK_INTF,
 					  enc_id);
 		break;
 	}
-- 
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[PATCH 07/25] drm/msm/dpu: reserve using crtc state

[Jeykumar Sankaran]

DPU maintained reservation lists to cache assigned
HW blocks for the display and a retrieval mechanism for
the individual DRM components to query their respective
HW blocks.

This patch uses the sub-classed CRTC state to store
and track HW blocks assigned for different components
of the display pipeline. It helps the driver:
- to get rid of unwanted store and retrieval RM API's
- to preserve HW resources assigned in atomic_check
  through atomic swap/duplicate.

Separate patch is submitted to remove resource
reservation in atomic_commit path.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 65 +++-------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           | 14 +++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 28 +++-------
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 20 ++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 58 ++++++++++++-------
 5 files changed, 72 insertions(+), 113 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4960641..0625f56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -421,69 +421,20 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
 	trace_dpu_crtc_complete_commit(DRMID(crtc));
 }
 
-static void _dpu_crtc_setup_mixer_for_encoder(
-		struct drm_crtc *crtc,
-		struct drm_encoder *enc)
+static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
 {
 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
-	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
-	struct dpu_rm *rm = &dpu_kms->rm;
 	struct dpu_crtc_mixer *mixer;
-	struct dpu_hw_ctl *last_valid_ctl = NULL;
-	int i;
-	struct dpu_rm_hw_iter lm_iter, ctl_iter;
-
-	dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
-	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
+	int i, ctl_index;
 
 	/* Set up all the mixers and ctls reserved by this encoder */
-	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
+	for (i = 0; i < cstate->num_mixers; i++) {
 		mixer = &cstate->mixers[i];
 
-		if (!dpu_rm_get_hw(rm, &lm_iter))
-			break;
-		mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
-
 		/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
-		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
-			DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
-					mixer->hw_lm->idx - LM_0);
-			mixer->lm_ctl = last_valid_ctl;
-		} else {
-			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
-			last_valid_ctl = mixer->lm_ctl;
-		}
-
-		/* Shouldn't happen, mixers are always >= ctls */
-		if (!mixer->lm_ctl) {
-			DPU_ERROR("no valid ctls found for lm %d\n",
-					mixer->hw_lm->idx - LM_0);
-			return;
-		}
-
-		cstate->num_mixers++;
-		DPU_DEBUG("setup mixer %d: lm %d\n",
-				i, mixer->hw_lm->idx - LM_0);
-		DPU_DEBUG("setup mixer %d: ctl %d\n",
-				i, mixer->lm_ctl->idx - CTL_0);
-	}
-}
-
-static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
-{
-	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
-	struct drm_encoder *enc;
-
-	mutex_lock(&dpu_crtc->crtc_lock);
-	/* Check for mixers on all encoders attached to this crtc */
-	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
-		if (enc->crtc != crtc)
-			continue;
-
-		_dpu_crtc_setup_mixer_for_encoder(crtc, enc);
+		ctl_index = min(i, cstate->num_ctls - 1);
+		mixer->lm_ctl = cstate->hw_ctls[ctl_index];
 	}
-
-	mutex_unlock(&dpu_crtc->crtc_lock);
 }
 
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
@@ -536,10 +487,8 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 	dev = crtc->dev;
 	smmu_state = &dpu_crtc->smmu_state;
 
-	if (!cstate->num_mixers) {
-		_dpu_crtc_setup_mixers(crtc);
-		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
-	}
+	_dpu_crtc_setup_mixers(crtc);
+	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
 
 	if (dpu_crtc->event) {
 		WARN_ON(dpu_crtc->event);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 75fdd3c..17aaad7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -84,12 +84,14 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
  * @lm_ctl:	CTL Path HW driver context
+ * @hw_pp:	Pingpong HW driver context
  * @mixer_op_mode:	mixer blending operation mode
  * @flush_mask:	mixer flush mask for ctl, mixer and pipe
  */
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
 	struct dpu_hw_ctl *lm_ctl;
+	struct dpu_hw_pingpong *hw_pp;
 	u32 mixer_op_mode;
 	u32 flush_mask;
 };
@@ -230,6 +232,18 @@ struct dpu_crtc_state {
 
 	u32 num_ctls;
 	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
+
+	/**
+	 * as drm encoders doesn't have dedicates state objects
+	 * and drm connectors are not owned by DPU, maintain
+	 * HW interface and other interface related blocks
+	 * in crtc state
+	 *
+	 * TODO: No support for clone mode yet where a crtc
+	 * can be attached with more than one encoder/connector.
+	 */
+	u32 num_intfs;
+	struct dpu_hw_intf *hw_intfs[CRTC_DUAL_MIXERS];
 };
 
 #define to_dpu_crtc_state(x) \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d12f896..17dbbc3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1001,9 +1001,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 	struct dpu_kms *dpu_kms;
 	struct list_head *connector_list;
 	struct drm_connector *conn = NULL, *conn_iter;
-	struct dpu_rm_hw_iter pp_iter, ctl_iter;
+	struct dpu_crtc_state *dpu_cstate;
 	struct msm_display_topology topology;
-	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 	int i = 0, ret;
 
 	if (!drm_enc) {
@@ -1043,27 +1042,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 		return;
 	}
 
-	dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
-	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
-		dpu_enc->hw_pp[i] = NULL;
-		if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
-			break;
-		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
-	}
-
-	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
-	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
-		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
-			break;
-		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
-	}
+	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
 
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 		int ctl_index;
 
 		if (phys) {
-			if (!dpu_enc->hw_pp[i]) {
+			if (!dpu_cstate->mixers[i].hw_pp) {
 				DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
 					     "at idx: %d\n", i);
 				return;
@@ -1071,14 +1057,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 
 			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
 
-			if (!hw_ctl[ctl_index]) {
+			if (!dpu_cstate->hw_ctls[ctl_index]) {
 				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
 					     "at idx: %d\n", ctl_index);
 				return;
 			}
 
-			phys->hw_pp = dpu_enc->hw_pp[i];
-			phys->hw_ctl = hw_ctl[ctl_index];
+			dpu_enc->hw_pp[i] = dpu_cstate->mixers[i].hw_pp;
+
+			phys->hw_pp = dpu_cstate->mixers[i].hw_pp;
+			phys->hw_ctl = dpu_cstate->hw_ctls[ctl_index];
 
 			phys->connector = conn->state->connector;
 			if (phys->ops.mode_set)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 84de385..4563f8d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -461,28 +461,20 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
 
 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 {
-	struct msm_drm_private *priv;
 	struct dpu_encoder_phys_vid *vid_enc;
-	struct dpu_rm_hw_iter iter;
 	struct dpu_hw_ctl *ctl;
+	struct dpu_crtc_state *dpu_cstate;
+	int i;
 	u32 flush_mask = 0;
 
-	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
-			!phys_enc->parent->dev->dev_private) {
-		DPU_ERROR("invalid encoder/device\n");
-		return;
-	}
-	priv = phys_enc->parent->dev->dev_private;
+	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
 
 	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
 	ctl = phys_enc->hw_ctl;
 
-	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
-	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
-		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
-
-		if (hw_intf->idx == phys_enc->intf_idx) {
-			vid_enc->hw_intf = hw_intf;
+	for (i = 0; i < dpu_cstate->num_intfs; i++) {
+		if (dpu_cstate->hw_intfs[i]->idx == phys_enc->intf_idx) {
+			vid_enc->hw_intf = dpu_cstate->hw_intfs[i];
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 377def7..5703b11 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -388,6 +388,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 }
 
 static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
+			       struct dpu_crtc_state *dpu_cstate,
 			       struct dpu_rm_requirements *reqs)
 
 {
@@ -449,16 +450,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		lm[i]->enc_id = enc_id;
 		pp[i]->enc_id = enc_id;
 
+		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
+		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
+
 		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
 					 pp[i]->id);
 	}
 
+	dpu_cstate->num_mixers = lm_count;
+
 	return rc;
 }
 
 static int _dpu_rm_reserve_ctls(
 		struct dpu_rm *rm,
 		uint32_t enc_id,
+		struct dpu_crtc_state *dpu_cstate,
 		const struct msm_display_topology *top)
 {
 	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
@@ -501,21 +508,24 @@ static int _dpu_rm_reserve_ctls(
 
 	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
 		ctls[i]->enc_id = enc_id;
+		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
+
 		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
 					  enc_id);
 	}
 
+	dpu_cstate->num_ctls = num_ctls;
+
 	return 0;
 }
 
-static int _dpu_rm_reserve_intf(
+static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 		struct dpu_rm *rm,
 		uint32_t enc_id,
 		uint32_t id,
 		enum dpu_hw_blk_type type)
 {
 	struct dpu_rm_hw_iter iter;
-	int ret = 0;
 
 	/* Find the block entry in the rm, and note the reservation */
 	dpu_rm_init_hw_iter(&iter, 0, type);
@@ -525,7 +535,7 @@ static int _dpu_rm_reserve_intf(
 
 		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
 			DPU_ERROR("type %d id %d already reserved\n", type, id);
-			return -ENAVAIL;
+			return NULL;
 		}
 
 		iter.blk->enc_id = enc_id;
@@ -535,56 +545,63 @@ static int _dpu_rm_reserve_intf(
 	}
 
 	/* Shouldn't happen since intfs are fixed at probe */
-	if (!iter.hw) {
+	if (!iter.blk) {
 		DPU_ERROR("couldn't find type %d id %d\n", type, id);
-		return -EINVAL;
+		return NULL;
 	}
 
-	return ret;
+	return iter.blk;
 }
 
 static int _dpu_rm_reserve_intf_related_hw(
 		struct dpu_rm *rm,
 		uint32_t enc_id,
+		struct dpu_crtc_state *dpu_cstate,
 		struct dpu_encoder_hw_resources *hw_res)
 {
-	int i, ret = 0;
-	u32 id;
+	struct dpu_rm_hw_blk *blk;
+	int i, num_intfs = 0;
 
 	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
 		if (hw_res->intfs[i] == INTF_MODE_NONE)
 			continue;
-		id = i + INTF_0;
-		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
+
+		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
 				DPU_HW_BLK_INTF);
-		if (ret)
-			return ret;
+		if (!blk)
+			return -ENAVAIL;
+
+		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
 	}
 
-	return ret;
+	dpu_cstate->num_intfs = num_intfs;
+
+	return 0;
 }
 
 static int _dpu_rm_make_reservation(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
-		struct drm_crtc_state *crtc_state,
+		struct dpu_crtc_state *dpu_cstate,
 		struct dpu_rm_requirements *reqs)
 {
 	int ret;
 
-	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
+	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
+	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
+				   &reqs->topology);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate CTL\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, &reqs->hw_res);
+	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, dpu_cstate,
+					      &reqs->hw_res);
 	if (ret)
 		return ret;
 
@@ -594,7 +611,6 @@ static int _dpu_rm_make_reservation(
 static int _dpu_rm_populate_requirements(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
-		struct drm_crtc_state *crtc_state,
 		struct dpu_rm_requirements *reqs,
 		struct msm_display_topology req_topology)
 {
@@ -642,6 +658,7 @@ int dpu_rm_reserve(
 		bool test_only)
 {
 	struct dpu_rm_requirements reqs;
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 	int ret;
 
 	/* Check if this is just a page-flip */
@@ -653,14 +670,13 @@ int dpu_rm_reserve(
 
 	mutex_lock(&rm->rm_lock);
 
-	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
-					    topology);
+	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
 	if (ret) {
 		DPU_ERROR("failed to populate hw requirements\n");
 		goto end;
 	}
 
-	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
+	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
 		_dpu_rm_release_reservation(rm, enc->base.id);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

[PATCH 08/25] drm/msm/dpu: release reservation using crtc state

[Jeykumar Sankaran]

Use the hw block pointers stored in crtc state to
release them back to RM resource pool. This change
is made to uncouple RM reservation from encoder_id.
Separate change is submitted to clean up RM of
encoder id tagging.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69 +++++++++++++++++++++++------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      |  6 +--
 3 files changed, 60 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 17dbbc3..a8fd14e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1223,7 +1223,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
 
 	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
 
-	dpu_rm_release(&dpu_kms->rm, drm_enc);
+	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);
 }
 
 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5703b11..619b596 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -625,27 +625,70 @@ static int _dpu_rm_populate_requirements(
 	return 0;
 }
 
-static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
+static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
+			      int id)
 {
 	struct dpu_rm_hw_blk *blk;
-	enum dpu_hw_blk_type type;
 
-	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
-		list_for_each_entry(blk, &rm->hw_blks[type], list) {
-			if (blk->enc_id == enc_id) {
-				blk->enc_id = 0;
-				DPU_DEBUG("rel enc %d %d %d\n", enc_id,
-					  blk->type, blk->id);
-			}
+	list_for_each_entry(blk, &rm->hw_blks[type], list) {
+		if (blk->hw->id == id) {
+			blk->enc_id = 0;
+			return 0;
 		}
 	}
+
+	DRM_DEBUG_KMS("failed to find hw id(%d) of type(%d) for releasing\n",
+		      id, type);
+
+	return -EINVAL;
 }
 
-void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc)
+static void _dpu_rm_release_reservation(struct dpu_rm *rm,
+					struct dpu_crtc_state *dpu_cstate)
 {
+	int i;
+
+	for (i = 0; i < dpu_cstate->num_mixers; i++) {
+		struct dpu_crtc_mixer *mixer = &dpu_cstate->mixers[i];
+
+		if (!mixer->hw_lm)
+			continue;
+
+		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_LM,
+					mixer->hw_lm->base.id))
+			mixer->hw_lm = NULL;
+
+		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_PINGPONG,
+					mixer->hw_pp->base.id))
+			mixer->hw_pp = NULL;
+	}
+
+	for (i = 0; i < dpu_cstate->num_ctls; i++) {
+		if (!dpu_cstate->hw_ctls[i])
+			continue;
+
+		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_CTL,
+					dpu_cstate->hw_ctls[i]->base.id))
+			dpu_cstate->hw_ctls[i] = NULL;
+	}
+
+	for (i = 0; i < dpu_cstate->num_intfs; i++) {
+		if (!dpu_cstate->hw_intfs[i])
+			continue;
+
+		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_INTF,
+					dpu_cstate->hw_intfs[i]->base.id))
+			dpu_cstate->hw_intfs[i] = NULL;
+	}
+}
+
+void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
+{
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+
 	mutex_lock(&rm->rm_lock);
 
-	_dpu_rm_release_reservation(rm, enc->base.id);
+	_dpu_rm_release_reservation(rm, dpu_cstate);
 
 	mutex_unlock(&rm->rm_lock);
 }
@@ -679,12 +722,12 @@ int dpu_rm_reserve(
 	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
-		_dpu_rm_release_reservation(rm, enc->base.id);
+		_dpu_rm_release_reservation(rm, dpu_cstate);
 	} else if (test_only) {
 		 /* test_only: test the reservation and then undo */
 		DPU_DEBUG("test_only: discard test [enc: %d]\n",
 				enc->base.id);
-		_dpu_rm_release_reservation(rm, enc->base.id);
+		_dpu_rm_release_reservation(rm, dpu_cstate);
 	}
 
 end:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index eb6a6ac..e48e8f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -95,13 +95,13 @@ int dpu_rm_reserve(struct dpu_rm *rm,
 		bool test_only);
 
 /**
- * dpu_rm_reserve - Given the encoder for the display chain, release any
+ * dpu_rm_release - Given the encoder for the display chain, release any
  *	HW blocks previously reserved for that use case.
  * @rm: DPU Resource Manager handle
- * @enc: DRM Encoder handle
+ * @crtc_state: atomic DRM state handle
  * @Return: 0 on Success otherwise -ERROR
  */
-void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc);
+void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
 
 /**
  * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 09/25] drm/msm/dpu: make RM iterator static

[Jeykumar Sankaran]

HW blocks reserved for a display are stored in crtc state.
No one outside RM is interested in using these API's for
HW block list iterations.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 37 ++++++++++++++-------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 46 ----------------------------------
 2 files changed, 20 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 619b596..24fc1c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -49,12 +49,26 @@ struct dpu_rm_hw_blk {
 	struct dpu_hw_blk *hw;
 };
 
+/**
+ * struct dpu_rm_hw_iter - iterator for use with dpu_rm
+ * @hw: dpu_hw object requested, or NULL on failure
+ * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
+ * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
+ * @type: Hardware Block Type client wishes to search for.
+ */
+struct dpu_rm_hw_iter {
+	void *hw;
+	struct dpu_rm_hw_blk *blk;
+	uint32_t enc_id;
+	enum dpu_hw_blk_type type;
+};
+
 struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
 {
 	return rm->hw_mdp;
 }
 
-void dpu_rm_init_hw_iter(
+static void _dpu_rm_init_hw_iter(
 		struct dpu_rm_hw_iter *iter,
 		uint32_t enc_id,
 		enum dpu_hw_blk_type type)
@@ -97,17 +111,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 	return false;
 }
 
-bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
-{
-	bool ret;
-
-	mutex_lock(&rm->rm_lock);
-	ret = _dpu_rm_get_hw_locked(rm, i);
-	mutex_unlock(&rm->rm_lock);
-
-	return ret;
-}
-
 static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
 {
 	switch (type) {
@@ -365,7 +368,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
+	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		if (iter.blk->id == lm_cfg->pingpong) {
 			*pp = iter.blk;
@@ -404,7 +407,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 	}
 
 	/* Find a primary mixer */
-	dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
+	_dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
 	while (lm_count != reqs->topology.num_lm &&
 			_dpu_rm_get_hw_locked(rm, &iter_i)) {
 		memset(&lm, 0, sizeof(lm));
@@ -421,7 +424,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		++lm_count;
 
 		/* Valid primary mixer found, find matching peers */
-		dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
+		_dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
 
 		while (lm_count != reqs->topology.num_lm &&
 				_dpu_rm_get_hw_locked(rm, &iter_j)) {
@@ -480,7 +483,7 @@ static int _dpu_rm_reserve_ctls(
 
 	needs_split_display = _dpu_rm_needs_split_display(top);
 
-	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
+	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
 		unsigned long features = ctl->caps->features;
@@ -528,7 +531,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 	struct dpu_rm_hw_iter iter;
 
 	/* Find the block entry in the rm, and note the reservation */
-	dpu_rm_init_hw_iter(&iter, 0, type);
+	_dpu_rm_init_hw_iter(&iter, 0, type);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		if (iter.blk->id != id)
 			continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index e48e8f2..c7e3b2b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -36,26 +36,6 @@ struct dpu_rm {
 };
 
 /**
- *  struct dpu_rm_hw_blk - resource manager internal structure
- *	forward declaration for single iterator definition without void pointer
- */
-struct dpu_rm_hw_blk;
-
-/**
- * struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @hw: dpu_hw object requested, or NULL on failure
- * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
- * @type: Hardware Block Type client wishes to search for.
- */
-struct dpu_rm_hw_iter {
-	void *hw;
-	struct dpu_rm_hw_blk *blk;
-	uint32_t enc_id;
-	enum dpu_hw_blk_type type;
-};
-
-/**
  * dpu_rm_init - Read hardware catalog and create reservation tracking objects
  *	for all HW blocks.
  * @rm: DPU Resource Manager handle
@@ -110,30 +90,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
  * @Return: Pointer to hw block or NULL
  */
 struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
-
-/**
- * dpu_rm_init_hw_iter - setup given iterator for new iteration over hw list
- *	using dpu_rm_get_hw
- * @iter: iter object to initialize
- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
- * @type: Hardware Block Type client wishes to search for.
- */
-void dpu_rm_init_hw_iter(
-		struct dpu_rm_hw_iter *iter,
-		uint32_t enc_id,
-		enum dpu_hw_blk_type type);
-/**
- * dpu_rm_get_hw - retrieve reserved hw object given encoder and hw type
- *	Meant to do a single pass through the hardware list to iteratively
- *	retrieve hardware blocks of a given type for a given encoder.
- *	Initialize an iterator object.
- *	Set hw block type of interest. Set encoder id of interest, 0 for any.
- *	Function returns first hw of type for that encoder.
- *	Subsequent calls will return the next reserved hw of that type in-order.
- *	Iterator HW pointer will be null on failure to find hw.
- * @rm: DPU Resource Manager handle
- * @iter: iterator object
- * @Return: true on match found, false on no match found
- */
-bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter);
 #endif /* __DPU_RM_H__ */
-- 
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a Linux Foundation Collaborative Project

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[PATCH 10/25] drm/msm/dpu: maintain hw_mdp in kms

[Jeykumar Sankaran]

hw_mdp block is common for displays. No need
to reserve per display.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  7 ++++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 20 --------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  | 10 ----------
 3 files changed, 6 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8309850..fdc89a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -689,6 +689,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
 	dpu_kms->vbif[VBIF_RT] = NULL;
 
+	if (dpu_kms->hw_mdp)
+		dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
+	dpu_kms->hw_mdp = NULL;
+
 	if (dpu_kms->mmio)
 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
 	dpu_kms->mmio = NULL;
@@ -1083,7 +1087,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 
 	dpu_kms->rm_init = true;
 
-	dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_kms->rm);
+	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
+					     dpu_kms->catalog);
 	if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {
 		rc = PTR_ERR(dpu_kms->hw_mdp);
 		if (!dpu_kms->hw_mdp)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 24fc1c7..561120d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -63,11 +63,6 @@ struct dpu_rm_hw_iter {
 	enum dpu_hw_blk_type type;
 };
 
-struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
-{
-	return rm->hw_mdp;
-}
-
 static void _dpu_rm_init_hw_iter(
 		struct dpu_rm_hw_iter *iter,
 		uint32_t enc_id,
@@ -151,9 +146,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 		}
 	}
 
-	dpu_hw_mdp_destroy(rm->hw_mdp);
-	rm->hw_mdp = NULL;
-
 	mutex_destroy(&rm->rm_lock);
 
 	return 0;
@@ -168,11 +160,8 @@ static int _dpu_rm_hw_blk_create(
 		void *hw_catalog_info)
 {
 	struct dpu_rm_hw_blk *blk;
-	struct dpu_hw_mdp *hw_mdp;
 	void *hw;
 
-	hw_mdp = rm->hw_mdp;
-
 	switch (type) {
 	case DPU_HW_BLK_LM:
 		hw = dpu_hw_lm_init(id, mmio, cat);
@@ -236,15 +225,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 	for (type = 0; type < DPU_HW_BLK_MAX; type++)
 		INIT_LIST_HEAD(&rm->hw_blks[type]);
 
-	/* Some of the sub-blocks require an mdptop to be created */
-	rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
-	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
-		rc = PTR_ERR(rm->hw_mdp);
-		rm->hw_mdp = NULL;
-		DPU_ERROR("failed: mdp hw not available\n");
-		goto fail;
-	}
-
 	/* Interrogate HW catalog and create tracking items for hw blocks */
 	for (i = 0; i < cat->mixer_count; i++) {
 		struct dpu_lm_cfg *lm = &cat->mixer[i];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index c7e3b2b..7ac1553 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,13 +24,11 @@
  * struct dpu_rm - DPU dynamic hardware resource manager
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
- * @hw_mdp: hardware object for mdp_top
  * @lm_max_width: cached layer mixer maximum width
  * @rm_lock: resource manager mutex
  */
 struct dpu_rm {
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
-	struct dpu_hw_mdp *hw_mdp;
 	uint32_t lm_max_width;
 	struct mutex rm_lock;
 };
@@ -82,12 +80,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
  * @Return: 0 on Success otherwise -ERROR
  */
 void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
-
-/**
- * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
- *	This is never reserved, and is usable by any display.
- * @rm: DPU Resource Manager handle
- * @Return: Pointer to hw block or NULL
- */
-struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
 #endif /* __DPU_RM_H__ */
-- 
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[PATCH 11/25] drm/msm/dpu: remove reserve in encoder mode_set

[Jeykumar Sankaran]

Now that we have crtc state tracking the reserved
HW resources, we have access to them after atomic swap.
So avoid reserving the resources in mode_set.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 ++---------------
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a8fd14e..dd482ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -636,7 +636,6 @@ static int dpu_encoder_virt_atomic_check(
 
 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 
-	/* Reserve dynamic resources now. Indicating AtomicTest phase */
 	if (!ret) {
 		/*
 		 * Avoid reserving resources when mode set is pending. Topology
@@ -645,7 +644,7 @@ static int dpu_encoder_virt_atomic_check(
 		if (drm_atomic_crtc_needs_modeset(crtc_state)
 				&& dpu_enc->mode_set_complete) {
 			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-					     topology, true);
+					     topology, false);
 			dpu_enc->mode_set_complete = false;
 		}
 	}
@@ -1002,8 +1001,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 	struct list_head *connector_list;
 	struct drm_connector *conn = NULL, *conn_iter;
 	struct dpu_crtc_state *dpu_cstate;
-	struct msm_display_topology topology;
-	int i = 0, ret;
+	int i = 0;
 
 	if (!drm_enc) {
 		DPU_ERROR("invalid encoder\n");
@@ -1031,17 +1029,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 		return;
 	}
 
-	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
-
-	/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
-	ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state,
-			     topology, false);
-	if (ret) {
-		DPU_ERROR_ENC(dpu_enc,
-				"failed to reserve hw resources, %d\n", ret);
-		return;
-	}
-
 	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
 
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-- 
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[PATCH 12/25] drm/msm/dpu: remove mode_set_complete

[Jeykumar Sankaran]

This flag was introduced as a fix to notify modeset complete
when hw reservations were happening in both atomic_check
and atomic_commit paths. Now that we are reserving only in
atomic_check, we can get rid of this flag.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd482ca..468b8fd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -167,7 +167,6 @@ enum dpu_enc_rc_states {
  *				clks and resources after IDLE_TIMEOUT time.
  * @vsync_event_work:		worker to handle vsync event for autorefresh
  * @topology:                   topology of the display
- * @mode_set_complete:          flag to indicate modeset completion
  * @idle_timeout:		idle timeout duration in milliseconds
  */
 struct dpu_encoder_virt {
@@ -204,7 +203,6 @@ struct dpu_encoder_virt {
 	struct kthread_delayed_work delayed_off_work;
 	struct kthread_work vsync_event_work;
 	struct msm_display_topology topology;
-	bool mode_set_complete;
 
 	u32 idle_timeout;
 };
@@ -636,18 +634,9 @@ static int dpu_encoder_virt_atomic_check(
 
 	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 
-	if (!ret) {
-		/*
-		 * Avoid reserving resources when mode set is pending. Topology
-		 * info may not be available to complete reservation.
-		 */
-		if (drm_atomic_crtc_needs_modeset(crtc_state)
-				&& dpu_enc->mode_set_complete) {
-			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-					     topology, false);
-			dpu_enc->mode_set_complete = false;
-		}
-	}
+	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
+		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
+				     topology, false);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
@@ -1060,8 +1049,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 				phys->ops.mode_set(phys, mode, adj_mode);
 		}
 	}
-
-	dpu_enc->mode_set_complete = true;
 }
 
 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
-- 
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[PATCH 13/25] drm/msm/dpu: make RM iterator hw type specific

[Jeykumar Sankaran]

Usage of hw block iterators are only RM internal. Instead
of using generic void pointers for HW blocks, use dpu
specific structure. It helps us to get rid of duplicate
hw block id's maintained in RM wrapper.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 561120d..303f1b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -38,13 +38,11 @@ struct dpu_rm_requirements {
 /**
  * struct dpu_rm_hw_blk - hardware block tracking list member
  * @list:	List head for list of all hardware blocks tracking items
- * @id:		Hardware ID number, within it's own space, ie. LM_X
  * @enc_id:	Encoder id to which this blk is binded
  * @hw:		Pointer to the hardware register access object for this block
  */
 struct dpu_rm_hw_blk {
 	struct list_head list;
-	uint32_t id;
 	uint32_t enc_id;
 	struct dpu_hw_blk *hw;
 };
@@ -57,7 +55,7 @@ struct dpu_rm_hw_blk {
  * @type: Hardware Block Type client wishes to search for.
  */
 struct dpu_rm_hw_iter {
-	void *hw;
+	struct dpu_hw_blk *hw;
 	struct dpu_rm_hw_blk *blk;
 	uint32_t enc_id;
 	enum dpu_hw_blk_type type;
@@ -96,7 +94,7 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 		if (i->enc_id == i->blk->enc_id) {
 			i->hw = i->blk->hw;
 			DPU_DEBUG("found type %d id %d for enc %d\n",
-					i->type, i->blk->id, i->enc_id);
+					i->type, i->blk->hw->id, i->enc_id);
 			return true;
 		}
 	}
@@ -197,7 +195,6 @@ static int _dpu_rm_hw_blk_create(
 		return -ENOMEM;
 	}
 
-	blk->id = id;
 	blk->hw = hw;
 	blk->enc_id = 0;
 	list_add_tail(&blk->list, &rm->hw_blks[type]);
@@ -350,7 +347,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 
 	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		if (iter.blk->id == lm_cfg->pingpong) {
+		if (iter.blk->hw->id == lm_cfg->pingpong) {
 			*pp = iter.blk;
 			break;
 		}
@@ -362,8 +359,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 	}
 
 	if (RESERVED_BY_OTHER(*pp, enc_id)) {
-		DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
-				(*pp)->id);
+		DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
+				(*pp)->hw->id);
 		return false;
 	}
 
@@ -436,8 +433,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
 		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
 
-		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
-					 pp[i]->id);
+		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM, enc_id,
+					 pp[i]->hw->id);
 	}
 
 	dpu_cstate->num_mixers = lm_count;
@@ -474,13 +471,13 @@ static int _dpu_rm_reserve_ctls(
 
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
 
-		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
+		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
 
 		if (needs_split_display != has_split_display)
 			continue;
 
 		ctls[i] = iter.blk;
-		DPU_DEBUG("ctl %d match\n", iter.blk->id);
+		DPU_DEBUG("ctl %d match\n", iter.blk->hw->id);
 
 		if (++i == num_ctls)
 			break;
@@ -493,7 +490,7 @@ static int _dpu_rm_reserve_ctls(
 		ctls[i]->enc_id = enc_id;
 		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
 
-		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
+		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
 					  enc_id);
 	}
 
@@ -513,7 +510,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 	/* Find the block entry in the rm, and note the reservation */
 	_dpu_rm_init_hw_iter(&iter, 0, type);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		if (iter.blk->id != id)
+		if (iter.blk->hw->id != id)
 			continue;
 
 		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
@@ -522,7 +519,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 		}
 
 		iter.blk->enc_id = enc_id;
-		trace_dpu_rm_reserve_intf(iter.blk->id, DPU_HW_BLK_INTF,
+		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF,
 					  enc_id);
 		break;
 	}
-- 
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a Linux Foundation Collaborative Project

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[PATCH 14/25] drm/msm/dpu: remove enc_id tagging for hw blocks

[Jeykumar Sankaran]

RM was using encoder id's to tag HW block's to reserve
and retrieve later for display pipeline. Now
that all the reserved HW blocks for a display are
maintained in its crtc state, no retrieval is needed.
This patch cleans up RM of encoder id tagging.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c    | 90 +++++++++----------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 28 ++++------
 2 files changed, 36 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 303f1b3..a8461b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -21,9 +21,6 @@
 #include "dpu_encoder.h"
 #include "dpu_trace.h"
 
-#define RESERVED_BY_OTHER(h, r)  \
-		((h)->enc_id && (h)->enc_id != r)
-
 /**
  * struct dpu_rm_requirements - Reservation requirements parameter bundle
  * @topology:  selected topology for the display
@@ -38,12 +35,13 @@ struct dpu_rm_requirements {
 /**
  * struct dpu_rm_hw_blk - hardware block tracking list member
  * @list:	List head for list of all hardware blocks tracking items
- * @enc_id:	Encoder id to which this blk is binded
+ * @in_use:     True, if the hw block is assigned to a display pipeline.
+ *		False, otherwise
  * @hw:		Pointer to the hardware register access object for this block
  */
 struct dpu_rm_hw_blk {
 	struct list_head list;
-	uint32_t enc_id;
+	bool in_use;
 	struct dpu_hw_blk *hw;
 };
 
@@ -51,23 +49,19 @@ struct dpu_rm_hw_blk {
  * struct dpu_rm_hw_iter - iterator for use with dpu_rm
  * @hw: dpu_hw object requested, or NULL on failure
  * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
- * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
  * @type: Hardware Block Type client wishes to search for.
  */
 struct dpu_rm_hw_iter {
 	struct dpu_hw_blk *hw;
 	struct dpu_rm_hw_blk *blk;
-	uint32_t enc_id;
 	enum dpu_hw_blk_type type;
 };
 
 static void _dpu_rm_init_hw_iter(
 		struct dpu_rm_hw_iter *iter,
-		uint32_t enc_id,
 		enum dpu_hw_blk_type type)
 {
 	memset(iter, 0, sizeof(*iter));
-	iter->enc_id = enc_id;
 	iter->type = type;
 }
 
@@ -91,16 +85,12 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 	i->blk = list_prepare_entry(i->blk, blk_list, list);
 
 	list_for_each_entry_continue(i->blk, blk_list, list) {
-		if (i->enc_id == i->blk->enc_id) {
+		if (!i->blk->in_use) {
 			i->hw = i->blk->hw;
-			DPU_DEBUG("found type %d id %d for enc %d\n",
-					i->type, i->blk->hw->id, i->enc_id);
 			return true;
 		}
 	}
 
-	DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
-
 	return false;
 }
 
@@ -196,7 +186,6 @@ static int _dpu_rm_hw_blk_create(
 	}
 
 	blk->hw = hw;
-	blk->enc_id = 0;
 	list_add_tail(&blk->list, &rm->hw_blks[type]);
 
 	return 0;
@@ -301,7 +290,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  *	proposed use case requirements, incl. hardwired dependent blocks like
  *	pingpong
  * @rm: dpu resource manager handle
- * @enc_id: encoder id requesting for allocation
  * @reqs: proposed use case requirements
  * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  *      blocks connected to the lm (pp) is available and appropriate
@@ -313,7 +301,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  */
 static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm *rm,
-		uint32_t enc_id,
 		struct dpu_rm_requirements *reqs,
 		struct dpu_rm_hw_blk *lm,
 		struct dpu_rm_hw_blk **pp,
@@ -339,13 +326,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		}
 	}
 
-	/* Already reserved? */
-	if (RESERVED_BY_OTHER(lm, enc_id)) {
-		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
-		return false;
-	}
-
-	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
+	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_PINGPONG);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		if (iter.blk->hw->id == lm_cfg->pingpong) {
 			*pp = iter.blk;
@@ -358,16 +339,10 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	if (RESERVED_BY_OTHER(*pp, enc_id)) {
-		DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
-				(*pp)->hw->id);
-		return false;
-	}
-
 	return true;
 }
 
-static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
+static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 			       struct dpu_crtc_state *dpu_cstate,
 			       struct dpu_rm_requirements *reqs)
 
@@ -384,7 +359,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 	}
 
 	/* Find a primary mixer */
-	_dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
+	_dpu_rm_init_hw_iter(&iter_i, DPU_HW_BLK_LM);
 	while (lm_count != reqs->topology.num_lm &&
 			_dpu_rm_get_hw_locked(rm, &iter_i)) {
 		memset(&lm, 0, sizeof(lm));
@@ -394,14 +369,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		lm[lm_count] = iter_i.blk;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, enc_id, reqs, lm[lm_count],
+				rm, reqs, lm[lm_count],
 				&pp[lm_count], NULL))
 			continue;
 
 		++lm_count;
 
 		/* Valid primary mixer found, find matching peers */
-		_dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
+		_dpu_rm_init_hw_iter(&iter_j, DPU_HW_BLK_LM);
 
 		while (lm_count != reqs->topology.num_lm &&
 				_dpu_rm_get_hw_locked(rm, &iter_j)) {
@@ -409,7 +384,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 				continue;
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, enc_id, reqs, iter_j.blk,
+					rm, reqs, iter_j.blk,
 					&pp[lm_count], iter_i.blk))
 				continue;
 
@@ -427,13 +402,13 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 		if (!lm[i])
 			break;
 
-		lm[i]->enc_id = enc_id;
-		pp[i]->enc_id = enc_id;
+		lm[i]->in_use = true;
+		pp[i]->in_use = true;
 
 		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
 		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
 
-		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM, enc_id,
+		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM,
 					 pp[i]->hw->id);
 	}
 
@@ -444,7 +419,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
 
 static int _dpu_rm_reserve_ctls(
 		struct dpu_rm *rm,
-		uint32_t enc_id,
 		struct dpu_crtc_state *dpu_cstate,
 		const struct msm_display_topology *top)
 {
@@ -460,15 +434,12 @@ static int _dpu_rm_reserve_ctls(
 
 	needs_split_display = _dpu_rm_needs_split_display(top);
 
-	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
+	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_CTL);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
 		unsigned long features = ctl->caps->features;
 		bool has_split_display;
 
-		if (RESERVED_BY_OTHER(iter.blk, enc_id))
-			continue;
-
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
 
 		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
@@ -487,11 +458,10 @@ static int _dpu_rm_reserve_ctls(
 		return -ENAVAIL;
 
 	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
-		ctls[i]->enc_id = enc_id;
+		ctls[i]->in_use = true;
 		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
 
-		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
-					  enc_id);
+		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL);
 	}
 
 	dpu_cstate->num_ctls = num_ctls;
@@ -501,26 +471,19 @@ static int _dpu_rm_reserve_ctls(
 
 static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 		struct dpu_rm *rm,
-		uint32_t enc_id,
 		uint32_t id,
 		enum dpu_hw_blk_type type)
 {
 	struct dpu_rm_hw_iter iter;
 
 	/* Find the block entry in the rm, and note the reservation */
-	_dpu_rm_init_hw_iter(&iter, 0, type);
+	_dpu_rm_init_hw_iter(&iter, type);
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		if (iter.blk->hw->id != id)
 			continue;
 
-		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
-			DPU_ERROR("type %d id %d already reserved\n", type, id);
-			return NULL;
-		}
+		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF);
 
-		iter.blk->enc_id = enc_id;
-		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF,
-					  enc_id);
 		break;
 	}
 
@@ -535,7 +498,6 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 
 static int _dpu_rm_reserve_intf_related_hw(
 		struct dpu_rm *rm,
-		uint32_t enc_id,
 		struct dpu_crtc_state *dpu_cstate,
 		struct dpu_encoder_hw_resources *hw_res)
 {
@@ -546,11 +508,12 @@ static int _dpu_rm_reserve_intf_related_hw(
 		if (hw_res->intfs[i] == INTF_MODE_NONE)
 			continue;
 
-		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
+		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
 				DPU_HW_BLK_INTF);
 		if (!blk)
 			return -ENAVAIL;
 
+		blk->in_use = true;
 		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
 	}
 
@@ -561,27 +524,24 @@ static int _dpu_rm_reserve_intf_related_hw(
 
 static int _dpu_rm_make_reservation(
 		struct dpu_rm *rm,
-		struct drm_encoder *enc,
 		struct dpu_crtc_state *dpu_cstate,
 		struct dpu_rm_requirements *reqs)
 {
 	int ret;
 
-	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
+	ret = _dpu_rm_reserve_lms(rm, dpu_cstate, reqs);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
-				   &reqs->topology);
+	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate, &reqs->topology);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate CTL\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, dpu_cstate,
-					      &reqs->hw_res);
+	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate, &reqs->hw_res);
 	if (ret)
 		return ret;
 
@@ -612,7 +572,7 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
 
 	list_for_each_entry(blk, &rm->hw_blks[type], list) {
 		if (blk->hw->id == id) {
-			blk->enc_id = 0;
+			blk->in_use = false;
 			return 0;
 		}
 	}
@@ -699,7 +659,7 @@ int dpu_rm_reserve(
 		goto end;
 	}
 
-	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
+	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
 		_dpu_rm_release_reservation(rm, dpu_cstate);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 636b31b..3061978 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -869,48 +869,42 @@
 );
 
 DECLARE_EVENT_CLASS(dpu_rm_iter_template,
-	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
-	TP_ARGS(id, type, enc_id),
+	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
+	TP_ARGS(id, type),
 	TP_STRUCT__entry(
 		__field(	uint32_t,		id	)
 		__field(	enum dpu_hw_blk_type,	type	)
-		__field(	uint32_t,		enc_id	)
 	),
 	TP_fast_assign(
 		__entry->id = id;
 		__entry->type = type;
-		__entry->enc_id = enc_id;
 	),
-	TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
-		  __entry->enc_id)
+	TP_printk("id:%d type:%d ", __entry->id, __entry->type)
 );
 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
-	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
-	TP_ARGS(id, type, enc_id)
+	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
+	TP_ARGS(id, type)
 );
 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
-	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
-	TP_ARGS(id, type, enc_id)
+	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
+	TP_ARGS(id, type)
 );
 
 TRACE_EVENT(dpu_rm_reserve_lms,
-	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id,
-		 uint32_t pp_id),
-	TP_ARGS(id, type, enc_id, pp_id),
+	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t pp_id),
+	TP_ARGS(id, type, pp_id),
 	TP_STRUCT__entry(
 		__field(	uint32_t,		id	)
 		__field(	enum dpu_hw_blk_type,	type	)
-		__field(	uint32_t,		enc_id	)
 		__field(	uint32_t,		pp_id	)
 	),
 	TP_fast_assign(
 		__entry->id = id;
 		__entry->type = type;
-		__entry->enc_id = enc_id;
 		__entry->pp_id = pp_id;
 	),
-	TP_printk("id:%d type:%d enc_id:%u pp_id:%u", __entry->id,
-		  __entry->type, __entry->enc_id, __entry->pp_id)
+	TP_printk("id:%d type:%d pp_id:%u", __entry->id,
+		  __entry->type, __entry->pp_id)
 );
 
 TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 15/25] drm/msm/dpu: avoid redundant hw blk reference

[Jeykumar Sankaran]

Get rid of hw block pointer in RM iter as we can
access the same through dpu_hw_blk.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index a8461b8..3a92a3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -47,12 +47,10 @@ struct dpu_rm_hw_blk {
 
 /**
  * struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @hw: dpu_hw object requested, or NULL on failure
  * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
  * @type: Hardware Block Type client wishes to search for.
  */
 struct dpu_rm_hw_iter {
-	struct dpu_hw_blk *hw;
 	struct dpu_rm_hw_blk *blk;
 	enum dpu_hw_blk_type type;
 };
@@ -74,7 +72,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 		return false;
 	}
 
-	i->hw = NULL;
 	blk_list = &rm->hw_blks[i->type];
 
 	if (i->blk && (&i->blk->list == blk_list)) {
@@ -84,12 +81,9 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
 
 	i->blk = list_prepare_entry(i->blk, blk_list, list);
 
-	list_for_each_entry_continue(i->blk, blk_list, list) {
-		if (!i->blk->in_use) {
-			i->hw = i->blk->hw;
+	list_for_each_entry_continue(i->blk, blk_list, list)
+		if (!i->blk->in_use)
 			return true;
-		}
-	}
 
 	return false;
 }
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 16/25] drm/msm/dpu: clean up test_only flag for RM reservation

[Jeykumar Sankaran]

Encoder uses test_only flag to differentiate RM reservations
invoked from atomic check and atomic_commit phases.
After reserving the HW blocks, if test_only was set, RM
releases the reservation. Retains them if not. Since we
got rid of RM reserve call from atomic_commit path, get rid
of this flag.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 13 +++----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      |  4 +---
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 468b8fd0..dd17528 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -636,7 +636,7 @@ static int dpu_encoder_virt_atomic_check(
 
 	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
 		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-				     topology, false);
+				     topology);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 3a92a3e..1234991 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -631,8 +631,7 @@ int dpu_rm_reserve(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
 		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology,
-		bool test_only)
+		struct msm_display_topology topology)
 {
 	struct dpu_rm_requirements reqs;
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
@@ -642,8 +641,8 @@ int dpu_rm_reserve(
 	if (!drm_atomic_crtc_needs_modeset(crtc_state))
 		return 0;
 
-	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d test_only %d\n",
-		      enc->base.id, crtc_state->crtc->base.id, test_only);
+	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
+		      enc->base.id, crtc_state->crtc->base.id);
 
 	mutex_lock(&rm->rm_lock);
 
@@ -657,13 +656,7 @@ int dpu_rm_reserve(
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
 		_dpu_rm_release_reservation(rm, dpu_cstate);
-	} else if (test_only) {
-		 /* test_only: test the reservation and then undo */
-		DPU_DEBUG("test_only: discard test [enc: %d]\n",
-				enc->base.id);
-		_dpu_rm_release_reservation(rm, dpu_cstate);
 	}
-
 end:
 	mutex_unlock(&rm->rm_lock);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 7ac1553..415eeec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -63,14 +63,12 @@ int dpu_rm_init(struct dpu_rm *rm,
  * @drm_enc: DRM Encoder handle
  * @crtc_state: Proposed Atomic DRM CRTC State handle
  * @topology: Pointer to topology info for the display
- * @test_only: Atomic-Test phase, discard results (unless property overrides)
  * @Return: 0 on Success otherwise -ERROR
  */
 int dpu_rm_reserve(struct dpu_rm *rm,
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology,
-		bool test_only);
+		struct msm_display_topology topology);
 
 /**
  * dpu_rm_release - Given the encoder for the display chain, release any
-- 
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[PATCH 17/25] drm/msm/dpu: remove RM HW block list iterator

[Jeykumar Sankaran]

Replacing with simpler linked list helper iterators.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 120 +++++++++++++--------------------
 1 file changed, 46 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 1234991..a79456c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -45,49 +45,6 @@ struct dpu_rm_hw_blk {
 	struct dpu_hw_blk *hw;
 };
 
-/**
- * struct dpu_rm_hw_iter - iterator for use with dpu_rm
- * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
- * @type: Hardware Block Type client wishes to search for.
- */
-struct dpu_rm_hw_iter {
-	struct dpu_rm_hw_blk *blk;
-	enum dpu_hw_blk_type type;
-};
-
-static void _dpu_rm_init_hw_iter(
-		struct dpu_rm_hw_iter *iter,
-		enum dpu_hw_blk_type type)
-{
-	memset(iter, 0, sizeof(*iter));
-	iter->type = type;
-}
-
-static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
-{
-	struct list_head *blk_list;
-
-	if (!rm || !i || i->type >= DPU_HW_BLK_MAX) {
-		DPU_ERROR("invalid rm\n");
-		return false;
-	}
-
-	blk_list = &rm->hw_blks[i->type];
-
-	if (i->blk && (&i->blk->list == blk_list)) {
-		DPU_DEBUG("attempt resume iteration past last\n");
-		return false;
-	}
-
-	i->blk = list_prepare_entry(i->blk, blk_list, list);
-
-	list_for_each_entry_continue(i->blk, blk_list, list)
-		if (!i->blk->in_use)
-			return true;
-
-	return false;
-}
-
 static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
 {
 	switch (type) {
@@ -301,7 +258,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm_hw_blk *primary_lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
-	struct dpu_rm_hw_iter iter;
+	struct dpu_rm_hw_blk *iter;
+	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_PINGPONG];
 
 	*pp = NULL;
 
@@ -320,10 +278,12 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		}
 	}
 
-	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_PINGPONG);
-	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		if (iter.blk->hw->id == lm_cfg->pingpong) {
-			*pp = iter.blk;
+	list_for_each_entry(iter, blk_list, list) {
+		if (iter->in_use)
+			continue;
+
+		if (iter->hw->id == lm_cfg->pingpong) {
+			*pp = iter;
 			break;
 		}
 	}
@@ -343,7 +303,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 {
 	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
-	struct dpu_rm_hw_iter iter_i, iter_j;
+	struct dpu_rm_hw_blk *iter_i, *iter_j;
+	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_LM];
 	int lm_count = 0;
 	int i, rc = 0;
 
@@ -353,14 +314,18 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 	}
 
 	/* Find a primary mixer */
-	_dpu_rm_init_hw_iter(&iter_i, DPU_HW_BLK_LM);
-	while (lm_count != reqs->topology.num_lm &&
-			_dpu_rm_get_hw_locked(rm, &iter_i)) {
+	list_for_each_entry(iter_i, blk_list, list) {
+		if (iter_i->in_use)
+			continue;
+
+		if (lm_count == reqs->topology.num_lm)
+			break;
+
 		memset(&lm, 0, sizeof(lm));
 		memset(&pp, 0, sizeof(pp));
 
 		lm_count = 0;
-		lm[lm_count] = iter_i.blk;
+		lm[lm_count] = iter_i;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
 				rm, reqs, lm[lm_count],
@@ -370,19 +335,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 		++lm_count;
 
 		/* Valid primary mixer found, find matching peers */
-		_dpu_rm_init_hw_iter(&iter_j, DPU_HW_BLK_LM);
+		list_for_each_entry(iter_j, blk_list, list) {
+			if (iter_j->in_use)
+				continue;
 
-		while (lm_count != reqs->topology.num_lm &&
-				_dpu_rm_get_hw_locked(rm, &iter_j)) {
-			if (iter_i.blk == iter_j.blk)
+			if (lm_count == reqs->topology.num_lm)
+				break;
+
+			if (iter_i == iter_j)
 				continue;
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, reqs, iter_j.blk,
-					&pp[lm_count], iter_i.blk))
+					rm, reqs, iter_j,
+					&pp[lm_count], iter_i))
 				continue;
 
-			lm[lm_count] = iter_j.blk;
+			lm[lm_count] = iter_j;
 			++lm_count;
 		}
 	}
@@ -417,7 +385,9 @@ static int _dpu_rm_reserve_ctls(
 		const struct msm_display_topology *top)
 {
 	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
-	struct dpu_rm_hw_iter iter;
+	struct dpu_rm_hw_blk *iter;
+	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_CTL];
+
 	int i = 0, num_ctls = 0;
 	bool needs_split_display = false;
 
@@ -428,21 +398,23 @@ static int _dpu_rm_reserve_ctls(
 
 	needs_split_display = _dpu_rm_needs_split_display(top);
 
-	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_CTL);
-	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
+	list_for_each_entry(iter, blk_list, list)  {
+		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter->hw);
 		unsigned long features = ctl->caps->features;
 		bool has_split_display;
 
+		if (iter->in_use)
+			continue;
+
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
 
-		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
+		DPU_DEBUG("ctl %d caps 0x%lX\n", iter->hw->id, features);
 
 		if (needs_split_display != has_split_display)
 			continue;
 
-		ctls[i] = iter.blk;
-		DPU_DEBUG("ctl %d match\n", iter.blk->hw->id);
+		ctls[i] = iter;
+		DPU_DEBUG("ctl %d match\n", iter->hw->id);
 
 		if (++i == num_ctls)
 			break;
@@ -468,26 +440,26 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
 		uint32_t id,
 		enum dpu_hw_blk_type type)
 {
-	struct dpu_rm_hw_iter iter;
+	struct dpu_rm_hw_blk *iter;
+	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
 
 	/* Find the block entry in the rm, and note the reservation */
-	_dpu_rm_init_hw_iter(&iter, type);
-	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		if (iter.blk->hw->id != id)
+	list_for_each_entry(iter, blk_list, list)  {
+		if (iter->hw->id != id || iter->in_use)
 			continue;
 
-		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF);
+		trace_dpu_rm_reserve_intf(iter->hw->id, DPU_HW_BLK_INTF);
 
 		break;
 	}
 
 	/* Shouldn't happen since intfs are fixed at probe */
-	if (!iter.blk) {
+	if (!iter) {
 		DPU_ERROR("couldn't find type %d id %d\n", type, id);
 		return NULL;
 	}
 
-	return iter.blk;
+	return iter;
 }
 
 static int _dpu_rm_reserve_intf_related_hw(
-- 
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[PATCH 18/25] drm/msm/dpu: merge RM interface reservation helpers

[Jeykumar Sankaran]

we don't have enough reasons why the HW block looping's
cannot happen in the same function. So merge them.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 63 ++++++++++++++--------------------
 1 file changed, 26 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index a79456c..bb59250 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -435,52 +435,39 @@ static int _dpu_rm_reserve_ctls(
 	return 0;
 }
 
-static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
-		struct dpu_rm *rm,
-		uint32_t id,
-		enum dpu_hw_blk_type type)
-{
-	struct dpu_rm_hw_blk *iter;
-	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
-
-	/* Find the block entry in the rm, and note the reservation */
-	list_for_each_entry(iter, blk_list, list)  {
-		if (iter->hw->id != id || iter->in_use)
-			continue;
-
-		trace_dpu_rm_reserve_intf(iter->hw->id, DPU_HW_BLK_INTF);
-
-		break;
-	}
-
-	/* Shouldn't happen since intfs are fixed at probe */
-	if (!iter) {
-		DPU_ERROR("couldn't find type %d id %d\n", type, id);
-		return NULL;
-	}
-
-	return iter;
-}
-
-static int _dpu_rm_reserve_intf_related_hw(
+static int _dpu_rm_reserve_intfs(
 		struct dpu_rm *rm,
 		struct dpu_crtc_state *dpu_cstate,
 		struct dpu_encoder_hw_resources *hw_res)
 {
-	struct dpu_rm_hw_blk *blk;
+	struct dpu_rm_hw_blk *iter;
+	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
 	int i, num_intfs = 0;
 
 	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
+		struct dpu_rm_hw_blk *intf_blk = NULL;
+
 		if (hw_res->intfs[i] == INTF_MODE_NONE)
 			continue;
 
-		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
-				DPU_HW_BLK_INTF);
-		if (!blk)
-			return -ENAVAIL;
+		list_for_each_entry(iter, blk_list, list)  {
+			if (iter->in_use)
+				continue;
+
+			if (iter->hw->id == (INTF_0 + i)) {
+				intf_blk = iter;
+				break;
+			}
+		}
+
+		if (!intf_blk)
+			return -EINVAL;
 
-		blk->in_use = true;
-		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
+		intf_blk->in_use = true;
+		dpu_cstate->hw_intfs[num_intfs++] =
+						to_dpu_hw_intf(intf_blk->hw);
+
+		trace_dpu_rm_reserve_intf(intf_blk->hw->id, DPU_HW_BLK_INTF);
 	}
 
 	dpu_cstate->num_intfs = num_intfs;
@@ -507,9 +494,11 @@ static int _dpu_rm_make_reservation(
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate, &reqs->hw_res);
-	if (ret)
+	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &reqs->hw_res);
+	if (ret) {
+		DPU_ERROR("unable to find appropriate INTF\n");
 		return ret;
+	}
 
 	return ret;
 }
-- 
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[PATCH 19/25] drm/msm/dpu: remove msm_display_topology

[Jeykumar Sankaran]

msm_display_topology was used for providing HW block
layout of the pipeline for a specific display topology.
We already got rid of its usage from DSI driver. In DPU,
it was used to provide the details on HW blocks while
reserving resources. Since we can use the crtc state used
for storing the assigned HW blocks for providing the info,
we can conveniently get rid of this structure.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 ++++------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 82 ++++++++---------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      |  4 +-
 drivers/gpu/drm/msm/msm_drv.h               | 12 -----
 4 files changed, 33 insertions(+), 94 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd17528..5d501c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -166,7 +166,6 @@ enum dpu_enc_rc_states {
  * @delayed_off_work:		delayed worker to schedule disabling of
  *				clks and resources after IDLE_TIMEOUT time.
  * @vsync_event_work:		worker to handle vsync event for autorefresh
- * @topology:                   topology of the display
  * @idle_timeout:		idle timeout duration in milliseconds
  */
 struct dpu_encoder_virt {
@@ -202,7 +201,6 @@ struct dpu_encoder_virt {
 	enum dpu_enc_rc_states rc_state;
 	struct kthread_delayed_work delayed_off_work;
 	struct kthread_work vsync_event_work;
-	struct msm_display_topology topology;
 
 	u32 idle_timeout;
 };
@@ -557,25 +555,19 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 	}
 }
 
-static struct msm_display_topology dpu_encoder_get_topology(
+static void _dpu_encoder_get_topology(
 			struct dpu_encoder_virt *dpu_enc,
-			struct dpu_kms *dpu_kms,
+			struct drm_crtc_state *crtc_state,
 			struct drm_display_mode *mode)
 {
-	struct msm_display_topology topology;
-	int i, intf_count = 0;
-
-	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
-		if (dpu_enc->phys_encs[i])
-			intf_count++;
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
 	/* User split topology for width > 1080 */
-	topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
-	topology.num_enc = 0;
-	topology.num_intf = intf_count;
-
-	return topology;
+	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
+	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
 }
+
 static int dpu_encoder_virt_atomic_check(
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state,
@@ -586,7 +578,6 @@ static int dpu_encoder_virt_atomic_check(
 	struct dpu_kms *dpu_kms;
 	const struct drm_display_mode *mode;
 	struct drm_display_mode *adj_mode;
-	struct msm_display_topology topology;
 	int i = 0;
 	int ret = 0;
 
@@ -632,11 +623,9 @@ static int dpu_encoder_virt_atomic_check(
 		}
 	}
 
-	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
-
+	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
 	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
-		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-				     topology);
+		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bb59250..85a0fe2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -23,11 +23,9 @@
 
 /**
  * struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @topology:  selected topology for the display
  * @hw_res:	   Hardware resources required as reported by the encoders
  */
 struct dpu_rm_requirements {
-	struct msm_display_topology topology;
 	struct dpu_encoder_hw_resources hw_res;
 };
 
@@ -231,9 +229,9 @@ int dpu_rm_init(struct dpu_rm *rm,
 	return rc;
 }
 
-static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
+static bool _dpu_rm_needs_split_display(const struct dpu_crtc_state *dpu_cstate)
 {
-	return top->num_intf > 1;
+	return dpu_cstate->num_intfs > 1;
 }
 
 /**
@@ -241,7 +239,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  *	proposed use case requirements, incl. hardwired dependent blocks like
  *	pingpong
  * @rm: dpu resource manager handle
- * @reqs: proposed use case requirements
  * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  *      blocks connected to the lm (pp) is available and appropriate
  * @pp: output parameter, pingpong block attached to the layer mixer.
@@ -252,7 +249,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  */
 static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm *rm,
-		struct dpu_rm_requirements *reqs,
 		struct dpu_rm_hw_blk *lm,
 		struct dpu_rm_hw_blk **pp,
 		struct dpu_rm_hw_blk *primary_lm)
@@ -297,9 +293,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 }
 
 static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
-			       struct dpu_crtc_state *dpu_cstate,
-			       struct dpu_rm_requirements *reqs)
-
+			       struct dpu_crtc_state *dpu_cstate)
 {
 	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
@@ -308,17 +302,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 	int lm_count = 0;
 	int i, rc = 0;
 
-	if (!reqs->topology.num_lm) {
-		DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
-		return -EINVAL;
-	}
-
 	/* Find a primary mixer */
 	list_for_each_entry(iter_i, blk_list, list) {
 		if (iter_i->in_use)
 			continue;
 
-		if (lm_count == reqs->topology.num_lm)
+		if (lm_count == dpu_cstate->num_mixers)
 			break;
 
 		memset(&lm, 0, sizeof(lm));
@@ -328,8 +317,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 		lm[lm_count] = iter_i;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, reqs, lm[lm_count],
-				&pp[lm_count], NULL))
+				rm, lm[lm_count], &pp[lm_count], NULL))
 			continue;
 
 		++lm_count;
@@ -339,15 +327,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 			if (iter_j->in_use)
 				continue;
 
-			if (lm_count == reqs->topology.num_lm)
+			if (lm_count == dpu_cstate->num_mixers)
 				break;
 
 			if (iter_i == iter_j)
 				continue;
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, reqs, iter_j,
-					&pp[lm_count], iter_i))
+					rm, iter_j, &pp[lm_count], iter_i))
 				continue;
 
 			lm[lm_count] = iter_j;
@@ -355,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 		}
 	}
 
-	if (lm_count != reqs->topology.num_lm) {
+	if (lm_count != dpu_cstate->num_mixers) {
 		DPU_DEBUG("unable to find appropriate mixers\n");
 		return -ENAVAIL;
 	}
@@ -374,29 +361,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 					 pp[i]->hw->id);
 	}
 
-	dpu_cstate->num_mixers = lm_count;
-
 	return rc;
 }
 
 static int _dpu_rm_reserve_ctls(
 		struct dpu_rm *rm,
-		struct dpu_crtc_state *dpu_cstate,
-		const struct msm_display_topology *top)
+		struct dpu_crtc_state *dpu_cstate)
 {
 	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *iter;
 	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_CTL];
-
-	int i = 0, num_ctls = 0;
+	int i = 0;
 	bool needs_split_display = false;
 
 	memset(&ctls, 0, sizeof(ctls));
 
-	/* each hw_intf needs its own hw_ctrl to program its control path */
-	num_ctls = top->num_intf;
-
-	needs_split_display = _dpu_rm_needs_split_display(top);
+	needs_split_display = _dpu_rm_needs_split_display(dpu_cstate);
 
 	list_for_each_entry(iter, blk_list, list)  {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter->hw);
@@ -416,22 +396,20 @@ static int _dpu_rm_reserve_ctls(
 		ctls[i] = iter;
 		DPU_DEBUG("ctl %d match\n", iter->hw->id);
 
-		if (++i == num_ctls)
+		if (++i == dpu_cstate->num_ctls)
 			break;
 	}
 
-	if (i != num_ctls)
+	if (i != dpu_cstate->num_ctls)
 		return -ENAVAIL;
 
-	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
+	for (i = 0; i < ARRAY_SIZE(ctls) && i < dpu_cstate->num_ctls; i++) {
 		ctls[i]->in_use = true;
 		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
 
 		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL);
 	}
 
-	dpu_cstate->num_ctls = num_ctls;
-
 	return 0;
 }
 
@@ -470,7 +448,8 @@ static int _dpu_rm_reserve_intfs(
 		trace_dpu_rm_reserve_intf(intf_blk->hw->id, DPU_HW_BLK_INTF);
 	}
 
-	dpu_cstate->num_intfs = num_intfs;
+	if (dpu_cstate->num_intfs != num_intfs)
+		return -EINVAL;
 
 	return 0;
 }
@@ -482,13 +461,13 @@ static int _dpu_rm_make_reservation(
 {
 	int ret;
 
-	ret = _dpu_rm_reserve_lms(rm, dpu_cstate, reqs);
+	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate, &reqs->topology);
+	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate CTL\n");
 		return ret;
@@ -503,21 +482,11 @@ static int _dpu_rm_make_reservation(
 	return ret;
 }
 
-static int _dpu_rm_populate_requirements(
-		struct dpu_rm *rm,
+static void _dpu_rm_populate_requirements(
 		struct drm_encoder *enc,
-		struct dpu_rm_requirements *reqs,
-		struct msm_display_topology req_topology)
+		struct dpu_rm_requirements *reqs)
 {
 	dpu_encoder_get_hw_resources(enc, &reqs->hw_res);
-
-	reqs->topology = req_topology;
-
-	DRM_DEBUG_KMS("num_lm: %d num_enc: %d num_intf: %d\n",
-		      reqs->topology.num_lm, reqs->topology.num_enc,
-		      reqs->topology.num_intf);
-
-	return 0;
 }
 
 static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
@@ -591,8 +560,7 @@ void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
 int dpu_rm_reserve(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
-		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology)
+		struct drm_crtc_state *crtc_state)
 {
 	struct dpu_rm_requirements reqs;
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
@@ -607,18 +575,14 @@ int dpu_rm_reserve(
 
 	mutex_lock(&rm->rm_lock);
 
-	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
-	if (ret) {
-		DPU_ERROR("failed to populate hw requirements\n");
-		goto end;
-	}
+	_dpu_rm_populate_requirements(enc, &reqs);
 
 	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
 		_dpu_rm_release_reservation(rm, dpu_cstate);
 	}
-end:
+
 	mutex_unlock(&rm->rm_lock);
 
 	return ret;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 415eeec..1626cef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -62,13 +62,11 @@ int dpu_rm_init(struct dpu_rm *rm,
  * @rm: DPU Resource Manager handle
  * @drm_enc: DRM Encoder handle
  * @crtc_state: Proposed Atomic DRM CRTC State handle
- * @topology: Pointer to topology info for the display
  * @Return: 0 on Success otherwise -ERROR
  */
 int dpu_rm_reserve(struct dpu_rm *rm,
 		struct drm_encoder *drm_enc,
-		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology);
+		struct drm_crtc_state *crtc_state);
 
 /**
  * dpu_rm_release - Given the encoder for the display chain, release any
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 9d11f32..3515fb0 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -113,18 +113,6 @@ enum msm_event_wait {
 };
 
 /**
- * struct msm_display_topology - defines a display topology pipeline
- * @num_lm:       number of layer mixers used
- * @num_enc:      number of compression encoder blocks used
- * @num_intf:     number of interfaces the panel is mounted on
- */
-struct msm_display_topology {
-	u32 num_lm;
-	u32 num_enc;
-	u32 num_intf;
-};
-
-/**
  * struct msm_display_info - defines display properties
  * @intf_type:          DRM_MODE_CONNECTOR_ display type
  * @capabilities:       Bitmask of display flags
-- 
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a Linux Foundation Collaborative Project

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[PATCH 20/25] drm/msm/dpu: refine layer mixer reservations

[Jeykumar Sankaran]

Validate layer mixer pairs for compatibility before retrieving
the connected pingpong blocks.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 61 ++++++++++------------------------
 1 file changed, 17 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 85a0fe2..f794d13 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -235,61 +235,32 @@ static bool _dpu_rm_needs_split_display(const struct dpu_crtc_state *dpu_cstate)
 }
 
 /**
- * _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets
- *	proposed use case requirements, incl. hardwired dependent blocks like
- *	pingpong
+ * _dpu_rm_get_connected_pp - retrieve hardwired pingpong block
  * @rm: dpu resource manager handle
  * @lm: proposed layer mixer, function checks if lm, and all other hardwired
- *      blocks connected to the lm (pp) is available and appropriate
- * @pp: output parameter, pingpong block attached to the layer mixer.
- *      NULL if pp was not available, or not matching requirements.
- * @primary_lm: if non-null, this function check if lm is compatible primary_lm
- *              as well as satisfying all other requirements
- * @Return: true if lm matches all requirements, false otherwise
+ * @Return: handle to ping pong rm block
  */
-static bool _dpu_rm_check_lm_and_get_connected_blks(
-		struct dpu_rm *rm,
-		struct dpu_rm_hw_blk *lm,
-		struct dpu_rm_hw_blk **pp,
-		struct dpu_rm_hw_blk *primary_lm)
+static struct dpu_rm_hw_blk *
+_dpu_rm_get_connected_pp(struct dpu_rm *rm, struct dpu_rm_hw_blk *lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
-	struct dpu_rm_hw_blk *iter;
 	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_PINGPONG];
-
-	*pp = NULL;
-
-	DPU_DEBUG("check lm %d pp %d\n",
-			   lm_cfg->id, lm_cfg->pingpong);
-
-	/* Check if this layer mixer is a peer of the proposed primary LM */
-	if (primary_lm) {
-		const struct dpu_lm_cfg *prim_lm_cfg =
-				to_dpu_hw_mixer(primary_lm->hw)->cap;
-
-		if (!test_bit(lm_cfg->id, &prim_lm_cfg->lm_pair_mask)) {
-			DPU_DEBUG("lm %d not peer of lm %d\n", lm_cfg->id,
-					prim_lm_cfg->id);
-			return false;
-		}
-	}
+	struct dpu_rm_hw_blk *iter, *pp = NULL;
 
 	list_for_each_entry(iter, blk_list, list) {
 		if (iter->in_use)
 			continue;
 
 		if (iter->hw->id == lm_cfg->pingpong) {
-			*pp = iter;
+			pp = iter;
 			break;
 		}
 	}
 
-	if (!*pp) {
-		DPU_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
-		return false;
-	}
+	if (!pp)
+		DPU_ERROR("failed to get pp on lm %d\n", lm->hw->id);
 
-	return true;
+	return pp;
 }
 
 static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
@@ -315,15 +286,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 
 		lm_count = 0;
 		lm[lm_count] = iter_i;
-
-		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, lm[lm_count], &pp[lm_count], NULL))
-			continue;
+		pp[lm_count] = _dpu_rm_get_connected_pp(rm, iter_i);
 
 		++lm_count;
 
 		/* Valid primary mixer found, find matching peers */
 		list_for_each_entry(iter_j, blk_list, list) {
+			const struct dpu_lm_cfg *prim_lm_cfg =
+					to_dpu_hw_mixer(iter_i->hw)->cap;
+
 			if (iter_j->in_use)
 				continue;
 
@@ -333,11 +304,13 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 			if (iter_i == iter_j)
 				continue;
 
-			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, iter_j, &pp[lm_count], iter_i))
+			if (!test_bit(iter_j->hw->id,
+				      &prim_lm_cfg->lm_pair_mask))
 				continue;
 
 			lm[lm_count] = iter_j;
+			pp[lm_count] = _dpu_rm_get_connected_pp(rm, iter_j);
+
 			++lm_count;
 		}
 	}
-- 
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a Linux Foundation Collaborative Project

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[PATCH 21/25] drm/msm/dpu: merge RM reservation helpers

[Jeykumar Sankaran]

We cleaned up RM reserve api's enough to get rid of
most of its unwanted checks and release handlers. To
improve further the readability of the function, merging
down the individual HW type allocators into one function.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 73 +++++++++++-----------------------
 1 file changed, 24 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f794d13..5304597 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -22,15 +22,6 @@
 #include "dpu_trace.h"
 
 /**
- * struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @hw_res:	   Hardware resources required as reported by the encoders
- */
-struct dpu_rm_requirements {
-	struct dpu_encoder_hw_resources hw_res;
-};
-
-
-/**
  * struct dpu_rm_hw_blk - hardware block tracking list member
  * @list:	List head for list of all hardware blocks tracking items
  * @in_use:     True, if the hw block is assigned to a display pipeline.
@@ -427,41 +418,6 @@ static int _dpu_rm_reserve_intfs(
 	return 0;
 }
 
-static int _dpu_rm_make_reservation(
-		struct dpu_rm *rm,
-		struct dpu_crtc_state *dpu_cstate,
-		struct dpu_rm_requirements *reqs)
-{
-	int ret;
-
-	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
-	if (ret) {
-		DPU_ERROR("unable to find appropriate mixers\n");
-		return ret;
-	}
-
-	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
-	if (ret) {
-		DPU_ERROR("unable to find appropriate CTL\n");
-		return ret;
-	}
-
-	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &reqs->hw_res);
-	if (ret) {
-		DPU_ERROR("unable to find appropriate INTF\n");
-		return ret;
-	}
-
-	return ret;
-}
-
-static void _dpu_rm_populate_requirements(
-		struct drm_encoder *enc,
-		struct dpu_rm_requirements *reqs)
-{
-	dpu_encoder_get_hw_resources(enc, &reqs->hw_res);
-}
-
 static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
 			      int id)
 {
@@ -535,7 +491,7 @@ int dpu_rm_reserve(
 		struct drm_encoder *enc,
 		struct drm_crtc_state *crtc_state)
 {
-	struct dpu_rm_requirements reqs;
+	struct dpu_encoder_hw_resources hw_res;
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 	int ret;
 
@@ -548,14 +504,33 @@ int dpu_rm_reserve(
 
 	mutex_lock(&rm->rm_lock);
 
-	_dpu_rm_populate_requirements(enc, &reqs);
+	dpu_encoder_get_hw_resources(enc, &hw_res);
 
-	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
+	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
 	if (ret) {
-		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
-		_dpu_rm_release_reservation(rm, dpu_cstate);
+		DPU_ERROR("unable to find appropriate mixers\n");
+		goto cleanup_on_fail;
 	}
 
+	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
+	if (ret) {
+		DPU_ERROR("unable to find appropriate CTL\n");
+		goto cleanup_on_fail;
+	}
+
+	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
+	if (ret) {
+		DPU_ERROR("unable to find appropriate INTF\n");
+		goto cleanup_on_fail;
+	}
+
+	mutex_unlock(&rm->rm_lock);
+
+	return ret;
+
+cleanup_on_fail:
+	_dpu_rm_release_reservation(rm, dpu_cstate);
+
 	mutex_unlock(&rm->rm_lock);
 
 	return ret;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 22/25] drm/msm/dpu: make crtc and encoder specific HW reservation

[Jeykumar Sankaran]

Instead of letting encoder make a centralized reservation for
all of its display DRM components, this path splits the
responsibility between CRTC and Encoder, each requesting
RM for the HW mapping of its own domain.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    | 31 +++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69 ++++++++++++++++++++++++-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      | 36 +++++++++++----
 4 files changed, 119 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0625f56..0536b8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,8 @@
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
 
+#define MAX_VDISPLAY_SPLIT 1080
+
 static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
 					    struct drm_display_mode *mode)
 {
@@ -448,6 +450,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 
 	for (i = 0; i < cstate->num_mixers; i++) {
 		struct drm_rect *r = &cstate->lm_bounds[i];
+
 		r->x1 = crtc_split_width * i;
 		r->y1 = 0;
 		r->x2 = r->x1 + crtc_split_width;
@@ -885,6 +888,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 	struct drm_display_mode *mode;
 	struct drm_encoder *encoder;
 	struct msm_drm_private *priv;
+	struct dpu_kms *dpu_kms;
 	unsigned long flags;
 
 	if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
@@ -895,6 +899,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 	cstate = to_dpu_crtc_state(crtc->state);
 	mode = &cstate->base.adjusted_mode;
 	priv = crtc->dev->dev_private;
+	dpu_kms = to_dpu_kms(priv->kms);
 
 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
 
@@ -953,6 +958,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 		crtc->state->event = NULL;
 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 	}
+
+	dpu_rm_crtc_release(&dpu_kms->rm, crtc->state);
 }
 
 static void dpu_crtc_enable(struct drm_crtc *crtc,
@@ -1004,6 +1011,21 @@ struct plane_state {
 	u32 pipe_id;
 };
 
+static void _dpu_crtc_get_topology(
+			struct drm_crtc_state *crtc_state,
+			struct drm_display_mode *mode)
+{
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+
+	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+
+	/**
+	 * encoder->atomic_check is invoked before crtc->atomic_check.
+	 * so dpu_cstate->num_intfs should have a non-zero value.
+	 */
+	dpu_cstate->num_ctls = dpu_cstate->num_intfs;
+}
+
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {
@@ -1014,6 +1036,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 	const struct drm_plane_state *pstate;
 	struct drm_plane *plane;
 	struct drm_display_mode *mode;
+	struct msm_drm_private *priv;
+	struct dpu_kms *dpu_kms;
 
 	int cnt = 0, rc = 0, mixer_width, i, z_pos;
 
@@ -1039,6 +1063,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		goto end;
 	}
 
+	priv = crtc->dev->dev_private;
+	dpu_kms = to_dpu_kms(priv->kms);
+
 	mode = &state->adjusted_mode;
 	DPU_DEBUG("%s: check", dpu_crtc->name);
 
@@ -1229,6 +1256,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 		}
 	}
 
+	_dpu_crtc_get_topology(state, mode);
+	if (drm_atomic_crtc_needs_modeset(state))
+		rc = dpu_rm_crtc_reserve(&dpu_kms->rm, state);
+
 end:
 	kfree(pstates);
 	return rc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5d501c8..ce66309 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -67,8 +67,6 @@
 
 #define IDLE_SHORT_TIMEOUT	1
 
-#define MAX_VDISPLAY_SPLIT 1080
-
 /**
  * enum dpu_enc_rc_events - events for resource control state machine
  * @DPU_ENC_RC_EVENT_KICKOFF:
@@ -557,14 +555,10 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 
 static void _dpu_encoder_get_topology(
 			struct dpu_encoder_virt *dpu_enc,
-			struct drm_crtc_state *crtc_state,
-			struct drm_display_mode *mode)
+			struct drm_crtc_state *crtc_state)
 {
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
-	/* User split topology for width > 1080 */
-	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
-	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
 	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
 }
 
@@ -623,9 +617,9 @@ static int dpu_encoder_virt_atomic_check(
 		}
 	}
 
-	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
+	_dpu_encoder_get_topology(dpu_enc, crtc_state);
 	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
-		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
+		ret = dpu_rm_encoder_reserve(&dpu_kms->rm, drm_enc, crtc_state);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
@@ -1186,7 +1180,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
 
 	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
 
-	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);
+	dpu_rm_encoder_release(&dpu_kms->rm, drm_enc->crtc->state);
 }
 
 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 5304597..901b1fc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -436,8 +436,8 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
 	return -EINVAL;
 }
 
-static void _dpu_rm_release_reservation(struct dpu_rm *rm,
-					struct dpu_crtc_state *dpu_cstate)
+static void _dpu_rm_crtc_release_reservation(struct dpu_rm *rm,
+					     struct dpu_crtc_state *dpu_cstate)
 {
 	int i;
 
@@ -464,6 +464,12 @@ static void _dpu_rm_release_reservation(struct dpu_rm *rm,
 					dpu_cstate->hw_ctls[i]->base.id))
 			dpu_cstate->hw_ctls[i] = NULL;
 	}
+}
+
+static void _dpu_rm_encoder_release_reservation(struct dpu_rm *rm,
+					      struct dpu_crtc_state *dpu_cstate)
+{
+	int i;
 
 	for (i = 0; i < dpu_cstate->num_intfs; i++) {
 		if (!dpu_cstate->hw_intfs[i])
@@ -475,23 +481,33 @@ static void _dpu_rm_release_reservation(struct dpu_rm *rm,
 	}
 }
 
-void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
+void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
 {
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
 	mutex_lock(&rm->rm_lock);
 
-	_dpu_rm_release_reservation(rm, dpu_cstate);
+	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
 
 	mutex_unlock(&rm->rm_lock);
 }
 
-int dpu_rm_reserve(
+void dpu_rm_encoder_release(struct dpu_rm *rm,
+			    struct drm_crtc_state *crtc_state)
+{
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+
+	mutex_lock(&rm->rm_lock);
+
+	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
+
+	mutex_unlock(&rm->rm_lock);
+}
+
+int dpu_rm_crtc_reserve(
 		struct dpu_rm *rm,
-		struct drm_encoder *enc,
 		struct drm_crtc_state *crtc_state)
 {
-	struct dpu_encoder_hw_resources hw_res;
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 	int ret;
 
@@ -499,12 +515,10 @@ int dpu_rm_reserve(
 	if (!drm_atomic_crtc_needs_modeset(crtc_state))
 		return 0;
 
-	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
-		      enc->base.id, crtc_state->crtc->base.id);
 
-	mutex_lock(&rm->rm_lock);
+	DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc_state->crtc->base.id);
 
-	dpu_encoder_get_hw_resources(enc, &hw_res);
+	mutex_lock(&rm->rm_lock);
 
 	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
 	if (ret) {
@@ -518,6 +532,37 @@ int dpu_rm_reserve(
 		goto cleanup_on_fail;
 	}
 
+	mutex_unlock(&rm->rm_lock);
+
+	return ret;
+
+cleanup_on_fail:
+	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
+
+	mutex_unlock(&rm->rm_lock);
+
+	return ret;
+}
+
+int dpu_rm_encoder_reserve(
+		struct dpu_rm *rm,
+		struct drm_encoder *enc,
+		struct drm_crtc_state *crtc_state)
+{
+	struct dpu_encoder_hw_resources hw_res;
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
+	int ret;
+
+	/* Check if this is just a page-flip */
+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
+		return 0;
+
+	DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
+
+	mutex_lock(&rm->rm_lock);
+
+	dpu_encoder_get_hw_resources(enc, &hw_res);
+
 	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate INTF\n");
@@ -529,7 +574,7 @@ int dpu_rm_reserve(
 	return ret;
 
 cleanup_on_fail:
-	_dpu_rm_release_reservation(rm, dpu_cstate);
+	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
 
 	mutex_unlock(&rm->rm_lock);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 1626cef..0b1deb0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -53,27 +53,45 @@ int dpu_rm_init(struct dpu_rm *rm,
 int dpu_rm_destroy(struct dpu_rm *rm);
 
 /**
- * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
- *	the use connections and user requirements, specified through related
+ * dpu_rm_encoder_reserve - Given an Encoder, analyze the use connections
+ *      and user requirements, specified through related
  *	topology control properties, and reserve hardware blocks to that
  *	display chain.
- *	HW blocks can then be accessed through dpu_rm_get_* functions.
- *	HW Reservations should be released via dpu_rm_release_hw.
  * @rm: DPU Resource Manager handle
  * @drm_enc: DRM Encoder handle
  * @crtc_state: Proposed Atomic DRM CRTC State handle
  * @Return: 0 on Success otherwise -ERROR
  */
-int dpu_rm_reserve(struct dpu_rm *rm,
+int dpu_rm_encoder_reserve(struct dpu_rm *rm,
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state);
 
 /**
- * dpu_rm_release - Given the encoder for the display chain, release any
- *	HW blocks previously reserved for that use case.
+ * dpu_rm_crtc_reserve - Given a CRTC, analyze the use connections
+ *      and user requirements, specified through related
+ *	topology control properties, and reserve hardware blocks to that
+ *	display chain.
  * @rm: DPU Resource Manager handle
- * @crtc_state: atomic DRM state handle
+ * @crtc_state: Proposed Atomic DRM CRTC State handle
  * @Return: 0 on Success otherwise -ERROR
  */
-void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
+int dpu_rm_crtc_reserve(struct dpu_rm *rm,
+		struct drm_crtc_state *crtc_state);
+
+/**
+ * dpu_rm_encoder_release - Given the encoder, release any
+ *	HW blocks previously reserved for that use case.
+ * @rm: DPU Resource Manager handle
+ * @crtc_state: Proposed Atomic DRM CRTC State handle
+ */
+void dpu_rm_encoder_release(struct dpu_rm *rm,
+			    struct drm_crtc_state *crtc_state);
+
+/**
+ * dpu_rm_crtc_release - Given the crtc, release any
+ *	HW blocks previously reserved for that use case.
+ * @rm: DPU Resource Manager handle
+ * @crtc_state: Proposed Atomic DRM CRTC State handle
+ */
+void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
 #endif /* __DPU_RM_H__ */
-- 
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[PATCH 23/25] drm/msm/dpu: remove max_width from RM

[Jeykumar Sankaran]

Unused variable in the driver.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12 ------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
 2 files changed, 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 901b1fc..34e09aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -166,18 +166,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 			DPU_ERROR("failed: lm hw not available\n");
 			goto fail;
 		}
-
-		if (!rm->lm_max_width) {
-			rm->lm_max_width = lm->sblk->maxwidth;
-		} else if (rm->lm_max_width != lm->sblk->maxwidth) {
-			/*
-			 * Don't expect to have hw where lm max widths differ.
-			 * If found, take the min.
-			 */
-			DPU_ERROR("unsupported: lm maxwidth differs\n");
-			if (rm->lm_max_width > lm->sblk->maxwidth)
-				rm->lm_max_width = lm->sblk->maxwidth;
-		}
 	}
 
 	for (i = 0; i < cat->pingpong_count; i++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 0b1deb0..8676fa5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,12 +24,10 @@
  * struct dpu_rm - DPU dynamic hardware resource manager
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
- * @lm_max_width: cached layer mixer maximum width
  * @rm_lock: resource manager mutex
  */
 struct dpu_rm {
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
-	uint32_t lm_max_width;
 	struct mutex rm_lock;
 };
 
-- 
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[PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces

[Jeykumar Sankaran]

Since HW reservations are happening through atomic_check
and all the display commits are catered by a single commit thread,
it is not necessary to protect the interfaces by a separate
mutex.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24 ------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
 2 files changed, 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 34e09aa..9a63128 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -74,8 +74,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 		}
 	}
 
-	mutex_destroy(&rm->rm_lock);
-
 	return 0;
 }
 
@@ -146,8 +144,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 	/* Clear, setup lists */
 	memset(rm, 0, sizeof(*rm));
 
-	mutex_init(&rm->rm_lock);
-
 	for (type = 0; type < DPU_HW_BLK_MAX; type++)
 		INIT_LIST_HEAD(&rm->hw_blks[type]);
 
@@ -473,11 +469,7 @@ void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
 {
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
-	mutex_lock(&rm->rm_lock);
-
 	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
-
-	mutex_unlock(&rm->rm_lock);
 }
 
 void dpu_rm_encoder_release(struct dpu_rm *rm,
@@ -485,11 +477,7 @@ void dpu_rm_encoder_release(struct dpu_rm *rm,
 {
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
-	mutex_lock(&rm->rm_lock);
-
 	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
-
-	mutex_unlock(&rm->rm_lock);
 }
 
 int dpu_rm_crtc_reserve(
@@ -506,8 +494,6 @@ int dpu_rm_crtc_reserve(
 
 	DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc_state->crtc->base.id);
 
-	mutex_lock(&rm->rm_lock);
-
 	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
@@ -520,15 +506,11 @@ int dpu_rm_crtc_reserve(
 		goto cleanup_on_fail;
 	}
 
-	mutex_unlock(&rm->rm_lock);
-
 	return ret;
 
 cleanup_on_fail:
 	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
 
-	mutex_unlock(&rm->rm_lock);
-
 	return ret;
 }
 
@@ -547,8 +529,6 @@ int dpu_rm_encoder_reserve(
 
 	DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
 
-	mutex_lock(&rm->rm_lock);
-
 	dpu_encoder_get_hw_resources(enc, &hw_res);
 
 	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
@@ -557,14 +537,10 @@ int dpu_rm_encoder_reserve(
 		goto cleanup_on_fail;
 	}
 
-	mutex_unlock(&rm->rm_lock);
-
 	return ret;
 
 cleanup_on_fail:
 	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
 
-	mutex_unlock(&rm->rm_lock);
-
 	return ret;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 8676fa5..9acbeba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,11 +24,9 @@
  * struct dpu_rm - DPU dynamic hardware resource manager
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
- * @rm_lock: resource manager mutex
  */
 struct dpu_rm {
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
-	struct mutex rm_lock;
 };
 
 /**
-- 
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[PATCH 25/25] drm/msm/dpu: maintain RM init check internally

[Jeykumar Sankaran]

Move and maintain RM initialization flag checks
from KMS to RM.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  6 +-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 12 ++++++++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  |  3 +++
 4 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fdc89a8..59ccc46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -668,9 +668,7 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 		}
 	}
 
-	if (dpu_kms->rm_init)
-		dpu_rm_destroy(&dpu_kms->rm);
-	dpu_kms->rm_init = false;
+	dpu_rm_destroy(&dpu_kms->rm);
 
 	if (dpu_kms->catalog)
 		dpu_hw_catalog_deinit(dpu_kms->catalog);
@@ -1085,8 +1083,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 		goto power_error;
 	}
 
-	dpu_kms->rm_init = true;
-
 	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
 					     dpu_kms->catalog);
 	if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 66d4666..1fff795 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -140,7 +140,6 @@ struct dpu_kms {
 	bool suspend_block;
 
 	struct dpu_rm rm;
-	bool rm_init;
 
 	struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
 	struct dpu_hw_mdp *hw_mdp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 9a63128..3452fb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -65,6 +65,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 	struct dpu_rm_hw_blk *hw_cur, *hw_nxt;
 	enum dpu_hw_blk_type type;
 
+	if (!rm->initialized)
+		return 0;
+
 	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
 		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
 				list) {
@@ -74,6 +77,8 @@ int dpu_rm_destroy(struct dpu_rm *rm)
 		}
 	}
 
+	rm->initialized = false;
+
 	return 0;
 }
 
@@ -141,6 +146,11 @@ int dpu_rm_init(struct dpu_rm *rm,
 		return -EINVAL;
 	}
 
+	if (rm->initialized) {
+		DPU_DEBUG("RM is already initialized\n");
+		return 0;
+	}
+
 	/* Clear, setup lists */
 	memset(rm, 0, sizeof(*rm));
 
@@ -196,6 +206,8 @@ int dpu_rm_init(struct dpu_rm *rm,
 		}
 	}
 
+	rm->initialized = true;
+
 	return 0;
 
 fail:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 9acbeba..74e5d58 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -24,9 +24,12 @@
  * struct dpu_rm - DPU dynamic hardware resource manager
  * @hw_blks: array of lists of hardware resources present in the system, one
  *	list per type of hardware block
+ * @initialized: True, when RM is initialized with hw block list.
+ *               False, otherwise
  */
 struct dpu_rm {
 	struct list_head hw_blks[DPU_HW_BLK_MAX];
+	bool initialized;
 };
 
 /**
-- 
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Re: [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Jordan Crouse]

On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
> Layer mixer/pingpong block counts and hw ctl block counts
> will not be same for all the topologies (e.g. layer
> mixer muxing to single interface)
> 
> Use the encoder's split_role info to retrieve the
> respective control path for programming.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 96cdf06..d12f896 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> +		int ctl_index;
>  
>  		if (phys) {
>  			if (!dpu_enc->hw_pp[i]) {
> @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  				return;
>  			}
>  
> -			if (!hw_ctl[i]) {
> +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
> +
> +			if (!hw_ctl[ctl_index]) {
>  				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
> -					     "at idx: %d\n", i);
> +					     "at idx: %d\n", ctl_index);

I know you are only updating the previous code but we shouldn't be splitting the
string here for grep purposes.

>  				return;
>  			}
>  
>  			phys->hw_pp = dpu_enc->hw_pp[i];
> -			phys->hw_ctl = hw_ctl[i];
> +			phys->hw_ctl = hw_ctl[ctl_index];
>  
>  			phys->connector = conn->state->connector;
>  			if (phys->ops.mode_set)

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Re: [PATCH 10/25] drm/msm/dpu: maintain hw_mdp in kms

[Jordan Crouse]

On Mon, Oct 08, 2018 at 09:27:27PM -0700, Jeykumar Sankaran wrote:
> hw_mdp block is common for displays. No need
> to reserve per display.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  7 ++++++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 20 --------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  | 10 ----------
>  3 files changed, 6 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 8309850..fdc89a8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -689,6 +689,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
>  		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
>  	dpu_kms->vbif[VBIF_RT] = NULL;
>  
> +	if (dpu_kms->hw_mdp)
> +		dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
> +	dpu_kms->hw_mdp = NULL;
> +
>  	if (dpu_kms->mmio)
>  		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
>  	dpu_kms->mmio = NULL;
> @@ -1083,7 +1087,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>  
>  	dpu_kms->rm_init = true;
>  
> -	dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_kms->rm);
> +	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
> +					     dpu_kms->catalog);
>  	if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {

dpu_hw_mdptop_init() only returns ERR_PTR so you can change this over to
IS_ERR().

>  		rc = PTR_ERR(dpu_kms->hw_mdp);
>  		if (!dpu_kms->hw_mdp)

And then you don't need this and whatever comes along below it.

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 24fc1c7..561120d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -63,11 +63,6 @@ struct dpu_rm_hw_iter {
>  	enum dpu_hw_blk_type type;
>  };
>  
> -struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
> -{
> -	return rm->hw_mdp;
> -}
> -
>  static void _dpu_rm_init_hw_iter(
>  		struct dpu_rm_hw_iter *iter,
>  		uint32_t enc_id,
> @@ -151,9 +146,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>  		}
>  	}
>  
> -	dpu_hw_mdp_destroy(rm->hw_mdp);
> -	rm->hw_mdp = NULL;
> -
>  	mutex_destroy(&rm->rm_lock);
>  
>  	return 0;
> @@ -168,11 +160,8 @@ static int _dpu_rm_hw_blk_create(
>  		void *hw_catalog_info)
>  {
>  	struct dpu_rm_hw_blk *blk;
> -	struct dpu_hw_mdp *hw_mdp;
>  	void *hw;
>  
> -	hw_mdp = rm->hw_mdp;
> -
>  	switch (type) {
>  	case DPU_HW_BLK_LM:
>  		hw = dpu_hw_lm_init(id, mmio, cat);
> @@ -236,15 +225,6 @@ int dpu_rm_init(struct dpu_rm *rm,
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++)
>  		INIT_LIST_HEAD(&rm->hw_blks[type]);
>  
> -	/* Some of the sub-blocks require an mdptop to be created */
> -	rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
> -	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
> -		rc = PTR_ERR(rm->hw_mdp);
> -		rm->hw_mdp = NULL;
> -		DPU_ERROR("failed: mdp hw not available\n");
> -		goto fail;
> -	}
> -
>  	/* Interrogate HW catalog and create tracking items for hw blocks */
>  	for (i = 0; i < cat->mixer_count; i++) {
>  		struct dpu_lm_cfg *lm = &cat->mixer[i];
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index c7e3b2b..7ac1553 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -24,13 +24,11 @@
>   * struct dpu_rm - DPU dynamic hardware resource manager
>   * @hw_blks: array of lists of hardware resources present in the system, one
>   *	list per type of hardware block
> - * @hw_mdp: hardware object for mdp_top
>   * @lm_max_width: cached layer mixer maximum width
>   * @rm_lock: resource manager mutex
>   */
>  struct dpu_rm {
>  	struct list_head hw_blks[DPU_HW_BLK_MAX];
> -	struct dpu_hw_mdp *hw_mdp;
>  	uint32_t lm_max_width;
>  	struct mutex rm_lock;
>  };
> @@ -82,12 +80,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
>   * @Return: 0 on Success otherwise -ERROR
>   */
>  void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
> -
> -/**
> - * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
> - *	This is never reserved, and is usable by any display.
> - * @rm: DPU Resource Manager handle
> - * @Return: Pointer to hw block or NULL
> - */
> -struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
>  #endif /* __DPU_RM_H__ */

-- 
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Re: [PATCH 18/25] drm/msm/dpu: merge RM interface reservation helpers

[Jordan Crouse]

On Mon, Oct 08, 2018 at 09:27:35PM -0700, Jeykumar Sankaran wrote:
> we don't have enough reasons why the HW block looping's
> cannot happen in the same function. So merge them.

looping's -> looping. So there are reasons one might break them out
but not interesting ones?

> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 63 ++++++++++++++--------------------
>  1 file changed, 26 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index a79456c..bb59250 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -435,52 +435,39 @@ static int _dpu_rm_reserve_ctls(
>  	return 0;
>  }
>  
> -static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
> -		struct dpu_rm *rm,
> -		uint32_t id,
> -		enum dpu_hw_blk_type type)
> -{
> -	struct dpu_rm_hw_blk *iter;
> -	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
> -
> -	/* Find the block entry in the rm, and note the reservation */
> -	list_for_each_entry(iter, blk_list, list)  {
> -		if (iter->hw->id != id || iter->in_use)
> -			continue;
> -
> -		trace_dpu_rm_reserve_intf(iter->hw->id, DPU_HW_BLK_INTF);
> -
> -		break;
> -	}
> -
> -	/* Shouldn't happen since intfs are fixed at probe */
> -	if (!iter) {
> -		DPU_ERROR("couldn't find type %d id %d\n", type, id);
> -		return NULL;
> -	}
> -
> -	return iter;
> -}
> -
> -static int _dpu_rm_reserve_intf_related_hw(
> +static int _dpu_rm_reserve_intfs(
>  		struct dpu_rm *rm,
>  		struct dpu_crtc_state *dpu_cstate,
>  		struct dpu_encoder_hw_resources *hw_res)
>  {
> -	struct dpu_rm_hw_blk *blk;
> +	struct dpu_rm_hw_blk *iter;
> +	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
>  	int i, num_intfs = 0;
>  
>  	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
> +		struct dpu_rm_hw_blk *intf_blk = NULL;
> +
>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>  			continue;
>  
> -		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
> -				DPU_HW_BLK_INTF);
> -		if (!blk)
> -			return -ENAVAIL;
> +		list_for_each_entry(iter, blk_list, list)  {
> +			if (iter->in_use)
> +				continue;
> +
> +			if (iter->hw->id == (INTF_0 + i)) {
> +				intf_blk = iter;
> +				break;
> +			}
> +		}
> +
> +		if (!intf_blk)
> +			return -EINVAL;
>  
> -		blk->in_use = true;
> -		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
> +		intf_blk->in_use = true;
> +		dpu_cstate->hw_intfs[num_intfs++] =
> +						to_dpu_hw_intf(intf_blk->hw);
> +
> +		trace_dpu_rm_reserve_intf(intf_blk->hw->id, DPU_HW_BLK_INTF);
>  	}
>  
>  	dpu_cstate->num_intfs = num_intfs;
> @@ -507,9 +494,11 @@ static int _dpu_rm_make_reservation(
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate, &reqs->hw_res);
> -	if (ret)
> +	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &reqs->hw_res);
> +	if (ret) {
> +		DPU_ERROR("unable to find appropriate INTF\n");

Since there is only once consumer of this function, I would move this error
message down into the sub-function and provide more debug information - like
which INTF wasn't found.

>  		return ret;
> +	}

And you don't need to return ret in this block - you can just drop out to the
bottom.

>  
>  	return ret;
>  }

-- 
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Re: [Freedreno] [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
> Layer mixer/pingpong block counts and hw ctl block counts
> will not be same for all the topologies (e.g. layer
> mixer muxing to single interface)
> 
> Use the encoder's split_role info to retrieve the
> respective control path for programming.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 96cdf06..d12f896 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> +		int ctl_index;
>  
>  		if (phys) {
>  			if (!dpu_enc->hw_pp[i]) {
> @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  				return;
>  			}
>  
> -			if (!hw_ctl[i]) {
> +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
> +

What if MAX_CHANNELS_PER_ENC isn't 2? Similarly, what if num_phys_encs >
MAX_CHANNELS_PER_ENC? It seems like there should be a more formal relationship
between all of these verious values (num_of_h_tiles assumed to be <= 2 as well).
If one of them changes beyond the assumed bound, the rest of the driver falls
over pretty hard.


> +			if (!hw_ctl[ctl_index]) {
>  				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
> -					     "at idx: %d\n", i);
> +					     "at idx: %d\n", ctl_index);
>  				return;

When you return on error here, should you give back the resources that you've
already provisioned?

>  			}
>  
>  			phys->hw_pp = dpu_enc->hw_pp[i];
> -			phys->hw_ctl = hw_ctl[i];
> +			phys->hw_ctl = hw_ctl[ctl_index];
>  
>  			phys->connector = conn->state->connector;
>  			if (phys->ops.mode_set)
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
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Re: [PATCH 18/25] drm/msm/dpu: merge RM interface reservation helpers

[Jeykumar Sankaran]

On 2018-10-09 09:50, Jordan Crouse wrote:
> On Mon, Oct 08, 2018 at 09:27:35PM -0700, Jeykumar Sankaran wrote:
>> we don't have enough reasons why the HW block looping's
>> cannot happen in the same function. So merge them.
> 
> looping's -> looping. So there are reasons one might break them out
> but not interesting ones?
> 
Not just yet. Once we start supporting different type of connectors such
as writeback & DP and the parsing logic for the respective type of
INTF grows up, we *may* want to split this up.

Thanks
Jeykumar S.

>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 63
> ++++++++++++++--------------------
>>  1 file changed, 26 insertions(+), 37 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index a79456c..bb59250 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -435,52 +435,39 @@ static int _dpu_rm_reserve_ctls(
>>  	return 0;
>>  }
>> 
>> -static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>> -		struct dpu_rm *rm,
>> -		uint32_t id,
>> -		enum dpu_hw_blk_type type)
>> -{
>> -	struct dpu_rm_hw_blk *iter;
>> -	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
>> -
>> -	/* Find the block entry in the rm, and note the reservation */
>> -	list_for_each_entry(iter, blk_list, list)  {
>> -		if (iter->hw->id != id || iter->in_use)
>> -			continue;
>> -
>> -		trace_dpu_rm_reserve_intf(iter->hw->id, DPU_HW_BLK_INTF);
>> -
>> -		break;
>> -	}
>> -
>> -	/* Shouldn't happen since intfs are fixed at probe */
>> -	if (!iter) {
>> -		DPU_ERROR("couldn't find type %d id %d\n", type, id);
>> -		return NULL;
>> -	}
>> -
>> -	return iter;
>> -}
>> -
>> -static int _dpu_rm_reserve_intf_related_hw(
>> +static int _dpu_rm_reserve_intfs(
>>  		struct dpu_rm *rm,
>>  		struct dpu_crtc_state *dpu_cstate,
>>  		struct dpu_encoder_hw_resources *hw_res)
>>  {
>> -	struct dpu_rm_hw_blk *blk;
>> +	struct dpu_rm_hw_blk *iter;
>> +	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_INTF];
>>  	int i, num_intfs = 0;
>> 
>>  	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
>> +		struct dpu_rm_hw_blk *intf_blk = NULL;
>> +
>>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>>  			continue;
>> 
>> -		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
>> -				DPU_HW_BLK_INTF);
>> -		if (!blk)
>> -			return -ENAVAIL;
>> +		list_for_each_entry(iter, blk_list, list)  {
>> +			if (iter->in_use)
>> +				continue;
>> +
>> +			if (iter->hw->id == (INTF_0 + i)) {
>> +				intf_blk = iter;
>> +				break;
>> +			}
>> +		}
>> +
>> +		if (!intf_blk)
>> +			return -EINVAL;
>> 
>> -		blk->in_use = true;
>> -		dpu_cstate->hw_intfs[num_intfs++] =
> to_dpu_hw_intf(blk->hw);
>> +		intf_blk->in_use = true;
>> +		dpu_cstate->hw_intfs[num_intfs++] =
>> +
> to_dpu_hw_intf(intf_blk->hw);
>> +
>> +		trace_dpu_rm_reserve_intf(intf_blk->hw->id,
> DPU_HW_BLK_INTF);
>>  	}
>> 
>>  	dpu_cstate->num_intfs = num_intfs;
>> @@ -507,9 +494,11 @@ static int _dpu_rm_make_reservation(
>>  		return ret;
>>  	}
>> 
>> -	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate,
> &reqs->hw_res);
>> -	if (ret)
>> +	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &reqs->hw_res);
>> +	if (ret) {
>> +		DPU_ERROR("unable to find appropriate INTF\n");
> 
> Since there is only once consumer of this function, I would move this
> error
> message down into the sub-function and provide more debug information -
> like
> which INTF wasn't found.
> 
>>  		return ret;
>> +	}
> 
> And you don't need to return ret in this block - you can just drop out 
> to
> the
> bottom.
> 
>> 
>>  	return ret;
>>  }

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Re: [PATCH 00/25] reserve RM resources in CRTC state

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:17PM -0700, Jeykumar Sankaran wrote:
> Submitting series of patches to clean up DPU resource manager (RM)
> of complicated hw iterations, redundant data maintenence and eventually
> modifying the DPU to reserve display HW blocks only in atomic check
> and caching the assigned HW blocks in atomic CRTC state.
> 

I get the following build error with this series:

In file included from ../include/linux/list.h:9:0,
                 from ../include/linux/wait.h:7,
                 from ../include/linux/wait_bit.h:8,
                 from ../include/linux/fs.h:6,
                 from ../include/linux/debugfs.h:15,
                 from ../drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:21:
../drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c: In function ‘_dpu_crtc_setup_mixers’:
../include/linux/kernel.h:845:29: warning: comparison of distinct pointer types lacks a cast
   (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
                             ^
../include/linux/kernel.h:859:4: note: in expansion of macro ‘__typecheck’
   (__typecheck(x, y) && __no_side_effects(x, y))
    ^~~~~~~~~~~
../include/linux/kernel.h:869:24: note: in expansion of macro ‘__safe_cmp’
  __builtin_choose_expr(__safe_cmp(x, y), \
                        ^~~~~~~~~~
../include/linux/kernel.h:878:19: note: in expansion of macro ‘__careful_cmp’
 #define min(x, y) __careful_cmp(x, y, <)
                   ^~~~~~~~~~~~~
../drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:437:15: note: in expansion of macro ‘min’
   ctl_index = min(i, cstate->num_ctls - 1);
               ^~~

> Thanks,
> Jeykumar S.
> 
> Jeykumar Sankaran (25):
>   drm/msm/dpu: fix hw ctl retrieval for mixer muxing
>   drm/msm/dpu: avoid tracking reservations in RM
>   drm/msm/dpu: remove dev from RM
>   drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration
>   drm/msm/dpu: remove encoder from crtc mixer struct
>   drm/msm/dpu: clean up redundant hw type
>   drm/msm/dpu: reserve using crtc state
>   drm/msm/dpu: release reservation using crtc state
>   drm/msm/dpu: make RM iterator static
>   drm/msm/dpu: maintain hw_mdp in kms
>   drm/msm/dpu: remove reserve in encoder mode_set
>   drm/msm/dpu: remove mode_set_complete
>   drm/msm/dpu: make RM iterator hw type specific
>   drm/msm/dpu: remove enc_id tagging for hw blocks
>   drm/msm/dpu: avoid redundant hw blk reference
>   drm/msm/dpu: clean up test_only flag for RM reservation
>   drm/msm/dpu: remove RM HW block list iterator
>   drm/msm/dpu: merge RM interface reservation helpers
>   drm/msm/dpu: remove msm_display_topology
>   drm/msm/dpu: refine layer mixer reservations
>   drm/msm/dpu: merge RM reservation helpers
>   drm/msm/dpu: make crtc and encoder specific HW reservation
>   drm/msm/dpu: remove max_width from RM
>   drm/msm/dpu: remove mutex locking for RM interfaces
>   drm/msm/dpu: maintain RM init check internally
> 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           |  98 ++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |  16 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  96 +--
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  20 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |  16 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 728 ++++++---------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 107 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h          |  28 +-
>  drivers/gpu/drm/msm/msm_drv.h                      |  12 -
>  10 files changed, 322 insertions(+), 800 deletions(-)
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:41PM -0700, Jeykumar Sankaran wrote:
> Since HW reservations are happening through atomic_check
> and all the display commits are catered by a single commit thread,
> it is not necessary to protect the interfaces by a separate
> mutex.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24 ------------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
>  2 files changed, 26 deletions(-)
> 

/snip

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 8676fa5..9acbeba 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -24,11 +24,9 @@
>   * struct dpu_rm - DPU dynamic hardware resource manager
>   * @hw_blks: array of lists of hardware resources present in the system, one
>   *	list per type of hardware block
> - * @rm_lock: resource manager mutex
>   */
>  struct dpu_rm {
>  	struct list_head hw_blks[DPU_HW_BLK_MAX];

At this point, there's really not much point to even having the rm. It's just
another level of indirection that IMO complicates the code. If you look
at the usage of hw_blks, the code is always looking at a specific type of
hw_blk, so the array is unnecessary.

dpu_kms could just keep a few arrays/lists of the hw types, and the crtc and encoder
reserve functions can just go in crtc/encoder.

Sean

> -	struct mutex rm_lock;
>  };
>  
>  /**
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 02/25] drm/msm/dpu: avoid tracking reservations in RM

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:19PM -0700, Jeykumar Sankaran wrote:
> RM was equipped with reservation tracking structure RSVP
> to cache HW reservation of displays for certain clients
> where atomic_checks (atomic commit with TEST_ONLY) for all
> the displays are called before their respective atomic_commits.
> Since DPU doesn't support the sequence anymore, clean up
> the support from RM. Replace rsvp with the corresponding
> encoder id to tag the HW blocks reserved.
> 

Can you put something to the effect of "This is temporary and removed in a
future patch" in the commit message?


Reviewed-by: Sean Paul <seanpaul@chromium.org>


> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 284 +++++----------------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   4 -
>  2 files changed, 43 insertions(+), 245 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index bdb1177..36a929b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -21,8 +21,8 @@
>  #include "dpu_encoder.h"
>  #include "dpu_trace.h"
>  
> -#define RESERVED_BY_OTHER(h, r) \
> -	((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
> +#define RESERVED_BY_OTHER(h, r)  \
> +		((h)->enc_id && (h)->enc_id != r)
>  
>  /**
>   * struct dpu_rm_requirements - Reservation requirements parameter bundle
> @@ -34,85 +34,23 @@ struct dpu_rm_requirements {
>  	struct dpu_encoder_hw_resources hw_res;
>  };
>  
> -/**
> - * struct dpu_rm_rsvp - Use Case Reservation tagging structure
> - *	Used to tag HW blocks as reserved by a CRTC->Encoder->Connector chain
> - *	By using as a tag, rather than lists of pointers to HW blocks used
> - *	we can avoid some list management since we don't know how many blocks
> - *	of each type a given use case may require.
> - * @list:	List head for list of all reservations
> - * @seq:	Global RSVP sequence number for debugging, especially for
> - *		differentiating differenct allocations for same encoder.
> - * @enc_id:	Reservations are tracked by Encoder DRM object ID.
> - *		CRTCs may be connected to multiple Encoders.
> - *		An encoder or connector id identifies the display path.
> - */
> -struct dpu_rm_rsvp {
> -	struct list_head list;
> -	uint32_t seq;
> -	uint32_t enc_id;
> -};
>  
>  /**
>   * struct dpu_rm_hw_blk - hardware block tracking list member
>   * @list:	List head for list of all hardware blocks tracking items
> - * @rsvp:	Pointer to use case reservation if reserved by a client
> - * @rsvp_nxt:	Temporary pointer used during reservation to the incoming
> - *		request. Will be swapped into rsvp if proposal is accepted
>   * @type:	Type of hardware block this structure tracks
>   * @id:		Hardware ID number, within it's own space, ie. LM_X
> - * @catalog:	Pointer to the hardware catalog entry for this block
> + * @enc_id:	Encoder id to which this blk is binded
>   * @hw:		Pointer to the hardware register access object for this block
>   */
>  struct dpu_rm_hw_blk {
>  	struct list_head list;
> -	struct dpu_rm_rsvp *rsvp;
> -	struct dpu_rm_rsvp *rsvp_nxt;
>  	enum dpu_hw_blk_type type;
>  	uint32_t id;
> +	uint32_t enc_id;
>  	struct dpu_hw_blk *hw;
>  };
>  
> -/**
> - * dpu_rm_dbg_rsvp_stage - enum of steps in making reservation for event logging
> - */
> -enum dpu_rm_dbg_rsvp_stage {
> -	DPU_RM_STAGE_BEGIN,
> -	DPU_RM_STAGE_AFTER_CLEAR,
> -	DPU_RM_STAGE_AFTER_RSVPNEXT,
> -	DPU_RM_STAGE_FINAL
> -};
> -
> -static void _dpu_rm_print_rsvps(
> -		struct dpu_rm *rm,
> -		enum dpu_rm_dbg_rsvp_stage stage)
> -{
> -	struct dpu_rm_rsvp *rsvp;
> -	struct dpu_rm_hw_blk *blk;
> -	enum dpu_hw_blk_type type;
> -
> -	DPU_DEBUG("%d\n", stage);
> -
> -	list_for_each_entry(rsvp, &rm->rsvps, list) {
> -		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
> -			      rsvp->enc_id);
> -	}
> -
> -	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
> -		list_for_each_entry(blk, &rm->hw_blks[type], list) {
> -			if (!blk->rsvp && !blk->rsvp_nxt)
> -				continue;
> -
> -			DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
> -				(blk->rsvp) ? blk->rsvp->seq : 0,
> -				(blk->rsvp) ? blk->rsvp->enc_id : 0,
> -				(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
> -				(blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
> -				blk->type, blk->id);
> -		}
> -	}
> -}
> -
>  struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
>  {
>  	return rm->hw_mdp;
> @@ -148,15 +86,13 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  	i->blk = list_prepare_entry(i->blk, blk_list, list);
>  
>  	list_for_each_entry_continue(i->blk, blk_list, list) {
> -		struct dpu_rm_rsvp *rsvp = i->blk->rsvp;
> -
>  		if (i->blk->type != i->type) {
>  			DPU_ERROR("found incorrect block type %d on %d list\n",
>  					i->blk->type, i->type);
>  			return false;
>  		}
>  
> -		if ((i->enc_id == 0) || (rsvp && rsvp->enc_id == i->enc_id)) {
> +		if (i->enc_id == i->blk->enc_id) {
>  			i->hw = i->blk->hw;
>  			DPU_DEBUG("found type %d id %d for enc %d\n",
>  					i->type, i->blk->id, i->enc_id);
> @@ -208,22 +144,9 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
>  
>  int dpu_rm_destroy(struct dpu_rm *rm)
>  {
> -
> -	struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt;
>  	struct dpu_rm_hw_blk *hw_cur, *hw_nxt;
>  	enum dpu_hw_blk_type type;
>  
> -	if (!rm) {
> -		DPU_ERROR("invalid rm\n");
> -		return -EINVAL;
> -	}
> -
> -	list_for_each_entry_safe(rsvp_cur, rsvp_nxt, &rm->rsvps, list) {
> -		list_del(&rsvp_cur->list);
> -		kfree(rsvp_cur);
> -	}
> -
> -
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
>  		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
>  				list) {
> @@ -293,6 +216,7 @@ static int _dpu_rm_hw_blk_create(
>  	blk->type = type;
>  	blk->id = id;
>  	blk->hw = hw;
> +	blk->enc_id = 0;
>  	list_add_tail(&blk->list, &rm->hw_blks[type]);
>  
>  	return 0;
> @@ -316,7 +240,6 @@ int dpu_rm_init(struct dpu_rm *rm,
>  
>  	mutex_init(&rm->rm_lock);
>  
> -	INIT_LIST_HEAD(&rm->rsvps);
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++)
>  		INIT_LIST_HEAD(&rm->hw_blks[type]);
>  
> @@ -410,7 +333,7 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
>   *	proposed use case requirements, incl. hardwired dependent blocks like
>   *	pingpong
>   * @rm: dpu resource manager handle
> - * @rsvp: reservation currently being created
> + * @enc_id: encoder id requesting for allocation
>   * @reqs: proposed use case requirements
>   * @lm: proposed layer mixer, function checks if lm, and all other hardwired
>   *      blocks connected to the lm (pp) is available and appropriate
> @@ -422,7 +345,7 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
>   */
>  static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> +		uint32_t enc_id,
>  		struct dpu_rm_requirements *reqs,
>  		struct dpu_rm_hw_blk *lm,
>  		struct dpu_rm_hw_blk **pp,
> @@ -449,7 +372,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  	}
>  
>  	/* Already reserved? */
> -	if (RESERVED_BY_OTHER(lm, rsvp)) {
> +	if (RESERVED_BY_OTHER(lm, enc_id)) {
>  		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
>  		return false;
>  	}
> @@ -467,7 +390,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		return false;
>  	}
>  
> -	if (RESERVED_BY_OTHER(*pp, rsvp)) {
> +	if (RESERVED_BY_OTHER(*pp, enc_id)) {
>  		DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
>  				(*pp)->id);
>  		return false;
> @@ -476,10 +399,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  	return true;
>  }
>  
> -static int _dpu_rm_reserve_lms(
> -		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> -		struct dpu_rm_requirements *reqs)
> +static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
> +			       struct dpu_rm_requirements *reqs)
>  
>  {
>  	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
> @@ -504,7 +425,7 @@ static int _dpu_rm_reserve_lms(
>  		lm[lm_count] = iter_i.blk;
>  
>  		if (!_dpu_rm_check_lm_and_get_connected_blks(
> -				rm, rsvp, reqs, lm[lm_count],
> +				rm, enc_id, reqs, lm[lm_count],
>  				&pp[lm_count], NULL))
>  			continue;
>  
> @@ -519,7 +440,7 @@ static int _dpu_rm_reserve_lms(
>  				continue;
>  
>  			if (!_dpu_rm_check_lm_and_get_connected_blks(
> -					rm, rsvp, reqs, iter_j.blk,
> +					rm, enc_id, reqs, iter_j.blk,
>  					&pp[lm_count], iter_i.blk))
>  				continue;
>  
> @@ -537,10 +458,10 @@ static int _dpu_rm_reserve_lms(
>  		if (!lm[i])
>  			break;
>  
> -		lm[i]->rsvp_nxt = rsvp;
> -		pp[i]->rsvp_nxt = rsvp;
> +		lm[i]->enc_id = enc_id;
> +		pp[i]->enc_id = enc_id;
>  
> -		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id,
> +		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, enc_id,
>  					 pp[i]->id);
>  	}
>  
> @@ -549,7 +470,7 @@ static int _dpu_rm_reserve_lms(
>  
>  static int _dpu_rm_reserve_ctls(
>  		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> +		uint32_t enc_id,
>  		const struct msm_display_topology *top)
>  {
>  	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
> @@ -570,7 +491,7 @@ static int _dpu_rm_reserve_ctls(
>  		unsigned long features = ctl->caps->features;
>  		bool has_split_display;
>  
> -		if (RESERVED_BY_OTHER(iter.blk, rsvp))
> +		if (RESERVED_BY_OTHER(iter.blk, enc_id))
>  			continue;
>  
>  		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
> @@ -591,9 +512,9 @@ static int _dpu_rm_reserve_ctls(
>  		return -ENAVAIL;
>  
>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
> -		ctls[i]->rsvp_nxt = rsvp;
> +		ctls[i]->enc_id = enc_id;
>  		trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
> -					  rsvp->enc_id);
> +					  enc_id);
>  	}
>  
>  	return 0;
> @@ -601,7 +522,7 @@ static int _dpu_rm_reserve_ctls(
>  
>  static int _dpu_rm_reserve_intf(
>  		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> +		uint32_t enc_id,
>  		uint32_t id,
>  		enum dpu_hw_blk_type type)
>  {
> @@ -614,14 +535,14 @@ static int _dpu_rm_reserve_intf(
>  		if (iter.blk->id != id)
>  			continue;
>  
> -		if (RESERVED_BY_OTHER(iter.blk, rsvp)) {
> +		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
>  			DPU_ERROR("type %d id %d already reserved\n", type, id);
>  			return -ENAVAIL;
>  		}
>  
> -		iter.blk->rsvp_nxt = rsvp;
> +		iter.blk->enc_id = enc_id;
>  		trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
> -					  rsvp->enc_id);
> +					  enc_id);
>  		break;
>  	}
>  
> @@ -636,7 +557,7 @@ static int _dpu_rm_reserve_intf(
>  
>  static int _dpu_rm_reserve_intf_related_hw(
>  		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> +		uint32_t enc_id,
>  		struct dpu_encoder_hw_resources *hw_res)
>  {
>  	int i, ret = 0;
> @@ -646,7 +567,7 @@ static int _dpu_rm_reserve_intf_related_hw(
>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>  			continue;
>  		id = i + INTF_0;
> -		ret = _dpu_rm_reserve_intf(rm, rsvp, id,
> +		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
>  				DPU_HW_BLK_INTF);
>  		if (ret)
>  			return ret;
> @@ -655,33 +576,27 @@ static int _dpu_rm_reserve_intf_related_hw(
>  	return ret;
>  }
>  
> -static int _dpu_rm_make_next_rsvp(
> +static int _dpu_rm_make_reservation(
>  		struct dpu_rm *rm,
>  		struct drm_encoder *enc,
>  		struct drm_crtc_state *crtc_state,
> -		struct dpu_rm_rsvp *rsvp,
>  		struct dpu_rm_requirements *reqs)
>  {
>  	int ret;
>  
> -	/* Create reservation info, tag reserved blocks with it as we go */
> -	rsvp->seq = ++rm->rsvp_next_seq;
> -	rsvp->enc_id = enc->base.id;
> -	list_add_tail(&rsvp->list, &rm->rsvps);
> -
> -	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
> +	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate mixers\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_ctls(rm, rsvp, &reqs->topology);
> +	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate CTL\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
> +	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, &reqs->hw_res);
>  	if (ret)
>  		return ret;
>  
> @@ -706,108 +621,31 @@ static int _dpu_rm_populate_requirements(
>  	return 0;
>  }
>  
> -static struct dpu_rm_rsvp *_dpu_rm_get_rsvp(
> -		struct dpu_rm *rm,
> -		struct drm_encoder *enc)
> +static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
>  {
> -	struct dpu_rm_rsvp *i;
> -
> -	if (!rm || !enc) {
> -		DPU_ERROR("invalid params\n");
> -		return NULL;
> -	}
> -
> -	if (list_empty(&rm->rsvps))
> -		return NULL;
> -
> -	list_for_each_entry(i, &rm->rsvps, list)
> -		if (i->enc_id == enc->base.id)
> -			return i;
> -
> -	return NULL;
> -}
> -
> -/**
> - * _dpu_rm_release_rsvp - release resources and release a reservation
> - * @rm:	KMS handle
> - * @rsvp:	RSVP pointer to release and release resources for
> - */
> -static void _dpu_rm_release_rsvp(struct dpu_rm *rm, struct dpu_rm_rsvp *rsvp)
> -{
> -	struct dpu_rm_rsvp *rsvp_c, *rsvp_n;
>  	struct dpu_rm_hw_blk *blk;
>  	enum dpu_hw_blk_type type;
>  
> -	if (!rsvp)
> -		return;
> -
> -	DPU_DEBUG("rel rsvp %d enc %d\n", rsvp->seq, rsvp->enc_id);
> -
> -	list_for_each_entry_safe(rsvp_c, rsvp_n, &rm->rsvps, list) {
> -		if (rsvp == rsvp_c) {
> -			list_del(&rsvp_c->list);
> -			break;
> -		}
> -	}
> -
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
>  		list_for_each_entry(blk, &rm->hw_blks[type], list) {
> -			if (blk->rsvp == rsvp) {
> -				blk->rsvp = NULL;
> -				DPU_DEBUG("rel rsvp %d enc %d %d %d\n",
> -						rsvp->seq, rsvp->enc_id,
> -						blk->type, blk->id);
> -			}
> -			if (blk->rsvp_nxt == rsvp) {
> -				blk->rsvp_nxt = NULL;
> -				DPU_DEBUG("rel rsvp_nxt %d enc %d %d %d\n",
> -						rsvp->seq, rsvp->enc_id,
> -						blk->type, blk->id);
> +			if (blk->enc_id == enc_id) {
> +				blk->enc_id = 0;
> +				DPU_DEBUG("rel enc %d %d %d\n", enc_id,
> +					  blk->type, blk->id);
>  			}
>  		}
>  	}
> -
> -	kfree(rsvp);
>  }
>  
>  void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc)
>  {
> -	struct dpu_rm_rsvp *rsvp;
> -
> -	if (!rm || !enc) {
> -		DPU_ERROR("invalid params\n");
> -		return;
> -	}
> -
>  	mutex_lock(&rm->rm_lock);
>  
> -	rsvp = _dpu_rm_get_rsvp(rm, enc);
> -	if (!rsvp) {
> -		DPU_ERROR("failed to find rsvp for enc %d\n", enc->base.id);
> -		goto end;
> -	}
> +	_dpu_rm_release_reservation(rm, enc->base.id);
>  
> -	_dpu_rm_release_rsvp(rm, rsvp);
> -end:
>  	mutex_unlock(&rm->rm_lock);
>  }
>  
> -static void _dpu_rm_commit_rsvp(struct dpu_rm *rm, struct dpu_rm_rsvp *rsvp)
> -{
> -	struct dpu_rm_hw_blk *blk;
> -	enum dpu_hw_blk_type type;
> -
> -	/* Swap next rsvp to be the active */
> -	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
> -		list_for_each_entry(blk, &rm->hw_blks[type], list) {
> -			if (blk->rsvp_nxt) {
> -				blk->rsvp = blk->rsvp_nxt;
> -				blk->rsvp_nxt = NULL;
> -			}
> -		}
> -	}
> -}
> -
>  int dpu_rm_reserve(
>  		struct dpu_rm *rm,
>  		struct drm_encoder *enc,
> @@ -815,7 +653,6 @@ int dpu_rm_reserve(
>  		struct msm_display_topology topology,
>  		bool test_only)
>  {
> -	struct dpu_rm_rsvp *rsvp_cur, *rsvp_nxt;
>  	struct dpu_rm_requirements reqs;
>  	int ret;
>  
> @@ -828,8 +665,6 @@ int dpu_rm_reserve(
>  
>  	mutex_lock(&rm->rm_lock);
>  
> -	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_BEGIN);
> -
>  	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
>  					    topology);
>  	if (ret) {
> @@ -837,50 +672,17 @@ int dpu_rm_reserve(
>  		goto end;
>  	}
>  
> -	/*
> -	 * We only support one active reservation per-hw-block. But to implement
> -	 * transactional semantics for test-only, and for allowing failure while
> -	 * modifying your existing reservation, over the course of this
> -	 * function we can have two reservations:
> -	 * Current: Existing reservation
> -	 * Next: Proposed reservation. The proposed reservation may fail, or may
> -	 *       be discarded if in test-only mode.
> -	 * If reservation is successful, and we're not in test-only, then we
> -	 * replace the current with the next.
> -	 */
> -	rsvp_nxt = kzalloc(sizeof(*rsvp_nxt), GFP_KERNEL);
> -	if (!rsvp_nxt) {
> -		ret = -ENOMEM;
> -		goto end;
> -	}
> -
> -	rsvp_cur = _dpu_rm_get_rsvp(rm, enc);
> -
> -	/* Check the proposed reservation, store it in hw's "next" field */
> -	ret = _dpu_rm_make_next_rsvp(rm, enc, crtc_state, rsvp_nxt, &reqs);
> -
> -	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_AFTER_RSVPNEXT);
> -
> +	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
>  	if (ret) {
>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
> -		_dpu_rm_release_rsvp(rm, rsvp_nxt);
> +		_dpu_rm_release_reservation(rm, enc->base.id);
>  	} else if (test_only) {
> -		/*
> -		 * Normally, if test_only, test the reservation and then undo
> -		 * However, if the user requests LOCK, then keep the reservation
> -		 * made during the atomic_check phase.
> -		 */
> -		DPU_DEBUG("test_only: discard test rsvp[s%de%d]\n",
> -				rsvp_nxt->seq, rsvp_nxt->enc_id);
> -		_dpu_rm_release_rsvp(rm, rsvp_nxt);
> -	} else {
> -		_dpu_rm_release_rsvp(rm, rsvp_cur);
> -
> -		_dpu_rm_commit_rsvp(rm, rsvp_nxt);
> +		 /* test_only: test the reservation and then undo */
> +		DPU_DEBUG("test_only: discard test [enc: %d]\n",
> +				enc->base.id);
> +		_dpu_rm_release_reservation(rm, enc->base.id);
>  	}
>  
> -	_dpu_rm_print_rsvps(rm, DPU_RM_STAGE_FINAL);
> -
>  end:
>  	mutex_unlock(&rm->rm_lock);
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index b8273bd..0dd3c21 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -23,21 +23,17 @@
>  /**
>   * struct dpu_rm - DPU dynamic hardware resource manager
>   * @dev: device handle for event logging purposes
> - * @rsvps: list of hardware reservations by each crtc->encoder->connector
>   * @hw_blks: array of lists of hardware resources present in the system, one
>   *	list per type of hardware block
>   * @hw_mdp: hardware object for mdp_top
>   * @lm_max_width: cached layer mixer maximum width
> - * @rsvp_next_seq: sequence number for next reservation for debugging purposes
>   * @rm_lock: resource manager mutex
>   */
>  struct dpu_rm {
>  	struct drm_device *dev;
> -	struct list_head rsvps;
>  	struct list_head hw_blks[DPU_HW_BLK_MAX];
>  	struct dpu_hw_mdp *hw_mdp;
>  	uint32_t lm_max_width;
> -	uint32_t rsvp_next_seq;
>  	struct mutex rm_lock;
>  };
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 03/25] drm/msm/dpu: remove dev from RM

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:20PM -0700, Jeykumar Sankaran wrote:
> Not used. Remove from RM.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 7 ++-----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  | 6 +-----
>  3 files changed, 4 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 0a683e6..8309850 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1075,8 +1075,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>  		goto power_error;
>  	}
>  
> -	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio,
> -			dpu_kms->dev);
> +	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
>  	if (rc) {
>  		DPU_ERROR("rm init failed: %d\n", rc);
>  		goto power_error;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 36a929b..5ce89b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -224,13 +224,12 @@ static int _dpu_rm_hw_blk_create(
>  
>  int dpu_rm_init(struct dpu_rm *rm,
>  		struct dpu_mdss_cfg *cat,
> -		void __iomem *mmio,
> -		struct drm_device *dev)
> +		void __iomem *mmio)
>  {
>  	int rc, i;
>  	enum dpu_hw_blk_type type;
>  
> -	if (!rm || !cat || !mmio || !dev) {
> +	if (!rm || !cat || !mmio) {
>  		DPU_ERROR("invalid kms\n");
>  		return -EINVAL;
>  	}
> @@ -243,8 +242,6 @@ int dpu_rm_init(struct dpu_rm *rm,
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++)
>  		INIT_LIST_HEAD(&rm->hw_blks[type]);
>  
> -	rm->dev = dev;
> -
>  	/* Some of the sub-blocks require an mdptop to be created */
>  	rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
>  	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 0dd3c21..f41fd19 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -22,7 +22,6 @@
>  
>  /**
>   * struct dpu_rm - DPU dynamic hardware resource manager
> - * @dev: device handle for event logging purposes
>   * @hw_blks: array of lists of hardware resources present in the system, one
>   *	list per type of hardware block
>   * @hw_mdp: hardware object for mdp_top
> @@ -30,7 +29,6 @@
>   * @rm_lock: resource manager mutex
>   */
>  struct dpu_rm {
> -	struct drm_device *dev;
>  	struct list_head hw_blks[DPU_HW_BLK_MAX];
>  	struct dpu_hw_mdp *hw_mdp;
>  	uint32_t lm_max_width;
> @@ -63,13 +61,11 @@ struct dpu_rm_hw_iter {
>   * @rm: DPU Resource Manager handle
>   * @cat: Pointer to hardware catalog
>   * @mmio: mapped register io address of MDP
> - * @dev: device handle for event logging purposes
>   * @Return: 0 on Success otherwise -ERROR
>   */
>  int dpu_rm_init(struct dpu_rm *rm,
>  		struct dpu_mdss_cfg *cat,
> -		void __iomem *mmio,
> -		struct drm_device *dev);
> +		void __iomem *mmio);
>  
>  /**
>   * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [PATCH 04/25] drm/msm/dpu: clean up dpu_rm_check_property_topctl declaration

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:21PM -0700, Jeykumar Sankaran wrote:
> Definition was removed already. Clean up header declaration.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index f41fd19..eb6a6ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -136,12 +136,4 @@ void dpu_rm_init_hw_iter(
>   * @Return: true on match found, false on no match found
>   */
>  bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter);
> -
> -/**
> - * dpu_rm_check_property_topctl - validate property bitmask before it is set
> - * @val: user's proposed topology control bitmask
> - * @Return: 0 on success or error
> - */
> -int dpu_rm_check_property_topctl(uint64_t val);
> -
>  #endif /* __DPU_RM_H__ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 05/25] drm/msm/dpu: remove encoder from crtc mixer struct

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:22PM -0700, Jeykumar Sankaran wrote:
> Not actively used. Clean up the crtc mixer struct.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
>  2 files changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d4530d6..4960641 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -461,8 +461,6 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  			return;
>  		}
>  
> -		mixer->encoder = enc;
> -
>  		cstate->num_mixers++;
>  		DPU_DEBUG("setup mixer %d: lm %d\n",
>  				i, mixer->hw_lm->idx - LM_0);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 3723b48..75fdd3c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -84,14 +84,12 @@ struct dpu_crtc_smmu_state_data {
>   * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
>   * @hw_lm:	LM HW Driver context
>   * @lm_ctl:	CTL Path HW driver context
> - * @encoder:	Encoder attached to this lm & ctl
>   * @mixer_op_mode:	mixer blending operation mode
>   * @flush_mask:	mixer flush mask for ctl, mixer and pipe
>   */
>  struct dpu_crtc_mixer {
>  	struct dpu_hw_mixer *hw_lm;
>  	struct dpu_hw_ctl *lm_ctl;
> -	struct drm_encoder *encoder;
>  	u32 mixer_op_mode;
>  	u32 flush_mask;
>  };
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [PATCH 06/25] drm/msm/dpu: clean up redundant hw type

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:23PM -0700, Jeykumar Sankaran wrote:
> struct dpu_hw_blk has hw block type info. Remove duplicate
> type tracking in struct dpu_rm_hw_blk.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 ++++-------------
>  1 file changed, 4 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 5ce89b9..377def7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -38,14 +38,12 @@ struct dpu_rm_requirements {
>  /**
>   * struct dpu_rm_hw_blk - hardware block tracking list member
>   * @list:	List head for list of all hardware blocks tracking items
> - * @type:	Type of hardware block this structure tracks
>   * @id:		Hardware ID number, within it's own space, ie. LM_X
>   * @enc_id:	Encoder id to which this blk is binded
>   * @hw:		Pointer to the hardware register access object for this block
>   */
>  struct dpu_rm_hw_blk {
>  	struct list_head list;
> -	enum dpu_hw_blk_type type;
>  	uint32_t id;
>  	uint32_t enc_id;
>  	struct dpu_hw_blk *hw;
> @@ -86,12 +84,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  	i->blk = list_prepare_entry(i->blk, blk_list, list);
>  
>  	list_for_each_entry_continue(i->blk, blk_list, list) {
> -		if (i->blk->type != i->type) {
> -			DPU_ERROR("found incorrect block type %d on %d list\n",
> -					i->blk->type, i->type);
> -			return false;
> -		}
> -
>  		if (i->enc_id == i->blk->enc_id) {
>  			i->hw = i->blk->hw;
>  			DPU_DEBUG("found type %d id %d for enc %d\n",
> @@ -151,7 +143,7 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>  		list_for_each_entry_safe(hw_cur, hw_nxt, &rm->hw_blks[type],
>  				list) {
>  			list_del(&hw_cur->list);
> -			_dpu_rm_hw_destroy(hw_cur->type, hw_cur->hw);
> +			_dpu_rm_hw_destroy(type, hw_cur->hw);
>  			kfree(hw_cur);
>  		}
>  	}
> @@ -213,7 +205,6 @@ static int _dpu_rm_hw_blk_create(
>  		return -ENOMEM;
>  	}
>  
> -	blk->type = type;
>  	blk->id = id;
>  	blk->hw = hw;
>  	blk->enc_id = 0;
> @@ -458,7 +449,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		lm[i]->enc_id = enc_id;
>  		pp[i]->enc_id = enc_id;
>  
> -		trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, enc_id,
> +		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
>  					 pp[i]->id);
>  	}
>  
> @@ -510,7 +501,7 @@ static int _dpu_rm_reserve_ctls(
>  
>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
>  		ctls[i]->enc_id = enc_id;
> -		trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
> +		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
>  					  enc_id);
>  	}
>  
> @@ -538,7 +529,7 @@ static int _dpu_rm_reserve_intf(
>  		}
>  
>  		iter.blk->enc_id = enc_id;
> -		trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
> +		trace_dpu_rm_reserve_intf(iter.blk->id, DPU_HW_BLK_INTF,

You should probably just remove the argument from the trace statements since
it's redundant.

Sean

>  					  enc_id);
>  		break;
>  	}
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [PATCH 22/25] drm/msm/dpu: make crtc and encoder specific HW reservation

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:39PM -0700, Jeykumar Sankaran wrote:
> Instead of letting encoder make a centralized reservation for
> all of its display DRM components, this path splits the
> responsibility between CRTC and Encoder, each requesting
> RM for the HW mapping of its own domain.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    | 31 +++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69 ++++++++++++++++++++++++-----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      | 36 +++++++++++----
>  4 files changed, 119 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 0625f56..0536b8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -47,6 +47,8 @@
>  #define LEFT_MIXER 0
>  #define RIGHT_MIXER 1
>  
> +#define MAX_VDISPLAY_SPLIT 1080
> +
>  static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
>  					    struct drm_display_mode *mode)
>  {
> @@ -448,6 +450,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>  
>  	for (i = 0; i < cstate->num_mixers; i++) {
>  		struct drm_rect *r = &cstate->lm_bounds[i];
> +
>  		r->x1 = crtc_split_width * i;
>  		r->y1 = 0;
>  		r->x2 = r->x1 + crtc_split_width;
> @@ -885,6 +888,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>  	struct drm_display_mode *mode;
>  	struct drm_encoder *encoder;
>  	struct msm_drm_private *priv;
> +	struct dpu_kms *dpu_kms;
>  	unsigned long flags;
>  
>  	if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
> @@ -895,6 +899,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>  	cstate = to_dpu_crtc_state(crtc->state);
>  	mode = &cstate->base.adjusted_mode;
>  	priv = crtc->dev->dev_private;
> +	dpu_kms = to_dpu_kms(priv->kms);
>  
>  	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>  
> @@ -953,6 +958,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>  		crtc->state->event = NULL;
>  		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
>  	}
> +
> +	dpu_rm_crtc_release(&dpu_kms->rm, crtc->state);
>  }
>  
>  static void dpu_crtc_enable(struct drm_crtc *crtc,
> @@ -1004,6 +1011,21 @@ struct plane_state {
>  	u32 pipe_id;
>  };
>  
> +static void _dpu_crtc_get_topology(
> +			struct drm_crtc_state *crtc_state,
> +			struct drm_display_mode *mode)
> +{
> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> +
> +	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
> +
> +	/**
> +	 * encoder->atomic_check is invoked before crtc->atomic_check.
> +	 * so dpu_cstate->num_intfs should have a non-zero value.
> +	 */
> +	dpu_cstate->num_ctls = dpu_cstate->num_intfs;

Why do we need num_ctls? Can't we just use dpu_cstate->num_intfs directly? Also,
you don't really need these in their own function, especially if num_ctls goes
away.

> +}
> +
>  static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  		struct drm_crtc_state *state)
>  {
> @@ -1014,6 +1036,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  	const struct drm_plane_state *pstate;
>  	struct drm_plane *plane;
>  	struct drm_display_mode *mode;
> +	struct msm_drm_private *priv;
> +	struct dpu_kms *dpu_kms;
>  
>  	int cnt = 0, rc = 0, mixer_width, i, z_pos;
>  
> @@ -1039,6 +1063,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  		goto end;
>  	}
>  
> +	priv = crtc->dev->dev_private;
> +	dpu_kms = to_dpu_kms(priv->kms);
> +
>  	mode = &state->adjusted_mode;
>  	DPU_DEBUG("%s: check", dpu_crtc->name);
>  
> @@ -1229,6 +1256,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  		}
>  	}
>  
> +	_dpu_crtc_get_topology(state, mode);
> +	if (drm_atomic_crtc_needs_modeset(state))
> +		rc = dpu_rm_crtc_reserve(&dpu_kms->rm, state);
> +
>  end:
>  	kfree(pstates);
>  	return rc;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 5d501c8..ce66309 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -67,8 +67,6 @@
>  
>  #define IDLE_SHORT_TIMEOUT	1
>  
> -#define MAX_VDISPLAY_SPLIT 1080
> -
>  /**
>   * enum dpu_enc_rc_events - events for resource control state machine
>   * @DPU_ENC_RC_EVENT_KICKOFF:
> @@ -557,14 +555,10 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
>  
>  static void _dpu_encoder_get_topology(
>  			struct dpu_encoder_virt *dpu_enc,
> -			struct drm_crtc_state *crtc_state,
> -			struct drm_display_mode *mode)
> +			struct drm_crtc_state *crtc_state)
>  {
>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>  
> -	/* User split topology for width > 1080 */
> -	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
> -	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
>  	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
>  }
>  
> @@ -623,9 +617,9 @@ static int dpu_encoder_virt_atomic_check(
>  		}
>  	}
>  
> -	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
> +	_dpu_encoder_get_topology(dpu_enc, crtc_state);
>  	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
> -		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
> +		ret = dpu_rm_encoder_reserve(&dpu_kms->rm, drm_enc, crtc_state);
>  
>  	if (!ret)
>  		drm_mode_set_crtcinfo(adj_mode, 0);
> @@ -1186,7 +1180,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
>  
>  	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
>  
> -	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);
> +	dpu_rm_encoder_release(&dpu_kms->rm, drm_enc->crtc->state);
>  }
>  
>  static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 5304597..901b1fc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -436,8 +436,8 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
>  	return -EINVAL;
>  }
>  
> -static void _dpu_rm_release_reservation(struct dpu_rm *rm,
> -					struct dpu_crtc_state *dpu_cstate)
> +static void _dpu_rm_crtc_release_reservation(struct dpu_rm *rm,
> +					     struct dpu_crtc_state *dpu_cstate)
>  {
>  	int i;
>  
> @@ -464,6 +464,12 @@ static void _dpu_rm_release_reservation(struct dpu_rm *rm,
>  					dpu_cstate->hw_ctls[i]->base.id))
>  			dpu_cstate->hw_ctls[i] = NULL;
>  	}
> +}
> +
> +static void _dpu_rm_encoder_release_reservation(struct dpu_rm *rm,
> +					      struct dpu_crtc_state *dpu_cstate)
> +{
> +	int i;
>  
>  	for (i = 0; i < dpu_cstate->num_intfs; i++) {
>  		if (!dpu_cstate->hw_intfs[i])
> @@ -475,23 +481,33 @@ static void _dpu_rm_release_reservation(struct dpu_rm *rm,
>  	}
>  }
>  
> -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
> +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
>  {
>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>  
>  	mutex_lock(&rm->rm_lock);
>  
> -	_dpu_rm_release_reservation(rm, dpu_cstate);
> +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
>  
>  	mutex_unlock(&rm->rm_lock);
>  }
>  
> -int dpu_rm_reserve(
> +void dpu_rm_encoder_release(struct dpu_rm *rm,
> +			    struct drm_crtc_state *crtc_state)
> +{
> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> +
> +	mutex_lock(&rm->rm_lock);
> +
> +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
> +
> +	mutex_unlock(&rm->rm_lock);
> +}
> +
> +int dpu_rm_crtc_reserve(
>  		struct dpu_rm *rm,
> -		struct drm_encoder *enc,
>  		struct drm_crtc_state *crtc_state)
>  {
> -	struct dpu_encoder_hw_resources hw_res;
>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>  	int ret;
>  
> @@ -499,12 +515,10 @@ int dpu_rm_reserve(
>  	if (!drm_atomic_crtc_needs_modeset(crtc_state))
>  		return 0;
>  
> -	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
> -		      enc->base.id, crtc_state->crtc->base.id);
>  
> -	mutex_lock(&rm->rm_lock);
> +	DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc_state->crtc->base.id);
>  
> -	dpu_encoder_get_hw_resources(enc, &hw_res);
> +	mutex_lock(&rm->rm_lock);
>  
>  	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
>  	if (ret) {
> @@ -518,6 +532,37 @@ int dpu_rm_reserve(
>  		goto cleanup_on_fail;
>  	}
>  
> +	mutex_unlock(&rm->rm_lock);
> +
> +	return ret;
> +
> +cleanup_on_fail:
> +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
> +
> +	mutex_unlock(&rm->rm_lock);
> +
> +	return ret;
> +}
> +
> +int dpu_rm_encoder_reserve(
> +		struct dpu_rm *rm,
> +		struct drm_encoder *enc,
> +		struct drm_crtc_state *crtc_state)
> +{
> +	struct dpu_encoder_hw_resources hw_res;
> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> +	int ret;
> +
> +	/* Check if this is just a page-flip */
> +	if (!drm_atomic_crtc_needs_modeset(crtc_state))
> +		return 0;
> +
> +	DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
> +
> +	mutex_lock(&rm->rm_lock);
> +
> +	dpu_encoder_get_hw_resources(enc, &hw_res);
> +
>  	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate INTF\n");
> @@ -529,7 +574,7 @@ int dpu_rm_reserve(
>  	return ret;
>  
>  cleanup_on_fail:
> -	_dpu_rm_release_reservation(rm, dpu_cstate);
> +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
>  
>  	mutex_unlock(&rm->rm_lock);
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 1626cef..0b1deb0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -53,27 +53,45 @@ int dpu_rm_init(struct dpu_rm *rm,
>  int dpu_rm_destroy(struct dpu_rm *rm);
>  
>  /**
> - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
> - *	the use connections and user requirements, specified through related
> + * dpu_rm_encoder_reserve - Given an Encoder, analyze the use connections
> + *      and user requirements, specified through related
>   *	topology control properties, and reserve hardware blocks to that
>   *	display chain.
> - *	HW blocks can then be accessed through dpu_rm_get_* functions.
> - *	HW Reservations should be released via dpu_rm_release_hw.
>   * @rm: DPU Resource Manager handle
>   * @drm_enc: DRM Encoder handle
>   * @crtc_state: Proposed Atomic DRM CRTC State handle
>   * @Return: 0 on Success otherwise -ERROR
>   */
> -int dpu_rm_reserve(struct dpu_rm *rm,
> +int dpu_rm_encoder_reserve(struct dpu_rm *rm,
>  		struct drm_encoder *drm_enc,
>  		struct drm_crtc_state *crtc_state);
>  
>  /**
> - * dpu_rm_release - Given the encoder for the display chain, release any
> - *	HW blocks previously reserved for that use case.
> + * dpu_rm_crtc_reserve - Given a CRTC, analyze the use connections
> + *      and user requirements, specified through related
> + *	topology control properties, and reserve hardware blocks to that
> + *	display chain.
>   * @rm: DPU Resource Manager handle
> - * @crtc_state: atomic DRM state handle
> + * @crtc_state: Proposed Atomic DRM CRTC State handle
>   * @Return: 0 on Success otherwise -ERROR
>   */
> -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
> +int dpu_rm_crtc_reserve(struct dpu_rm *rm,
> +		struct drm_crtc_state *crtc_state);
> +
> +/**
> + * dpu_rm_encoder_release - Given the encoder, release any
> + *	HW blocks previously reserved for that use case.
> + * @rm: DPU Resource Manager handle
> + * @crtc_state: Proposed Atomic DRM CRTC State handle
> + */
> +void dpu_rm_encoder_release(struct dpu_rm *rm,
> +			    struct drm_crtc_state *crtc_state);
> +
> +/**
> + * dpu_rm_crtc_release - Given the crtc, release any
> + *	HW blocks previously reserved for that use case.
> + * @rm: DPU Resource Manager handle
> + * @crtc_state: Proposed Atomic DRM CRTC State handle
> + */
> +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
>  #endif /* __DPU_RM_H__ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [PATCH 07/25] drm/msm/dpu: reserve using crtc state

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:24PM -0700, Jeykumar Sankaran wrote:
> DPU maintained reservation lists to cache assigned
> HW blocks for the display and a retrieval mechanism for
> the individual DRM components to query their respective
> HW blocks.
> 
> This patch uses the sub-classed CRTC state to store
> and track HW blocks assigned for different components
> of the display pipeline. It helps the driver:
> - to get rid of unwanted store and retrieval RM API's
> - to preserve HW resources assigned in atomic_check
>   through atomic swap/duplicate.
> 
> Separate patch is submitted to remove resource
> reservation in atomic_commit path.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 65 +++-------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           | 14 +++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 28 +++-------
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 20 ++-----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 58 ++++++++++++-------
>  5 files changed, 72 insertions(+), 113 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 4960641..0625f56 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -421,69 +421,20 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
>  	trace_dpu_crtc_complete_commit(DRMID(crtc));
>  }
>  
> -static void _dpu_crtc_setup_mixer_for_encoder(
> -		struct drm_crtc *crtc,
> -		struct drm_encoder *enc)
> +static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>  {
>  	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
> -	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
> -	struct dpu_rm *rm = &dpu_kms->rm;
>  	struct dpu_crtc_mixer *mixer;
> -	struct dpu_hw_ctl *last_valid_ctl = NULL;
> -	int i;
> -	struct dpu_rm_hw_iter lm_iter, ctl_iter;
> -
> -	dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
> -	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
> +	int i, ctl_index;
>  
>  	/* Set up all the mixers and ctls reserved by this encoder */
> -	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
> +	for (i = 0; i < cstate->num_mixers; i++) {
>  		mixer = &cstate->mixers[i];
>  
> -		if (!dpu_rm_get_hw(rm, &lm_iter))
> -			break;
> -		mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
> -
>  		/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
> -		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
> -			DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
> -					mixer->hw_lm->idx - LM_0);
> -			mixer->lm_ctl = last_valid_ctl;
> -		} else {
> -			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
> -			last_valid_ctl = mixer->lm_ctl;
> -		}
> -
> -		/* Shouldn't happen, mixers are always >= ctls */
> -		if (!mixer->lm_ctl) {
> -			DPU_ERROR("no valid ctls found for lm %d\n",
> -					mixer->hw_lm->idx - LM_0);
> -			return;
> -		}
> -
> -		cstate->num_mixers++;
> -		DPU_DEBUG("setup mixer %d: lm %d\n",
> -				i, mixer->hw_lm->idx - LM_0);
> -		DPU_DEBUG("setup mixer %d: ctl %d\n",
> -				i, mixer->lm_ctl->idx - CTL_0);
> -	}
> -}
> -
> -static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
> -{
> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> -	struct drm_encoder *enc;
> -
> -	mutex_lock(&dpu_crtc->crtc_lock);
> -	/* Check for mixers on all encoders attached to this crtc */
> -	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
> -		if (enc->crtc != crtc)
> -			continue;
> -
> -		_dpu_crtc_setup_mixer_for_encoder(crtc, enc);
> +		ctl_index = min(i, cstate->num_ctls - 1);

This is another one of those places I mentioned where we're just assuming a
value is going to be in a certain range. If num_ctls/num_intfs/num_phys_encs
(all the same value afaict) is 0, we end up in a bad place.

At a minimum, there should be a WARN_ON/BUG_ON somewhere ensuring this can never
drop below 0.

> +		mixer->lm_ctl = cstate->hw_ctls[ctl_index];
>  	}
> -
> -	mutex_unlock(&dpu_crtc->crtc_lock);
>  }
>  
>  static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
> @@ -536,10 +487,8 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
>  	dev = crtc->dev;
>  	smmu_state = &dpu_crtc->smmu_state;
>  
> -	if (!cstate->num_mixers) {
> -		_dpu_crtc_setup_mixers(crtc);
> -		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
> -	}
> +	_dpu_crtc_setup_mixers(crtc);
> +	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>  
>  	if (dpu_crtc->event) {
>  		WARN_ON(dpu_crtc->event);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 75fdd3c..17aaad7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -84,12 +84,14 @@ struct dpu_crtc_smmu_state_data {
>   * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
>   * @hw_lm:	LM HW Driver context
>   * @lm_ctl:	CTL Path HW driver context
> + * @hw_pp:	Pingpong HW driver context
>   * @mixer_op_mode:	mixer blending operation mode
>   * @flush_mask:	mixer flush mask for ctl, mixer and pipe
>   */
>  struct dpu_crtc_mixer {
>  	struct dpu_hw_mixer *hw_lm;
>  	struct dpu_hw_ctl *lm_ctl;
> +	struct dpu_hw_pingpong *hw_pp;
>  	u32 mixer_op_mode;
>  	u32 flush_mask;
>  };
> @@ -230,6 +232,18 @@ struct dpu_crtc_state {
>  
>  	u32 num_ctls;
>  	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
> +
> +	/**
> +	 * as drm encoders doesn't have dedicates state objects
> +	 * and drm connectors are not owned by DPU, maintain
> +	 * HW interface and other interface related blocks
> +	 * in crtc state

Can you use private state instead?

> +	 *
> +	 * TODO: No support for clone mode yet where a crtc
> +	 * can be attached with more than one encoder/connector.
> +	 */
> +	u32 num_intfs;
> +	struct dpu_hw_intf *hw_intfs[CRTC_DUAL_MIXERS];
>  };
>  
>  #define to_dpu_crtc_state(x) \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index d12f896..17dbbc3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1001,9 +1001,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  	struct dpu_kms *dpu_kms;
>  	struct list_head *connector_list;
>  	struct drm_connector *conn = NULL, *conn_iter;
> -	struct dpu_rm_hw_iter pp_iter, ctl_iter;
> +	struct dpu_crtc_state *dpu_cstate;
>  	struct msm_display_topology topology;
> -	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>  	int i = 0, ret;
>  
>  	if (!drm_enc) {
> @@ -1043,27 +1042,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  		return;
>  	}
>  
> -	dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG);
> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> -		dpu_enc->hw_pp[i] = NULL;
> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
> -			break;
> -		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
> -	}
> -
> -	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
> -			break;
> -		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
> -	}
> +	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
>  
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>  		int ctl_index;
>  
>  		if (phys) {
> -			if (!dpu_enc->hw_pp[i]) {
> +			if (!dpu_cstate->mixers[i].hw_pp) {
>  				DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
>  					     "at idx: %d\n", i);
>  				return;
> @@ -1071,14 +1057,16 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  
>  			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0;
>  
> -			if (!hw_ctl[ctl_index]) {
> +			if (!dpu_cstate->hw_ctls[ctl_index]) {
>  				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
>  					     "at idx: %d\n", ctl_index);
>  				return;
>  			}
>  
> -			phys->hw_pp = dpu_enc->hw_pp[i];
> -			phys->hw_ctl = hw_ctl[ctl_index];
> +			dpu_enc->hw_pp[i] = dpu_cstate->mixers[i].hw_pp;
> +
> +			phys->hw_pp = dpu_cstate->mixers[i].hw_pp;
> +			phys->hw_ctl = dpu_cstate->hw_ctls[ctl_index];
>  
>  			phys->connector = conn->state->connector;
>  			if (phys->ops.mode_set)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 84de385..4563f8d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -461,28 +461,20 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
>  
>  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
>  {
> -	struct msm_drm_private *priv;
>  	struct dpu_encoder_phys_vid *vid_enc;
> -	struct dpu_rm_hw_iter iter;
>  	struct dpu_hw_ctl *ctl;
> +	struct dpu_crtc_state *dpu_cstate;
> +	int i;
>  	u32 flush_mask = 0;
>  
> -	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
> -			!phys_enc->parent->dev->dev_private) {
> -		DPU_ERROR("invalid encoder/device\n");
> -		return;
> -	}
> -	priv = phys_enc->parent->dev->dev_private;
> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>  
>  	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
>  	ctl = phys_enc->hw_ctl;
>  
> -	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
> -	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
> -		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
> -
> -		if (hw_intf->idx == phys_enc->intf_idx) {
> -			vid_enc->hw_intf = hw_intf;
> +	for (i = 0; i < dpu_cstate->num_intfs; i++) {
> +		if (dpu_cstate->hw_intfs[i]->idx == phys_enc->intf_idx) {
> +			vid_enc->hw_intf = dpu_cstate->hw_intfs[i];
>  			break;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 377def7..5703b11 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -388,6 +388,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  }
>  
>  static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
> +			       struct dpu_crtc_state *dpu_cstate,
>  			       struct dpu_rm_requirements *reqs)
>  
>  {
> @@ -449,16 +450,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		lm[i]->enc_id = enc_id;
>  		pp[i]->enc_id = enc_id;
>  
> +		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
> +		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
> +
>  		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
>  					 pp[i]->id);
>  	}
>  
> +	dpu_cstate->num_mixers = lm_count;
> +
>  	return rc;
>  }
>  
>  static int _dpu_rm_reserve_ctls(
>  		struct dpu_rm *rm,
>  		uint32_t enc_id,
> +		struct dpu_crtc_state *dpu_cstate,
>  		const struct msm_display_topology *top)
>  {
>  	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
> @@ -501,21 +508,24 @@ static int _dpu_rm_reserve_ctls(
>  
>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
>  		ctls[i]->enc_id = enc_id;
> +		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
> +
>  		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
>  					  enc_id);
>  	}
>  
> +	dpu_cstate->num_ctls = num_ctls;
> +
>  	return 0;
>  }
>  
> -static int _dpu_rm_reserve_intf(
> +static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  		struct dpu_rm *rm,
>  		uint32_t enc_id,
>  		uint32_t id,
>  		enum dpu_hw_blk_type type)
>  {
>  	struct dpu_rm_hw_iter iter;
> -	int ret = 0;
>  
>  	/* Find the block entry in the rm, and note the reservation */
>  	dpu_rm_init_hw_iter(&iter, 0, type);
> @@ -525,7 +535,7 @@ static int _dpu_rm_reserve_intf(
>  
>  		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
>  			DPU_ERROR("type %d id %d already reserved\n", type, id);
> -			return -ENAVAIL;
> +			return NULL;
>  		}
>  
>  		iter.blk->enc_id = enc_id;
> @@ -535,56 +545,63 @@ static int _dpu_rm_reserve_intf(
>  	}
>  
>  	/* Shouldn't happen since intfs are fixed at probe */
> -	if (!iter.hw) {
> +	if (!iter.blk) {
>  		DPU_ERROR("couldn't find type %d id %d\n", type, id);
> -		return -EINVAL;
> +		return NULL;
>  	}
>  
> -	return ret;
> +	return iter.blk;
>  }
>  
>  static int _dpu_rm_reserve_intf_related_hw(
>  		struct dpu_rm *rm,
>  		uint32_t enc_id,
> +		struct dpu_crtc_state *dpu_cstate,
>  		struct dpu_encoder_hw_resources *hw_res)
>  {
> -	int i, ret = 0;
> -	u32 id;
> +	struct dpu_rm_hw_blk *blk;
> +	int i, num_intfs = 0;
>  
>  	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>  			continue;
> -		id = i + INTF_0;
> -		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
> +
> +		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
>  				DPU_HW_BLK_INTF);
> -		if (ret)
> -			return ret;
> +		if (!blk)
> +			return -ENAVAIL;
> +
> +		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
>  	}
>  
> -	return ret;
> +	dpu_cstate->num_intfs = num_intfs;
> +
> +	return 0;
>  }
>  
>  static int _dpu_rm_make_reservation(
>  		struct dpu_rm *rm,
>  		struct drm_encoder *enc,
> -		struct drm_crtc_state *crtc_state,
> +		struct dpu_crtc_state *dpu_cstate,
>  		struct dpu_rm_requirements *reqs)
>  {
>  	int ret;
>  
> -	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
> +	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate mixers\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
> +	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
> +				   &reqs->topology);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate CTL\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, &reqs->hw_res);
> +	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, dpu_cstate,
> +					      &reqs->hw_res);
>  	if (ret)
>  		return ret;
>  
> @@ -594,7 +611,6 @@ static int _dpu_rm_make_reservation(
>  static int _dpu_rm_populate_requirements(
>  		struct dpu_rm *rm,
>  		struct drm_encoder *enc,
> -		struct drm_crtc_state *crtc_state,
>  		struct dpu_rm_requirements *reqs,
>  		struct msm_display_topology req_topology)
>  {
> @@ -642,6 +658,7 @@ int dpu_rm_reserve(
>  		bool test_only)
>  {
>  	struct dpu_rm_requirements reqs;
> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>  	int ret;
>  
>  	/* Check if this is just a page-flip */
> @@ -653,14 +670,13 @@ int dpu_rm_reserve(
>  
>  	mutex_lock(&rm->rm_lock);
>  
> -	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
> -					    topology);
> +	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
>  	if (ret) {
>  		DPU_ERROR("failed to populate hw requirements\n");
>  		goto end;
>  	}
>  
> -	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
> +	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
>  	if (ret) {
>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>  		_dpu_rm_release_reservation(rm, enc->base.id);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 07/25] drm/msm/dpu: reserve using crtc state

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2894 bytes --]

Hi Jeykumar,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robclark/msm-next]
[also build test WARNING on next-20181009]
[cannot apply to v4.19-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jeykumar-Sankaran/reserve-RM-resources-in-CRTC-state/20181010-031051
base:   git://people.freedesktop.org/~robclark/linux msm-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   In file included from include/linux/list.h:9:0,
                    from include/linux/wait.h:7,
                    from include/linux/wait_bit.h:8,
                    from include/linux/fs.h:6,
                    from include/linux/debugfs.h:15,
                    from drivers/gpu//drm/msm/disp/dpu1/dpu_crtc.c:21:
   drivers/gpu//drm/msm/disp/dpu1/dpu_crtc.c: In function '_dpu_crtc_setup_mixers':
   include/linux/kernel.h:845:29: warning: comparison of distinct pointer types lacks a cast
      (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
                                ^
   include/linux/kernel.h:859:4: note: in expansion of macro '__typecheck'
      (__typecheck(x, y) && __no_side_effects(x, y))
       ^~~~~~~~~~~
   include/linux/kernel.h:869:24: note: in expansion of macro '__safe_cmp'
     __builtin_choose_expr(__safe_cmp(x, y), \
                           ^~~~~~~~~~
   include/linux/kernel.h:878:19: note: in expansion of macro '__careful_cmp'
    #define min(x, y) __careful_cmp(x, y, <)
                      ^~~~~~~~~~~~~
>> drivers/gpu//drm/msm/disp/dpu1/dpu_crtc.c:435:15: note: in expansion of macro 'min'
      ctl_index = min(i, cstate->num_ctls - 1);
                  ^~~

vim +/min +435 drivers/gpu//drm/msm/disp/dpu1/dpu_crtc.c

   423	
   424	static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
   425	{
   426		struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
   427		struct dpu_crtc_mixer *mixer;
   428		int i, ctl_index;
   429	
   430		/* Set up all the mixers and ctls reserved by this encoder */
   431		for (i = 0; i < cstate->num_mixers; i++) {
   432			mixer = &cstate->mixers[i];
   433	
   434			/* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
 > 435			ctl_index = min(i, cstate->num_ctls - 1);
   436			mixer->lm_ctl = cstate->hw_ctls[ctl_index];
   437		}
   438	}
   439	

---
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Re: [PATCH 06/25] drm/msm/dpu: clean up redundant hw type

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4466 bytes --]

Hi Jeykumar,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robclark/msm-next]
[also build test ERROR on next-20181009]
[cannot apply to v4.19-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jeykumar-Sankaran/reserve-RM-resources-in-CRTC-state/20181010-031051
base:   git://people.freedesktop.org/~robclark/linux msm-next
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm64 

Note: the linux-review/Jeykumar-Sankaran/reserve-RM-resources-in-CRTC-state/20181010-031051 HEAD c098339a791502c4a3732a304890f36240874372 builds fine.
      It only hurts bisectibility.

All error/warnings (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
                    from include/drm/drmP.h:73,
                    from drivers/gpu/drm/msm/msm_drv.h:39,
                    from drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h:22,
                    from drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:16:
   drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c: In function '_dpu_rm_release_reservation':
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:622:11: error: 'struct dpu_rm_hw_blk' has no member named 'type'
           blk->type, blk->id);
              ^
   include/drm/drm_print.h:352:30: note: in definition of macro 'DRM_DEBUG'
     drm_dbg(DRM_UT_CORE, fmt, ##__VA_ARGS__)
                                 ^~~~~~~~~~~
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:621:5: note: in expansion of macro 'DPU_DEBUG'
        DPU_DEBUG("rel enc %d %d %d\n", enc_id,
        ^~~~~~~~~
   In file included from include/linux/printk.h:336:0,
                    from include/linux/kernel.h:14,
                    from drivers/gpu/drm/msm/msm_drv.h:22,
                    from drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h:22,
                    from drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:16:
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:622:11: error: 'struct dpu_rm_hw_blk' has no member named 'type'
           blk->type, blk->id);
              ^
   include/linux/dynamic_debug.h:128:10: note: in definition of macro 'dynamic_pr_debug'
           ##__VA_ARGS__);  \
             ^~~~~~~~~~~
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h:48:4: note: in expansion of macro 'pr_debug'
       pr_debug(fmt, ##__VA_ARGS__);                      \
       ^~~~~~~~
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c:621:5: note: in expansion of macro 'DPU_DEBUG'
        DPU_DEBUG("rel enc %d %d %d\n", enc_id,
        ^~~~~~~~~

vim +622 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

25fdd593 Jeykumar Sankaran 2018-06-27  611  
0ff27752 Jeykumar Sankaran 2018-10-08  612  static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
25fdd593 Jeykumar Sankaran 2018-06-27  613  {
25fdd593 Jeykumar Sankaran 2018-06-27  614  	struct dpu_rm_hw_blk *blk;
25fdd593 Jeykumar Sankaran 2018-06-27  615  	enum dpu_hw_blk_type type;
25fdd593 Jeykumar Sankaran 2018-06-27  616  
25fdd593 Jeykumar Sankaran 2018-06-27  617  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
25fdd593 Jeykumar Sankaran 2018-06-27  618  		list_for_each_entry(blk, &rm->hw_blks[type], list) {
0ff27752 Jeykumar Sankaran 2018-10-08  619  			if (blk->enc_id == enc_id) {
0ff27752 Jeykumar Sankaran 2018-10-08  620  				blk->enc_id = 0;
0ff27752 Jeykumar Sankaran 2018-10-08 @621  				DPU_DEBUG("rel enc %d %d %d\n", enc_id,
25fdd593 Jeykumar Sankaran 2018-06-27 @622  					  blk->type, blk->id);
25fdd593 Jeykumar Sankaran 2018-06-27  623  			}
25fdd593 Jeykumar Sankaran 2018-06-27  624  		}
25fdd593 Jeykumar Sankaran 2018-06-27  625  	}
25fdd593 Jeykumar Sankaran 2018-06-27  626  }
25fdd593 Jeykumar Sankaran 2018-06-27  627  

:::::: The code at line 622 was first introduced by commit
:::::: 25fdd5933e4c0f5fe2ea5cd59994f8ac5fbe90ef drm/msm: Add SDM845 DPU support

:::::: TO: Jeykumar Sankaran <jsanka-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
:::::: CC: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

---
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Re: [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Jeykumar Sankaran]

On 2018-10-09 11:07, Sean Paul wrote:
> On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
>> Layer mixer/pingpong block counts and hw ctl block counts
>> will not be same for all the topologies (e.g. layer
>> mixer muxing to single interface)
>> 
>> Use the encoder's split_role info to retrieve the
>> respective control path for programming.
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 96cdf06..d12f896 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>> 
>>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> +		int ctl_index;
>> 
>>  		if (phys) {
>>  			if (!dpu_enc->hw_pp[i]) {
>> @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  				return;
>>  			}
>> 
>> -			if (!hw_ctl[i]) {
>> +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
> : 0;
>> +
> 
> What if MAX_CHANNELS_PER_ENC isn't 2? Similarly, what if num_phys_encs 
> >
> MAX_CHANNELS_PER_ENC? It seems like there should be a more formal
> relationship
> between all of these verious values (num_of_h_tiles assumed to be <= 2 
> as
> well).
> If one of them changes beyond the assumed bound, the rest of the driver
> falls
> over pretty hard.
> 
MAX_CHANNELS_PER_ENC is set to 2 to represent HW limitation on the 
chipset as
we cannot gang up more than 2 LM chain to an interface. Supporting more 
than 2
might demand much larger changes than validating for boundaries.

num_phys_enc is the max no of phys encoders we create as we are looping 
through
num_of_h_tiles which cannot be more than priv->dsi array size.

So its very unlikely we would expect these loops to go out of bound!

Thanks,
Jeykumar S.
> 
>> +			if (!hw_ctl[ctl_index]) {
>>  				DPU_ERROR_ENC(dpu_enc, "no ctl block
> assigned"
>> -					     "at idx: %d\n", i);
>> +					     "at idx: %d\n", ctl_index);
>>  				return;
> 
> When you return on error here, should you give back the resources that
> you've
> already provisioned?
> 
>>  			}
>> 
>>  			phys->hw_pp = dpu_enc->hw_pp[i];
>> -			phys->hw_ctl = hw_ctl[i];
>> +			phys->hw_ctl = hw_ctl[ctl_index];
>> 
>>  			phys->connector = conn->state->connector;
>>  			if (phys->ops.mode_set)
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 
>> _______________________________________________
>> Freedreno mailing list
>> Freedreno@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
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Re: [PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces

[Jeykumar Sankaran]

On 2018-10-09 12:57, Sean Paul wrote:
> On Mon, Oct 08, 2018 at 09:27:41PM -0700, Jeykumar Sankaran wrote:
>> Since HW reservations are happening through atomic_check
>> and all the display commits are catered by a single commit thread,
>> it is not necessary to protect the interfaces by a separate
>> mutex.
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24 ------------------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
>>  2 files changed, 26 deletions(-)
>> 
> 
> /snip
> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index 8676fa5..9acbeba 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -24,11 +24,9 @@
>>   * struct dpu_rm - DPU dynamic hardware resource manager
>>   * @hw_blks: array of lists of hardware resources present in the
> system, one
>>   *	list per type of hardware block
>> - * @rm_lock: resource manager mutex
>>   */
>>  struct dpu_rm {
>>  	struct list_head hw_blks[DPU_HW_BLK_MAX];
> 
> At this point, there's really not much point to even having the rm. 
> It's
> just
> another level of indirection that IMO complicates the code. If you look
> at the usage of hw_blks, the code is always looking at a specific type 
> of
> hw_blk, so the array is unnecessary.
> 
> dpu_kms could just keep a few arrays/lists of the hw types, and the 
> crtc
> and encoder
> reserve functions can just go in crtc/encoder.
> 
> Sean
> 
RM has been reduced to its current form to manage only LM/PP, CTL and 
interfaces.
Our eventual plan is to support all the advanced HW blocks and its 
features in
an upstream friendly way. When RM grows to manage all its subblocks, 
iteration
logic may get heavy since the chipset have HW chain restrictions on 
various hw blocks.
To provide room for the growth, I suggest keeping the allocation
helpers in a separate file. But I can see why you want to maintain the 
HW block lists
in the KMS.

Thanks,
Jeykumar S.
>> -	struct mutex rm_lock;
>>  };
>> 
>>  /**
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 
>> _______________________________________________
>> Freedreno mailing list
>> Freedreno@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
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Re: [PATCH 22/25] drm/msm/dpu: make crtc and encoder specific HW reservation

[Jeykumar Sankaran]

On 2018-10-09 13:41, Sean Paul wrote:
> On Mon, Oct 08, 2018 at 09:27:39PM -0700, Jeykumar Sankaran wrote:
>> Instead of letting encoder make a centralized reservation for
>> all of its display DRM components, this path splits the
>> responsibility between CRTC and Encoder, each requesting
>> RM for the HW mapping of its own domain.
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    | 31 +++++++++++++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++----
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69
> ++++++++++++++++++++++++-----
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      | 36 +++++++++++----
>>  4 files changed, 119 insertions(+), 31 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 0625f56..0536b8a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -47,6 +47,8 @@
>>  #define LEFT_MIXER 0
>>  #define RIGHT_MIXER 1
>> 
>> +#define MAX_VDISPLAY_SPLIT 1080
>> +
>>  static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state
> *cstate,
>>  					    struct drm_display_mode *mode)
>>  {
>> @@ -448,6 +450,7 @@ static void _dpu_crtc_setup_lm_bounds(struct
> drm_crtc *crtc,
>> 
>>  	for (i = 0; i < cstate->num_mixers; i++) {
>>  		struct drm_rect *r = &cstate->lm_bounds[i];
>> +
>>  		r->x1 = crtc_split_width * i;
>>  		r->y1 = 0;
>>  		r->x2 = r->x1 + crtc_split_width;
>> @@ -885,6 +888,7 @@ static void dpu_crtc_disable(struct drm_crtc 
>> *crtc)
>>  	struct drm_display_mode *mode;
>>  	struct drm_encoder *encoder;
>>  	struct msm_drm_private *priv;
>> +	struct dpu_kms *dpu_kms;
>>  	unsigned long flags;
>> 
>>  	if (!crtc || !crtc->dev || !crtc->dev->dev_private ||
> !crtc->state) {
>> @@ -895,6 +899,7 @@ static void dpu_crtc_disable(struct drm_crtc 
>> *crtc)
>>  	cstate = to_dpu_crtc_state(crtc->state);
>>  	mode = &cstate->base.adjusted_mode;
>>  	priv = crtc->dev->dev_private;
>> +	dpu_kms = to_dpu_kms(priv->kms);
>> 
>>  	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>> 
>> @@ -953,6 +958,8 @@ static void dpu_crtc_disable(struct drm_crtc 
>> *crtc)
>>  		crtc->state->event = NULL;
>>  		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
>>  	}
>> +
>> +	dpu_rm_crtc_release(&dpu_kms->rm, crtc->state);
>>  }
>> 
>>  static void dpu_crtc_enable(struct drm_crtc *crtc,
>> @@ -1004,6 +1011,21 @@ struct plane_state {
>>  	u32 pipe_id;
>>  };
>> 
>> +static void _dpu_crtc_get_topology(
>> +			struct drm_crtc_state *crtc_state,
>> +			struct drm_display_mode *mode)
>> +{
>> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>> +
>> +	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2
> : 1;
>> +
>> +	/**
>> +	 * encoder->atomic_check is invoked before crtc->atomic_check.
>> +	 * so dpu_cstate->num_intfs should have a non-zero value.
>> +	 */
>> +	dpu_cstate->num_ctls = dpu_cstate->num_intfs;
> 
> Why do we need num_ctls? Can't we just use dpu_cstate->num_intfs 
> directly?
> Also,
> you don't really need these in their own function, especially if 
> num_ctls
> goes
> away.
> 
Yes. I can live with just that. But since dpu_cstate maintains HW arrays
for each type, I thought it would be more readable if I could use
separate variables to track their counts instead of iterating over
ctl arrays over dpu_cstate->num_intfs and leaving comments that both
will be same for this version of hardware.

Also, the counts need not be the same for all the Snapdragon variants.

Thanks,
Jeykumar S.
>> +}
>> +
>>  static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>>  		struct drm_crtc_state *state)
>>  {
>> @@ -1014,6 +1036,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> *crtc,
>>  	const struct drm_plane_state *pstate;
>>  	struct drm_plane *plane;
>>  	struct drm_display_mode *mode;
>> +	struct msm_drm_private *priv;
>> +	struct dpu_kms *dpu_kms;
>> 
>>  	int cnt = 0, rc = 0, mixer_width, i, z_pos;
>> 
>> @@ -1039,6 +1063,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> *crtc,
>>  		goto end;
>>  	}
>> 
>> +	priv = crtc->dev->dev_private;
>> +	dpu_kms = to_dpu_kms(priv->kms);
>> +
>>  	mode = &state->adjusted_mode;
>>  	DPU_DEBUG("%s: check", dpu_crtc->name);
>> 
>> @@ -1229,6 +1256,10 @@ static int dpu_crtc_atomic_check(struct 
>> drm_crtc
> *crtc,
>>  		}
>>  	}
>> 
>> +	_dpu_crtc_get_topology(state, mode);
>> +	if (drm_atomic_crtc_needs_modeset(state))
>> +		rc = dpu_rm_crtc_reserve(&dpu_kms->rm, state);
>> +
>>  end:
>>  	kfree(pstates);
>>  	return rc;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 5d501c8..ce66309 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -67,8 +67,6 @@
>> 
>>  #define IDLE_SHORT_TIMEOUT	1
>> 
>> -#define MAX_VDISPLAY_SPLIT 1080
>> -
>>  /**
>>   * enum dpu_enc_rc_events - events for resource control state machine
>>   * @DPU_ENC_RC_EVENT_KICKOFF:
>> @@ -557,14 +555,10 @@ static void _dpu_encoder_adjust_mode(struct
> drm_connector *connector,
>> 
>>  static void _dpu_encoder_get_topology(
>>  			struct dpu_encoder_virt *dpu_enc,
>> -			struct drm_crtc_state *crtc_state,
>> -			struct drm_display_mode *mode)
>> +			struct drm_crtc_state *crtc_state)
>>  {
>>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>> 
>> -	/* User split topology for width > 1080 */
>> -	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2
> : 1;
>> -	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
>>  	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
>>  }
>> 
>> @@ -623,9 +617,9 @@ static int dpu_encoder_virt_atomic_check(
>>  		}
>>  	}
>> 
>> -	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
>> +	_dpu_encoder_get_topology(dpu_enc, crtc_state);
>>  	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
>> -		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
>> +		ret = dpu_rm_encoder_reserve(&dpu_kms->rm, drm_enc,
> crtc_state);
>> 
>>  	if (!ret)
>>  		drm_mode_set_crtcinfo(adj_mode, 0);
>> @@ -1186,7 +1180,7 @@ static void dpu_encoder_virt_disable(struct
> drm_encoder *drm_enc)
>> 
>>  	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
>> 
>> -	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);
>> +	dpu_rm_encoder_release(&dpu_kms->rm, drm_enc->crtc->state);
>>  }
>> 
>>  static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg 
>> *catalog,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index 5304597..901b1fc 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -436,8 +436,8 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm,
> enum dpu_hw_blk_type type,
>>  	return -EINVAL;
>>  }
>> 
>> -static void _dpu_rm_release_reservation(struct dpu_rm *rm,
>> -					struct dpu_crtc_state *dpu_cstate)
>> +static void _dpu_rm_crtc_release_reservation(struct dpu_rm *rm,
>> +					     struct dpu_crtc_state
> *dpu_cstate)
>>  {
>>  	int i;
>> 
>> @@ -464,6 +464,12 @@ static void _dpu_rm_release_reservation(struct
> dpu_rm *rm,
>>  					dpu_cstate->hw_ctls[i]->base.id))
>>  			dpu_cstate->hw_ctls[i] = NULL;
>>  	}
>> +}
>> +
>> +static void _dpu_rm_encoder_release_reservation(struct dpu_rm *rm,
>> +					      struct dpu_crtc_state
> *dpu_cstate)
>> +{
>> +	int i;
>> 
>>  	for (i = 0; i < dpu_cstate->num_intfs; i++) {
>>  		if (!dpu_cstate->hw_intfs[i])
>> @@ -475,23 +481,33 @@ static void _dpu_rm_release_reservation(struct
> dpu_rm *rm,
>>  	}
>>  }
>> 
>> -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state
> *crtc_state)
>> +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state
> *crtc_state)
>>  {
>>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>> 
>>  	mutex_lock(&rm->rm_lock);
>> 
>> -	_dpu_rm_release_reservation(rm, dpu_cstate);
>> +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
>> 
>>  	mutex_unlock(&rm->rm_lock);
>>  }
>> 
>> -int dpu_rm_reserve(
>> +void dpu_rm_encoder_release(struct dpu_rm *rm,
>> +			    struct drm_crtc_state *crtc_state)
>> +{
>> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>> +
>> +	mutex_lock(&rm->rm_lock);
>> +
>> +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
>> +
>> +	mutex_unlock(&rm->rm_lock);
>> +}
>> +
>> +int dpu_rm_crtc_reserve(
>>  		struct dpu_rm *rm,
>> -		struct drm_encoder *enc,
>>  		struct drm_crtc_state *crtc_state)
>>  {
>> -	struct dpu_encoder_hw_resources hw_res;
>>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>>  	int ret;
>> 
>> @@ -499,12 +515,10 @@ int dpu_rm_reserve(
>>  	if (!drm_atomic_crtc_needs_modeset(crtc_state))
>>  		return 0;
>> 
>> -	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
>> -		      enc->base.id, crtc_state->crtc->base.id);
>> 
>> -	mutex_lock(&rm->rm_lock);
>> +	DRM_DEBUG_KMS("reserving hw for crtc %d\n",
> crtc_state->crtc->base.id);
>> 
>> -	dpu_encoder_get_hw_resources(enc, &hw_res);
>> +	mutex_lock(&rm->rm_lock);
>> 
>>  	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
>>  	if (ret) {
>> @@ -518,6 +532,37 @@ int dpu_rm_reserve(
>>  		goto cleanup_on_fail;
>>  	}
>> 
>> +	mutex_unlock(&rm->rm_lock);
>> +
>> +	return ret;
>> +
>> +cleanup_on_fail:
>> +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
>> +
>> +	mutex_unlock(&rm->rm_lock);
>> +
>> +	return ret;
>> +}
>> +
>> +int dpu_rm_encoder_reserve(
>> +		struct dpu_rm *rm,
>> +		struct drm_encoder *enc,
>> +		struct drm_crtc_state *crtc_state)
>> +{
>> +	struct dpu_encoder_hw_resources hw_res;
>> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>> +	int ret;
>> +
>> +	/* Check if this is just a page-flip */
>> +	if (!drm_atomic_crtc_needs_modeset(crtc_state))
>> +		return 0;
>> +
>> +	DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
>> +
>> +	mutex_lock(&rm->rm_lock);
>> +
>> +	dpu_encoder_get_hw_resources(enc, &hw_res);
>> +
>>  	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
>>  	if (ret) {
>>  		DPU_ERROR("unable to find appropriate INTF\n");
>> @@ -529,7 +574,7 @@ int dpu_rm_reserve(
>>  	return ret;
>> 
>>  cleanup_on_fail:
>> -	_dpu_rm_release_reservation(rm, dpu_cstate);
>> +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
>> 
>>  	mutex_unlock(&rm->rm_lock);
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index 1626cef..0b1deb0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -53,27 +53,45 @@ int dpu_rm_init(struct dpu_rm *rm,
>>  int dpu_rm_destroy(struct dpu_rm *rm);
>> 
>>  /**
>> - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain,
> analyze
>> - *	the use connections and user requirements, specified through
> related
>> + * dpu_rm_encoder_reserve - Given an Encoder, analyze the use
> connections
>> + *      and user requirements, specified through related
>>   *	topology control properties, and reserve hardware blocks to that
>>   *	display chain.
>> - *	HW blocks can then be accessed through dpu_rm_get_* functions.
>> - *	HW Reservations should be released via dpu_rm_release_hw.
>>   * @rm: DPU Resource Manager handle
>>   * @drm_enc: DRM Encoder handle
>>   * @crtc_state: Proposed Atomic DRM CRTC State handle
>>   * @Return: 0 on Success otherwise -ERROR
>>   */
>> -int dpu_rm_reserve(struct dpu_rm *rm,
>> +int dpu_rm_encoder_reserve(struct dpu_rm *rm,
>>  		struct drm_encoder *drm_enc,
>>  		struct drm_crtc_state *crtc_state);
>> 
>>  /**
>> - * dpu_rm_release - Given the encoder for the display chain, release
> any
>> - *	HW blocks previously reserved for that use case.
>> + * dpu_rm_crtc_reserve - Given a CRTC, analyze the use connections
>> + *      and user requirements, specified through related
>> + *	topology control properties, and reserve hardware blocks to that
>> + *	display chain.
>>   * @rm: DPU Resource Manager handle
>> - * @crtc_state: atomic DRM state handle
>> + * @crtc_state: Proposed Atomic DRM CRTC State handle
>>   * @Return: 0 on Success otherwise -ERROR
>>   */
>> -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state
> *crtc_state);
>> +int dpu_rm_crtc_reserve(struct dpu_rm *rm,
>> +		struct drm_crtc_state *crtc_state);
>> +
>> +/**
>> + * dpu_rm_encoder_release - Given the encoder, release any
>> + *	HW blocks previously reserved for that use case.
>> + * @rm: DPU Resource Manager handle
>> + * @crtc_state: Proposed Atomic DRM CRTC State handle
>> + */
>> +void dpu_rm_encoder_release(struct dpu_rm *rm,
>> +			    struct drm_crtc_state *crtc_state);
>> +
>> +/**
>> + * dpu_rm_crtc_release - Given the crtc, release any
>> + *	HW blocks previously reserved for that use case.
>> + * @rm: DPU Resource Manager handle
>> + * @crtc_state: Proposed Atomic DRM CRTC State handle
>> + */
>> +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state
> *crtc_state);
>>  #endif /* __DPU_RM_H__ */
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 
>> _______________________________________________
>> Freedreno mailing list
>> Freedreno@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
Jeykumar S
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Re: [PATCH 07/25] drm/msm/dpu: reserve using crtc state

[Jeykumar Sankaran]

On 2018-10-09 14:06, Sean Paul wrote:
> On Mon, Oct 08, 2018 at 09:27:24PM -0700, Jeykumar Sankaran wrote:
>> DPU maintained reservation lists to cache assigned
>> HW blocks for the display and a retrieval mechanism for
>> the individual DRM components to query their respective
>> HW blocks.
>> 
>> This patch uses the sub-classed CRTC state to store
>> and track HW blocks assigned for different components
>> of the display pipeline. It helps the driver:
>> - to get rid of unwanted store and retrieval RM API's
>> - to preserve HW resources assigned in atomic_check
>>   through atomic swap/duplicate.
>> 
>> Separate patch is submitted to remove resource
>> reservation in atomic_commit path.
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 65
> +++-------------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           | 14 +++++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 28 +++-------
>>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 20 ++-----
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 58
> ++++++++++++-------
>>  5 files changed, 72 insertions(+), 113 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 4960641..0625f56 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -421,69 +421,20 @@ void dpu_crtc_complete_commit(struct drm_crtc
> *crtc,
>>  	trace_dpu_crtc_complete_commit(DRMID(crtc));
>>  }
>> 
>> -static void _dpu_crtc_setup_mixer_for_encoder(
>> -		struct drm_crtc *crtc,
>> -		struct drm_encoder *enc)
>> +static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>>  {
>>  	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>> -	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>> -	struct dpu_rm *rm = &dpu_kms->rm;
>>  	struct dpu_crtc_mixer *mixer;
>> -	struct dpu_hw_ctl *last_valid_ctl = NULL;
>> -	int i;
>> -	struct dpu_rm_hw_iter lm_iter, ctl_iter;
>> -
>> -	dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
>> -	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
>> +	int i, ctl_index;
>> 
>>  	/* Set up all the mixers and ctls reserved by this encoder */
>> -	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++)
> {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		mixer = &cstate->mixers[i];
>> 
>> -		if (!dpu_rm_get_hw(rm, &lm_iter))
>> -			break;
>> -		mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
>> -
>>  		/* CTL may be <= LMs, if <, multiple LMs controlled by 1
> CTL */
>> -		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
>> -			DPU_DEBUG("no ctl assigned to lm %d, using
> previous\n",
>> -					mixer->hw_lm->idx - LM_0);
>> -			mixer->lm_ctl = last_valid_ctl;
>> -		} else {
>> -			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
>> -			last_valid_ctl = mixer->lm_ctl;
>> -		}
>> -
>> -		/* Shouldn't happen, mixers are always >= ctls */
>> -		if (!mixer->lm_ctl) {
>> -			DPU_ERROR("no valid ctls found for lm %d\n",
>> -					mixer->hw_lm->idx - LM_0);
>> -			return;
>> -		}
>> -
>> -		cstate->num_mixers++;
>> -		DPU_DEBUG("setup mixer %d: lm %d\n",
>> -				i, mixer->hw_lm->idx - LM_0);
>> -		DPU_DEBUG("setup mixer %d: ctl %d\n",
>> -				i, mixer->lm_ctl->idx - CTL_0);
>> -	}
>> -}
>> -
>> -static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>> -{
>> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>> -	struct drm_encoder *enc;
>> -
>> -	mutex_lock(&dpu_crtc->crtc_lock);
>> -	/* Check for mixers on all encoders attached to this crtc */
>> -	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list,
> head) {
>> -		if (enc->crtc != crtc)
>> -			continue;
>> -
>> -		_dpu_crtc_setup_mixer_for_encoder(crtc, enc);
>> +		ctl_index = min(i, cstate->num_ctls - 1);
> 
> This is another one of those places I mentioned where we're just 
> assuming
> a
> value is going to be in a certain range. If
> num_ctls/num_intfs/num_phys_encs
> (all the same value afaict) is 0, we end up in a bad place.
Even though all these variables have the same value, they are 
representing the
sizes of logically seperate components.

> 
> At a minimum, there should be a WARN_ON/BUG_ON somewhere ensuring this 
> can
> never
> drop below 0.
Isn't RM guaranteeing that? I can add the WARN_ON checks on these
num_xxx when the HW blocks are allocated.

Thanks,
Jeykumar S.
> 
>> +		mixer->lm_ctl = cstate->hw_ctls[ctl_index];
>>  	}
>> -
>> -	mutex_unlock(&dpu_crtc->crtc_lock);
>>  }
>> 
>>  static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>> @@ -536,10 +487,8 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> *crtc,
>>  	dev = crtc->dev;
>>  	smmu_state = &dpu_crtc->smmu_state;
>> 
>> -	if (!cstate->num_mixers) {
>> -		_dpu_crtc_setup_mixers(crtc);
>> -		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>> -	}
>> +	_dpu_crtc_setup_mixers(crtc);
>> +	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>> 
>>  	if (dpu_crtc->event) {
>>  		WARN_ON(dpu_crtc->event);
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 75fdd3c..17aaad7 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -84,12 +84,14 @@ struct dpu_crtc_smmu_state_data {
>>   * struct dpu_crtc_mixer: stores the map for each virtual pipeline in
> the CRTC
>>   * @hw_lm:	LM HW Driver context
>>   * @lm_ctl:	CTL Path HW driver context
>> + * @hw_pp:	Pingpong HW driver context
>>   * @mixer_op_mode:	mixer blending operation mode
>>   * @flush_mask:	mixer flush mask for ctl, mixer and pipe
>>   */
>>  struct dpu_crtc_mixer {
>>  	struct dpu_hw_mixer *hw_lm;
>>  	struct dpu_hw_ctl *lm_ctl;
>> +	struct dpu_hw_pingpong *hw_pp;
>>  	u32 mixer_op_mode;
>>  	u32 flush_mask;
>>  };
>> @@ -230,6 +232,18 @@ struct dpu_crtc_state {
>> 
>>  	u32 num_ctls;
>>  	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
>> +
>> +	/**
>> +	 * as drm encoders doesn't have dedicates state objects
>> +	 * and drm connectors are not owned by DPU, maintain
>> +	 * HW interface and other interface related blocks
>> +	 * in crtc state
> 
> Can you use private state instead?
hmm.. It's time for me to revisit the old patch:
https://patchwork.freedesktop.org/patch/230100/
> 
>> +	 *
>> +	 * TODO: No support for clone mode yet where a crtc
>> +	 * can be attached with more than one encoder/connector.
>> +	 */
>> +	u32 num_intfs;
>> +	struct dpu_hw_intf *hw_intfs[CRTC_DUAL_MIXERS];
>>  };
>> 
>>  #define to_dpu_crtc_state(x) \
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index d12f896..17dbbc3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -1001,9 +1001,8 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  	struct dpu_kms *dpu_kms;
>>  	struct list_head *connector_list;
>>  	struct drm_connector *conn = NULL, *conn_iter;
>> -	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>> +	struct dpu_crtc_state *dpu_cstate;
>>  	struct msm_display_topology topology;
>> -	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>>  	int i = 0, ret;
>> 
>>  	if (!drm_enc) {
>> @@ -1043,27 +1042,14 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  		return;
>>  	}
>> 
>> -	dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id,
> DPU_HW_BLK_PINGPONG);
>> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
>> -		dpu_enc->hw_pp[i] = NULL;
>> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
>> -			break;
>> -		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
>> -	}
>> -
>> -	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
>> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
>> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
>> -			break;
>> -		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
>> -	}
>> +	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
>> 
>>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>>  		int ctl_index;
>> 
>>  		if (phys) {
>> -			if (!dpu_enc->hw_pp[i]) {
>> +			if (!dpu_cstate->mixers[i].hw_pp) {
>>  				DPU_ERROR_ENC(dpu_enc, "no pp block
> assigned"
>>  					     "at idx: %d\n", i);
>>  				return;
>> @@ -1071,14 +1057,16 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>> 
>>  			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
> : 0;
>> 
>> -			if (!hw_ctl[ctl_index]) {
>> +			if (!dpu_cstate->hw_ctls[ctl_index]) {
>>  				DPU_ERROR_ENC(dpu_enc, "no ctl block
> assigned"
>>  					     "at idx: %d\n", ctl_index);
>>  				return;
>>  			}
>> 
>> -			phys->hw_pp = dpu_enc->hw_pp[i];
>> -			phys->hw_ctl = hw_ctl[ctl_index];
>> +			dpu_enc->hw_pp[i] = dpu_cstate->mixers[i].hw_pp;
>> +
>> +			phys->hw_pp = dpu_cstate->mixers[i].hw_pp;
>> +			phys->hw_ctl = dpu_cstate->hw_ctls[ctl_index];
>> 
>>  			phys->connector = conn->state->connector;
>>  			if (phys->ops.mode_set)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> index 84de385..4563f8d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> @@ -461,28 +461,20 @@ static int
> dpu_encoder_phys_vid_control_vblank_irq(
>> 
>>  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys
> *phys_enc)
>>  {
>> -	struct msm_drm_private *priv;
>>  	struct dpu_encoder_phys_vid *vid_enc;
>> -	struct dpu_rm_hw_iter iter;
>>  	struct dpu_hw_ctl *ctl;
>> +	struct dpu_crtc_state *dpu_cstate;
>> +	int i;
>>  	u32 flush_mask = 0;
>> 
>> -	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
>> -			!phys_enc->parent->dev->dev_private) {
>> -		DPU_ERROR("invalid encoder/device\n");
>> -		return;
>> -	}
>> -	priv = phys_enc->parent->dev->dev_private;
>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>> 
>>  	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
>>  	ctl = phys_enc->hw_ctl;
>> 
>> -	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id,
> DPU_HW_BLK_INTF);
>> -	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
>> -		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf
> *)iter.hw;
>> -
>> -		if (hw_intf->idx == phys_enc->intf_idx) {
>> -			vid_enc->hw_intf = hw_intf;
>> +	for (i = 0; i < dpu_cstate->num_intfs; i++) {
>> +		if (dpu_cstate->hw_intfs[i]->idx == phys_enc->intf_idx) {
>> +			vid_enc->hw_intf = dpu_cstate->hw_intfs[i];
>>  			break;
>>  		}
>>  	}
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index 377def7..5703b11 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -388,6 +388,7 @@ static bool 
>> _dpu_rm_check_lm_and_get_connected_blks(
>>  }
>> 
>>  static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>> +			       struct dpu_crtc_state *dpu_cstate,
>>  			       struct dpu_rm_requirements *reqs)
>> 
>>  {
>> @@ -449,16 +450,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm 
>> *rm,
> uint32_t enc_id,
>>  		lm[i]->enc_id = enc_id;
>>  		pp[i]->enc_id = enc_id;
>> 
>> +		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
>> +		dpu_cstate->mixers[i].hw_pp =
> to_dpu_hw_pingpong(pp[i]->hw);
>> +
>>  		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
>>  					 pp[i]->id);
>>  	}
>> 
>> +	dpu_cstate->num_mixers = lm_count;
>> +
>>  	return rc;
>>  }
>> 
>>  static int _dpu_rm_reserve_ctls(
>>  		struct dpu_rm *rm,
>>  		uint32_t enc_id,
>> +		struct dpu_crtc_state *dpu_cstate,
>>  		const struct msm_display_topology *top)
>>  {
>>  	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
>> @@ -501,21 +508,24 @@ static int _dpu_rm_reserve_ctls(
>> 
>>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
>>  		ctls[i]->enc_id = enc_id;
>> +		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
>> +
>>  		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
>>  					  enc_id);
>>  	}
>> 
>> +	dpu_cstate->num_ctls = num_ctls;
>> +
>>  	return 0;
>>  }
>> 
>> -static int _dpu_rm_reserve_intf(
>> +static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>>  		struct dpu_rm *rm,
>>  		uint32_t enc_id,
>>  		uint32_t id,
>>  		enum dpu_hw_blk_type type)
>>  {
>>  	struct dpu_rm_hw_iter iter;
>> -	int ret = 0;
>> 
>>  	/* Find the block entry in the rm, and note the reservation */
>>  	dpu_rm_init_hw_iter(&iter, 0, type);
>> @@ -525,7 +535,7 @@ static int _dpu_rm_reserve_intf(
>> 
>>  		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
>>  			DPU_ERROR("type %d id %d already reserved\n",
> type, id);
>> -			return -ENAVAIL;
>> +			return NULL;
>>  		}
>> 
>>  		iter.blk->enc_id = enc_id;
>> @@ -535,56 +545,63 @@ static int _dpu_rm_reserve_intf(
>>  	}
>> 
>>  	/* Shouldn't happen since intfs are fixed at probe */
>> -	if (!iter.hw) {
>> +	if (!iter.blk) {
>>  		DPU_ERROR("couldn't find type %d id %d\n", type, id);
>> -		return -EINVAL;
>> +		return NULL;
>>  	}
>> 
>> -	return ret;
>> +	return iter.blk;
>>  }
>> 
>>  static int _dpu_rm_reserve_intf_related_hw(
>>  		struct dpu_rm *rm,
>>  		uint32_t enc_id,
>> +		struct dpu_crtc_state *dpu_cstate,
>>  		struct dpu_encoder_hw_resources *hw_res)
>>  {
>> -	int i, ret = 0;
>> -	u32 id;
>> +	struct dpu_rm_hw_blk *blk;
>> +	int i, num_intfs = 0;
>> 
>>  	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
>>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>>  			continue;
>> -		id = i + INTF_0;
>> -		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
>> +
>> +		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
>>  				DPU_HW_BLK_INTF);
>> -		if (ret)
>> -			return ret;
>> +		if (!blk)
>> +			return -ENAVAIL;
>> +
>> +		dpu_cstate->hw_intfs[num_intfs++] =
> to_dpu_hw_intf(blk->hw);
>>  	}
>> 
>> -	return ret;
>> +	dpu_cstate->num_intfs = num_intfs;
>> +
>> +	return 0;
>>  }
>> 
>>  static int _dpu_rm_make_reservation(
>>  		struct dpu_rm *rm,
>>  		struct drm_encoder *enc,
>> -		struct drm_crtc_state *crtc_state,
>> +		struct dpu_crtc_state *dpu_cstate,
>>  		struct dpu_rm_requirements *reqs)
>>  {
>>  	int ret;
>> 
>> -	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
>> +	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
>>  	if (ret) {
>>  		DPU_ERROR("unable to find appropriate mixers\n");
>>  		return ret;
>>  	}
>> 
>> -	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
>> +	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
>> +				   &reqs->topology);
>>  	if (ret) {
>>  		DPU_ERROR("unable to find appropriate CTL\n");
>>  		return ret;
>>  	}
>> 
>> -	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id,
> &reqs->hw_res);
>> +	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id,
> dpu_cstate,
>> +					      &reqs->hw_res);
>>  	if (ret)
>>  		return ret;
>> 
>> @@ -594,7 +611,6 @@ static int _dpu_rm_make_reservation(
>>  static int _dpu_rm_populate_requirements(
>>  		struct dpu_rm *rm,
>>  		struct drm_encoder *enc,
>> -		struct drm_crtc_state *crtc_state,
>>  		struct dpu_rm_requirements *reqs,
>>  		struct msm_display_topology req_topology)
>>  {
>> @@ -642,6 +658,7 @@ int dpu_rm_reserve(
>>  		bool test_only)
>>  {
>>  	struct dpu_rm_requirements reqs;
>> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>>  	int ret;
>> 
>>  	/* Check if this is just a page-flip */
>> @@ -653,14 +670,13 @@ int dpu_rm_reserve(
>> 
>>  	mutex_lock(&rm->rm_lock);
>> 
>> -	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
>> -					    topology);
>> +	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
>>  	if (ret) {
>>  		DPU_ERROR("failed to populate hw requirements\n");
>>  		goto end;
>>  	}
>> 
>> -	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
>> +	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
>>  	if (ret) {
>>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>>  		_dpu_rm_release_reservation(rm, enc->base.id);
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Freedreno@lists.freedesktop.org
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Re: [Freedreno] [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Sean Paul]

On Tue, Oct 09, 2018 at 10:46:41PM -0700, Jeykumar Sankaran wrote:
> On 2018-10-09 11:07, Sean Paul wrote:
> > On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
> > > Layer mixer/pingpong block counts and hw ctl block counts
> > > will not be same for all the topologies (e.g. layer
> > > mixer muxing to single interface)
> > > 
> > > Use the encoder's split_role info to retrieve the
> > > respective control path for programming.
> > > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index 96cdf06..d12f896 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > > 
> > >  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > >  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > > +		int ctl_index;
> > > 
> > >  		if (phys) {
> > >  			if (!dpu_enc->hw_pp[i]) {
> > > @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > >  				return;
> > >  			}
> > > 
> > > -			if (!hw_ctl[i]) {
> > > +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
> > : 0;
> > > +
> > 
> > What if MAX_CHANNELS_PER_ENC isn't 2? Similarly, what if num_phys_encs >
> > MAX_CHANNELS_PER_ENC? It seems like there should be a more formal
> > relationship
> > between all of these verious values (num_of_h_tiles assumed to be <= 2
> > as
> > well).
> > If one of them changes beyond the assumed bound, the rest of the driver
> > falls
> > over pretty hard.
> > 
> MAX_CHANNELS_PER_ENC is set to 2 to represent HW limitation on the chipset
> as
> we cannot gang up more than 2 LM chain to an interface. Supporting more than
> 2
> might demand much larger changes than validating for boundaries.
> 
> num_phys_enc is the max no of phys encoders we create as we are looping
> through
> num_of_h_tiles which cannot be more than priv->dsi array size.
> 
> So its very unlikely we would expect these loops to go out of bound!

For now, sure. However a new revision of hardware will be a pain to add support
for if we add more assumptions, and secondly it makes it _really_ hard to
understand the code if you don't have Qualcomm employee-level access to the
hardware design :).

So this is why I'm advocating for the reduction of the number of "num_of_"
values we assume are all in the same range. It's a lot easier to understand the
hardware when you can see that a phys encoder is needed per h tile, and that a
ctl/pp is needed per phys encoder.

Anyways, just my $0.02.

Sean

> 
> Thanks,
> Jeykumar S.
> > 
> > > +			if (!hw_ctl[ctl_index]) {
> > >  				DPU_ERROR_ENC(dpu_enc, "no ctl block
> > assigned"
> > > -					     "at idx: %d\n", i);
> > > +					     "at idx: %d\n", ctl_index);
> > >  				return;
> > 
> > When you return on error here, should you give back the resources that
> > you've
> > already provisioned?
> > 
> > >  			}
> > > 
> > >  			phys->hw_pp = dpu_enc->hw_pp[i];
> > > -			phys->hw_ctl = hw_ctl[i];
> > > +			phys->hw_ctl = hw_ctl[ctl_index];
> > > 
> > >  			phys->connector = conn->state->connector;
> > >  			if (phys->ops.mode_set)
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> > > _______________________________________________
> > > Freedreno mailing list
> > > Freedreno@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/freedreno
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [PATCH 22/25] drm/msm/dpu: make crtc and encoder specific HW reservation

[Sean Paul]

On Tue, Oct 09, 2018 at 11:15:02PM -0700, Jeykumar Sankaran wrote:
> On 2018-10-09 13:41, Sean Paul wrote:
> > On Mon, Oct 08, 2018 at 09:27:39PM -0700, Jeykumar Sankaran wrote:
> > > Instead of letting encoder make a centralized reservation for
> > > all of its display DRM components, this path splits the
> > > responsibility between CRTC and Encoder, each requesting
> > > RM for the HW mapping of its own domain.
> > > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    | 31 +++++++++++++
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++----
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69
> > ++++++++++++++++++++++++-----
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      | 36 +++++++++++----
> > >  4 files changed, 119 insertions(+), 31 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > index 0625f56..0536b8a 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > @@ -47,6 +47,8 @@
> > >  #define LEFT_MIXER 0
> > >  #define RIGHT_MIXER 1
> > > 
> > > +#define MAX_VDISPLAY_SPLIT 1080
> > > +
> > >  static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state
> > *cstate,
> > >  					    struct drm_display_mode *mode)
> > >  {
> > > @@ -448,6 +450,7 @@ static void _dpu_crtc_setup_lm_bounds(struct
> > drm_crtc *crtc,
> > > 
> > >  	for (i = 0; i < cstate->num_mixers; i++) {
> > >  		struct drm_rect *r = &cstate->lm_bounds[i];
> > > +
> > >  		r->x1 = crtc_split_width * i;
> > >  		r->y1 = 0;
> > >  		r->x2 = r->x1 + crtc_split_width;
> > > @@ -885,6 +888,7 @@ static void dpu_crtc_disable(struct drm_crtc
> > > *crtc)
> > >  	struct drm_display_mode *mode;
> > >  	struct drm_encoder *encoder;
> > >  	struct msm_drm_private *priv;
> > > +	struct dpu_kms *dpu_kms;
> > >  	unsigned long flags;
> > > 
> > >  	if (!crtc || !crtc->dev || !crtc->dev->dev_private ||
> > !crtc->state) {
> > > @@ -895,6 +899,7 @@ static void dpu_crtc_disable(struct drm_crtc
> > > *crtc)
> > >  	cstate = to_dpu_crtc_state(crtc->state);
> > >  	mode = &cstate->base.adjusted_mode;
> > >  	priv = crtc->dev->dev_private;
> > > +	dpu_kms = to_dpu_kms(priv->kms);
> > > 
> > >  	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
> > > 
> > > @@ -953,6 +958,8 @@ static void dpu_crtc_disable(struct drm_crtc
> > > *crtc)
> > >  		crtc->state->event = NULL;
> > >  		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
> > >  	}
> > > +
> > > +	dpu_rm_crtc_release(&dpu_kms->rm, crtc->state);
> > >  }
> > > 
> > >  static void dpu_crtc_enable(struct drm_crtc *crtc,
> > > @@ -1004,6 +1011,21 @@ struct plane_state {
> > >  	u32 pipe_id;
> > >  };
> > > 
> > > +static void _dpu_crtc_get_topology(
> > > +			struct drm_crtc_state *crtc_state,
> > > +			struct drm_display_mode *mode)
> > > +{
> > > +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > > +
> > > +	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2
> > : 1;
> > > +
> > > +	/**
> > > +	 * encoder->atomic_check is invoked before crtc->atomic_check.
> > > +	 * so dpu_cstate->num_intfs should have a non-zero value.
> > > +	 */
> > > +	dpu_cstate->num_ctls = dpu_cstate->num_intfs;
> > 
> > Why do we need num_ctls? Can't we just use dpu_cstate->num_intfs
> > directly?
> > Also,
> > you don't really need these in their own function, especially if
> > num_ctls
> > goes
> > away.
> > 
> Yes. I can live with just that. But since dpu_cstate maintains HW arrays
> for each type, I thought it would be more readable if I could use
> separate variables to track their counts instead of iterating over
> ctl arrays over dpu_cstate->num_intfs and leaving comments that both
> will be same for this version of hardware.

You could change the name to make it more generic. AFAICT,

num_h_tiles == num_phys_encs == num_intfs == num_ctls

So storing it as num_h_tiles might make more sense.

> 
> Also, the counts need not be the same for all the Snapdragon variants.

This is probably a good thing. It doesn't seem like the current driver would
work if these values were different, so making it explicit is a good signal that
more invasive changes are needed.

Sean

> 
> Thanks,
> Jeykumar S.
> > > +}
> > > +
> > >  static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
> > >  		struct drm_crtc_state *state)
> > >  {
> > > @@ -1014,6 +1036,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> > *crtc,
> > >  	const struct drm_plane_state *pstate;
> > >  	struct drm_plane *plane;
> > >  	struct drm_display_mode *mode;
> > > +	struct msm_drm_private *priv;
> > > +	struct dpu_kms *dpu_kms;
> > > 
> > >  	int cnt = 0, rc = 0, mixer_width, i, z_pos;
> > > 
> > > @@ -1039,6 +1063,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> > *crtc,
> > >  		goto end;
> > >  	}
> > > 
> > > +	priv = crtc->dev->dev_private;
> > > +	dpu_kms = to_dpu_kms(priv->kms);
> > > +
> > >  	mode = &state->adjusted_mode;
> > >  	DPU_DEBUG("%s: check", dpu_crtc->name);
> > > 
> > > @@ -1229,6 +1256,10 @@ static int dpu_crtc_atomic_check(struct
> > > drm_crtc
> > *crtc,
> > >  		}
> > >  	}
> > > 
> > > +	_dpu_crtc_get_topology(state, mode);
> > > +	if (drm_atomic_crtc_needs_modeset(state))
> > > +		rc = dpu_rm_crtc_reserve(&dpu_kms->rm, state);
> > > +
> > >  end:
> > >  	kfree(pstates);
> > >  	return rc;
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index 5d501c8..ce66309 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -67,8 +67,6 @@
> > > 
> > >  #define IDLE_SHORT_TIMEOUT	1
> > > 
> > > -#define MAX_VDISPLAY_SPLIT 1080
> > > -
> > >  /**
> > >   * enum dpu_enc_rc_events - events for resource control state machine
> > >   * @DPU_ENC_RC_EVENT_KICKOFF:
> > > @@ -557,14 +555,10 @@ static void _dpu_encoder_adjust_mode(struct
> > drm_connector *connector,
> > > 
> > >  static void _dpu_encoder_get_topology(
> > >  			struct dpu_encoder_virt *dpu_enc,
> > > -			struct drm_crtc_state *crtc_state,
> > > -			struct drm_display_mode *mode)
> > > +			struct drm_crtc_state *crtc_state)
> > >  {
> > >  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > > 
> > > -	/* User split topology for width > 1080 */
> > > -	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2
> > : 1;
> > > -	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
> > >  	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
> > >  }
> > > 
> > > @@ -623,9 +617,9 @@ static int dpu_encoder_virt_atomic_check(
> > >  		}
> > >  	}
> > > 
> > > -	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
> > > +	_dpu_encoder_get_topology(dpu_enc, crtc_state);
> > >  	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
> > > -		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
> > > +		ret = dpu_rm_encoder_reserve(&dpu_kms->rm, drm_enc,
> > crtc_state);
> > > 
> > >  	if (!ret)
> > >  		drm_mode_set_crtcinfo(adj_mode, 0);
> > > @@ -1186,7 +1180,7 @@ static void dpu_encoder_virt_disable(struct
> > drm_encoder *drm_enc)
> > > 
> > >  	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
> > > 
> > > -	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);
> > > +	dpu_rm_encoder_release(&dpu_kms->rm, drm_enc->crtc->state);
> > >  }
> > > 
> > >  static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg
> > > *catalog,
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > index 5304597..901b1fc 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > @@ -436,8 +436,8 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm,
> > enum dpu_hw_blk_type type,
> > >  	return -EINVAL;
> > >  }
> > > 
> > > -static void _dpu_rm_release_reservation(struct dpu_rm *rm,
> > > -					struct dpu_crtc_state *dpu_cstate)
> > > +static void _dpu_rm_crtc_release_reservation(struct dpu_rm *rm,
> > > +					     struct dpu_crtc_state
> > *dpu_cstate)
> > >  {
> > >  	int i;
> > > 
> > > @@ -464,6 +464,12 @@ static void _dpu_rm_release_reservation(struct
> > dpu_rm *rm,
> > >  					dpu_cstate->hw_ctls[i]->base.id))
> > >  			dpu_cstate->hw_ctls[i] = NULL;
> > >  	}
> > > +}
> > > +
> > > +static void _dpu_rm_encoder_release_reservation(struct dpu_rm *rm,
> > > +					      struct dpu_crtc_state
> > *dpu_cstate)
> > > +{
> > > +	int i;
> > > 
> > >  	for (i = 0; i < dpu_cstate->num_intfs; i++) {
> > >  		if (!dpu_cstate->hw_intfs[i])
> > > @@ -475,23 +481,33 @@ static void _dpu_rm_release_reservation(struct
> > dpu_rm *rm,
> > >  	}
> > >  }
> > > 
> > > -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state
> > *crtc_state)
> > > +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state
> > *crtc_state)
> > >  {
> > >  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > > 
> > >  	mutex_lock(&rm->rm_lock);
> > > 
> > > -	_dpu_rm_release_reservation(rm, dpu_cstate);
> > > +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
> > > 
> > >  	mutex_unlock(&rm->rm_lock);
> > >  }
> > > 
> > > -int dpu_rm_reserve(
> > > +void dpu_rm_encoder_release(struct dpu_rm *rm,
> > > +			    struct drm_crtc_state *crtc_state)
> > > +{
> > > +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > > +
> > > +	mutex_lock(&rm->rm_lock);
> > > +
> > > +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
> > > +
> > > +	mutex_unlock(&rm->rm_lock);
> > > +}
> > > +
> > > +int dpu_rm_crtc_reserve(
> > >  		struct dpu_rm *rm,
> > > -		struct drm_encoder *enc,
> > >  		struct drm_crtc_state *crtc_state)
> > >  {
> > > -	struct dpu_encoder_hw_resources hw_res;
> > >  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > >  	int ret;
> > > 
> > > @@ -499,12 +515,10 @@ int dpu_rm_reserve(
> > >  	if (!drm_atomic_crtc_needs_modeset(crtc_state))
> > >  		return 0;
> > > 
> > > -	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
> > > -		      enc->base.id, crtc_state->crtc->base.id);
> > > 
> > > -	mutex_lock(&rm->rm_lock);
> > > +	DRM_DEBUG_KMS("reserving hw for crtc %d\n",
> > crtc_state->crtc->base.id);
> > > 
> > > -	dpu_encoder_get_hw_resources(enc, &hw_res);
> > > +	mutex_lock(&rm->rm_lock);
> > > 
> > >  	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
> > >  	if (ret) {
> > > @@ -518,6 +532,37 @@ int dpu_rm_reserve(
> > >  		goto cleanup_on_fail;
> > >  	}
> > > 
> > > +	mutex_unlock(&rm->rm_lock);
> > > +
> > > +	return ret;
> > > +
> > > +cleanup_on_fail:
> > > +	_dpu_rm_crtc_release_reservation(rm, dpu_cstate);
> > > +
> > > +	mutex_unlock(&rm->rm_lock);
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +int dpu_rm_encoder_reserve(
> > > +		struct dpu_rm *rm,
> > > +		struct drm_encoder *enc,
> > > +		struct drm_crtc_state *crtc_state)
> > > +{
> > > +	struct dpu_encoder_hw_resources hw_res;
> > > +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> > > +	int ret;
> > > +
> > > +	/* Check if this is just a page-flip */
> > > +	if (!drm_atomic_crtc_needs_modeset(crtc_state))
> > > +		return 0;
> > > +
> > > +	DRM_DEBUG_KMS("reserving hw for enc %d\n", enc->base.id);
> > > +
> > > +	mutex_lock(&rm->rm_lock);
> > > +
> > > +	dpu_encoder_get_hw_resources(enc, &hw_res);
> > > +
> > >  	ret = _dpu_rm_reserve_intfs(rm, dpu_cstate, &hw_res);
> > >  	if (ret) {
> > >  		DPU_ERROR("unable to find appropriate INTF\n");
> > > @@ -529,7 +574,7 @@ int dpu_rm_reserve(
> > >  	return ret;
> > > 
> > >  cleanup_on_fail:
> > > -	_dpu_rm_release_reservation(rm, dpu_cstate);
> > > +	_dpu_rm_encoder_release_reservation(rm, dpu_cstate);
> > > 
> > >  	mutex_unlock(&rm->rm_lock);
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > index 1626cef..0b1deb0 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > @@ -53,27 +53,45 @@ int dpu_rm_init(struct dpu_rm *rm,
> > >  int dpu_rm_destroy(struct dpu_rm *rm);
> > > 
> > >  /**
> > > - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain,
> > analyze
> > > - *	the use connections and user requirements, specified through
> > related
> > > + * dpu_rm_encoder_reserve - Given an Encoder, analyze the use
> > connections
> > > + *      and user requirements, specified through related
> > >   *	topology control properties, and reserve hardware blocks to that
> > >   *	display chain.
> > > - *	HW blocks can then be accessed through dpu_rm_get_* functions.
> > > - *	HW Reservations should be released via dpu_rm_release_hw.
> > >   * @rm: DPU Resource Manager handle
> > >   * @drm_enc: DRM Encoder handle
> > >   * @crtc_state: Proposed Atomic DRM CRTC State handle
> > >   * @Return: 0 on Success otherwise -ERROR
> > >   */
> > > -int dpu_rm_reserve(struct dpu_rm *rm,
> > > +int dpu_rm_encoder_reserve(struct dpu_rm *rm,
> > >  		struct drm_encoder *drm_enc,
> > >  		struct drm_crtc_state *crtc_state);
> > > 
> > >  /**
> > > - * dpu_rm_release - Given the encoder for the display chain, release
> > any
> > > - *	HW blocks previously reserved for that use case.
> > > + * dpu_rm_crtc_reserve - Given a CRTC, analyze the use connections
> > > + *      and user requirements, specified through related
> > > + *	topology control properties, and reserve hardware blocks to that
> > > + *	display chain.
> > >   * @rm: DPU Resource Manager handle
> > > - * @crtc_state: atomic DRM state handle
> > > + * @crtc_state: Proposed Atomic DRM CRTC State handle
> > >   * @Return: 0 on Success otherwise -ERROR
> > >   */
> > > -void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state
> > *crtc_state);
> > > +int dpu_rm_crtc_reserve(struct dpu_rm *rm,
> > > +		struct drm_crtc_state *crtc_state);
> > > +
> > > +/**
> > > + * dpu_rm_encoder_release - Given the encoder, release any
> > > + *	HW blocks previously reserved for that use case.
> > > + * @rm: DPU Resource Manager handle
> > > + * @crtc_state: Proposed Atomic DRM CRTC State handle
> > > + */
> > > +void dpu_rm_encoder_release(struct dpu_rm *rm,
> > > +			    struct drm_crtc_state *crtc_state);
> > > +
> > > +/**
> > > + * dpu_rm_crtc_release - Given the crtc, release any
> > > + *	HW blocks previously reserved for that use case.
> > > + * @rm: DPU Resource Manager handle
> > > + * @crtc_state: Proposed Atomic DRM CRTC State handle
> > > + */
> > > +void dpu_rm_crtc_release(struct dpu_rm *rm, struct drm_crtc_state
> > *crtc_state);
> > >  #endif /* __DPU_RM_H__ */
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> > > _______________________________________________
> > > Freedreno mailing list
> > > Freedreno@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/freedreno
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces

[Sean Paul]

On Tue, Oct 09, 2018 at 11:03:24PM -0700, Jeykumar Sankaran wrote:
> On 2018-10-09 12:57, Sean Paul wrote:
> > On Mon, Oct 08, 2018 at 09:27:41PM -0700, Jeykumar Sankaran wrote:
> > > Since HW reservations are happening through atomic_check
> > > and all the display commits are catered by a single commit thread,
> > > it is not necessary to protect the interfaces by a separate
> > > mutex.
> > > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24 ------------------------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
> > >  2 files changed, 26 deletions(-)
> > > 
> > 
> > /snip
> > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > index 8676fa5..9acbeba 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > @@ -24,11 +24,9 @@
> > >   * struct dpu_rm - DPU dynamic hardware resource manager
> > >   * @hw_blks: array of lists of hardware resources present in the
> > system, one
> > >   *	list per type of hardware block
> > > - * @rm_lock: resource manager mutex
> > >   */
> > >  struct dpu_rm {
> > >  	struct list_head hw_blks[DPU_HW_BLK_MAX];
> > 
> > At this point, there's really not much point to even having the rm. It's
> > just
> > another level of indirection that IMO complicates the code. If you look
> > at the usage of hw_blks, the code is always looking at a specific type
> > of
> > hw_blk, so the array is unnecessary.
> > 
> > dpu_kms could just keep a few arrays/lists of the hw types, and the crtc
> > and encoder
> > reserve functions can just go in crtc/encoder.
> > 
> > Sean
> > 
> RM has been reduced to its current form to manage only LM/PP, CTL and
> interfaces.
> Our eventual plan is to support all the advanced HW blocks and its features
> in
> an upstream friendly way. When RM grows to manage all its subblocks,
> iteration
> logic may get heavy since the chipset have HW chain restrictions on various
> hw blocks.
> To provide room for the growth, I suggest keeping the allocation
> helpers in a separate file. But I can see why you want to maintain the HW
> block lists
> in the KMS.

At least for the blocks that exist, using the RM is unnecessary, does that
change for the current blocks when you add more? I'm guessing their code will
remain unchanged.

If the new blocks you're adding have a lot of commonality, perhaps it makes
sense to re-introduce the RM, but IMO it doesn't make sense for lm/ctl/pp.

Sean

> 
> Thanks,
> Jeykumar S.
> > > -	struct mutex rm_lock;
> > >  };
> > > 
> > >  /**
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> > > _______________________________________________
> > > Freedreno mailing list
> > > Freedreno@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/freedreno
> 
> -- 
> Jeykumar S

-- 
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Re: [PATCH 08/25] drm/msm/dpu: release reservation using crtc state

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:25PM -0700, Jeykumar Sankaran wrote:
> Use the hw block pointers stored in crtc state to
> release them back to RM resource pool. This change
> is made to uncouple RM reservation from encoder_id.
> Separate change is submitted to clean up RM of
> encoder id tagging.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 69 +++++++++++++++++++++++------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      |  6 +--
>  3 files changed, 60 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 17dbbc3..a8fd14e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1223,7 +1223,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
>  
>  	DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
>  
> -	dpu_rm_release(&dpu_kms->rm, drm_enc);
> +	dpu_rm_release(&dpu_kms->rm, drm_enc->crtc->state);

From drm_encoder.h:

        * @crtc: Currently bound CRTC, only really meaningful for non-atomic
        * drivers.  Atomic drivers should instead check
        * &drm_connector_state.crtc.


>  }
>  
>  static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 5703b11..619b596 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -625,27 +625,70 @@ static int _dpu_rm_populate_requirements(
>  	return 0;
>  }
>  
> -static void _dpu_rm_release_reservation(struct dpu_rm *rm, uint32_t enc_id)
> +static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
> +			      int id)
>  {
>  	struct dpu_rm_hw_blk *blk;
> -	enum dpu_hw_blk_type type;
>  
> -	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
> -		list_for_each_entry(blk, &rm->hw_blks[type], list) {
> -			if (blk->enc_id == enc_id) {
> -				blk->enc_id = 0;
> -				DPU_DEBUG("rel enc %d %d %d\n", enc_id,
> -					  blk->type, blk->id);
> -			}
> +	list_for_each_entry(blk, &rm->hw_blks[type], list) {
> +		if (blk->hw->id == id) {
> +			blk->enc_id = 0;
> +			return 0;
>  		}
>  	}
> +
> +	DRM_DEBUG_KMS("failed to find hw id(%d) of type(%d) for releasing\n",
> +		      id, type);
> +
> +	return -EINVAL;
>  }
>  
> -void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc)
> +static void _dpu_rm_release_reservation(struct dpu_rm *rm,
> +					struct dpu_crtc_state *dpu_cstate)
>  {
> +	int i;
> +
> +	for (i = 0; i < dpu_cstate->num_mixers; i++) {
> +		struct dpu_crtc_mixer *mixer = &dpu_cstate->mixers[i];
> +
> +		if (!mixer->hw_lm)
> +			continue;
> +
> +		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_LM,
> +					mixer->hw_lm->base.id))
> +			mixer->hw_lm = NULL;
> +
> +		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_PINGPONG,
> +					mixer->hw_pp->base.id))
> +			mixer->hw_pp = NULL;
> +	}
> +
> +	for (i = 0; i < dpu_cstate->num_ctls; i++) {
> +		if (!dpu_cstate->hw_ctls[i])
> +			continue;
> +
> +		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_CTL,
> +					dpu_cstate->hw_ctls[i]->base.id))
> +			dpu_cstate->hw_ctls[i] = NULL;
> +	}
> +
> +	for (i = 0; i < dpu_cstate->num_intfs; i++) {
> +		if (!dpu_cstate->hw_intfs[i])
> +			continue;
> +
> +		if (!_dpu_rm_release_hw(rm, DPU_HW_BLK_INTF,
> +					dpu_cstate->hw_intfs[i]->base.id))
> +			dpu_cstate->hw_intfs[i] = NULL;
> +	}
> +}
> +
> +void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
> +{
> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> +
>  	mutex_lock(&rm->rm_lock);
>  
> -	_dpu_rm_release_reservation(rm, enc->base.id);
> +	_dpu_rm_release_reservation(rm, dpu_cstate);
>  
>  	mutex_unlock(&rm->rm_lock);
>  }
> @@ -679,12 +722,12 @@ int dpu_rm_reserve(
>  	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
>  	if (ret) {
>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
> -		_dpu_rm_release_reservation(rm, enc->base.id);
> +		_dpu_rm_release_reservation(rm, dpu_cstate);
>  	} else if (test_only) {
>  		 /* test_only: test the reservation and then undo */
>  		DPU_DEBUG("test_only: discard test [enc: %d]\n",
>  				enc->base.id);
> -		_dpu_rm_release_reservation(rm, enc->base.id);
> +		_dpu_rm_release_reservation(rm, dpu_cstate);
>  	}
>  
>  end:
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index eb6a6ac..e48e8f2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -95,13 +95,13 @@ int dpu_rm_reserve(struct dpu_rm *rm,
>  		bool test_only);
>  
>  /**
> - * dpu_rm_reserve - Given the encoder for the display chain, release any
> + * dpu_rm_release - Given the encoder for the display chain, release any
>   *	HW blocks previously reserved for that use case.
>   * @rm: DPU Resource Manager handle
> - * @enc: DRM Encoder handle
> + * @crtc_state: atomic DRM state handle
>   * @Return: 0 on Success otherwise -ERROR
>   */
> -void dpu_rm_release(struct dpu_rm *rm, struct drm_encoder *enc);
> +void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
>  
>  /**
>   * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 09/25] drm/msm/dpu: make RM iterator static

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:26PM -0700, Jeykumar Sankaran wrote:
> HW blocks reserved for a display are stored in crtc state.
> No one outside RM is interested in using these API's for
> HW block list iterations.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 37 ++++++++++++++-------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 46 ----------------------------------
>  2 files changed, 20 insertions(+), 63 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 619b596..24fc1c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -49,12 +49,26 @@ struct dpu_rm_hw_blk {
>  	struct dpu_hw_blk *hw;
>  };
>  
> +/**
> + * struct dpu_rm_hw_iter - iterator for use with dpu_rm
> + * @hw: dpu_hw object requested, or NULL on failure
> + * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
> + * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
> + * @type: Hardware Block Type client wishes to search for.
> + */
> +struct dpu_rm_hw_iter {
> +	void *hw;
> +	struct dpu_rm_hw_blk *blk;
> +	uint32_t enc_id;
> +	enum dpu_hw_blk_type type;
> +};
> +
>  struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
>  {
>  	return rm->hw_mdp;
>  }
>  
> -void dpu_rm_init_hw_iter(
> +static void _dpu_rm_init_hw_iter(
>  		struct dpu_rm_hw_iter *iter,
>  		uint32_t enc_id,
>  		enum dpu_hw_blk_type type)
> @@ -97,17 +111,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  	return false;
>  }
>  
> -bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
> -{
> -	bool ret;
> -
> -	mutex_lock(&rm->rm_lock);
> -	ret = _dpu_rm_get_hw_locked(rm, i);
> -	mutex_unlock(&rm->rm_lock);
> -
> -	return ret;
> -}
> -
>  static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
>  {
>  	switch (type) {
> @@ -365,7 +368,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		return false;
>  	}
>  
> -	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
> +	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		if (iter.blk->id == lm_cfg->pingpong) {
>  			*pp = iter.blk;
> @@ -404,7 +407,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  	}
>  
>  	/* Find a primary mixer */
> -	dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
> +	_dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
>  	while (lm_count != reqs->topology.num_lm &&
>  			_dpu_rm_get_hw_locked(rm, &iter_i)) {
>  		memset(&lm, 0, sizeof(lm));
> @@ -421,7 +424,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		++lm_count;
>  
>  		/* Valid primary mixer found, find matching peers */
> -		dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
> +		_dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
>  
>  		while (lm_count != reqs->topology.num_lm &&
>  				_dpu_rm_get_hw_locked(rm, &iter_j)) {
> @@ -480,7 +483,7 @@ static int _dpu_rm_reserve_ctls(
>  
>  	needs_split_display = _dpu_rm_needs_split_display(top);
>  
> -	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
> +	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
>  		unsigned long features = ctl->caps->features;
> @@ -528,7 +531,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  	struct dpu_rm_hw_iter iter;
>  
>  	/* Find the block entry in the rm, and note the reservation */
> -	dpu_rm_init_hw_iter(&iter, 0, type);
> +	_dpu_rm_init_hw_iter(&iter, 0, type);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		if (iter.blk->id != id)
>  			continue;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index e48e8f2..c7e3b2b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -36,26 +36,6 @@ struct dpu_rm {
>  };
>  
>  /**
> - *  struct dpu_rm_hw_blk - resource manager internal structure
> - *	forward declaration for single iterator definition without void pointer
> - */
> -struct dpu_rm_hw_blk;
> -
> -/**
> - * struct dpu_rm_hw_iter - iterator for use with dpu_rm
> - * @hw: dpu_hw object requested, or NULL on failure
> - * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
> - * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
> - * @type: Hardware Block Type client wishes to search for.
> - */
> -struct dpu_rm_hw_iter {
> -	void *hw;
> -	struct dpu_rm_hw_blk *blk;
> -	uint32_t enc_id;
> -	enum dpu_hw_blk_type type;
> -};
> -
> -/**
>   * dpu_rm_init - Read hardware catalog and create reservation tracking objects
>   *	for all HW blocks.
>   * @rm: DPU Resource Manager handle
> @@ -110,30 +90,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
>   * @Return: Pointer to hw block or NULL
>   */
>  struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
> -
> -/**
> - * dpu_rm_init_hw_iter - setup given iterator for new iteration over hw list
> - *	using dpu_rm_get_hw
> - * @iter: iter object to initialize
> - * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
> - * @type: Hardware Block Type client wishes to search for.
> - */
> -void dpu_rm_init_hw_iter(
> -		struct dpu_rm_hw_iter *iter,
> -		uint32_t enc_id,
> -		enum dpu_hw_blk_type type);
> -/**
> - * dpu_rm_get_hw - retrieve reserved hw object given encoder and hw type
> - *	Meant to do a single pass through the hardware list to iteratively
> - *	retrieve hardware blocks of a given type for a given encoder.
> - *	Initialize an iterator object.
> - *	Set hw block type of interest. Set encoder id of interest, 0 for any.
> - *	Function returns first hw of type for that encoder.
> - *	Subsequent calls will return the next reserved hw of that type in-order.
> - *	Iterator HW pointer will be null on failure to find hw.
> - * @rm: DPU Resource Manager handle
> - * @iter: iterator object
> - * @Return: true on match found, false on no match found
> - */
> -bool dpu_rm_get_hw(struct dpu_rm *rm, struct dpu_rm_hw_iter *iter);
>  #endif /* __DPU_RM_H__ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [PATCH 10/25] drm/msm/dpu: maintain hw_mdp in kms

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:27PM -0700, Jeykumar Sankaran wrote:
> hw_mdp block is common for displays. No need
> to reserve per display.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  7 ++++++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  | 20 --------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  | 10 ----------
>  3 files changed, 6 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 8309850..fdc89a8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -689,6 +689,10 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
>  		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
>  	dpu_kms->vbif[VBIF_RT] = NULL;
>  
> +	if (dpu_kms->hw_mdp)
> +		dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
> +	dpu_kms->hw_mdp = NULL;
> +
>  	if (dpu_kms->mmio)
>  		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
>  	dpu_kms->mmio = NULL;
> @@ -1083,7 +1087,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>  
>  	dpu_kms->rm_init = true;
>  
> -	dpu_kms->hw_mdp = dpu_rm_get_mdp(&dpu_kms->rm);
> +	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
> +					     dpu_kms->catalog);
>  	if (IS_ERR_OR_NULL(dpu_kms->hw_mdp)) {
>  		rc = PTR_ERR(dpu_kms->hw_mdp);
>  		if (!dpu_kms->hw_mdp)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 24fc1c7..561120d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -63,11 +63,6 @@ struct dpu_rm_hw_iter {
>  	enum dpu_hw_blk_type type;
>  };
>  
> -struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
> -{
> -	return rm->hw_mdp;
> -}
> -
>  static void _dpu_rm_init_hw_iter(
>  		struct dpu_rm_hw_iter *iter,
>  		uint32_t enc_id,
> @@ -151,9 +146,6 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>  		}
>  	}
>  
> -	dpu_hw_mdp_destroy(rm->hw_mdp);
> -	rm->hw_mdp = NULL;
> -
>  	mutex_destroy(&rm->rm_lock);
>  
>  	return 0;
> @@ -168,11 +160,8 @@ static int _dpu_rm_hw_blk_create(
>  		void *hw_catalog_info)
>  {
>  	struct dpu_rm_hw_blk *blk;
> -	struct dpu_hw_mdp *hw_mdp;
>  	void *hw;
>  
> -	hw_mdp = rm->hw_mdp;
> -
>  	switch (type) {
>  	case DPU_HW_BLK_LM:
>  		hw = dpu_hw_lm_init(id, mmio, cat);
> @@ -236,15 +225,6 @@ int dpu_rm_init(struct dpu_rm *rm,
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++)
>  		INIT_LIST_HEAD(&rm->hw_blks[type]);
>  
> -	/* Some of the sub-blocks require an mdptop to be created */
> -	rm->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, mmio, cat);
> -	if (IS_ERR_OR_NULL(rm->hw_mdp)) {
> -		rc = PTR_ERR(rm->hw_mdp);
> -		rm->hw_mdp = NULL;
> -		DPU_ERROR("failed: mdp hw not available\n");
> -		goto fail;
> -	}
> -
>  	/* Interrogate HW catalog and create tracking items for hw blocks */
>  	for (i = 0; i < cat->mixer_count; i++) {
>  		struct dpu_lm_cfg *lm = &cat->mixer[i];
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index c7e3b2b..7ac1553 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -24,13 +24,11 @@
>   * struct dpu_rm - DPU dynamic hardware resource manager
>   * @hw_blks: array of lists of hardware resources present in the system, one
>   *	list per type of hardware block
> - * @hw_mdp: hardware object for mdp_top
>   * @lm_max_width: cached layer mixer maximum width
>   * @rm_lock: resource manager mutex
>   */
>  struct dpu_rm {
>  	struct list_head hw_blks[DPU_HW_BLK_MAX];
> -	struct dpu_hw_mdp *hw_mdp;
>  	uint32_t lm_max_width;
>  	struct mutex rm_lock;
>  };
> @@ -82,12 +80,4 @@ int dpu_rm_reserve(struct dpu_rm *rm,
>   * @Return: 0 on Success otherwise -ERROR
>   */
>  void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state);
> -
> -/**
> - * dpu_rm_get_mdp - Retrieve HW block for MDP TOP.
> - *	This is never reserved, and is usable by any display.
> - * @rm: DPU Resource Manager handle
> - * @Return: Pointer to hw block or NULL
> - */
> -struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm);
>  #endif /* __DPU_RM_H__ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 11/25] drm/msm/dpu: remove reserve in encoder mode_set

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:28PM -0700, Jeykumar Sankaran wrote:
> Now that we have crtc state tracking the reserved
> HW resources, we have access to them after atomic swap.
> So avoid reserving the resources in mode_set.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 ++---------------
>  1 file changed, 2 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index a8fd14e..dd482ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -636,7 +636,6 @@ static int dpu_encoder_virt_atomic_check(
>  
>  	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
>  
> -	/* Reserve dynamic resources now. Indicating AtomicTest phase */
>  	if (!ret) {
>  		/*
>  		 * Avoid reserving resources when mode set is pending. Topology
> @@ -645,7 +644,7 @@ static int dpu_encoder_virt_atomic_check(
>  		if (drm_atomic_crtc_needs_modeset(crtc_state)
>  				&& dpu_enc->mode_set_complete) {
>  			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> -					     topology, true);
> +					     topology, false);
>  			dpu_enc->mode_set_complete = false;
>  		}
>  	}
> @@ -1002,8 +1001,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  	struct list_head *connector_list;
>  	struct drm_connector *conn = NULL, *conn_iter;
>  	struct dpu_crtc_state *dpu_cstate;
> -	struct msm_display_topology topology;
> -	int i = 0, ret;
> +	int i = 0;
>  
>  	if (!drm_enc) {
>  		DPU_ERROR("invalid encoder\n");
> @@ -1031,17 +1029,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  		return;
>  	}
>  
> -	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
> -
> -	/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
> -	ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state,
> -			     topology, false);
> -	if (ret) {
> -		DPU_ERROR_ENC(dpu_enc,
> -				"failed to reserve hw resources, %d\n", ret);
> -		return;
> -	}
> -
>  	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
>  
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

-- 
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Re: [PATCH 12/25] drm/msm/dpu: remove mode_set_complete

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:29PM -0700, Jeykumar Sankaran wrote:
> This flag was introduced as a fix to notify modeset complete
> when hw reservations were happening in both atomic_check
> and atomic_commit paths. Now that we are reserving only in
> atomic_check, we can get rid of this flag.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 +++----------------
>  1 file changed, 3 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index dd482ca..468b8fd0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -167,7 +167,6 @@ enum dpu_enc_rc_states {
>   *				clks and resources after IDLE_TIMEOUT time.
>   * @vsync_event_work:		worker to handle vsync event for autorefresh
>   * @topology:                   topology of the display
> - * @mode_set_complete:          flag to indicate modeset completion
>   * @idle_timeout:		idle timeout duration in milliseconds
>   */
>  struct dpu_encoder_virt {
> @@ -204,7 +203,6 @@ struct dpu_encoder_virt {
>  	struct kthread_delayed_work delayed_off_work;
>  	struct kthread_work vsync_event_work;
>  	struct msm_display_topology topology;
> -	bool mode_set_complete;
>  
>  	u32 idle_timeout;
>  };
> @@ -636,18 +634,9 @@ static int dpu_encoder_virt_atomic_check(
>  
>  	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
>  
> -	if (!ret) {
> -		/*
> -		 * Avoid reserving resources when mode set is pending. Topology
> -		 * info may not be available to complete reservation.
> -		 */
> -		if (drm_atomic_crtc_needs_modeset(crtc_state)
> -				&& dpu_enc->mode_set_complete) {
> -			ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> -					     topology, false);
> -			dpu_enc->mode_set_complete = false;
> -		}
> -	}
> +	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
> +		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> +				     topology, false);
>  
>  	if (!ret)
>  		drm_mode_set_crtcinfo(adj_mode, 0);
> @@ -1060,8 +1049,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  				phys->ops.mode_set(phys, mode, adj_mode);
>  		}
>  	}
> -
> -	dpu_enc->mode_set_complete = true;
>  }
>  
>  static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 13/25] drm/msm/dpu: make RM iterator hw type specific

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:30PM -0700, Jeykumar Sankaran wrote:
> Usage of hw block iterators are only RM internal. Instead
> of using generic void pointers for HW blocks, use dpu
> specific structure. It helps us to get rid of duplicate
> hw block id's maintained in RM wrapper.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 27 ++++++++++++---------------
>  1 file changed, 12 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 561120d..303f1b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -38,13 +38,11 @@ struct dpu_rm_requirements {
>  /**
>   * struct dpu_rm_hw_blk - hardware block tracking list member
>   * @list:	List head for list of all hardware blocks tracking items
> - * @id:		Hardware ID number, within it's own space, ie. LM_X
>   * @enc_id:	Encoder id to which this blk is binded
>   * @hw:		Pointer to the hardware register access object for this block
>   */
>  struct dpu_rm_hw_blk {
>  	struct list_head list;
> -	uint32_t id;
>  	uint32_t enc_id;
>  	struct dpu_hw_blk *hw;
>  };
> @@ -57,7 +55,7 @@ struct dpu_rm_hw_blk {
>   * @type: Hardware Block Type client wishes to search for.
>   */
>  struct dpu_rm_hw_iter {
> -	void *hw;
> +	struct dpu_hw_blk *hw;
>  	struct dpu_rm_hw_blk *blk;
>  	uint32_t enc_id;
>  	enum dpu_hw_blk_type type;
> @@ -96,7 +94,7 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  		if (i->enc_id == i->blk->enc_id) {
>  			i->hw = i->blk->hw;
>  			DPU_DEBUG("found type %d id %d for enc %d\n",
> -					i->type, i->blk->id, i->enc_id);
> +					i->type, i->blk->hw->id, i->enc_id);
>  			return true;
>  		}
>  	}
> @@ -197,7 +195,6 @@ static int _dpu_rm_hw_blk_create(
>  		return -ENOMEM;
>  	}
>  
> -	blk->id = id;
>  	blk->hw = hw;
>  	blk->enc_id = 0;
>  	list_add_tail(&blk->list, &rm->hw_blks[type]);
> @@ -350,7 +347,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  
>  	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
> -		if (iter.blk->id == lm_cfg->pingpong) {
> +		if (iter.blk->hw->id == lm_cfg->pingpong) {
>  			*pp = iter.blk;
>  			break;
>  		}
> @@ -362,8 +359,8 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  	}
>  
>  	if (RESERVED_BY_OTHER(*pp, enc_id)) {
> -		DPU_DEBUG("lm %d pp %d already reserved\n", lm->id,
> -				(*pp)->id);
> +		DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
> +				(*pp)->hw->id);
>  		return false;
>  	}
>  
> @@ -436,8 +433,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
>  		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
>  
> -		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
> -					 pp[i]->id);
> +		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM, enc_id,
> +					 pp[i]->hw->id);
>  	}
>  
>  	dpu_cstate->num_mixers = lm_count;
> @@ -474,13 +471,13 @@ static int _dpu_rm_reserve_ctls(
>  
>  		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
>  
> -		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
> +		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
>  
>  		if (needs_split_display != has_split_display)
>  			continue;
>  
>  		ctls[i] = iter.blk;
> -		DPU_DEBUG("ctl %d match\n", iter.blk->id);
> +		DPU_DEBUG("ctl %d match\n", iter.blk->hw->id);
>  
>  		if (++i == num_ctls)
>  			break;
> @@ -493,7 +490,7 @@ static int _dpu_rm_reserve_ctls(
>  		ctls[i]->enc_id = enc_id;
>  		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
>  
> -		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
> +		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
>  					  enc_id);
>  	}
>  
> @@ -513,7 +510,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  	/* Find the block entry in the rm, and note the reservation */
>  	_dpu_rm_init_hw_iter(&iter, 0, type);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
> -		if (iter.blk->id != id)
> +		if (iter.blk->hw->id != id)
>  			continue;
>  
>  		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
> @@ -522,7 +519,7 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  		}
>  
>  		iter.blk->enc_id = enc_id;
> -		trace_dpu_rm_reserve_intf(iter.blk->id, DPU_HW_BLK_INTF,
> +		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF,
>  					  enc_id);
>  		break;
>  	}
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 14/25] drm/msm/dpu: remove enc_id tagging for hw blocks

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:31PM -0700, Jeykumar Sankaran wrote:
> RM was using encoder id's to tag HW block's to reserve
> and retrieve later for display pipeline. Now
> that all the reserved HW blocks for a display are
> maintained in its crtc state, no retrieval is needed.
> This patch cleans up RM of encoder id tagging.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c    | 90 +++++++++----------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 28 ++++------
>  2 files changed, 36 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 303f1b3..a8461b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -21,9 +21,6 @@
>  #include "dpu_encoder.h"
>  #include "dpu_trace.h"
>  
> -#define RESERVED_BY_OTHER(h, r)  \
> -		((h)->enc_id && (h)->enc_id != r)
> -
>  /**
>   * struct dpu_rm_requirements - Reservation requirements parameter bundle
>   * @topology:  selected topology for the display
> @@ -38,12 +35,13 @@ struct dpu_rm_requirements {
>  /**
>   * struct dpu_rm_hw_blk - hardware block tracking list member
>   * @list:	List head for list of all hardware blocks tracking items
> - * @enc_id:	Encoder id to which this blk is binded
> + * @in_use:     True, if the hw block is assigned to a display pipeline.
> + *		False, otherwise
>   * @hw:		Pointer to the hardware register access object for this block
>   */
>  struct dpu_rm_hw_blk {
>  	struct list_head list;
> -	uint32_t enc_id;
> +	bool in_use;

How do the reservations work for TEST_ONLY commits? At a quick glance it looks
like they might be marked in_use?

Sean

>  	struct dpu_hw_blk *hw;
>  };
>  
> @@ -51,23 +49,19 @@ struct dpu_rm_hw_blk {
>   * struct dpu_rm_hw_iter - iterator for use with dpu_rm
>   * @hw: dpu_hw object requested, or NULL on failure
>   * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
> - * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for Any Encoder
>   * @type: Hardware Block Type client wishes to search for.
>   */
>  struct dpu_rm_hw_iter {
>  	struct dpu_hw_blk *hw;
>  	struct dpu_rm_hw_blk *blk;
> -	uint32_t enc_id;
>  	enum dpu_hw_blk_type type;
>  };
>  
>  static void _dpu_rm_init_hw_iter(
>  		struct dpu_rm_hw_iter *iter,
> -		uint32_t enc_id,
>  		enum dpu_hw_blk_type type)
>  {
>  	memset(iter, 0, sizeof(*iter));
> -	iter->enc_id = enc_id;
>  	iter->type = type;
>  }
>  
> @@ -91,16 +85,12 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  	i->blk = list_prepare_entry(i->blk, blk_list, list);
>  
>  	list_for_each_entry_continue(i->blk, blk_list, list) {
> -		if (i->enc_id == i->blk->enc_id) {
> +		if (!i->blk->in_use) {
>  			i->hw = i->blk->hw;
> -			DPU_DEBUG("found type %d id %d for enc %d\n",
> -					i->type, i->blk->hw->id, i->enc_id);
>  			return true;
>  		}
>  	}
>  
> -	DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
> -
>  	return false;
>  }
>  
> @@ -196,7 +186,6 @@ static int _dpu_rm_hw_blk_create(
>  	}
>  
>  	blk->hw = hw;
> -	blk->enc_id = 0;
>  	list_add_tail(&blk->list, &rm->hw_blks[type]);
>  
>  	return 0;
> @@ -301,7 +290,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
>   *	proposed use case requirements, incl. hardwired dependent blocks like
>   *	pingpong
>   * @rm: dpu resource manager handle
> - * @enc_id: encoder id requesting for allocation
>   * @reqs: proposed use case requirements
>   * @lm: proposed layer mixer, function checks if lm, and all other hardwired
>   *      blocks connected to the lm (pp) is available and appropriate
> @@ -313,7 +301,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
>   */
>  static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		struct dpu_rm *rm,
> -		uint32_t enc_id,
>  		struct dpu_rm_requirements *reqs,
>  		struct dpu_rm_hw_blk *lm,
>  		struct dpu_rm_hw_blk **pp,
> @@ -339,13 +326,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		}
>  	}
>  
> -	/* Already reserved? */
> -	if (RESERVED_BY_OTHER(lm, enc_id)) {
> -		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
> -		return false;
> -	}
> -
> -	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
> +	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_PINGPONG);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		if (iter.blk->hw->id == lm_cfg->pingpong) {
>  			*pp = iter.blk;
> @@ -358,16 +339,10 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
>  		return false;
>  	}
>  
> -	if (RESERVED_BY_OTHER(*pp, enc_id)) {
> -		DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
> -				(*pp)->hw->id);
> -		return false;
> -	}
> -
>  	return true;
>  }
>  
> -static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
> +static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
>  			       struct dpu_crtc_state *dpu_cstate,
>  			       struct dpu_rm_requirements *reqs)
>  
> @@ -384,7 +359,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  	}
>  
>  	/* Find a primary mixer */
> -	_dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
> +	_dpu_rm_init_hw_iter(&iter_i, DPU_HW_BLK_LM);
>  	while (lm_count != reqs->topology.num_lm &&
>  			_dpu_rm_get_hw_locked(rm, &iter_i)) {
>  		memset(&lm, 0, sizeof(lm));
> @@ -394,14 +369,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		lm[lm_count] = iter_i.blk;
>  
>  		if (!_dpu_rm_check_lm_and_get_connected_blks(
> -				rm, enc_id, reqs, lm[lm_count],
> +				rm, reqs, lm[lm_count],
>  				&pp[lm_count], NULL))
>  			continue;
>  
>  		++lm_count;
>  
>  		/* Valid primary mixer found, find matching peers */
> -		_dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
> +		_dpu_rm_init_hw_iter(&iter_j, DPU_HW_BLK_LM);
>  
>  		while (lm_count != reqs->topology.num_lm &&
>  				_dpu_rm_get_hw_locked(rm, &iter_j)) {
> @@ -409,7 +384,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  				continue;
>  
>  			if (!_dpu_rm_check_lm_and_get_connected_blks(
> -					rm, enc_id, reqs, iter_j.blk,
> +					rm, reqs, iter_j.blk,
>  					&pp[lm_count], iter_i.blk))
>  				continue;
>  
> @@ -427,13 +402,13 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  		if (!lm[i])
>  			break;
>  
> -		lm[i]->enc_id = enc_id;
> -		pp[i]->enc_id = enc_id;
> +		lm[i]->in_use = true;
> +		pp[i]->in_use = true;
>  
>  		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
>  		dpu_cstate->mixers[i].hw_pp = to_dpu_hw_pingpong(pp[i]->hw);
>  
> -		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM, enc_id,
> +		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM,
>  					 pp[i]->hw->id);
>  	}
>  
> @@ -444,7 +419,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>  
>  static int _dpu_rm_reserve_ctls(
>  		struct dpu_rm *rm,
> -		uint32_t enc_id,
>  		struct dpu_crtc_state *dpu_cstate,
>  		const struct msm_display_topology *top)
>  {
> @@ -460,15 +434,12 @@ static int _dpu_rm_reserve_ctls(
>  
>  	needs_split_display = _dpu_rm_needs_split_display(top);
>  
> -	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
> +	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_CTL);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
>  		unsigned long features = ctl->caps->features;
>  		bool has_split_display;
>  
> -		if (RESERVED_BY_OTHER(iter.blk, enc_id))
> -			continue;
> -
>  		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
>  
>  		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id, features);
> @@ -487,11 +458,10 @@ static int _dpu_rm_reserve_ctls(
>  		return -ENAVAIL;
>  
>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
> -		ctls[i]->enc_id = enc_id;
> +		ctls[i]->in_use = true;
>  		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
>  
> -		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
> -					  enc_id);
> +		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL);
>  	}
>  
>  	dpu_cstate->num_ctls = num_ctls;
> @@ -501,26 +471,19 @@ static int _dpu_rm_reserve_ctls(
>  
>  static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  		struct dpu_rm *rm,
> -		uint32_t enc_id,
>  		uint32_t id,
>  		enum dpu_hw_blk_type type)
>  {
>  	struct dpu_rm_hw_iter iter;
>  
>  	/* Find the block entry in the rm, and note the reservation */
> -	_dpu_rm_init_hw_iter(&iter, 0, type);
> +	_dpu_rm_init_hw_iter(&iter, type);
>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>  		if (iter.blk->hw->id != id)
>  			continue;
>  
> -		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
> -			DPU_ERROR("type %d id %d already reserved\n", type, id);
> -			return NULL;
> -		}
> +		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF);
>  
> -		iter.blk->enc_id = enc_id;
> -		trace_dpu_rm_reserve_intf(iter.blk->hw->id, DPU_HW_BLK_INTF,
> -					  enc_id);
>  		break;
>  	}
>  
> @@ -535,7 +498,6 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>  
>  static int _dpu_rm_reserve_intf_related_hw(
>  		struct dpu_rm *rm,
> -		uint32_t enc_id,
>  		struct dpu_crtc_state *dpu_cstate,
>  		struct dpu_encoder_hw_resources *hw_res)
>  {
> @@ -546,11 +508,12 @@ static int _dpu_rm_reserve_intf_related_hw(
>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>  			continue;
>  
> -		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
> +		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
>  				DPU_HW_BLK_INTF);
>  		if (!blk)
>  			return -ENAVAIL;
>  
> +		blk->in_use = true;
>  		dpu_cstate->hw_intfs[num_intfs++] = to_dpu_hw_intf(blk->hw);
>  	}
>  
> @@ -561,27 +524,24 @@ static int _dpu_rm_reserve_intf_related_hw(
>  
>  static int _dpu_rm_make_reservation(
>  		struct dpu_rm *rm,
> -		struct drm_encoder *enc,
>  		struct dpu_crtc_state *dpu_cstate,
>  		struct dpu_rm_requirements *reqs)
>  {
>  	int ret;
>  
> -	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
> +	ret = _dpu_rm_reserve_lms(rm, dpu_cstate, reqs);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate mixers\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
> -				   &reqs->topology);
> +	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate, &reqs->topology);
>  	if (ret) {
>  		DPU_ERROR("unable to find appropriate CTL\n");
>  		return ret;
>  	}
>  
> -	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id, dpu_cstate,
> -					      &reqs->hw_res);
> +	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate, &reqs->hw_res);
>  	if (ret)
>  		return ret;
>  
> @@ -612,7 +572,7 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
>  
>  	list_for_each_entry(blk, &rm->hw_blks[type], list) {
>  		if (blk->hw->id == id) {
> -			blk->enc_id = 0;
> +			blk->in_use = false;
>  			return 0;
>  		}
>  	}
> @@ -699,7 +659,7 @@ int dpu_rm_reserve(
>  		goto end;
>  	}
>  
> -	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
> +	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
>  	if (ret) {
>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>  		_dpu_rm_release_reservation(rm, dpu_cstate);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index 636b31b..3061978 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -869,48 +869,42 @@
>  );
>  
>  DECLARE_EVENT_CLASS(dpu_rm_iter_template,
> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> -	TP_ARGS(id, type, enc_id),
> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
> +	TP_ARGS(id, type),
>  	TP_STRUCT__entry(
>  		__field(	uint32_t,		id	)
>  		__field(	enum dpu_hw_blk_type,	type	)
> -		__field(	uint32_t,		enc_id	)
>  	),
>  	TP_fast_assign(
>  		__entry->id = id;
>  		__entry->type = type;
> -		__entry->enc_id = enc_id;
>  	),
> -	TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
> -		  __entry->enc_id)
> +	TP_printk("id:%d type:%d ", __entry->id, __entry->type)
>  );
>  DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> -	TP_ARGS(id, type, enc_id)
> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
> +	TP_ARGS(id, type)
>  );
>  DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> -	TP_ARGS(id, type, enc_id)
> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
> +	TP_ARGS(id, type)
>  );
>  
>  TRACE_EVENT(dpu_rm_reserve_lms,
> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id,
> -		 uint32_t pp_id),
> -	TP_ARGS(id, type, enc_id, pp_id),
> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t pp_id),
> +	TP_ARGS(id, type, pp_id),
>  	TP_STRUCT__entry(
>  		__field(	uint32_t,		id	)
>  		__field(	enum dpu_hw_blk_type,	type	)
> -		__field(	uint32_t,		enc_id	)
>  		__field(	uint32_t,		pp_id	)
>  	),
>  	TP_fast_assign(
>  		__entry->id = id;
>  		__entry->type = type;
> -		__entry->enc_id = enc_id;
>  		__entry->pp_id = pp_id;
>  	),
> -	TP_printk("id:%d type:%d enc_id:%u pp_id:%u", __entry->id,
> -		  __entry->type, __entry->enc_id, __entry->pp_id)
> +	TP_printk("id:%d type:%d pp_id:%u", __entry->id,
> +		  __entry->type, __entry->pp_id)
>  );
>  
>  TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 15/25] drm/msm/dpu: avoid redundant hw blk reference

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:32PM -0700, Jeykumar Sankaran wrote:
> Get rid of hw block pointer in RM iter as we can
> access the same through dpu_hw_blk.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index a8461b8..3a92a3e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -47,12 +47,10 @@ struct dpu_rm_hw_blk {
>  
>  /**
>   * struct dpu_rm_hw_iter - iterator for use with dpu_rm
> - * @hw: dpu_hw object requested, or NULL on failure
>   * @blk: dpu_rm internal block representation. Clients ignore. Used as iterator.
>   * @type: Hardware Block Type client wishes to search for.
>   */
>  struct dpu_rm_hw_iter {
> -	struct dpu_hw_blk *hw;
>  	struct dpu_rm_hw_blk *blk;
>  	enum dpu_hw_blk_type type;
>  };
> @@ -74,7 +72,6 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  		return false;
>  	}
>  
> -	i->hw = NULL;
>  	blk_list = &rm->hw_blks[i->type];
>  
>  	if (i->blk && (&i->blk->list == blk_list)) {
> @@ -84,12 +81,9 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm *rm, struct dpu_rm_hw_iter *i)
>  
>  	i->blk = list_prepare_entry(i->blk, blk_list, list);
>  
> -	list_for_each_entry_continue(i->blk, blk_list, list) {
> -		if (!i->blk->in_use) {
> -			i->hw = i->blk->hw;
> +	list_for_each_entry_continue(i->blk, blk_list, list)
> +		if (!i->blk->in_use)
>  			return true;
> -		}
> -	}
>  
>  	return false;
>  }
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 16/25] drm/msm/dpu: clean up test_only flag for RM reservation

[Sean Paul]

On Mon, Oct 08, 2018 at 09:27:33PM -0700, Jeykumar Sankaran wrote:
> Encoder uses test_only flag to differentiate RM reservations
> invoked from atomic check and atomic_commit phases.
> After reserving the HW blocks, if test_only was set, RM
> releases the reservation. Retains them if not. Since we
> got rid of RM reserve call from atomic_commit path, get rid
> of this flag.

I think I'm being dense, but I still don't see how the test_only path doesn't
result in lasting reservations.

Sean

> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 13 +++----------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h      |  4 +---
>  3 files changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 468b8fd0..dd17528 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -636,7 +636,7 @@ static int dpu_encoder_virt_atomic_check(
>  
>  	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
>  		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
> -				     topology, false);
> +				     topology);
>  
>  	if (!ret)
>  		drm_mode_set_crtcinfo(adj_mode, 0);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 3a92a3e..1234991 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -631,8 +631,7 @@ int dpu_rm_reserve(
>  		struct dpu_rm *rm,
>  		struct drm_encoder *enc,
>  		struct drm_crtc_state *crtc_state,
> -		struct msm_display_topology topology,
> -		bool test_only)
> +		struct msm_display_topology topology)
>  {
>  	struct dpu_rm_requirements reqs;
>  	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
> @@ -642,8 +641,8 @@ int dpu_rm_reserve(
>  	if (!drm_atomic_crtc_needs_modeset(crtc_state))
>  		return 0;
>  
> -	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d test_only %d\n",
> -		      enc->base.id, crtc_state->crtc->base.id, test_only);
> +	DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n",
> +		      enc->base.id, crtc_state->crtc->base.id);
>  
>  	mutex_lock(&rm->rm_lock);
>  
> @@ -657,13 +656,7 @@ int dpu_rm_reserve(
>  	if (ret) {
>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>  		_dpu_rm_release_reservation(rm, dpu_cstate);
> -	} else if (test_only) {
> -		 /* test_only: test the reservation and then undo */
> -		DPU_DEBUG("test_only: discard test [enc: %d]\n",
> -				enc->base.id);
> -		_dpu_rm_release_reservation(rm, dpu_cstate);
>  	}
> -
>  end:
>  	mutex_unlock(&rm->rm_lock);
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 7ac1553..415eeec 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -63,14 +63,12 @@ int dpu_rm_init(struct dpu_rm *rm,
>   * @drm_enc: DRM Encoder handle
>   * @crtc_state: Proposed Atomic DRM CRTC State handle
>   * @topology: Pointer to topology info for the display
> - * @test_only: Atomic-Test phase, discard results (unless property overrides)
>   * @Return: 0 on Success otherwise -ERROR
>   */
>  int dpu_rm_reserve(struct dpu_rm *rm,
>  		struct drm_encoder *drm_enc,
>  		struct drm_crtc_state *crtc_state,
> -		struct msm_display_topology topology,
> -		bool test_only);
> +		struct msm_display_topology topology);
>  
>  /**
>   * dpu_rm_release - Given the encoder for the display chain, release any
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Jeykumar Sankaran]

On 2018-10-10 07:29, Sean Paul wrote:
> On Tue, Oct 09, 2018 at 10:46:41PM -0700, Jeykumar Sankaran wrote:
>> On 2018-10-09 11:07, Sean Paul wrote:
>> > On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
>> > > Layer mixer/pingpong block counts and hw ctl block counts
>> > > will not be same for all the topologies (e.g. layer
>> > > mixer muxing to single interface)
>> > >
>> > > Use the encoder's split_role info to retrieve the
>> > > respective control path for programming.
>> > >
>> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> > > ---
>> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
>> > >  1 file changed, 6 insertions(+), 3 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> > > index 96cdf06..d12f896 100644
>> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> > > @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct
>> > drm_encoder *drm_enc,
>> > >
>> > >  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>> > >  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> > > +		int ctl_index;
>> > >
>> > >  		if (phys) {
>> > >  			if (!dpu_enc->hw_pp[i]) {
>> > > @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct
>> > drm_encoder *drm_enc,
>> > >  				return;
>> > >  			}
>> > >
>> > > -			if (!hw_ctl[i]) {
>> > > +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
>> > : 0;
>> > > +
>> >
>> > What if MAX_CHANNELS_PER_ENC isn't 2? Similarly, what if num_phys_encs
>> 
>> > MAX_CHANNELS_PER_ENC? It seems like there should be a more formal
>> > relationship
>> > between all of these verious values (num_of_h_tiles assumed to be <= 2
>> > as
>> > well).
>> > If one of them changes beyond the assumed bound, the rest of the
> driver
>> > falls
>> > over pretty hard.
>> >
>> MAX_CHANNELS_PER_ENC is set to 2 to represent HW limitation on the
> chipset
>> as
>> we cannot gang up more than 2 LM chain to an interface. Supporting 
>> more
> than
>> 2
>> might demand much larger changes than validating for boundaries.
>> 
>> num_phys_enc is the max no of phys encoders we create as we are 
>> looping
>> through
>> num_of_h_tiles which cannot be more than priv->dsi array size.
>> 
>> So its very unlikely we would expect these loops to go out of bound!
> 
> For now, sure. However a new revision of hardware will be a pain to add
> support
> for if we add more assumptions, and secondly it makes it _really_ hard 
> to
> understand the code if you don't have Qualcomm employee-level access to
> the
> hardware design :).
> 
I am having a hard time understanding why you have to see these counts 
as
"assumptions".

Except for MAX_CHANNELS_PER_ENC, all the other counts are either 
calculated
or derived from the other modules linked to the topology.

h_tiles is the drm_connector terminology which represents the number of 
panels
the display is driving. We use this information to determine the HW
block chains in the MDP. HW blocks counts (pp or ctl) need not be same
as the h_tile count to replace them with.

I believe maintaining the counts independently at each layer allows us 
to have more
flexibility to support independent HW chaining for future revisions.

Would it be more convincing if I get the MAX_CHANNELS_PER_ENC value from 
catalog.c?

> So this is why I'm advocating for the reduction of the number of 
> "num_of_"
> values we assume are all in the same range. It's a lot easier to
> understand the
> hardware when you can see that a phys encoder is needed per h tile, and
> that a
> ctl/pp is needed per phys encoder.
This is exactly the idea I don't want to convey to the reader. For the 
LM merge path,
each phys encoder will not be having its own control. Based on the 
topology we
are supporting, HW block counts can vary. We can even drive:
- 2 interfaces with 1 ctl and 1 ping pong
- 1 interface with 1 ctl and 2 ping pongs
- 1 interface with 1 ctl and 1 ping pong

Thanks,
Jeykumar S.

> 
> Anyways, just my $0.02.
> 
> Sean
> 
>> 
>> Thanks,
>> Jeykumar S.
>> >
>> > > +			if (!hw_ctl[ctl_index]) {
>> > >  				DPU_ERROR_ENC(dpu_enc, "no ctl block
>> > assigned"
>> > > -					     "at idx: %d\n", i);
>> > > +					     "at idx: %d\n", ctl_index);
>> > >  				return;
>> >
>> > When you return on error here, should you give back the resources that
>> > you've
>> > already provisioned?
>> >
>> > >  			}
>> > >
>> > >  			phys->hw_pp = dpu_enc->hw_pp[i];
>> > > -			phys->hw_ctl = hw_ctl[i];
>> > > +			phys->hw_ctl = hw_ctl[ctl_index];
>> > >
>> > >  			phys->connector = conn->state->connector;
>> > >  			if (phys->ops.mode_set)
>> > > --
>> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> > Forum,
>> > > a Linux Foundation Collaborative Project
>> > >
>> > > _______________________________________________
>> > > Freedreno mailing list
>> > > Freedreno@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/freedreno
>> 
>> --
>> Jeykumar S

-- 
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Re: [Freedreno] [PATCH 24/25] drm/msm/dpu: remove mutex locking for RM interfaces

[Jeykumar Sankaran]

On 2018-10-10 07:36, Sean Paul wrote:
> On Tue, Oct 09, 2018 at 11:03:24PM -0700, Jeykumar Sankaran wrote:
>> On 2018-10-09 12:57, Sean Paul wrote:
>> > On Mon, Oct 08, 2018 at 09:27:41PM -0700, Jeykumar Sankaran wrote:
>> > > Since HW reservations are happening through atomic_check
>> > > and all the display commits are catered by a single commit thread,
>> > > it is not necessary to protect the interfaces by a separate
>> > > mutex.
>> > >
>> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> > > ---
>> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 24
> ------------------------
>> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 --
>> > >  2 files changed, 26 deletions(-)
>> > >
>> >
>> > /snip
>> >
>> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> > > index 8676fa5..9acbeba 100644
>> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> > > @@ -24,11 +24,9 @@
>> > >   * struct dpu_rm - DPU dynamic hardware resource manager
>> > >   * @hw_blks: array of lists of hardware resources present in the
>> > system, one
>> > >   *	list per type of hardware block
>> > > - * @rm_lock: resource manager mutex
>> > >   */
>> > >  struct dpu_rm {
>> > >  	struct list_head hw_blks[DPU_HW_BLK_MAX];
>> >
>> > At this point, there's really not much point to even having the rm.
> It's
>> > just
>> > another level of indirection that IMO complicates the code. If you
> look
>> > at the usage of hw_blks, the code is always looking at a specific type
>> > of
>> > hw_blk, so the array is unnecessary.
>> >
>> > dpu_kms could just keep a few arrays/lists of the hw types, and the
> crtc
>> > and encoder
>> > reserve functions can just go in crtc/encoder.
>> >
>> > Sean
>> >
>> RM has been reduced to its current form to manage only LM/PP, CTL and
>> interfaces.
>> Our eventual plan is to support all the advanced HW blocks and its
> features
>> in
>> an upstream friendly way. When RM grows to manage all its subblocks,
>> iteration
>> logic may get heavy since the chipset have HW chain restrictions on
> various
>> hw blocks.
>> To provide room for the growth, I suggest keeping the allocation
>> helpers in a separate file. But I can see why you want to maintain the
> HW
>> block lists
>> in the KMS.
> 
> At least for the blocks that exist, using the RM is unnecessary, does 
> that
> change for the current blocks when you add more? I'm guessing their 
> code
> will
> remain unchanged.
> 
Yes. But to seperate out the allocation logics, I prefered the separate
file. I guess we can hold off the discussion until we need those 
enhancements.

I can get rid of the RM files for now and move the allocation functions 
to
the respective files (CRTC / Encoder).

Thanks,
Jeykumar S.
> If the new blocks you're adding have a lot of commonality, perhaps it
> makes
> sense to re-introduce the RM, but IMO it doesn't make sense for 
> lm/ctl/pp.
> 
> Sean
> 
>> 
>> Thanks,
>> Jeykumar S.
>> > > -	struct mutex rm_lock;
>> > >  };
>> > >
>> > >  /**
>> > > --
>> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> > Forum,
>> > > a Linux Foundation Collaborative Project
>> > >
>> > > _______________________________________________
>> > > Freedreno mailing list
>> > > Freedreno@lists.freedesktop.org
>> > > https://lists.freedesktop.org/mailman/listinfo/freedreno
>> 
>> --
>> Jeykumar S

-- 
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Re: [PATCH 14/25] drm/msm/dpu: remove enc_id tagging for hw blocks

[Jeykumar Sankaran]

On 2018-10-10 08:06, Sean Paul wrote:
> On Mon, Oct 08, 2018 at 09:27:31PM -0700, Jeykumar Sankaran wrote:
>> RM was using encoder id's to tag HW block's to reserve
>> and retrieve later for display pipeline. Now
>> that all the reserved HW blocks for a display are
>> maintained in its crtc state, no retrieval is needed.
>> This patch cleans up RM of encoder id tagging.
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c    | 90
> +++++++++----------------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 28 ++++------
>>  2 files changed, 36 insertions(+), 82 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index 303f1b3..a8461b8 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -21,9 +21,6 @@
>>  #include "dpu_encoder.h"
>>  #include "dpu_trace.h"
>> 
>> -#define RESERVED_BY_OTHER(h, r)  \
>> -		((h)->enc_id && (h)->enc_id != r)
>> -
>>  /**
>>   * struct dpu_rm_requirements - Reservation requirements parameter
> bundle
>>   * @topology:  selected topology for the display
>> @@ -38,12 +35,13 @@ struct dpu_rm_requirements {
>>  /**
>>   * struct dpu_rm_hw_blk - hardware block tracking list member
>>   * @list:	List head for list of all hardware blocks tracking items
>> - * @enc_id:	Encoder id to which this blk is binded
>> + * @in_use:     True, if the hw block is assigned to a display
> pipeline.
>> + *		False, otherwise
>>   * @hw:		Pointer to the hardware register access object for
> this block
>>   */
>>  struct dpu_rm_hw_blk {
>>  	struct list_head list;
>> -	uint32_t enc_id;
>> +	bool in_use;
> 
> How do the reservations work for TEST_ONLY commits? At a quick glance 
> it
> looks
> like they might be marked in_use?

Yes. We have a bug. I guess I should be releasing them in 
drm_crtc_destroy_state.

Thanks and Regards,
Jeykumar S.
> 
> Sean
> 
>>  	struct dpu_hw_blk *hw;
>>  };
>> 
>> @@ -51,23 +49,19 @@ struct dpu_rm_hw_blk {
>>   * struct dpu_rm_hw_iter - iterator for use with dpu_rm
>>   * @hw: dpu_hw object requested, or NULL on failure
>>   * @blk: dpu_rm internal block representation. Clients ignore. Used 
>> as
> iterator.
>> - * @enc_id: DRM ID of Encoder client wishes to search for, or 0 for 
>> Any
> Encoder
>>   * @type: Hardware Block Type client wishes to search for.
>>   */
>>  struct dpu_rm_hw_iter {
>>  	struct dpu_hw_blk *hw;
>>  	struct dpu_rm_hw_blk *blk;
>> -	uint32_t enc_id;
>>  	enum dpu_hw_blk_type type;
>>  };
>> 
>>  static void _dpu_rm_init_hw_iter(
>>  		struct dpu_rm_hw_iter *iter,
>> -		uint32_t enc_id,
>>  		enum dpu_hw_blk_type type)
>>  {
>>  	memset(iter, 0, sizeof(*iter));
>> -	iter->enc_id = enc_id;
>>  	iter->type = type;
>>  }
>> 
>> @@ -91,16 +85,12 @@ static bool _dpu_rm_get_hw_locked(struct dpu_rm 
>> *rm,
> struct dpu_rm_hw_iter *i)
>>  	i->blk = list_prepare_entry(i->blk, blk_list, list);
>> 
>>  	list_for_each_entry_continue(i->blk, blk_list, list) {
>> -		if (i->enc_id == i->blk->enc_id) {
>> +		if (!i->blk->in_use) {
>>  			i->hw = i->blk->hw;
>> -			DPU_DEBUG("found type %d id %d for enc %d\n",
>> -					i->type, i->blk->hw->id,
> i->enc_id);
>>  			return true;
>>  		}
>>  	}
>> 
>> -	DPU_DEBUG("no match, type %d for enc %d\n", i->type, i->enc_id);
>> -
>>  	return false;
>>  }
>> 
>> @@ -196,7 +186,6 @@ static int _dpu_rm_hw_blk_create(
>>  	}
>> 
>>  	blk->hw = hw;
>> -	blk->enc_id = 0;
>>  	list_add_tail(&blk->list, &rm->hw_blks[type]);
>> 
>>  	return 0;
>> @@ -301,7 +290,6 @@ static bool _dpu_rm_needs_split_display(const 
>> struct
> msm_display_topology *top)
>>   *	proposed use case requirements, incl. hardwired dependent blocks
> like
>>   *	pingpong
>>   * @rm: dpu resource manager handle
>> - * @enc_id: encoder id requesting for allocation
>>   * @reqs: proposed use case requirements
>>   * @lm: proposed layer mixer, function checks if lm, and all other
> hardwired
>>   *      blocks connected to the lm (pp) is available and appropriate
>> @@ -313,7 +301,6 @@ static bool _dpu_rm_needs_split_display(const 
>> struct
> msm_display_topology *top)
>>   */
>>  static bool _dpu_rm_check_lm_and_get_connected_blks(
>>  		struct dpu_rm *rm,
>> -		uint32_t enc_id,
>>  		struct dpu_rm_requirements *reqs,
>>  		struct dpu_rm_hw_blk *lm,
>>  		struct dpu_rm_hw_blk **pp,
>> @@ -339,13 +326,7 @@ static bool
> _dpu_rm_check_lm_and_get_connected_blks(
>>  		}
>>  	}
>> 
>> -	/* Already reserved? */
>> -	if (RESERVED_BY_OTHER(lm, enc_id)) {
>> -		DPU_DEBUG("lm %d already reserved\n", lm_cfg->id);
>> -		return false;
>> -	}
>> -
>> -	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_PINGPONG);
>> +	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_PINGPONG);
>>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>>  		if (iter.blk->hw->id == lm_cfg->pingpong) {
>>  			*pp = iter.blk;
>> @@ -358,16 +339,10 @@ static bool
> _dpu_rm_check_lm_and_get_connected_blks(
>>  		return false;
>>  	}
>> 
>> -	if (RESERVED_BY_OTHER(*pp, enc_id)) {
>> -		DPU_DEBUG("lm %d pp %d already reserved\n", lm->hw->id,
>> -				(*pp)->hw->id);
>> -		return false;
>> -	}
>> -
>>  	return true;
>>  }
>> 
>> -static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>> +static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
>>  			       struct dpu_crtc_state *dpu_cstate,
>>  			       struct dpu_rm_requirements *reqs)
>> 
>> @@ -384,7 +359,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> uint32_t enc_id,
>>  	}
>> 
>>  	/* Find a primary mixer */
>> -	_dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_LM);
>> +	_dpu_rm_init_hw_iter(&iter_i, DPU_HW_BLK_LM);
>>  	while (lm_count != reqs->topology.num_lm &&
>>  			_dpu_rm_get_hw_locked(rm, &iter_i)) {
>>  		memset(&lm, 0, sizeof(lm));
>> @@ -394,14 +369,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm 
>> *rm,
> uint32_t enc_id,
>>  		lm[lm_count] = iter_i.blk;
>> 
>>  		if (!_dpu_rm_check_lm_and_get_connected_blks(
>> -				rm, enc_id, reqs, lm[lm_count],
>> +				rm, reqs, lm[lm_count],
>>  				&pp[lm_count], NULL))
>>  			continue;
>> 
>>  		++lm_count;
>> 
>>  		/* Valid primary mixer found, find matching peers */
>> -		_dpu_rm_init_hw_iter(&iter_j, 0, DPU_HW_BLK_LM);
>> +		_dpu_rm_init_hw_iter(&iter_j, DPU_HW_BLK_LM);
>> 
>>  		while (lm_count != reqs->topology.num_lm &&
>>  				_dpu_rm_get_hw_locked(rm, &iter_j)) {
>> @@ -409,7 +384,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> uint32_t enc_id,
>>  				continue;
>> 
>>  			if (!_dpu_rm_check_lm_and_get_connected_blks(
>> -					rm, enc_id, reqs, iter_j.blk,
>> +					rm, reqs, iter_j.blk,
>>  					&pp[lm_count], iter_i.blk))
>>  				continue;
>> 
>> @@ -427,13 +402,13 @@ static int _dpu_rm_reserve_lms(struct dpu_rm 
>> *rm,
> uint32_t enc_id,
>>  		if (!lm[i])
>>  			break;
>> 
>> -		lm[i]->enc_id = enc_id;
>> -		pp[i]->enc_id = enc_id;
>> +		lm[i]->in_use = true;
>> +		pp[i]->in_use = true;
>> 
>>  		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
>>  		dpu_cstate->mixers[i].hw_pp =
> to_dpu_hw_pingpong(pp[i]->hw);
>> 
>> -		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM,
> enc_id,
>> +		trace_dpu_rm_reserve_lms(lm[i]->hw->id, DPU_HW_BLK_LM,
>>  					 pp[i]->hw->id);
>>  	}
>> 
>> @@ -444,7 +419,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
> uint32_t enc_id,
>> 
>>  static int _dpu_rm_reserve_ctls(
>>  		struct dpu_rm *rm,
>> -		uint32_t enc_id,
>>  		struct dpu_crtc_state *dpu_cstate,
>>  		const struct msm_display_topology *top)
>>  {
>> @@ -460,15 +434,12 @@ static int _dpu_rm_reserve_ctls(
>> 
>>  	needs_split_display = _dpu_rm_needs_split_display(top);
>> 
>> -	_dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CTL);
>> +	_dpu_rm_init_hw_iter(&iter, DPU_HW_BLK_CTL);
>>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>>  		const struct dpu_hw_ctl *ctl =
> to_dpu_hw_ctl(iter.blk->hw);
>>  		unsigned long features = ctl->caps->features;
>>  		bool has_split_display;
>> 
>> -		if (RESERVED_BY_OTHER(iter.blk, enc_id))
>> -			continue;
>> -
>>  		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
>> 
>>  		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->hw->id,
> features);
>> @@ -487,11 +458,10 @@ static int _dpu_rm_reserve_ctls(
>>  		return -ENAVAIL;
>> 
>>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
>> -		ctls[i]->enc_id = enc_id;
>> +		ctls[i]->in_use = true;
>>  		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
>> 
>> -		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL,
>> -					  enc_id);
>> +		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id,
> DPU_HW_BLK_CTL);
>>  	}
>> 
>>  	dpu_cstate->num_ctls = num_ctls;
>> @@ -501,26 +471,19 @@ static int _dpu_rm_reserve_ctls(
>> 
>>  static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>>  		struct dpu_rm *rm,
>> -		uint32_t enc_id,
>>  		uint32_t id,
>>  		enum dpu_hw_blk_type type)
>>  {
>>  	struct dpu_rm_hw_iter iter;
>> 
>>  	/* Find the block entry in the rm, and note the reservation */
>> -	_dpu_rm_init_hw_iter(&iter, 0, type);
>> +	_dpu_rm_init_hw_iter(&iter, type);
>>  	while (_dpu_rm_get_hw_locked(rm, &iter)) {
>>  		if (iter.blk->hw->id != id)
>>  			continue;
>> 
>> -		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
>> -			DPU_ERROR("type %d id %d already reserved\n",
> type, id);
>> -			return NULL;
>> -		}
>> +		trace_dpu_rm_reserve_intf(iter.blk->hw->id,
> DPU_HW_BLK_INTF);
>> 
>> -		iter.blk->enc_id = enc_id;
>> -		trace_dpu_rm_reserve_intf(iter.blk->hw->id,
> DPU_HW_BLK_INTF,
>> -					  enc_id);
>>  		break;
>>  	}
>> 
>> @@ -535,7 +498,6 @@ static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>> 
>>  static int _dpu_rm_reserve_intf_related_hw(
>>  		struct dpu_rm *rm,
>> -		uint32_t enc_id,
>>  		struct dpu_crtc_state *dpu_cstate,
>>  		struct dpu_encoder_hw_resources *hw_res)
>>  {
>> @@ -546,11 +508,12 @@ static int _dpu_rm_reserve_intf_related_hw(
>>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>>  			continue;
>> 
>> -		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
>> +		blk = _dpu_rm_reserve_intf(rm, i + INTF_0,
>>  				DPU_HW_BLK_INTF);
>>  		if (!blk)
>>  			return -ENAVAIL;
>> 
>> +		blk->in_use = true;
>>  		dpu_cstate->hw_intfs[num_intfs++] =
> to_dpu_hw_intf(blk->hw);
>>  	}
>> 
>> @@ -561,27 +524,24 @@ static int _dpu_rm_reserve_intf_related_hw(
>> 
>>  static int _dpu_rm_make_reservation(
>>  		struct dpu_rm *rm,
>> -		struct drm_encoder *enc,
>>  		struct dpu_crtc_state *dpu_cstate,
>>  		struct dpu_rm_requirements *reqs)
>>  {
>>  	int ret;
>> 
>> -	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
>> +	ret = _dpu_rm_reserve_lms(rm, dpu_cstate, reqs);
>>  	if (ret) {
>>  		DPU_ERROR("unable to find appropriate mixers\n");
>>  		return ret;
>>  	}
>> 
>> -	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
>> -				   &reqs->topology);
>> +	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate, &reqs->topology);
>>  	if (ret) {
>>  		DPU_ERROR("unable to find appropriate CTL\n");
>>  		return ret;
>>  	}
>> 
>> -	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id,
> dpu_cstate,
>> -					      &reqs->hw_res);
>> +	ret = _dpu_rm_reserve_intf_related_hw(rm, dpu_cstate,
> &reqs->hw_res);
>>  	if (ret)
>>  		return ret;
>> 
>> @@ -612,7 +572,7 @@ static int _dpu_rm_release_hw(struct dpu_rm *rm,
> enum dpu_hw_blk_type type,
>> 
>>  	list_for_each_entry(blk, &rm->hw_blks[type], list) {
>>  		if (blk->hw->id == id) {
>> -			blk->enc_id = 0;
>> +			blk->in_use = false;
>>  			return 0;
>>  		}
>>  	}
>> @@ -699,7 +659,7 @@ int dpu_rm_reserve(
>>  		goto end;
>>  	}
>> 
>> -	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
>> +	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
>>  	if (ret) {
>>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>>  		_dpu_rm_release_reservation(rm, dpu_cstate);
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> index 636b31b..3061978 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> @@ -869,48 +869,42 @@
>>  );
>> 
>>  DECLARE_EVENT_CLASS(dpu_rm_iter_template,
>> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
>> -	TP_ARGS(id, type, enc_id),
>> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
>> +	TP_ARGS(id, type),
>>  	TP_STRUCT__entry(
>>  		__field(	uint32_t,		id	)
>>  		__field(	enum dpu_hw_blk_type,	type	)
>> -		__field(	uint32_t,		enc_id	)
>>  	),
>>  	TP_fast_assign(
>>  		__entry->id = id;
>>  		__entry->type = type;
>> -		__entry->enc_id = enc_id;
>>  	),
>> -	TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
>> -		  __entry->enc_id)
>> +	TP_printk("id:%d type:%d ", __entry->id, __entry->type)
>>  );
>>  DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
>> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
>> -	TP_ARGS(id, type, enc_id)
>> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
>> +	TP_ARGS(id, type)
>>  );
>>  DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
>> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
>> -	TP_ARGS(id, type, enc_id)
>> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type),
>> +	TP_ARGS(id, type)
>>  );
>> 
>>  TRACE_EVENT(dpu_rm_reserve_lms,
>> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id,
>> -		 uint32_t pp_id),
>> -	TP_ARGS(id, type, enc_id, pp_id),
>> +	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t pp_id),
>> +	TP_ARGS(id, type, pp_id),
>>  	TP_STRUCT__entry(
>>  		__field(	uint32_t,		id	)
>>  		__field(	enum dpu_hw_blk_type,	type	)
>> -		__field(	uint32_t,		enc_id	)
>>  		__field(	uint32_t,		pp_id	)
>>  	),
>>  	TP_fast_assign(
>>  		__entry->id = id;
>>  		__entry->type = type;
>> -		__entry->enc_id = enc_id;
>>  		__entry->pp_id = pp_id;
>>  	),
>> -	TP_printk("id:%d type:%d enc_id:%u pp_id:%u", __entry->id,
>> -		  __entry->type, __entry->enc_id, __entry->pp_id)
>> +	TP_printk("id:%d type:%d pp_id:%u", __entry->id,
>> +		  __entry->type, __entry->pp_id)
>>  );
>> 
>>  TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Freedreno@lists.freedesktop.org
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Re: [PATCH 01/25] drm/msm/dpu: fix hw ctl retrieval for mixer muxing

[Sean Paul]

On Wed, Oct 10, 2018 at 11:35:56AM -0700, Jeykumar Sankaran wrote:
> On 2018-10-10 07:29, Sean Paul wrote:
> > On Tue, Oct 09, 2018 at 10:46:41PM -0700, Jeykumar Sankaran wrote:
> > > On 2018-10-09 11:07, Sean Paul wrote:
> > > > On Mon, Oct 08, 2018 at 09:27:18PM -0700, Jeykumar Sankaran wrote:
> > > > > Layer mixer/pingpong block counts and hw ctl block counts
> > > > > will not be same for all the topologies (e.g. layer
> > > > > mixer muxing to single interface)
> > > > >
> > > > > Use the encoder's split_role info to retrieve the
> > > > > respective control path for programming.
> > > > >
> > > > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > > > ---
> > > > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 9 ++++++---
> > > > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > > index 96cdf06..d12f896 100644
> > > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > > @@ -1060,6 +1060,7 @@ static void dpu_encoder_virt_mode_set(struct
> > > > drm_encoder *drm_enc,
> > > > >
> > > > >  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > > > >  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > > > > +		int ctl_index;
> > > > >
> > > > >  		if (phys) {
> > > > >  			if (!dpu_enc->hw_pp[i]) {
> > > > > @@ -1068,14 +1069,16 @@ static void dpu_encoder_virt_mode_set(struct
> > > > drm_encoder *drm_enc,
> > > > >  				return;
> > > > >  			}
> > > > >
> > > > > -			if (!hw_ctl[i]) {
> > > > > +			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
> > > > : 0;
> > > > > +
> > > >
> > > > What if MAX_CHANNELS_PER_ENC isn't 2? Similarly, what if num_phys_encs
> > > 
> > > > MAX_CHANNELS_PER_ENC? It seems like there should be a more formal
> > > > relationship
> > > > between all of these verious values (num_of_h_tiles assumed to be <= 2
> > > > as
> > > > well).
> > > > If one of them changes beyond the assumed bound, the rest of the
> > driver
> > > > falls
> > > > over pretty hard.
> > > >
> > > MAX_CHANNELS_PER_ENC is set to 2 to represent HW limitation on the
> > chipset
> > > as
> > > we cannot gang up more than 2 LM chain to an interface. Supporting
> > > more
> > than
> > > 2
> > > might demand much larger changes than validating for boundaries.
> > > 
> > > num_phys_enc is the max no of phys encoders we create as we are
> > > looping
> > > through
> > > num_of_h_tiles which cannot be more than priv->dsi array size.
> > > 
> > > So its very unlikely we would expect these loops to go out of bound!
> > 
> > For now, sure. However a new revision of hardware will be a pain to add
> > support
> > for if we add more assumptions, and secondly it makes it _really_ hard
> > to
> > understand the code if you don't have Qualcomm employee-level access to
> > the
> > hardware design :).
> > 
> I am having a hard time understanding why you have to see these counts as
> "assumptions".


        ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1 : 0
        if (!hw_ctl[ctl_index]) {

Assumes that ARRAY_SIZE(hw_ctl) > 1 if phys is a slave


        if (!dpu_enc->hw_pp[i]) {

Assumes that ARRAY_SIZE(hw_pp) >= ARRAY_SIZE(dpu_enc->phys_encs)


> 
> Except for MAX_CHANNELS_PER_ENC, all the other counts are either calculated
> or derived from the other modules linked to the topology.
> 
> h_tiles is the drm_connector terminology which represents the number of
> panels
> the display is driving. We use this information to determine the HW
> block chains in the MDP. HW blocks counts (pp or ctl) need not be same
> as the h_tile count to replace them with.

I must be missing something, because it seems that there's a 1:1 mapping of

num_h_tiles : num_phys_encs

And for each physical encoder, there's exactly one intf, pp, ctl assigned to it.
The issue I had was that when we loop through N phys_encs, we assume that there
are at least N hw blocks.

I think the takeaway is that I don't understand the hardware and its constraints
as well as you, so if this makes sense to you, let's go with it. Perhaps I'll
stare at it a while longer to try to refine my mental model.

Sean

> 
> I believe maintaining the counts independently at each layer allows us to
> have more
> flexibility to support independent HW chaining for future revisions.
> 
> Would it be more convincing if I get the MAX_CHANNELS_PER_ENC value from
> catalog.c?
> 
> > So this is why I'm advocating for the reduction of the number of
> > "num_of_"
> > values we assume are all in the same range. It's a lot easier to
> > understand the
> > hardware when you can see that a phys encoder is needed per h tile, and
> > that a
> > ctl/pp is needed per phys encoder.
> This is exactly the idea I don't want to convey to the reader. For the LM
> merge path,
> each phys encoder will not be having its own control. Based on the topology
> we
> are supporting, HW block counts can vary. We can even drive:
> - 2 interfaces with 1 ctl and 1 ping pong
> - 1 interface with 1 ctl and 2 ping pongs
> - 1 interface with 1 ctl and 1 ping pong
> 
> Thanks,
> Jeykumar S.
> 
> > 
> > Anyways, just my $0.02.
> > 
> > Sean
> > 
> > > 
> > > Thanks,
> > > Jeykumar S.
> > > >
> > > > > +			if (!hw_ctl[ctl_index]) {
> > > > >  				DPU_ERROR_ENC(dpu_enc, "no ctl block
> > > > assigned"
> > > > > -					     "at idx: %d\n", i);
> > > > > +					     "at idx: %d\n", ctl_index);
> > > > >  				return;
> > > >
> > > > When you return on error here, should you give back the resources that
> > > > you've
> > > > already provisioned?
> > > >
> > > > >  			}
> > > > >
> > > > >  			phys->hw_pp = dpu_enc->hw_pp[i];
> > > > > -			phys->hw_ctl = hw_ctl[i];
> > > > > +			phys->hw_ctl = hw_ctl[ctl_index];
> > > > >
> > > > >  			phys->connector = conn->state->connector;
> > > > >  			if (phys->ops.mode_set)
> > > > > --
> > > > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > > > Forum,
> > > > > a Linux Foundation Collaborative Project
> > > > >
> > > > > _______________________________________________
> > > > > Freedreno mailing list
> > > > > Freedreno@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/freedreno
> > > 
> > > --
> > > Jeykumar S
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
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Re: [PATCH 07/25] drm/msm/dpu: reserve using crtc state

[Jeykumar Sankaran]

On 2018-10-09 23:28, Jeykumar Sankaran wrote:
> On 2018-10-09 14:06, Sean Paul wrote:
>> On Mon, Oct 08, 2018 at 09:27:24PM -0700, Jeykumar Sankaran wrote:
>>> DPU maintained reservation lists to cache assigned
>>> HW blocks for the display and a retrieval mechanism for
>>> the individual DRM components to query their respective
>>> HW blocks.
>>> 
>>> This patch uses the sub-classed CRTC state to store
>>> and track HW blocks assigned for different components
>>> of the display pipeline. It helps the driver:
>>> - to get rid of unwanted store and retrieval RM API's
>>> - to preserve HW resources assigned in atomic_check
>>>   through atomic swap/duplicate.
>>> 
>>> Separate patch is submitted to remove resource
>>> reservation in atomic_commit path.
>>> 
>>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>>> ---
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 65
>> +++-------------------
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           | 14 +++++
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 28 +++-------
>>>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 20 ++-----
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 58
>> ++++++++++++-------
>>>  5 files changed, 72 insertions(+), 113 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> index 4960641..0625f56 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> @@ -421,69 +421,20 @@ void dpu_crtc_complete_commit(struct drm_crtc
>> *crtc,
>>>  	trace_dpu_crtc_complete_commit(DRMID(crtc));
>>>  }
>>> 
>>> -static void _dpu_crtc_setup_mixer_for_encoder(
>>> -		struct drm_crtc *crtc,
>>> -		struct drm_encoder *enc)
>>> +static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>>>  {
>>>  	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>>> -	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>>> -	struct dpu_rm *rm = &dpu_kms->rm;
>>>  	struct dpu_crtc_mixer *mixer;
>>> -	struct dpu_hw_ctl *last_valid_ctl = NULL;
>>> -	int i;
>>> -	struct dpu_rm_hw_iter lm_iter, ctl_iter;
>>> -
>>> -	dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM);
>>> -	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
>>> +	int i, ctl_index;
>>> 
>>>  	/* Set up all the mixers and ctls reserved by this encoder */
>>> -	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++)
>> {
>>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>>  		mixer = &cstate->mixers[i];
>>> 
>>> -		if (!dpu_rm_get_hw(rm, &lm_iter))
>>> -			break;
>>> -		mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
>>> -
>>>  		/* CTL may be <= LMs, if <, multiple LMs controlled by 1
>> CTL */
>>> -		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
>>> -			DPU_DEBUG("no ctl assigned to lm %d, using
>> previous\n",
>>> -					mixer->hw_lm->idx - LM_0);
>>> -			mixer->lm_ctl = last_valid_ctl;
>>> -		} else {
>>> -			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
>>> -			last_valid_ctl = mixer->lm_ctl;
>>> -		}
>>> -
>>> -		/* Shouldn't happen, mixers are always >= ctls */
>>> -		if (!mixer->lm_ctl) {
>>> -			DPU_ERROR("no valid ctls found for lm %d\n",
>>> -					mixer->hw_lm->idx - LM_0);
>>> -			return;
>>> -		}
>>> -
>>> -		cstate->num_mixers++;
>>> -		DPU_DEBUG("setup mixer %d: lm %d\n",
>>> -				i, mixer->hw_lm->idx - LM_0);
>>> -		DPU_DEBUG("setup mixer %d: ctl %d\n",
>>> -				i, mixer->lm_ctl->idx - CTL_0);
>>> -	}
>>> -}
>>> -
>>> -static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>>> -{
>>> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>>> -	struct drm_encoder *enc;
>>> -
>>> -	mutex_lock(&dpu_crtc->crtc_lock);
>>> -	/* Check for mixers on all encoders attached to this crtc */
>>> -	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list,
>> head) {
>>> -		if (enc->crtc != crtc)
>>> -			continue;
>>> -
>>> -		_dpu_crtc_setup_mixer_for_encoder(crtc, enc);
>>> +		ctl_index = min(i, cstate->num_ctls - 1);
>> 
>> This is another one of those places I mentioned where we're just 
>> assuming
>> a
>> value is going to be in a certain range. If
>> num_ctls/num_intfs/num_phys_encs
>> (all the same value afaict) is 0, we end up in a bad place.
> Even though all these variables have the same value, they are 
> representing the
> sizes of logically seperate components.
> 
>> 
>> At a minimum, there should be a WARN_ON/BUG_ON somewhere ensuring this 
>> can
>> never
>> drop below 0.
> Isn't RM guaranteeing that? I can add the WARN_ON checks on these
> num_xxx when the HW blocks are allocated.
> 
> Thanks,
> Jeykumar S.
>> 
>>> +		mixer->lm_ctl = cstate->hw_ctls[ctl_index];
>>>  	}
>>> -
>>> -	mutex_unlock(&dpu_crtc->crtc_lock);
>>>  }
>>> 
>>>  static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>>> @@ -536,10 +487,8 @@ static void dpu_crtc_atomic_begin(struct 
>>> drm_crtc
>> *crtc,
>>>  	dev = crtc->dev;
>>>  	smmu_state = &dpu_crtc->smmu_state;
>>> 
>>> -	if (!cstate->num_mixers) {
>>> -		_dpu_crtc_setup_mixers(crtc);
>>> -		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>>> -	}
>>> +	_dpu_crtc_setup_mixers(crtc);
>>> +	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>>> 
>>>  	if (dpu_crtc->event) {
>>>  		WARN_ON(dpu_crtc->event);
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> index 75fdd3c..17aaad7 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> @@ -84,12 +84,14 @@ struct dpu_crtc_smmu_state_data {
>>>   * struct dpu_crtc_mixer: stores the map for each virtual pipeline 
>>> in
>> the CRTC
>>>   * @hw_lm:	LM HW Driver context
>>>   * @lm_ctl:	CTL Path HW driver context
>>> + * @hw_pp:	Pingpong HW driver context
>>>   * @mixer_op_mode:	mixer blending operation mode
>>>   * @flush_mask:	mixer flush mask for ctl, mixer and pipe
>>>   */
>>>  struct dpu_crtc_mixer {
>>>  	struct dpu_hw_mixer *hw_lm;
>>>  	struct dpu_hw_ctl *lm_ctl;
>>> +	struct dpu_hw_pingpong *hw_pp;
>>>  	u32 mixer_op_mode;
>>>  	u32 flush_mask;
>>>  };
>>> @@ -230,6 +232,18 @@ struct dpu_crtc_state {
>>> 
>>>  	u32 num_ctls;
>>>  	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
>>> +
>>> +	/**
>>> +	 * as drm encoders doesn't have dedicates state objects
>>> +	 * and drm connectors are not owned by DPU, maintain
>>> +	 * HW interface and other interface related blocks
>>> +	 * in crtc state
>> 
>> Can you use private state instead?
> hmm.. It's time for me to revisit the old patch:
> https://patchwork.freedesktop.org/patch/230100/
>> 
Please note that using drm_priv_obj_state to track the per
display hw reservation, I need to maintain MAX_CRTCS drm_priv_obj's
in dpu_kms.

The design would not be the same as mdp5 model since mdp5 uses the
same priv_obj to track the resources of all CRTC's and also maintains
the per crtc hw information in mdp5_crtc_state.

Thanks,
Jeykumar S.

>>> +	 *
>>> +	 * TODO: No support for clone mode yet where a crtc
>>> +	 * can be attached with more than one encoder/connector.
>>> +	 */
>>> +	u32 num_intfs;
>>> +	struct dpu_hw_intf *hw_intfs[CRTC_DUAL_MIXERS];
>>>  };
>>> 
>>>  #define to_dpu_crtc_state(x) \
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> index d12f896..17dbbc3 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>>> @@ -1001,9 +1001,8 @@ static void dpu_encoder_virt_mode_set(struct
>> drm_encoder *drm_enc,
>>>  	struct dpu_kms *dpu_kms;
>>>  	struct list_head *connector_list;
>>>  	struct drm_connector *conn = NULL, *conn_iter;
>>> -	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>>> +	struct dpu_crtc_state *dpu_cstate;
>>>  	struct msm_display_topology topology;
>>> -	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>>>  	int i = 0, ret;
>>> 
>>>  	if (!drm_enc) {
>>> @@ -1043,27 +1042,14 @@ static void dpu_encoder_virt_mode_set(struct
>> drm_encoder *drm_enc,
>>>  		return;
>>>  	}
>>> 
>>> -	dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id,
>> DPU_HW_BLK_PINGPONG);
>>> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
>>> -		dpu_enc->hw_pp[i] = NULL;
>>> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter))
>>> -			break;
>>> -		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
>>> -	}
>>> -
>>> -	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
>>> -	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
>>> -		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
>>> -			break;
>>> -		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
>>> -	}
>>> +	dpu_cstate = to_dpu_crtc_state(drm_enc->crtc->state);
>>> 
>>>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>>>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>>>  		int ctl_index;
>>> 
>>>  		if (phys) {
>>> -			if (!dpu_enc->hw_pp[i]) {
>>> +			if (!dpu_cstate->mixers[i].hw_pp) {
>>>  				DPU_ERROR_ENC(dpu_enc, "no pp block
>> assigned"
>>>  					     "at idx: %d\n", i);
>>>  				return;
>>> @@ -1071,14 +1057,16 @@ static void dpu_encoder_virt_mode_set(struct
>> drm_encoder *drm_enc,
>>> 
>>>  			ctl_index = phys->split_role == ENC_ROLE_SLAVE ? 1
>> : 0;
>>> 
>>> -			if (!hw_ctl[ctl_index]) {
>>> +			if (!dpu_cstate->hw_ctls[ctl_index]) {
>>>  				DPU_ERROR_ENC(dpu_enc, "no ctl block
>> assigned"
>>>  					     "at idx: %d\n", ctl_index);
>>>  				return;
>>>  			}
>>> 
>>> -			phys->hw_pp = dpu_enc->hw_pp[i];
>>> -			phys->hw_ctl = hw_ctl[ctl_index];
>>> +			dpu_enc->hw_pp[i] = dpu_cstate->mixers[i].hw_pp;
>>> +
>>> +			phys->hw_pp = dpu_cstate->mixers[i].hw_pp;
>>> +			phys->hw_ctl = dpu_cstate->hw_ctls[ctl_index];
>>> 
>>>  			phys->connector = conn->state->connector;
>>>  			if (phys->ops.mode_set)
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>>> index 84de385..4563f8d 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>>> @@ -461,28 +461,20 @@ static int
>> dpu_encoder_phys_vid_control_vblank_irq(
>>> 
>>>  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys
>> *phys_enc)
>>>  {
>>> -	struct msm_drm_private *priv;
>>>  	struct dpu_encoder_phys_vid *vid_enc;
>>> -	struct dpu_rm_hw_iter iter;
>>>  	struct dpu_hw_ctl *ctl;
>>> +	struct dpu_crtc_state *dpu_cstate;
>>> +	int i;
>>>  	u32 flush_mask = 0;
>>> 
>>> -	if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
>>> -			!phys_enc->parent->dev->dev_private) {
>>> -		DPU_ERROR("invalid encoder/device\n");
>>> -		return;
>>> -	}
>>> -	priv = phys_enc->parent->dev->dev_private;
>>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>> 
>>>  	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
>>>  	ctl = phys_enc->hw_ctl;
>>> 
>>> -	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id,
>> DPU_HW_BLK_INTF);
>>> -	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
>>> -		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf
>> *)iter.hw;
>>> -
>>> -		if (hw_intf->idx == phys_enc->intf_idx) {
>>> -			vid_enc->hw_intf = hw_intf;
>>> +	for (i = 0; i < dpu_cstate->num_intfs; i++) {
>>> +		if (dpu_cstate->hw_intfs[i]->idx == phys_enc->intf_idx) {
>>> +			vid_enc->hw_intf = dpu_cstate->hw_intfs[i];
>>>  			break;
>>>  		}
>>>  	}
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> index 377def7..5703b11 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>>> @@ -388,6 +388,7 @@ static bool 
>>> _dpu_rm_check_lm_and_get_connected_blks(
>>>  }
>>> 
>>>  static int _dpu_rm_reserve_lms(struct dpu_rm *rm, uint32_t enc_id,
>>> +			       struct dpu_crtc_state *dpu_cstate,
>>>  			       struct dpu_rm_requirements *reqs)
>>> 
>>>  {
>>> @@ -449,16 +450,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm 
>>> *rm,
>> uint32_t enc_id,
>>>  		lm[i]->enc_id = enc_id;
>>>  		pp[i]->enc_id = enc_id;
>>> 
>>> +		dpu_cstate->mixers[i].hw_lm = to_dpu_hw_mixer(lm[i]->hw);
>>> +		dpu_cstate->mixers[i].hw_pp =
>> to_dpu_hw_pingpong(pp[i]->hw);
>>> +
>>>  		trace_dpu_rm_reserve_lms(lm[i]->id, DPU_HW_BLK_LM, enc_id,
>>>  					 pp[i]->id);
>>>  	}
>>> 
>>> +	dpu_cstate->num_mixers = lm_count;
>>> +
>>>  	return rc;
>>>  }
>>> 
>>>  static int _dpu_rm_reserve_ctls(
>>>  		struct dpu_rm *rm,
>>>  		uint32_t enc_id,
>>> +		struct dpu_crtc_state *dpu_cstate,
>>>  		const struct msm_display_topology *top)
>>>  {
>>>  	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
>>> @@ -501,21 +508,24 @@ static int _dpu_rm_reserve_ctls(
>>> 
>>>  	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
>>>  		ctls[i]->enc_id = enc_id;
>>> +		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
>>> +
>>>  		trace_dpu_rm_reserve_ctls(ctls[i]->id, DPU_HW_BLK_CTL,
>>>  					  enc_id);
>>>  	}
>>> 
>>> +	dpu_cstate->num_ctls = num_ctls;
>>> +
>>>  	return 0;
>>>  }
>>> 
>>> -static int _dpu_rm_reserve_intf(
>>> +static struct dpu_rm_hw_blk *_dpu_rm_reserve_intf(
>>>  		struct dpu_rm *rm,
>>>  		uint32_t enc_id,
>>>  		uint32_t id,
>>>  		enum dpu_hw_blk_type type)
>>>  {
>>>  	struct dpu_rm_hw_iter iter;
>>> -	int ret = 0;
>>> 
>>>  	/* Find the block entry in the rm, and note the reservation */
>>>  	dpu_rm_init_hw_iter(&iter, 0, type);
>>> @@ -525,7 +535,7 @@ static int _dpu_rm_reserve_intf(
>>> 
>>>  		if (RESERVED_BY_OTHER(iter.blk, enc_id)) {
>>>  			DPU_ERROR("type %d id %d already reserved\n",
>> type, id);
>>> -			return -ENAVAIL;
>>> +			return NULL;
>>>  		}
>>> 
>>>  		iter.blk->enc_id = enc_id;
>>> @@ -535,56 +545,63 @@ static int _dpu_rm_reserve_intf(
>>>  	}
>>> 
>>>  	/* Shouldn't happen since intfs are fixed at probe */
>>> -	if (!iter.hw) {
>>> +	if (!iter.blk) {
>>>  		DPU_ERROR("couldn't find type %d id %d\n", type, id);
>>> -		return -EINVAL;
>>> +		return NULL;
>>>  	}
>>> 
>>> -	return ret;
>>> +	return iter.blk;
>>>  }
>>> 
>>>  static int _dpu_rm_reserve_intf_related_hw(
>>>  		struct dpu_rm *rm,
>>>  		uint32_t enc_id,
>>> +		struct dpu_crtc_state *dpu_cstate,
>>>  		struct dpu_encoder_hw_resources *hw_res)
>>>  {
>>> -	int i, ret = 0;
>>> -	u32 id;
>>> +	struct dpu_rm_hw_blk *blk;
>>> +	int i, num_intfs = 0;
>>> 
>>>  	for (i = 0; i < ARRAY_SIZE(hw_res->intfs); i++) {
>>>  		if (hw_res->intfs[i] == INTF_MODE_NONE)
>>>  			continue;
>>> -		id = i + INTF_0;
>>> -		ret = _dpu_rm_reserve_intf(rm, enc_id, id,
>>> +
>>> +		blk = _dpu_rm_reserve_intf(rm, enc_id, i + INTF_0,
>>>  				DPU_HW_BLK_INTF);
>>> -		if (ret)
>>> -			return ret;
>>> +		if (!blk)
>>> +			return -ENAVAIL;
>>> +
>>> +		dpu_cstate->hw_intfs[num_intfs++] =
>> to_dpu_hw_intf(blk->hw);
>>>  	}
>>> 
>>> -	return ret;
>>> +	dpu_cstate->num_intfs = num_intfs;
>>> +
>>> +	return 0;
>>>  }
>>> 
>>>  static int _dpu_rm_make_reservation(
>>>  		struct dpu_rm *rm,
>>>  		struct drm_encoder *enc,
>>> -		struct drm_crtc_state *crtc_state,
>>> +		struct dpu_crtc_state *dpu_cstate,
>>>  		struct dpu_rm_requirements *reqs)
>>>  {
>>>  	int ret;
>>> 
>>> -	ret = _dpu_rm_reserve_lms(rm, enc->base.id, reqs);
>>> +	ret = _dpu_rm_reserve_lms(rm, enc->base.id, dpu_cstate, reqs);
>>>  	if (ret) {
>>>  		DPU_ERROR("unable to find appropriate mixers\n");
>>>  		return ret;
>>>  	}
>>> 
>>> -	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, &reqs->topology);
>>> +	ret = _dpu_rm_reserve_ctls(rm, enc->base.id, dpu_cstate,
>>> +				   &reqs->topology);
>>>  	if (ret) {
>>>  		DPU_ERROR("unable to find appropriate CTL\n");
>>>  		return ret;
>>>  	}
>>> 
>>> -	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id,
>> &reqs->hw_res);
>>> +	ret = _dpu_rm_reserve_intf_related_hw(rm, enc->base.id,
>> dpu_cstate,
>>> +					      &reqs->hw_res);
>>>  	if (ret)
>>>  		return ret;
>>> 
>>> @@ -594,7 +611,6 @@ static int _dpu_rm_make_reservation(
>>>  static int _dpu_rm_populate_requirements(
>>>  		struct dpu_rm *rm,
>>>  		struct drm_encoder *enc,
>>> -		struct drm_crtc_state *crtc_state,
>>>  		struct dpu_rm_requirements *reqs,
>>>  		struct msm_display_topology req_topology)
>>>  {
>>> @@ -642,6 +658,7 @@ int dpu_rm_reserve(
>>>  		bool test_only)
>>>  {
>>>  	struct dpu_rm_requirements reqs;
>>> +	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
>>>  	int ret;
>>> 
>>>  	/* Check if this is just a page-flip */
>>> @@ -653,14 +670,13 @@ int dpu_rm_reserve(
>>> 
>>>  	mutex_lock(&rm->rm_lock);
>>> 
>>> -	ret = _dpu_rm_populate_requirements(rm, enc, crtc_state, &reqs,
>>> -					    topology);
>>> +	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
>>>  	if (ret) {
>>>  		DPU_ERROR("failed to populate hw requirements\n");
>>>  		goto end;
>>>  	}
>>> 
>>> -	ret = _dpu_rm_make_reservation(rm, enc, crtc_state, &reqs);
>>> +	ret = _dpu_rm_make_reservation(rm, enc, dpu_cstate, &reqs);
>>>  	if (ret) {
>>>  		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
>>>  		_dpu_rm_release_reservation(rm, enc->base.id);
>>> --
>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>>> a Linux Foundation Collaborative Project
>>> 

-- 
Jeykumar S
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