* [RFC] drm/amd/display: add SI support to AMD DC
@ 2018-10-08 2:23 Mauro Rossi
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
[PATCH 01/10] drm/amd/display: add asics info for SI parts
[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
[PATCH 09/10] drm/amdgpu: enable DC support for SI parts
[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
The series adds preliminar SI support as a Proof Of Concept,
based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
Android-x86 need/motivation lies in the following chain of dependencies:
Vulkan radv requires gbm gralloc prime_fd support,
gbm gralloc requires drm hwcomposer,
drm hwcomposer requires Atomic Display Framework,
Atomic Display Framework requires AMD DC, currently not supporting SI.
So the goals are:
1) to get Vulkan radv working on SI parts for android-x86.
2) to remove the gap in SI (GCN 1st gen) not having atomic support.
DCE6 specific code was implemented as a replica of existing DCE8 support
and based on how DCE8 specific code was added on top of DCE10,11 support
by adding dce60* sources, functions, macros for each existing in dce80*
CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
During this first iteration of review, there are aspects to verify:
- dce60 code has been added mechanically, so there may be redundancies
and space for refactoring part of the code
- dce60_resources was having too many building errors due to missing DCE6 macros
in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- gfx6 may require some ad hoc initialization, skipped for the moment
- Hainan specific code requires review, as some documentation and code paths
seem to point that famility may not have DCE6, please confirm
- video decoding blocks code have not been touched
- dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
- dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
- dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
- dc/amdgpu_dm/* changes may be incomplete
- Any other omissis to be reviewed
- Feedback on best testing strategy required
Review from an expert of the DC impacted modules is recommended
SW Layer
/===============================================================\
| DC Display Timing Mode Asic |
| Interface Service Service Manager Capability* |
| |
| Display Topology Display Link Adapter |
| Path Manager Capability Service Service |
| Service |
|---------------------------------------------------------------|
| GPIO* IRQ I2cAux HW BIOS |
| Service** Manager* Sequencer* Parser* |
| |
| Connector Encoder Audio GPU Controller |
| |
\===============================================================/
HW Layer
Legend:
*dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
**dce60 support was added using dce_8_0_{d,sh_mask}.h headers
Android-x86 preliminary tests results:
[Boots with drm gralloc]
3DMark Slingshot
GFXbench OpenGLES benchmarks OK
V1 GPU benchmark (OpenGLES) OK
Regression in Google Chrome, Youtube (app does not show up)
Regression in Olympus Rising, Chicken Invaders (app does not show up)
[Boots with drm hwcomposer + gbm gralloc]
Google Chrome, Youtube are OK
Vulkan radv HAL API becomes available with hwc+gbm gralloc
V1 GPU benchmark (Vulkan API) OK
Sacha Willems examples OK
Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
Kind regards
Mauro Rossi
android-x86 team
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 01/10] drm/amd/display: add asics info for SI parts
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support Mauro Rossi
` (10 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL
Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 40 +++++++++++++++++++
.../gpu/drm/amd/display/include/dal_types.h | 3 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 25029ed42d89..adea98e0b4b6 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -30,6 +30,34 @@
* ASIC internal revision ID
*/
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
+#define SI_TAHITI_P_A0 0x01
+#define SI_TAHITI_P_B0 0x05
+#define SI_TAHITI_P_B1 0x06
+#define SI_PITCAIRN_PM_A0 0x14
+#define SI_PITCAIRN_PM_A1 0x15
+#define SI_CAPEVERDE_M_A0 0x28
+#define SI_CAPEVERDE_M_A1 0x29
+#define SI_OLAND_M_A0 0x3C
+#define SI_HAINAN_V_A0 0x46
+
+#define SI_UNKNOWN 0xFF
+
+#define ASIC_REV_IS_TAHITI_P(rev) \
+ ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
+
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
+ ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
+
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
+ ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
+
+#define ASIC_REV_IS_OLAND_M(rev) \
+ ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
+
+#define ASIC_REV_IS_HAINAN_V(rev) \
+ ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
+
/* DCE80 (based on ci_id.h in Perforce) */
#define CI_BONAIRE_M_A0 0x14
#define CI_BONAIRE_M_A1 0x15
@@ -143,12 +171,24 @@
/*
* ASIC chip ID
*/
+
+/* DCE60 */
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
+
/* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839
#define DEVICE_ID_TEMASH_983D 0x983D
/* Asic Family IDs for different asic family. */
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 840142b65f8b..df1d3f9d8e14 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -34,6 +34,9 @@ struct dc_bios;
enum dce_version {
DCE_VERSION_UNKNOWN = (-1),
+ DCE_VERSION_6_0,
+ DCE_VERSION_6_1,
+ DCE_VERSION_6_4,
DCE_VERSION_8_0,
DCE_VERSION_8_1,
DCE_VERSION_8_3,
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-08 2:23 ` [PATCH 01/10] drm/amd/display: add asics info for SI parts Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 03/10] drm/amd/display: dc/core: " Mauro Rossi
` (9 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
only to build dce60_resource.c due to missing *_DCE60 macros/registers/masks
IMPORTANT: Coding of dce60_resource.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
.../drm/amd/display/dc/dce/dce_clock_source.c | 15 +
drivers/gpu/drm/amd/display/dc/dce60/Makefile | 34 +
.../amd/display/dc/dce60/dce60_hw_sequencer.c | 81 +
.../amd/display/dc/dce60/dce60_hw_sequencer.h | 36 +
.../drm/amd/display/dc/dce60/dce60_resource.c | 1348 +++++++++++++++++
.../drm/amd/display/dc/dce60/dce60_resource.h | 47 +
.../display/dc/dce60/dce60_timing_generator.c | 242 +++
.../display/dc/dce60/dce60_timing_generator.h | 39 +
.../include/asic_reg/dce/dce_6_0_sh_mask.h | 4 +
10 files changed, 1850 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..d5d5acd57559 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -36,6 +36,10 @@ DC_LIBS += dce110
DC_LIBS += dce100
DC_LIBS += dce80
+ifdef CONFIG_DRM_AMD_DC_SI
+DC_LIBS += dce60
+endif
+
AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
include $(AMD_DC)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ca137757a69e..d96c977e451b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -580,6 +580,11 @@ static uint32_t dce110_get_pix_clk_dividers(
}
switch (cs->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -941,6 +946,11 @@ static bool dce110_program_pix_clk(
bp_pc_params.signal_type = pix_clk_params->signal_type;
switch (clock_source->ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
@@ -1296,6 +1306,11 @@ bool dce110_clk_src_construct(
fw_info.external_clock_source_frequency_for_dp;
switch (clk_src->base.ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/Makefile b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
new file mode 100644
index 000000000000..39afd7c59a7c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/Makefile
@@ -0,0 +1,34 @@
+#
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \
+ dce60_resource.o
+
+AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)
+
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
new file mode 100644
index 000000000000..f04d77b8d8a9
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+#include "core_types.h"
+#include "dce60_hw_sequencer.h"
+
+#include "dce/dce_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dce100/dce100_hw_sequencer.h"
+
+/* include DCE8 register header files */
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+struct dce60_hw_seq_reg_offsets {
+ uint32_t crtc;
+};
+
+static const struct dce60_hw_seq_reg_offsets reg_offsets[] = {
+{
+ .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+}
+};
+
+#define HW_REG_CRTC(reg, id)\
+ (reg + reg_offsets[id].crtc)
+
+/*******************************************************************************
+ * Private definitions
+ ******************************************************************************/
+
+/***************************PIPE_CONTROL***********************************/
+
+void dce60_hw_sequencer_construct(struct dc *dc)
+{
+ dce110_hw_sequencer_construct(dc);
+
+ dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
+ dc->hwss.pipe_control_lock = dce_pipe_control_lock;
+ dc->hwss.set_bandwidth = dce100_set_bandwidth;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
new file mode 100644
index 000000000000..e7ce63b1f75a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h
@@ -0,0 +1,36 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCE60_H__
+#define __DC_HWSS_DCE60_H__
+
+#include "core_types.h"
+
+struct dc;
+
+void dce60_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_HWSS_DCE60_H__ */
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
new file mode 100644
index 000000000000..3c7568811697
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -0,0 +1,1348 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "dm_services.h"
+
+#include "link_encoder.h"
+#include "stream_encoder.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "irq/dce60/irq_service_dce60.h"
+#include "dce110/dce110_timing_generator.h"
+#include "dce110/dce110_resource.h"
+#include "dce60/dce60_timing_generator.h"
+#include "dce/dce_mem_input.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
+#include "dce/dce_mem_input.h"
+#include "dce/dce_ipp.h"
+#include "dce/dce_transform.h"
+#include "dce/dce_opp.h"
+#include "dce/dce_clocks.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "dce60/dce60_hw_sequencer.h"
+#include "dce100/dce100_resource.h"
+
+#include "reg_helper.h"
+
+#include "dce/dce_dmcu.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_abm.h"
+/* TODO remove this include */
+
+#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
+#include "gmc/gmc_6_0_d.h"
+#include "gmc/gmc_6_0_sh_mask.h"
+#endif
+
+#ifndef mmDP_DPHY_INTERNAL_CTRL
+#define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
+#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
+#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
+#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
+#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
+#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
+#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
+#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
+#endif
+
+
+#ifndef mmBIOS_SCRATCH_2
+ #define mmBIOS_SCRATCH_2 0x05CB
+ #define mmBIOS_SCRATCH_6 0x05CF
+#endif
+
+#ifndef mmDP_DPHY_FAST_TRAINING
+ #define mmDP_DPHY_FAST_TRAINING 0x1CCE
+ #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
+ #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
+ #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
+ #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
+ #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
+ #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
+ #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
+#endif
+
+
+#ifndef mmHPD_DC_HPD_CONTROL
+ #define mmHPD_DC_HPD_CONTROL 0x189A
+ #define mmHPD0_DC_HPD_CONTROL 0x189A
+ #define mmHPD1_DC_HPD_CONTROL 0x18A2
+ #define mmHPD2_DC_HPD_CONTROL 0x18AA
+ #define mmHPD3_DC_HPD_CONTROL 0x18B2
+ #define mmHPD4_DC_HPD_CONTROL 0x18BA
+ #define mmHPD5_DC_HPD_CONTROL 0x18C2
+#endif
+
+#define DCE11_DIG_FE_CNTL 0x4a00
+#define DCE11_DIG_BE_CNTL 0x4a47
+#define DCE11_DP_SEC 0x4ac3
+
+static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
+ {
+ .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ },
+ {
+ .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ },
+ {
+ .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ },
+ {
+ .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ },
+ {
+ .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ },
+ {
+ .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
+ .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
+ .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
+ - mmDPG_WATERMARK_MASK_CONTROL),
+ }
+};
+
+/* set register offset */
+#define SR(reg_name)\
+ .reg_name = mm ## reg_name
+
+/* set register offset with instance */
+#define SRI(reg_name, block, id)\
+ .reg_name = mm ## block ## id ## _ ## reg_name
+
+
+static const struct dccg_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dccg_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dccg_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+#define ipp_regs(id)\
+[id] = {\
+ IPP_COMMON_REG_LIST_DCE_BASE(id)\
+}
+
+static const struct dce_ipp_registers ipp_regs[] = {
+ ipp_regs(0),
+ ipp_regs(1),
+ ipp_regs(2),
+ ipp_regs(3),
+ ipp_regs(4),
+ ipp_regs(5)
+};
+
+static const struct dce_ipp_shift ipp_shift = {
+ IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_ipp_mask ipp_mask = {
+ IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+#define transform_regs(id)\
+[id] = {\
+ XFM_COMMON_REG_LIST_DCE80(id)\
+}
+
+static const struct dce_transform_registers xfm_regs[] = {
+ transform_regs(0),
+ transform_regs(1),
+ transform_regs(2),
+ transform_regs(3),
+ transform_regs(4),
+ transform_regs(5)
+};
+
+static const struct dce_transform_shift xfm_shift = {
+ XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
+};
+
+static const struct dce_transform_mask xfm_mask = {
+ XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
+};
+
+#define aux_regs(id)\
+[id] = {\
+ AUX_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
+ aux_regs(0),
+ aux_regs(1),
+ aux_regs(2),
+ aux_regs(3),
+ aux_regs(4),
+ aux_regs(5)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+ HPD_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+ hpd_regs(0),
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5)
+};
+
+#define link_regs(id)\
+[id] = {\
+ LE_DCE80_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_registers link_enc_regs[] = {
+ link_regs(0),
+ link_regs(1),
+ link_regs(2),
+ link_regs(3),
+ link_regs(4),
+ link_regs(5),
+ link_regs(6),
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+ SE_COMMON_REG_LIST_DCE_BASE(id),\
+ .AFMT_CNTL = 0,\
+}
+
+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
+ stream_enc_regs(0),
+ stream_enc_regs(1),
+ stream_enc_regs(2),
+ stream_enc_regs(3),
+ stream_enc_regs(4),
+ stream_enc_regs(5),
+ stream_enc_regs(6)
+};
+
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+ OPP_DCE_80_REG_LIST(id),\
+}
+
+static const struct dce_opp_registers opp_regs[] = {
+ opp_regs(0),
+ opp_regs(1),
+ opp_regs(2),
+ opp_regs(3),
+ opp_regs(4),
+ opp_regs(5)
+};
+
+static const struct dce_opp_shift opp_shift = {
+ OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
+};
+
+static const struct dce_opp_mask opp_mask = {
+ OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+ AUX_COMMON_REG_LIST(id), \
+ .AUX_RESET_MASK = 0 \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+ aux_engine_regs(0),
+ aux_engine_regs(1),
+ aux_engine_regs(2),
+ aux_engine_regs(3),
+ aux_engine_regs(4),
+ aux_engine_regs(5)
+};
+
+#define audio_regs(id)\
+[id] = {\
+ AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+ audio_regs(0),
+ audio_regs(1),
+ audio_regs(2),
+ audio_regs(3),
+ audio_regs(4),
+ audio_regs(5),
+ audio_regs(6),
+};
+
+static const struct dce_audio_shift audio_shift = {
+ AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_aduio_mask audio_mask = {
+ AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define clk_src_regs(id)\
+[id] = {\
+ CS_COMMON_REG_LIST_DCE_80(id),\
+}
+
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+ clk_src_regs(0),
+ clk_src_regs(1),
+ clk_src_regs(2)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+ CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+ CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+static const struct bios_registers bios_regs = {
+ .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
+
+static const struct resource_caps res_cap = {
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 2,
+};
+
+static const struct resource_caps res_cap_61 = {
+ .num_timing_generator = 4,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 2,
+};
+
+static const struct resource_caps res_cap_64 = {
+ .num_timing_generator = 2,
+ .num_audio = 2,
+ .num_stream_encoder = 2,
+ .num_pll = 2,
+};
+
+static const struct dce_dmcu_registers dmcu_regs = {
+ DMCU_DCE80_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+ DMCU_MASK_SH_LIST_DCE80(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+ DMCU_MASK_SH_LIST_DCE80(_MASK)
+};
+static const struct dce_abm_registers abm_regs = {
+ ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+ ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCE110(_MASK)
+};
+
+#define CTX ctx
+#define REG(reg) mm ## reg
+
+#ifndef mmCC_DC_HDMI_STRAPS
+#define mmCC_DC_HDMI_STRAPS 0x1918
+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
+#endif
+
+static void read_dce_straps(
+ struct dc_context *ctx,
+ struct resource_straps *straps)
+{
+ REG_GET_2(CC_DC_HDMI_STRAPS,
+ HDMI_DISABLE, &straps->hdmi_disable,
+ AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
+
+ REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
+}
+
+static struct audio *create_audio(
+ struct dc_context *ctx, unsigned int inst)
+{
+ return dce_audio_create(ctx, inst,
+ &audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct timing_generator *dce60_timing_generator_create(
+ struct dc_context *ctx,
+ uint32_t instance,
+ const struct dce110_timing_generator_offsets *offsets)
+{
+ struct dce110_timing_generator *tg110 =
+ kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
+
+ if (!tg110)
+ return NULL;
+
+ dce60_timing_generator_construct(tg110, ctx, instance, offsets);
+ return &tg110->base;
+}
+
+static struct output_pixel_processor *dce60_opp_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dce110_opp *opp =
+ kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
+
+ if (!opp)
+ return NULL;
+
+ dce110_opp_construct(opp,
+ ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
+ return &opp->base;
+}
+
+struct aux_engine *dce60_aux_engine_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct aux_engine_dce110 *aux_engine =
+ kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+ if (!aux_engine)
+ return NULL;
+
+ dce110_aux_engine_construct(aux_engine, ctx, inst,
+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+ &aux_engine_regs[inst]);
+
+ return &aux_engine->base;
+}
+
+static struct stream_encoder *dce60_stream_encoder_create(
+ enum engine_id eng_id,
+ struct dc_context *ctx)
+{
+ struct dce110_stream_encoder *enc110 =
+ kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
+
+ if (!enc110)
+ return NULL;
+
+ dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id],
+ &se_shift, &se_mask);
+ return &enc110->base;
+}
+
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_DCE8_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_DCE8_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_hwseq *dce60_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
+static const struct resource_create_funcs res_create_funcs = {
+ .read_dce_straps = read_dce_straps,
+ .create_audio = create_audio,
+ .create_stream_encoder = dce60_stream_encoder_create,
+ .create_hwseq = dce60_hwseq_create,
+};
+
+#define mi_inst_regs(id) { \
+ MI_DCE8_REG_LIST(id), \
+ .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
+}
+static const struct dce_mem_input_registers mi_regs[] = {
+ mi_inst_regs(0),
+ mi_inst_regs(1),
+ mi_inst_regs(2),
+ mi_inst_regs(3),
+ mi_inst_regs(4),
+ mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+ MI_DCE8_MASK_SH_LIST(__SHIFT),
+ .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+ MI_DCE8_MASK_SH_LIST(_MASK),
+ .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
+};
+
+static struct mem_input *dce60_mem_input_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
+ GFP_KERNEL);
+
+ if (!dce_mi) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
+ dce_mi->wa.single_head_rdreq_dmif_limit = 2;
+ return &dce_mi->base;
+}
+
+static void dce60_transform_destroy(struct transform **xfm)
+{
+ kfree(TO_DCE_TRANSFORM(*xfm));
+ *xfm = NULL;
+}
+
+static struct transform *dce60_transform_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dce_transform *transform =
+ kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
+
+ if (!transform)
+ return NULL;
+
+ dce_transform_construct(transform, ctx, inst,
+ &xfm_regs[inst], &xfm_shift, &xfm_mask);
+ transform->prescaler_on = false;
+ return &transform->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+ .max_hdmi_deep_color = COLOR_DEPTH_121212,
+ .max_hdmi_pixel_clock = 297000,
+ .flags.bits.IS_HBR2_CAPABLE = true,
+ .flags.bits.IS_TPS3_CAPABLE = true,
+ .flags.bits.IS_YCBCR_CAPABLE = true
+};
+
+struct link_encoder *dce60_link_encoder_create(
+ const struct encoder_init_data *enc_init_data)
+{
+ struct dce110_link_encoder *enc110 =
+ kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
+
+ if (!enc110)
+ return NULL;
+
+ dce110_link_encoder_construct(enc110,
+ enc_init_data,
+ &link_enc_feature,
+ &link_enc_regs[enc_init_data->transmitter],
+ &link_enc_aux_regs[enc_init_data->channel - 1],
+ &link_enc_hpd_regs[enc_init_data->hpd_source]);
+ return &enc110->base;
+}
+
+struct clock_source *dce60_clock_source_create(
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ bool dp_clk_src)
+{
+ struct dce110_clk_src *clk_src =
+ kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+ if (!clk_src)
+ return NULL;
+
+ if (dce110_clk_src_construct(clk_src, ctx, bios, id,
+ regs, &cs_shift, &cs_mask)) {
+ clk_src->base.dp_clk_src = dp_clk_src;
+ return &clk_src->base;
+ }
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
+
+void dce60_clock_source_destroy(struct clock_source **clk_src)
+{
+ kfree(TO_DCE110_CLK_SRC(*clk_src));
+ *clk_src = NULL;
+}
+
+static struct input_pixel_processor *dce60_ipp_create(
+ struct dc_context *ctx, uint32_t inst)
+{
+ struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
+
+ if (!ipp) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_ipp_construct(ipp, ctx, inst,
+ &ipp_regs[inst], &ipp_shift, &ipp_mask);
+ return &ipp->base;
+}
+
+static void destruct(struct dce110_resource_pool *pool)
+{
+ unsigned int i;
+
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ if (pool->base.opps[i] != NULL)
+ dce110_opp_destroy(&pool->base.opps[i]);
+
+ if (pool->base.transforms[i] != NULL)
+ dce60_transform_destroy(&pool->base.transforms[i]);
+
+ if (pool->base.ipps[i] != NULL)
+ dce_ipp_destroy(&pool->base.ipps[i]);
+
+ if (pool->base.mis[i] != NULL) {
+ kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
+ pool->base.mis[i] = NULL;
+ }
+
+ if (pool->base.timing_generators[i] != NULL) {
+ kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
+ pool->base.timing_generators[i] = NULL;
+ }
+
+ if (pool->base.engines[i] != NULL)
+ dce110_engine_destroy(&pool->base.engines[i]);
+ }
+
+ for (i = 0; i < pool->base.stream_enc_count; i++) {
+ if (pool->base.stream_enc[i] != NULL)
+ kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] != NULL) {
+ dce60_clock_source_destroy(&pool->base.clock_sources[i]);
+ }
+ }
+
+ if (pool->base.abm != NULL)
+ dce_abm_destroy(&pool->base.abm);
+
+ if (pool->base.dmcu != NULL)
+ dce_dmcu_destroy(&pool->base.dmcu);
+
+ if (pool->base.dp_clock_source != NULL)
+ dce60_clock_source_destroy(&pool->base.dp_clock_source);
+
+ for (i = 0; i < pool->base.audio_count; i++) {
+ if (pool->base.audios[i] != NULL) {
+ dce_aud_destroy(&pool->base.audios[i]);
+ }
+ }
+
+ if (pool->base.dccg != NULL)
+ dce_dccg_destroy(&pool->base.dccg);
+
+ if (pool->base.irqs != NULL) {
+ dal_irq_service_destroy(&pool->base.irqs);
+ }
+}
+
+bool dce60_validate_bandwidth(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ /* TODO implement when needed but for now hardcode max value*/
+ context->bw.dce.dispclk_khz = 681000;
+ context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
+
+ return true;
+}
+
+static bool dce60_validate_surface_sets(
+ struct dc_state *context)
+{
+ int i;
+
+ for (i = 0; i < context->stream_count; i++) {
+ if (context->stream_status[i].plane_count == 0)
+ continue;
+
+ if (context->stream_status[i].plane_count > 1)
+ return false;
+
+ if (context->stream_status[i].plane_states[0]->format
+ >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ return false;
+ }
+
+ return true;
+}
+
+enum dc_status dce60_validate_global(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ if (!dce60_validate_surface_sets(context))
+ return DC_FAIL_SURFACE_VALIDATE;
+
+ return DC_OK;
+}
+
+static void dce60_destroy_resource_pool(struct resource_pool **pool)
+{
+ struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
+
+ destruct(dce110_pool);
+ kfree(dce110_pool);
+ *pool = NULL;
+}
+
+static const struct resource_funcs dce60_res_pool_funcs = {
+ .destroy = dce60_destroy_resource_pool,
+ .link_enc_create = dce60_link_encoder_create,
+ .validate_bandwidth = dce60_validate_bandwidth,
+ .validate_plane = dce100_validate_plane,
+ .add_stream_to_ctx = dce100_add_stream_to_ctx,
+ .validate_global = dce60_validate_global
+};
+
+static bool dce60_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+{
+ unsigned int i;
+ struct dc_context *ctx = dc->ctx;
+ struct dc_firmware_info info;
+ struct dc_bios *bp;
+ struct dm_pp_static_clock_info static_clk_info = {0};
+
+ ctx->dc_bios->regs = &bios_regs;
+
+ pool->base.res_cap = &res_cap;
+ pool->base.funcs = &dce60_res_pool_funcs;
+
+
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+ pool->base.pipe_count = res_cap.num_timing_generator;
+ pool->base.timing_generator_count = res_cap.num_timing_generator;
+ dc->caps.max_downscale_ratio = 200;
+ dc->caps.i2c_speed_in_khz = 40;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.dual_link_dvi = true;
+
+ /*************************************************
+ * Create resources *
+ *************************************************/
+
+ bp = ctx->dc_bios;
+
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+ info.external_clock_source_frequency_for_dp != 0) {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
+ pool->base.clock_sources[1] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+ pool->base.clock_sources[2] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+ pool->base.clk_src_count = 3;
+
+ } else {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+ pool->base.clock_sources[1] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+ pool->base.clk_src_count = 2;
+ }
+
+ if (pool->base.dp_clock_source == NULL) {
+ dm_error("DC: failed to create dp clock source!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] == NULL) {
+ dm_error("DC: failed to create clock sources!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+ }
+
+ pool->base.dccg = dce_dccg_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
+ if (pool->base.dccg == NULL) {
+ dm_error("DC: failed to create display clock!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.dmcu = dce_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+ if (pool->base.dmcu == NULL) {
+ dm_error("DC: failed to create dmcu!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.abm = dce_abm_create(ctx,
+ &abm_regs,
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.abm == NULL) {
+ dm_error("DC: failed to create abm!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.dccg->max_clks_state =
+ static_clk_info.max_clocks_state;
+
+ {
+ struct irq_service_init_data init_data;
+ init_data.ctx = dc->ctx;
+ pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+ if (!pool->base.irqs)
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ pool->base.timing_generators[i] = dce60_timing_generator_create(
+ ctx, i, &dce60_tg_offsets[i]);
+ if (pool->base.timing_generators[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create tg!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+ if (pool->base.mis[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create memory input!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+ if (pool->base.ipps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create input pixel processor!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.transforms[i] = dce60_transform_create(ctx, i);
+ if (pool->base.transforms[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create transform!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.opps[i] = dce60_opp_create(ctx, i);
+ if (pool->base.opps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
+ if (pool->base.engines[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC:failed to create aux engine!!\n");
+ goto res_create_fail;
+ }
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+ dce60_hw_sequencer_construct(dc);
+
+ return true;
+
+res_create_fail:
+ destruct(pool);
+ return false;
+}
+
+struct resource_pool *dce60_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc)
+{
+ struct dce110_resource_pool *pool =
+ kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+ if (!pool)
+ return NULL;
+
+ if (dce60_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
+
+static bool dce61_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+{
+ unsigned int i;
+ struct dc_context *ctx = dc->ctx;
+ struct dc_firmware_info info;
+ struct dc_bios *bp;
+ struct dm_pp_static_clock_info static_clk_info = {0};
+
+ ctx->dc_bios->regs = &bios_regs;
+
+ pool->base.res_cap = &res_cap_61;
+ pool->base.funcs = &dce60_res_pool_funcs;
+
+
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+ pool->base.pipe_count = res_cap_61.num_timing_generator;
+ pool->base.timing_generator_count = res_cap_61.num_timing_generator;
+ dc->caps.max_downscale_ratio = 200;
+ dc->caps.i2c_speed_in_khz = 40;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
+
+ /*************************************************
+ * Create resources *
+ *************************************************/
+
+ bp = ctx->dc_bios;
+
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+ info.external_clock_source_frequency_for_dp != 0) {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
+ pool->base.clock_sources[1] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+ pool->base.clock_sources[2] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+ pool->base.clk_src_count = 3;
+
+ } else {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
+ pool->base.clock_sources[1] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
+ pool->base.clk_src_count = 2;
+ }
+
+ if (pool->base.dp_clock_source == NULL) {
+ dm_error("DC: failed to create dp clock source!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] == NULL) {
+ dm_error("DC: failed to create clock sources!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+ }
+
+ pool->base.dccg = dce_dccg_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
+ if (pool->base.dccg == NULL) {
+ dm_error("DC: failed to create display clock!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.dmcu = dce_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+ if (pool->base.dmcu == NULL) {
+ dm_error("DC: failed to create dmcu!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.abm = dce_abm_create(ctx,
+ &abm_regs,
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.abm == NULL) {
+ dm_error("DC: failed to create abm!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.dccg->max_clks_state =
+ static_clk_info.max_clocks_state;
+
+ {
+ struct irq_service_init_data init_data;
+ init_data.ctx = dc->ctx;
+ pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+ if (!pool->base.irqs)
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ pool->base.timing_generators[i] = dce60_timing_generator_create(
+ ctx, i, &dce60_tg_offsets[i]);
+ if (pool->base.timing_generators[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create tg!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+ if (pool->base.mis[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create memory input!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+ if (pool->base.ipps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create input pixel processor!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.transforms[i] = dce60_transform_create(ctx, i);
+ if (pool->base.transforms[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create transform!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.opps[i] = dce60_opp_create(ctx, i);
+ if (pool->base.opps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+ dce60_hw_sequencer_construct(dc);
+
+ return true;
+
+res_create_fail:
+ destruct(pool);
+ return false;
+}
+
+struct resource_pool *dce61_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc)
+{
+ struct dce110_resource_pool *pool =
+ kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+ if (!pool)
+ return NULL;
+
+ if (dce61_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
+
+static bool dce64_construct(
+ uint8_t num_virtual_links,
+ struct dc *dc,
+ struct dce110_resource_pool *pool)
+{
+ unsigned int i;
+ struct dc_context *ctx = dc->ctx;
+ struct dc_firmware_info info;
+ struct dc_bios *bp;
+ struct dm_pp_static_clock_info static_clk_info = {0};
+
+ ctx->dc_bios->regs = &bios_regs;
+
+ pool->base.res_cap = &res_cap_64;
+ pool->base.funcs = &dce60_res_pool_funcs;
+
+
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+ pool->base.pipe_count = res_cap_64.num_timing_generator;
+ pool->base.timing_generator_count = res_cap_64.num_timing_generator;
+ dc->caps.max_downscale_ratio = 200;
+ dc->caps.i2c_speed_in_khz = 40;
+ dc->caps.max_cursor_size = 128;
+ dc->caps.is_apu = true;
+
+ /*************************************************
+ * Create resources *
+ *************************************************/
+
+ bp = ctx->dc_bios;
+
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
+ info.external_clock_source_frequency_for_dp != 0) {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
+ pool->base.clock_sources[1] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
+ pool->base.clk_src_count = 2;
+
+ } else {
+ pool->base.dp_clock_source =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
+
+ pool->base.clock_sources[0] =
+ dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
+ pool->base.clk_src_count = 1;
+ }
+
+ if (pool->base.dp_clock_source == NULL) {
+ dm_error("DC: failed to create dp clock source!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] == NULL) {
+ dm_error("DC: failed to create clock sources!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+ }
+
+ pool->base.dccg = dce_dccg_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
+ if (pool->base.dccg == NULL) {
+ dm_error("DC: failed to create display clock!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.dmcu = dce_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+ if (pool->base.dmcu == NULL) {
+ dm_error("DC: failed to create dmcu!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.abm = dce_abm_create(ctx,
+ &abm_regs,
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.abm == NULL) {
+ dm_error("DC: failed to create abm!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.dccg->max_clks_state =
+ static_clk_info.max_clocks_state;
+
+ {
+ struct irq_service_init_data init_data;
+ init_data.ctx = dc->ctx;
+ pool->base.irqs = dal_irq_service_dce60_create(&init_data);
+ if (!pool->base.irqs)
+ goto res_create_fail;
+ }
+
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ pool->base.timing_generators[i] = dce60_timing_generator_create(
+ ctx, i, &dce60_tg_offsets[i]);
+ if (pool->base.timing_generators[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create tg!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.mis[i] = dce60_mem_input_create(ctx, i);
+ if (pool->base.mis[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create memory input!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.ipps[i] = dce60_ipp_create(ctx, i);
+ if (pool->base.ipps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create input pixel processor!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.transforms[i] = dce60_transform_create(ctx, i);
+ if (pool->base.transforms[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create transform!\n");
+ goto res_create_fail;
+ }
+
+ pool->base.opps[i] = dce60_opp_create(ctx, i);
+ if (pool->base.opps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create output pixel processor!\n");
+ goto res_create_fail;
+ }
+ }
+
+ dc->caps.max_planes = pool->base.pipe_count;
+ dc->caps.disable_dp_clk_share = true;
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+ dce60_hw_sequencer_construct(dc);
+
+ return true;
+
+res_create_fail:
+ destruct(pool);
+ return false;
+}
+
+struct resource_pool *dce64_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc)
+{
+ struct dce110_resource_pool *pool =
+ kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
+
+ if (!pool)
+ return NULL;
+
+ if (dce64_construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
new file mode 100644
index 000000000000..b30e4e4ed7c0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.h
@@ -0,0 +1,47 @@
+/*
+* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCE60_H__
+#define __DC_RESOURCE_DCE60_H__
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+
+struct resource_pool *dce60_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc);
+
+struct resource_pool *dce61_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc);
+
+struct resource_pool *dce64_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct dc *dc);
+
+#endif /* __DC_RESOURCE_DCE60_H__ */
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
new file mode 100644
index 000000000000..90b610367af8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE6 register header files */
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#include "dc_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/logger_interface.h"
+#include "../dce110/dce110_timing_generator.h"
+#include "dce60_timing_generator.h"
+
+#include "timing_generator.h"
+
+enum black_color_format {
+ BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
+ BLACK_COLOR_FORMAT_RGB_LIMITED,
+ BLACK_COLOR_FORMAT_YUV_TV,
+ BLACK_COLOR_FORMAT_YUV_CV,
+ BLACK_COLOR_FORMAT_YUV_SUPER_AA,
+
+ BLACK_COLOR_FORMAT_COUNT
+};
+
+static const struct dce110_timing_generator_offsets reg_offsets[] = {
+{
+ .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+ .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+ .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+ .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+ .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+},
+{
+ .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
+ .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+}
+};
+
+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
+
+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
+
+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
+#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
+
+static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
+{
+ uint64_t pix_dur;
+ uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
+ + DCE110TG_FROM_TG(tg)->offsets.dmif;
+ uint32_t value = dm_read_reg(tg->ctx, addr);
+
+ if (pix_clk_khz == 0)
+ return;
+
+ pix_dur = 1000000000 / pix_clk_khz;
+
+ set_reg_field_value(
+ value,
+ pix_dur,
+ DPG_PIPE_ARBITRATION_CONTROL1,
+ PIXEL_DURATION);
+
+ dm_write_reg(tg->ctx, addr, value);
+}
+
+static void program_timing(struct timing_generator *tg,
+ const struct dc_crtc_timing *timing,
+ bool use_vbios)
+{
+ if (!use_vbios)
+ program_pix_dur(tg, timing->pix_clk_khz);
+
+ dce110_tg_program_timing(tg, timing, use_vbios);
+}
+
+static void dce60_timing_generator_enable_advanced_request(
+ struct timing_generator *tg,
+ bool enable,
+ const struct dc_crtc_timing *timing)
+{
+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+ uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
+ uint32_t value = dm_read_reg(tg->ctx, addr);
+
+ if (enable) {
+ set_reg_field_value(
+ value,
+ 0,
+ CRTC_START_LINE_CONTROL,
+ CRTC_LEGACY_REQUESTOR_EN);
+ } else {
+ set_reg_field_value(
+ value,
+ 1,
+ CRTC_START_LINE_CONTROL,
+ CRTC_LEGACY_REQUESTOR_EN);
+ }
+
+ if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
+ set_reg_field_value(
+ value,
+ 3,
+ CRTC_START_LINE_CONTROL,
+ CRTC_ADVANCED_START_LINE_POSITION);
+ set_reg_field_value(
+ value,
+ 0,
+ CRTC_START_LINE_CONTROL,
+ CRTC_PREFETCH_EN);
+ } else {
+ set_reg_field_value(
+ value,
+ 4,
+ CRTC_START_LINE_CONTROL,
+ CRTC_ADVANCED_START_LINE_POSITION);
+ set_reg_field_value(
+ value,
+ 1,
+ CRTC_START_LINE_CONTROL,
+ CRTC_PREFETCH_EN);
+ }
+
+ set_reg_field_value(
+ value,
+ 1,
+ CRTC_START_LINE_CONTROL,
+ CRTC_PROGRESSIVE_START_LINE_EARLY);
+
+ set_reg_field_value(
+ value,
+ 1,
+ CRTC_START_LINE_CONTROL,
+ CRTC_INTERLACE_START_LINE_EARLY);
+
+ dm_write_reg(tg->ctx, addr, value);
+}
+
+static const struct timing_generator_funcs dce60_tg_funcs = {
+ .validate_timing = dce110_tg_validate_timing,
+ .program_timing = program_timing,
+ .enable_crtc = dce110_timing_generator_enable_crtc,
+ .disable_crtc = dce110_timing_generator_disable_crtc,
+ .is_counter_moving = dce110_timing_generator_is_counter_moving,
+ .get_position = dce110_timing_generator_get_position,
+ .get_frame_count = dce110_timing_generator_get_vblank_counter,
+ .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
+ .set_early_control = dce110_timing_generator_set_early_control,
+ .wait_for_state = dce110_tg_wait_for_state,
+ .set_blank = dce110_tg_set_blank,
+ .is_blanked = dce110_tg_is_blanked,
+ .set_colors = dce110_tg_set_colors,
+ .set_overscan_blank_color =
+ dce110_timing_generator_set_overscan_color_black,
+ .set_blank_color = dce110_timing_generator_program_blank_color,
+ .disable_vga = dce110_timing_generator_disable_vga,
+ .did_triggered_reset_occur =
+ dce110_timing_generator_did_triggered_reset_occur,
+ .setup_global_swap_lock =
+ dce110_timing_generator_setup_global_swap_lock,
+ .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
+ .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
+ .tear_down_global_swap_lock =
+ dce110_timing_generator_tear_down_global_swap_lock,
+ .set_drr = dce110_timing_generator_set_drr,
+ .set_static_screen_control =
+ dce110_timing_generator_set_static_screen_control,
+ .set_test_pattern = dce110_timing_generator_set_test_pattern,
+ .arm_vert_intr = dce110_arm_vert_intr,
+
+ /* DCE6.0 overrides */
+ .enable_advanced_request =
+ dce60_timing_generator_enable_advanced_request,
+ .configure_crc = dce110_configure_crc,
+ .get_crc = dce110_get_crc,
+};
+
+void dce60_timing_generator_construct(
+ struct dce110_timing_generator *tg110,
+ struct dc_context *ctx,
+ uint32_t instance,
+ const struct dce110_timing_generator_offsets *offsets)
+{
+ tg110->controller_id = CONTROLLER_ID_D0 + instance;
+ tg110->base.inst = instance;
+ tg110->offsets = *offsets;
+ tg110->derived_offsets = reg_offsets[instance];
+
+ tg110->base.funcs = &dce60_tg_funcs;
+
+ tg110->base.ctx = ctx;
+ tg110->base.bp = ctx->dc_bios;
+
+ tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
+ tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
+
+ tg110->min_h_blank = 56;
+ tg110->min_h_front_porch = 4;
+ tg110->min_h_back_porch = 4;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
new file mode 100644
index 000000000000..8972cd0d5815
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_timing_generator.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_TIMING_GENERATOR_DCE60_H__
+#define __DC_TIMING_GENERATOR_DCE60_H__
+
+#include "timing_generator.h"
+#include "../include/grph_object_id.h"
+
+/* DCE6.0 implementation inherits from DCE11.0 */
+void dce60_timing_generator_construct(
+ struct dce110_timing_generator *tg,
+ struct dc_context *ctx,
+ uint32_t instance,
+ const struct dce110_timing_generator_offsets *offsets);
+
+#endif /* __DC_TIMING_GENERATOR_DCE60_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
index abe05bc80752..5492c6b98525 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
@@ -2264,6 +2264,10 @@
#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010
#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L
#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L
#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000
#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-08 2:23 ` [PATCH 01/10] drm/amd/display: add asics info for SI parts Mauro Rossi
2018-10-08 2:23 ` [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6 Mauro Rossi
` (8 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added as branching of existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index ea6beccfd89d..16568e79d4b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -37,6 +37,9 @@
#include "virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/dce60_resource.h"
+#endif
#include "dce80/dce80_resource.h"
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
@@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case FAMILY_SI:
+ if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
+ ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_0;
+ else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
+ dc_version = DCE_VERSION_6_4;
+ else
+ dc_version = DCE_VERSION_6_1;
+ break;
+#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
@@ -106,6 +121,20 @@ struct resource_pool *dc_create_resource_pool(
struct resource_pool *res_pool = NULL;
switch (dc_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ res_pool = dce60_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_1:
+ res_pool = dce61_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+ case DCE_VERSION_6_4:
+ res_pool = dce64_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
num_virtual_links, dc);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (2 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 03/10] drm/amd/display: dc/core: " Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 05/10] drm/amd/display: dc/gpio: " Mauro Rossi
` (7 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/bios/Makefile | 9 +
.../display/dc/bios/command_table_helper.c | 8 +
.../display/dc/bios/command_table_helper.h | 3 +
.../display/dc/bios/command_table_helper2.c | 8 +
.../display/dc/bios/command_table_helper2.h | 3 +
.../bios/dce60/command_table_helper_dce60.c | 354 ++++++++++++++++++
.../bios/dce60/command_table_helper_dce60.h | 33 ++
7 files changed, 418 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 239e86bbec5a..ed6b5e9763f6 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -31,6 +31,15 @@ AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
+###############################################################################
+# DCE 6x
+###############################################################################
+# All DCE6.x are derived from DCE6.0, so 6.0 MUST be defined if ANY of
+# DCE6.x is compiled.
+ifdef CONFIG_DRM_AMD_DC_SI
+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce60/command_table_helper_dce60.o
+endif
+
###############################################################################
# DCE 8x
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index 253bbb1eea60..48b4ef03fc8f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -36,6 +36,14 @@ bool dal_bios_parser_init_cmd_tbl_helper(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
index 4c3789df253d..dfd30aaf4032 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER_H__
#define __DAL_COMMAND_TABLE_HELPER_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index bbbcef566c55..dad302564da4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -37,6 +37,14 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
enum dce_version dce)
{
switch (dce) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ *h = dal_cmd_tbl_helper_dce60_get_table();
+ return true;
+#endif
+
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
index 785fcb20a1b9..66e0a3e73768 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
@@ -26,6 +26,9 @@
#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
#define __DAL_COMMAND_TABLE_HELPER2_H__
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/command_table_helper_dce60.h"
+#endif
#include "dce80/command_table_helper_dce80.h"
#include "dce110/command_table_helper_dce110.h"
#include "dce112/command_table_helper2_dce112.h"
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
new file mode 100644
index 000000000000..552778ce9835
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "atom.h"
+
+#include "include/grph_object_id.h"
+#include "include/grph_object_defs.h"
+#include "include/bios_parser_types.h"
+
+#include "../command_table_helper.h"
+
+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
+{
+ uint8_t atom_action = 0;
+
+ switch (action) {
+ case ENCODER_CONTROL_ENABLE:
+ atom_action = ATOM_ENABLE;
+ break;
+ case ENCODER_CONTROL_DISABLE:
+ atom_action = ATOM_DISABLE;
+ break;
+ case ENCODER_CONTROL_SETUP:
+ atom_action = ATOM_ENCODER_CMD_SETUP;
+ break;
+ case ENCODER_CONTROL_INIT:
+ atom_action = ATOM_ENCODER_INIT;
+ break;
+ default:
+ BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
+ break;
+ }
+
+ return atom_action;
+}
+
+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
+{
+ bool result = false;
+
+ if (atom_engine_id != NULL)
+ switch (id) {
+ case ENGINE_ID_DIGA:
+ *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGB:
+ *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGC:
+ *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGD:
+ *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGE:
+ *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGF:
+ *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DIGG:
+ *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
+ result = true;
+ break;
+ case ENGINE_ID_DACA:
+ *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
+ result = true;
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+static bool clock_source_id_to_atom(
+ enum clock_source_id id,
+ uint32_t *atom_pll_id)
+{
+ bool result = true;
+
+ if (atom_pll_id != NULL)
+ switch (id) {
+ case CLOCK_SOURCE_ID_PLL0:
+ *atom_pll_id = ATOM_PPLL0;
+ break;
+ case CLOCK_SOURCE_ID_PLL1:
+ *atom_pll_id = ATOM_PPLL1;
+ break;
+ case CLOCK_SOURCE_ID_PLL2:
+ *atom_pll_id = ATOM_PPLL2;
+ break;
+ case CLOCK_SOURCE_ID_EXTERNAL:
+ *atom_pll_id = ATOM_PPLL_INVALID;
+ break;
+ case CLOCK_SOURCE_ID_DFS:
+ *atom_pll_id = ATOM_EXT_PLL1;
+ break;
+ case CLOCK_SOURCE_ID_VCE:
+ /* for VCE encoding,
+ * we need to pass in ATOM_PPLL_INVALID
+ */
+ *atom_pll_id = ATOM_PPLL_INVALID;
+ break;
+ case CLOCK_SOURCE_ID_DP_DTO:
+ /* When programming DP DTO PLL ID should be invalid */
+ *atom_pll_id = ATOM_PPLL_INVALID;
+ break;
+ case CLOCK_SOURCE_ID_UNDEFINED:
+ BREAK_TO_DEBUGGER(); /* check when this will happen! */
+ *atom_pll_id = ATOM_PPLL_INVALID;
+ result = false;
+ break;
+ default:
+ result = false;
+ break;
+ }
+
+ return result;
+}
+
+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
+ enum clock_source_id id)
+{
+ uint8_t atom_phy_clk_src_id = 0;
+
+ switch (id) {
+ case CLOCK_SOURCE_ID_PLL0:
+ atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
+ break;
+ case CLOCK_SOURCE_ID_PLL1:
+ atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
+ break;
+ case CLOCK_SOURCE_ID_PLL2:
+ atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
+ break;
+ case CLOCK_SOURCE_ID_EXTERNAL:
+ atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
+ break;
+ default:
+ atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
+ break;
+ }
+
+ return atom_phy_clk_src_id >> 2;
+}
+
+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
+{
+ uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
+
+ switch (s) {
+ case SIGNAL_TYPE_DISPLAY_PORT:
+ case SIGNAL_TYPE_EDP:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
+ break;
+ case SIGNAL_TYPE_LVDS:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
+ break;
+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
+ case SIGNAL_TYPE_DVI_DUAL_LINK:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
+ break;
+ case SIGNAL_TYPE_HDMI_TYPE_A:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
+ break;
+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
+ break;
+ default:
+ atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
+ break;
+ }
+
+ return atom_dig_mode;
+}
+
+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
+{
+ uint8_t atom_hpd_sel = 0;
+
+ switch (id) {
+ case HPD_SOURCEID1:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
+ break;
+ case HPD_SOURCEID2:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
+ break;
+ case HPD_SOURCEID3:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
+ break;
+ case HPD_SOURCEID4:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
+ break;
+ case HPD_SOURCEID5:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
+ break;
+ case HPD_SOURCEID6:
+ atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
+ break;
+ case HPD_SOURCEID_UNKNOWN:
+ default:
+ atom_hpd_sel = 0;
+ break;
+ }
+ return atom_hpd_sel >> 4;
+}
+
+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
+{
+ uint8_t atom_dig_encoder_sel = 0;
+
+ switch (id) {
+ case ENGINE_ID_DIGA:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+ break;
+ case ENGINE_ID_DIGB:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
+ break;
+ case ENGINE_ID_DIGC:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
+ break;
+ case ENGINE_ID_DIGD:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
+ break;
+ case ENGINE_ID_DIGE:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
+ break;
+ case ENGINE_ID_DIGF:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
+ break;
+ case ENGINE_ID_DIGG:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
+ break;
+ default:
+ atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
+ break;
+ }
+
+ return atom_dig_encoder_sel;
+}
+
+static uint8_t phy_id_to_atom(enum transmitter t)
+{
+ uint8_t atom_phy_id;
+
+ switch (t) {
+ case TRANSMITTER_UNIPHY_A:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYA;
+ break;
+ case TRANSMITTER_UNIPHY_B:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYB;
+ break;
+ case TRANSMITTER_UNIPHY_C:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYC;
+ break;
+ case TRANSMITTER_UNIPHY_D:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYD;
+ break;
+ case TRANSMITTER_UNIPHY_E:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYE;
+ break;
+ case TRANSMITTER_UNIPHY_F:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYF;
+ break;
+ case TRANSMITTER_UNIPHY_G:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYG;
+ break;
+ default:
+ atom_phy_id = ATOM_PHY_ID_UNIPHYA;
+ break;
+ }
+ return atom_phy_id;
+}
+
+static uint8_t disp_power_gating_action_to_atom(
+ enum bp_pipe_control_action action)
+{
+ uint8_t atom_pipe_action = 0;
+
+ switch (action) {
+ case ASIC_PIPE_DISABLE:
+ atom_pipe_action = ATOM_DISABLE;
+ break;
+ case ASIC_PIPE_ENABLE:
+ atom_pipe_action = ATOM_ENABLE;
+ break;
+ case ASIC_PIPE_INIT:
+ atom_pipe_action = ATOM_INIT;
+ break;
+ default:
+ BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
+ break;
+ }
+
+ return atom_pipe_action;
+}
+
+static const struct command_table_helper command_table_helper_funcs = {
+ .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
+ .encoder_action_to_atom = encoder_action_to_atom,
+ .engine_bp_to_atom = engine_bp_to_atom,
+ .clock_source_id_to_atom = clock_source_id_to_atom,
+ .clock_source_id_to_atom_phy_clk_src_id =
+ clock_source_id_to_atom_phy_clk_src_id,
+ .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
+ .hpd_sel_to_atom = hpd_sel_to_atom,
+ .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
+ .phy_id_to_atom = phy_id_to_atom,
+ .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
+ .assign_control_parameter =
+ dal_cmd_table_helper_assign_control_parameter,
+ .clock_source_id_to_ref_clk_src =
+ dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
+ .transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
+ .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
+ .encoder_mode_bp_to_atom =
+ dal_cmd_table_helper_encoder_mode_bp_to_atom,
+};
+
+const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void)
+{
+ return &command_table_helper_funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
new file mode 100644
index 000000000000..591c796d0bf1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce60/command_table_helper_dce60.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE60_H__
+#define __DAL_COMMAND_TABLE_HELPER_DCE60_H__
+
+struct command_table_helper;
+
+const struct command_table_helper *dal_cmd_tbl_helper_dce60_get_table(void);
+
+#endif
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (3 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6 Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 06/10] drm/amd/display: dc/i2caux: " Mauro Rossi
` (6 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added replicating existing DCE8 implementation.
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 12 +
.../display/dc/gpio/dce60/hw_factory_dce60.c | 174 ++++++++
.../display/dc/gpio/dce60/hw_factory_dce60.h | 32 ++
.../dc/gpio/dce60/hw_translate_dce60.c | 411 ++++++++++++++++++
.../dc/gpio/dce60/hw_translate_dce60.h | 32 ++
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 10 +
.../drm/amd/display/dc/gpio/hw_translate.c | 10 +
7 files changed, 681 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..122ca9991100 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
+###############################################################################
+# DCE 6x
+###############################################################################
+# all DCE6.x are derived from DCE6.0
+ifdef CONFIG_DRM_AMD_DC_SI
+GPIO_DCE60 = hw_translate_dce60.o hw_factory_dce60.o
+
+AMD_DAL_GPIO_DCE60 = $(addprefix $(AMDDALPATH)/dc/gpio/dce60/,$(GPIO_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE60)
+endif
+
###############################################################################
# DCE 8x
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
new file mode 100644
index 000000000000..64afe9b48c5f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Mauro Rossi <issor.oruam@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+#include "hw_factory_dce60.h"
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+#define REG(reg_name)\
+ mm ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define HPD_REG_LIST_DCE6(id) \
+ HPD_GPIO_REG_LIST(id), \
+ .int_status = mmDC_HPD ## id ## _INT_STATUS,\
+ .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
+
+#define HPD_MASK_SH_LIST_DCE6(mask_sh) \
+ .DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
+ .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
+ .DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
+ .DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST_DCE6(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5),
+ hpd_regs(6)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+ HPD_MASK_SH_LIST_DCE6(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+ HPD_MASK_SH_LIST_DCE6(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+ ddc_data_regs(1),
+ ddc_data_regs(2),
+ ddc_data_regs(3),
+ ddc_data_regs(4),
+ ddc_data_regs(5),
+ ddc_data_regs(6),
+ ddc_vga_data_regs,
+ ddc_i2c_data_regs
+};
+
+static const struct ddc_registers ddc_clk_regs[] = {
+ ddc_clk_regs(1),
+ ddc_clk_regs(2),
+ ddc_clk_regs(3),
+ ddc_clk_regs(4),
+ ddc_clk_regs(5),
+ ddc_clk_regs(6),
+ ddc_vga_clk_regs,
+ ddc_i2c_clk_regs
+};
+
+static const struct ddc_sh_mask ddc_shift = {
+ DDC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct ddc_sh_mask ddc_mask = {
+ DDC_MASK_SH_LIST(_MASK)
+};
+
+static void define_ddc_registers(
+ struct hw_gpio_pin *pin,
+ uint32_t en)
+{
+ struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+ switch (pin->id) {
+ case GPIO_ID_DDC_DATA:
+ ddc->regs = &ddc_data_regs[en];
+ ddc->base.regs = &ddc_data_regs[en].gpio;
+ break;
+ case GPIO_ID_DDC_CLOCK:
+ ddc->regs = &ddc_clk_regs[en];
+ ddc->base.regs = &ddc_clk_regs[en].gpio;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ return;
+ }
+
+ ddc->shifts = &ddc_shift;
+ ddc->masks = &ddc_mask;
+
+}
+
+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+ struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
+
+ hpd->regs = &hpd_regs[en];
+ hpd->shifts = &hpd_shift;
+ hpd->masks = &hpd_mask;
+ hpd->base.regs = &hpd_regs[en].gpio;
+}
+
+static const struct hw_factory_funcs funcs = {
+ .create_ddc_data = dal_hw_ddc_create,
+ .create_ddc_clock = dal_hw_ddc_create,
+ .create_generic = NULL,
+ .create_hpd = dal_hw_hpd_create,
+ .create_sync = NULL,
+ .create_gsl = NULL,
+ .define_hpd_registers = define_hpd_registers,
+ .define_ddc_registers = define_ddc_registers
+};
+
+void dal_hw_factory_dce60_init(
+ struct hw_factory *factory)
+{
+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
+ factory->number_of_pins[GPIO_ID_GENERIC] = 7;
+ factory->number_of_pins[GPIO_ID_HPD] = 6;
+ factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
+ factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+ factory->number_of_pins[GPIO_ID_SYNC] = 2;
+ factory->number_of_pins[GPIO_ID_GSL] = 4;
+
+ factory->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
new file mode 100644
index 000000000000..52fd436533ed
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_factory_dce60.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_FACTORY_DCE60_H__
+#define __DAL_HW_FACTORY_DCE60_H__
+
+void dal_hw_factory_dce60_init(
+ struct hw_factory *factory);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
new file mode 100644
index 000000000000..f86ee8587f1b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/gpio_types.h"
+#include "../hw_translate.h"
+
+#include "hw_translate_dce60.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+#include "smu/smu_6_0_d.h"
+
+/*
+ * @brief
+ * Returns index of first bit (starting with LSB) which is set
+ */
+static uint32_t index_from_vector(
+ uint32_t vector)
+{
+ uint32_t result = 0;
+ uint32_t mask = 1;
+
+ do {
+ if (vector == mask)
+ return result;
+
+ ++result;
+ mask <<= 1;
+ } while (mask);
+
+ BREAK_TO_DEBUGGER();
+
+ return GPIO_ENUM_UNKNOWN;
+}
+
+static bool offset_to_id(
+ uint32_t offset,
+ uint32_t mask,
+ enum gpio_id *id,
+ uint32_t *en)
+{
+ switch (offset) {
+ /* GENERIC */
+ case mmDC_GPIO_GENERIC_A:
+ *id = GPIO_ID_GENERIC;
+ switch (mask) {
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+ *en = GPIO_GENERIC_A;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
+ *en = GPIO_GENERIC_B;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
+ *en = GPIO_GENERIC_C;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
+ *en = GPIO_GENERIC_D;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
+ *en = GPIO_GENERIC_E;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
+ *en = GPIO_GENERIC_F;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
+ *en = GPIO_GENERIC_G;
+ return true;
+ default:
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+ break;
+ /* HPD */
+ case mmDC_GPIO_HPD_A:
+ *id = GPIO_ID_HPD;
+ switch (mask) {
+ case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
+ *en = GPIO_HPD_1;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
+ *en = GPIO_HPD_2;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
+ *en = GPIO_HPD_3;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
+ *en = GPIO_HPD_4;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
+ *en = GPIO_HPD_5;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
+ *en = GPIO_HPD_6;
+ return true;
+ default:
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+ break;
+ /* SYNCA */
+ case mmDC_GPIO_SYNCA_A:
+ *id = GPIO_ID_SYNC;
+ switch (mask) {
+ case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
+ *en = GPIO_SYNC_HSYNC_A;
+ return true;
+ case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
+ *en = GPIO_SYNC_VSYNC_A;
+ return true;
+ default:
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+ break;
+ /* mmDC_GPIO_GENLK_MASK */
+ case mmDC_GPIO_GENLK_A:
+ *id = GPIO_ID_GSL;
+ switch (mask) {
+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
+ *en = GPIO_GSL_GENLOCK_CLOCK;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
+ *en = GPIO_GSL_GENLOCK_VSYNC;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
+ *en = GPIO_GSL_SWAPLOCK_A;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
+ *en = GPIO_GSL_SWAPLOCK_B;
+ return true;
+ default:
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+ break;
+ /* GPIOPAD */
+ case mmGPIOPAD_A:
+ *id = GPIO_ID_GPIO_PAD;
+ *en = index_from_vector(mask);
+ return (*en <= GPIO_GPIO_PAD_MAX);
+ /* DDC */
+ /* we don't care about the GPIO_ID for DDC
+ * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
+ * directly in the create method */
+ case mmDC_GPIO_DDC1_A:
+ *en = GPIO_DDC_LINE_DDC1;
+ return true;
+ case mmDC_GPIO_DDC2_A:
+ *en = GPIO_DDC_LINE_DDC2;
+ return true;
+ case mmDC_GPIO_DDC3_A:
+ *en = GPIO_DDC_LINE_DDC3;
+ return true;
+ case mmDC_GPIO_DDC4_A:
+ *en = GPIO_DDC_LINE_DDC4;
+ return true;
+ case mmDC_GPIO_DDC5_A:
+ *en = GPIO_DDC_LINE_DDC5;
+ return true;
+ case mmDC_GPIO_DDC6_A:
+ *en = GPIO_DDC_LINE_DDC6;
+ return true;
+ case mmDC_GPIO_DDCVGA_A:
+ *en = GPIO_DDC_LINE_DDC_VGA;
+ return true;
+ /* GPIO_I2CPAD */
+ case mmDC_GPIO_I2CPAD_A:
+ *en = GPIO_DDC_LINE_I2C_PAD;
+ return true;
+ /* Not implemented */
+ case mmDC_GPIO_PWRSEQ_A:
+ case mmDC_GPIO_PAD_STRENGTH_1:
+ case mmDC_GPIO_PAD_STRENGTH_2:
+ case mmDC_GPIO_DEBUG:
+ return false;
+ /* UNEXPECTED */
+ default:
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+}
+
+static bool id_to_offset(
+ enum gpio_id id,
+ uint32_t en,
+ struct gpio_pin_info *info)
+{
+ bool result = true;
+
+ switch (id) {
+ case GPIO_ID_DDC_DATA:
+ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
+ switch (en) {
+ case GPIO_DDC_LINE_DDC1:
+ info->offset = mmDC_GPIO_DDC1_A;
+ break;
+ case GPIO_DDC_LINE_DDC2:
+ info->offset = mmDC_GPIO_DDC2_A;
+ break;
+ case GPIO_DDC_LINE_DDC3:
+ info->offset = mmDC_GPIO_DDC3_A;
+ break;
+ case GPIO_DDC_LINE_DDC4:
+ info->offset = mmDC_GPIO_DDC4_A;
+ break;
+ case GPIO_DDC_LINE_DDC5:
+ info->offset = mmDC_GPIO_DDC5_A;
+ break;
+ case GPIO_DDC_LINE_DDC6:
+ info->offset = mmDC_GPIO_DDC6_A;
+ break;
+ case GPIO_DDC_LINE_DDC_VGA:
+ info->offset = mmDC_GPIO_DDCVGA_A;
+ break;
+ case GPIO_DDC_LINE_I2C_PAD:
+ info->offset = mmDC_GPIO_I2CPAD_A;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_DDC_CLOCK:
+ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
+ switch (en) {
+ case GPIO_DDC_LINE_DDC1:
+ info->offset = mmDC_GPIO_DDC1_A;
+ break;
+ case GPIO_DDC_LINE_DDC2:
+ info->offset = mmDC_GPIO_DDC2_A;
+ break;
+ case GPIO_DDC_LINE_DDC3:
+ info->offset = mmDC_GPIO_DDC3_A;
+ break;
+ case GPIO_DDC_LINE_DDC4:
+ info->offset = mmDC_GPIO_DDC4_A;
+ break;
+ case GPIO_DDC_LINE_DDC5:
+ info->offset = mmDC_GPIO_DDC5_A;
+ break;
+ case GPIO_DDC_LINE_DDC6:
+ info->offset = mmDC_GPIO_DDC6_A;
+ break;
+ case GPIO_DDC_LINE_DDC_VGA:
+ info->offset = mmDC_GPIO_DDCVGA_A;
+ break;
+ case GPIO_DDC_LINE_I2C_PAD:
+ info->offset = mmDC_GPIO_I2CPAD_A;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_GENERIC:
+ info->offset = mmDC_GPIO_GENERIC_A;
+ switch (en) {
+ case GPIO_GENERIC_A:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
+ break;
+ case GPIO_GENERIC_B:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
+ break;
+ case GPIO_GENERIC_C:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
+ break;
+ case GPIO_GENERIC_D:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
+ break;
+ case GPIO_GENERIC_E:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
+ break;
+ case GPIO_GENERIC_F:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
+ break;
+ case GPIO_GENERIC_G:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_HPD:
+ info->offset = mmDC_GPIO_HPD_A;
+ switch (en) {
+ case GPIO_HPD_1:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
+ break;
+ case GPIO_HPD_2:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
+ break;
+ case GPIO_HPD_3:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
+ break;
+ case GPIO_HPD_4:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
+ break;
+ case GPIO_HPD_5:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
+ break;
+ case GPIO_HPD_6:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_SYNC:
+ switch (en) {
+ case GPIO_SYNC_HSYNC_A:
+ info->offset = mmDC_GPIO_SYNCA_A;
+ info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
+ break;
+ case GPIO_SYNC_VSYNC_A:
+ info->offset = mmDC_GPIO_SYNCA_A;
+ info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
+ break;
+ case GPIO_SYNC_HSYNC_B:
+ case GPIO_SYNC_VSYNC_B:
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_GSL:
+ switch (en) {
+ case GPIO_GSL_GENLOCK_CLOCK:
+ info->offset = mmDC_GPIO_GENLK_A;
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
+ break;
+ case GPIO_GSL_GENLOCK_VSYNC:
+ info->offset = mmDC_GPIO_GENLK_A;
+ info->mask =
+ DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
+ break;
+ case GPIO_GSL_SWAPLOCK_A:
+ info->offset = mmDC_GPIO_GENLK_A;
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
+ break;
+ case GPIO_GSL_SWAPLOCK_B:
+ info->offset = mmDC_GPIO_GENLK_A;
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+ break;
+ case GPIO_ID_GPIO_PAD:
+ info->offset = mmGPIOPAD_A;
+ info->mask = (1 << en);
+ result = (info->mask <= GPIO_GPIO_PAD_MAX);
+ break;
+ case GPIO_ID_VIP_PAD:
+ default:
+ BREAK_TO_DEBUGGER();
+ result = false;
+ }
+
+ if (result) {
+ info->offset_y = info->offset + 2;
+ info->offset_en = info->offset + 1;
+ info->offset_mask = info->offset - 1;
+
+ info->mask_y = info->mask;
+ info->mask_en = info->mask;
+ info->mask_mask = info->mask;
+ }
+
+ return result;
+}
+
+static const struct hw_translate_funcs funcs = {
+ .offset_to_id = offset_to_id,
+ .id_to_offset = id_to_offset,
+};
+
+void dal_hw_translate_dce60_init(
+ struct hw_translate *translate)
+{
+ translate->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
new file mode 100644
index 000000000000..c65a9d80c53c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce60/hw_translate_dce60.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_TRANSLATE_DCE60_H__
+#define __DAL_HW_TRANSLATE_DCE60_H__
+
+void dal_hw_translate_dce60_init(
+ struct hw_translate *tr);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 0caee3523017..7bb922b0f579 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -40,6 +40,9 @@
* Post-requisites: headers required by this unit
*/
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/hw_factory_dce60.h"
+#endif
#include "dce80/hw_factory_dce80.h"
#include "dce110/hw_factory_dce110.h"
#include "dce120/hw_factory_dce120.h"
@@ -64,6 +67,13 @@ bool dal_hw_factory_init(
}
switch (dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ dal_hw_factory_dce60_init(factory);
+ return true;
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 55c707488541..650af17ed12c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -40,6 +40,9 @@
* Post-requisites: headers required by this unit
*/
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/hw_translate_dce60.h"
+#endif
#include "dce80/hw_translate_dce80.h"
#include "dce110/hw_translate_dce110.h"
#include "dce120/hw_translate_dce120.h"
@@ -64,6 +67,13 @@ bool dal_hw_translate_init(
}
switch (dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ dal_hw_translate_dce60_init(translate);
+ return true;
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (4 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 05/10] drm/amd/display: dc/gpio: " Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 07/10] drm/amd/display: dc/irq: " Mauro Rossi
` (5 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added replicating existing DCE8 implementation.
---
.../gpu/drm/amd/display/dc/i2caux/Makefile | 12 +
.../dc/i2caux/dce60/i2c_hw_engine_dce60.c | 875 ++++++++++++++++++
.../dc/i2caux/dce60/i2c_hw_engine_dce60.h | 54 ++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.c | 173 ++++
.../dc/i2caux/dce60/i2c_sw_engine_dce60.h | 43 +
.../display/dc/i2caux/dce60/i2caux_dce60.c | 284 ++++++
.../display/dc/i2caux/dce60/i2caux_dce60.h | 38 +
.../gpu/drm/amd/display/dc/i2caux/i2caux.c | 10 +
8 files changed, 1489 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index 352885cb4d07..80f58a357879 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -30,6 +30,18 @@ AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
+###############################################################################
+# DCE 6x family
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_SI
+I2CAUX_DCE60 = i2caux_dce60.o i2c_hw_engine_dce60.o \
+ i2c_sw_engine_dce60.o
+
+AMD_DAL_I2CAUX_DCE60 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce60/,$(I2CAUX_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE60)
+endif
+
###############################################################################
# DCE 8x family
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
new file mode 100644
index 000000000000..a945e00ce913
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.c
@@ -0,0 +1,875 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_hw_engine.h"
+#include "../i2c_generic_hw_engine.h"
+/*
+ * Header of this unit
+ */
+
+#include "i2c_hw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+/*
+ * This unit
+ */
+
+enum dc_i2c_status {
+ DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
+ DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
+};
+
+enum dc_i2c_arbitration {
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
+};
+
+enum {
+ /* No timeout in HW
+ * (timeout implemented in SW by querying status) */
+ I2C_SETUP_TIME_LIMIT = 255,
+ I2C_HW_BUFFER_SIZE = 144
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_hw_engine *'
+ * to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_HW_ENGINE(ptr) \
+ container_of((ptr), struct i2c_hw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast pointer to 'struct i2c_engine *'
+ * to pointer to 'struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+ FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
+
+/*
+ * @brief
+ * Cast pointer to 'struct engine *'
+ * to 'pointer to struct i2c_hw_engine_dce60 *'
+ */
+#define FROM_ENGINE(ptr) \
+ FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
+
+static void disable_i2c_hw_engine(
+ struct i2c_hw_engine_dce60 *engine)
+{
+ const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+ uint32_t value = 0;
+
+ struct dc_context *ctx = NULL;
+
+ ctx = engine->base.base.base.ctx;
+
+ value = dm_read_reg(ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_ENABLE);
+
+ dm_write_reg(ctx, addr, value);
+}
+
+static void release_engine(
+ struct engine *engine)
+{
+ struct i2c_hw_engine_dce60 *hw_engine = FROM_ENGINE(engine);
+
+ struct i2c_engine *base = NULL;
+ bool safe_to_reset;
+ uint32_t value = 0;
+
+ base = &hw_engine->base.base;
+
+ /* Restore original HW engine speed */
+
+ base->funcs->set_speed(base, hw_engine->base.original_speed);
+
+ /* Release I2C */
+ {
+ value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_ARBITRATION,
+ DC_I2C_SW_DONE_USING_I2C_REG);
+
+ dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
+ }
+
+ /* Reset HW engine */
+ {
+ uint32_t i2c_sw_status = 0;
+
+ value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+ i2c_sw_status = get_reg_field_value(
+ value,
+ DC_I2C_SW_STATUS,
+ DC_I2C_SW_STATUS);
+ /* if used by SW, safe to reset */
+ safe_to_reset = (i2c_sw_status == 1);
+ }
+ {
+ value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
+
+ if (safe_to_reset)
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_CONTROL,
+ DC_I2C_SW_STATUS_RESET);
+
+ dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
+ }
+
+ /* HW I2c engine - clock gating feature */
+ if (!hw_engine->engine_keep_power_up_count)
+ disable_i2c_hw_engine(hw_engine);
+}
+
+static void destruct(
+ struct i2c_hw_engine_dce60 *engine)
+{
+ dal_i2c_hw_engine_destruct(&engine->base);
+}
+
+static void destroy(
+ struct i2c_engine **i2c_engine)
+{
+ struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(*i2c_engine);
+
+ destruct(engine);
+
+ kfree(engine);
+
+ *i2c_engine = NULL;
+}
+
+static bool setup_engine(
+ struct i2c_engine *i2c_engine)
+{
+ uint32_t value = 0;
+ struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+ /* Program pin select */
+ {
+ const uint32_t addr = mmDC_I2C_CONTROL;
+
+ value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_GO);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SEND_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SW_STATUS_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_TRANSACTION_COUNT);
+
+ set_reg_field_value(
+ value,
+ engine->engine_id,
+ DC_I2C_CONTROL,
+ DC_I2C_DDC_SELECT);
+
+ dm_write_reg(i2c_engine->base.ctx, addr, value);
+ }
+
+ /* Program time limit */
+ {
+ const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+
+ value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+ set_reg_field_value(
+ value,
+ I2C_SETUP_TIME_LIMIT,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_TIME_LIMIT);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_ENABLE);
+
+ dm_write_reg(i2c_engine->base.ctx, addr, value);
+ }
+
+ /* Program HW priority
+ * set to High - interrupt software I2C at any time
+ * Enable restart of SW I2C that was interrupted by HW
+ * disable queuing of software while I2C is in use by HW */
+ {
+ value = dm_read_reg(i2c_engine->base.ctx,
+ mmDC_I2C_ARBITRATION);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_ARBITRATION,
+ DC_I2C_NO_QUEUED_SW_GO);
+
+ set_reg_field_value(
+ value,
+ DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+ DC_I2C_ARBITRATION,
+ DC_I2C_SW_PRIORITY);
+
+ dm_write_reg(i2c_engine->base.ctx,
+ mmDC_I2C_ARBITRATION, value);
+ }
+
+ return true;
+}
+
+static uint32_t get_speed(
+ const struct i2c_engine *i2c_engine)
+{
+ const struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+ const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
+
+ uint32_t pre_scale = 0;
+
+ uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+ pre_scale = get_reg_field_value(
+ value,
+ DC_I2C_DDC1_SPEED,
+ DC_I2C_DDC1_PRESCALE);
+
+ /* [anaumov] it seems following is unnecessary */
+ /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
+
+ return pre_scale ?
+ engine->reference_frequency / pre_scale :
+ engine->base.default_speed;
+}
+
+static void set_speed(
+ struct i2c_engine *i2c_engine,
+ uint32_t speed)
+{
+ struct i2c_hw_engine_dce60 *engine = FROM_I2C_ENGINE(i2c_engine);
+
+ if (speed) {
+ const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
+
+ uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
+
+ set_reg_field_value(
+ value,
+ engine->reference_frequency / speed,
+ DC_I2C_DDC1_SPEED,
+ DC_I2C_DDC1_PRESCALE);
+
+ set_reg_field_value(
+ value,
+ 2,
+ DC_I2C_DDC1_SPEED,
+ DC_I2C_DDC1_THRESHOLD);
+
+ dm_write_reg(i2c_engine->base.ctx, addr, value);
+ }
+}
+
+static inline void reset_hw_engine(struct engine *engine)
+{
+ uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_CONTROL,
+ DC_I2C_SW_STATUS_RESET);
+
+ dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
+}
+
+static bool is_hw_busy(struct engine *engine)
+{
+ uint32_t i2c_sw_status = 0;
+
+ uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+ i2c_sw_status = get_reg_field_value(
+ value,
+ DC_I2C_SW_STATUS,
+ DC_I2C_SW_STATUS);
+
+ if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
+ return false;
+
+ reset_hw_engine(engine);
+
+ value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
+
+ i2c_sw_status = get_reg_field_value(
+ value,
+ DC_I2C_SW_STATUS,
+ DC_I2C_SW_STATUS);
+
+ return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
+}
+
+/*
+ * @brief
+ * DC_GPIO_DDC MM register offsets
+ */
+static const uint32_t transaction_addr[] = {
+ mmDC_I2C_TRANSACTION0,
+ mmDC_I2C_TRANSACTION1,
+ mmDC_I2C_TRANSACTION2,
+ mmDC_I2C_TRANSACTION3
+};
+
+static bool process_transaction(
+ struct i2c_hw_engine_dce60 *engine,
+ struct i2c_request_transaction_data *request)
+{
+ uint32_t length = request->length;
+ uint8_t *buffer = request->data;
+
+ bool last_transaction = false;
+ uint32_t value = 0;
+
+ struct dc_context *ctx = NULL;
+
+ ctx = engine->base.base.base.ctx;
+
+ {
+ const uint32_t addr =
+ transaction_addr[engine->transaction_count];
+
+ value = dm_read_reg(ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_TRANSACTION0,
+ DC_I2C_STOP_ON_NACK0);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_TRANSACTION0,
+ DC_I2C_START0);
+
+ if ((engine->transaction_count == 3) ||
+ (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
+ (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_TRANSACTION0,
+ DC_I2C_STOP0);
+
+ last_transaction = true;
+ } else
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_TRANSACTION0,
+ DC_I2C_STOP0);
+
+ set_reg_field_value(
+ value,
+ (0 != (request->action &
+ I2CAUX_TRANSACTION_ACTION_I2C_READ)),
+ DC_I2C_TRANSACTION0,
+ DC_I2C_RW0);
+
+ set_reg_field_value(
+ value,
+ length,
+ DC_I2C_TRANSACTION0,
+ DC_I2C_COUNT0);
+
+ dm_write_reg(ctx, addr, value);
+ }
+
+ /* Write the I2C address and I2C data
+ * into the hardware circular buffer, one byte per entry.
+ * As an example, the 7-bit I2C slave address for CRT monitor
+ * for reading DDC/EDID information is 0b1010001.
+ * For an I2C send operation, the LSB must be programmed to 0;
+ * for I2C receive operation, the LSB must be programmed to 1. */
+
+ {
+ value = 0;
+
+ set_reg_field_value(
+ value,
+ false,
+ DC_I2C_DATA,
+ DC_I2C_DATA_RW);
+
+ set_reg_field_value(
+ value,
+ request->address,
+ DC_I2C_DATA,
+ DC_I2C_DATA);
+
+ if (engine->transaction_count == 0) {
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DATA,
+ DC_I2C_INDEX);
+
+ /*enable index write*/
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_DATA,
+ DC_I2C_INDEX_WRITE);
+ }
+
+ dm_write_reg(ctx, mmDC_I2C_DATA, value);
+
+ if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DATA,
+ DC_I2C_INDEX_WRITE);
+
+ while (length) {
+
+ set_reg_field_value(
+ value,
+ *buffer++,
+ DC_I2C_DATA,
+ DC_I2C_DATA);
+
+ dm_write_reg(ctx, mmDC_I2C_DATA, value);
+ --length;
+ }
+ }
+ }
+
+ ++engine->transaction_count;
+ engine->buffer_used_bytes += length + 1;
+
+ return last_transaction;
+}
+
+static void execute_transaction(
+ struct i2c_hw_engine_dce60 *engine)
+{
+ uint32_t value = 0;
+ struct dc_context *ctx = NULL;
+
+ ctx = engine->base.base.base.ctx;
+
+ {
+ const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
+
+ value = dm_read_reg(ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_DATA_DRIVE_EN);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_CLK_DRIVE_EN);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_DATA_DRIVE_SEL);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_DDC1_SETUP,
+ DC_I2C_DDC1_INTRA_BYTE_DELAY);
+
+ dm_write_reg(ctx, addr, value);
+ }
+
+ {
+ const uint32_t addr = mmDC_I2C_CONTROL;
+
+ value = dm_read_reg(ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SW_STATUS_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_SEND_RESET);
+
+ set_reg_field_value(
+ value,
+ 0,
+ DC_I2C_CONTROL,
+ DC_I2C_GO);
+
+ set_reg_field_value(
+ value,
+ engine->transaction_count - 1,
+ DC_I2C_CONTROL,
+ DC_I2C_TRANSACTION_COUNT);
+
+ dm_write_reg(ctx, addr, value);
+ }
+
+ /* start I2C transfer */
+ {
+ const uint32_t addr = mmDC_I2C_CONTROL;
+
+ value = dm_read_reg(ctx, addr);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_CONTROL,
+ DC_I2C_GO);
+
+ dm_write_reg(ctx, addr, value);
+ }
+
+ /* all transactions were executed and HW buffer became empty
+ * (even though it actually happens when status becomes DONE) */
+ engine->transaction_count = 0;
+ engine->buffer_used_bytes = 0;
+}
+
+static void submit_channel_request(
+ struct i2c_engine *engine,
+ struct i2c_request_transaction_data *request)
+{
+ request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
+
+ if (!process_transaction(FROM_I2C_ENGINE(engine), request))
+ return;
+
+ if (is_hw_busy(&engine->base)) {
+ request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
+ return;
+ }
+
+ execute_transaction(FROM_I2C_ENGINE(engine));
+}
+
+static void process_channel_reply(
+ struct i2c_engine *engine,
+ struct i2c_reply_transaction_data *reply)
+{
+ uint32_t length = reply->length;
+ uint8_t *buffer = reply->data;
+
+ uint32_t value = 0;
+
+ /*set index*/
+ set_reg_field_value(
+ value,
+ length - 1,
+ DC_I2C_DATA,
+ DC_I2C_INDEX);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_DATA,
+ DC_I2C_DATA_RW);
+
+ set_reg_field_value(
+ value,
+ 1,
+ DC_I2C_DATA,
+ DC_I2C_INDEX_WRITE);
+
+ dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
+
+ while (length) {
+ /* after reading the status,
+ * if the I2C operation executed successfully
+ * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
+ * should read data bytes from I2C circular data buffer */
+
+ value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
+
+ *buffer++ = get_reg_field_value(
+ value,
+ DC_I2C_DATA,
+ DC_I2C_DATA);
+
+ --length;
+ }
+}
+
+static enum i2c_channel_operation_result get_channel_status(
+ struct i2c_engine *engine,
+ uint8_t *returned_bytes)
+{
+ uint32_t i2c_sw_status = 0;
+ uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
+
+ i2c_sw_status = get_reg_field_value(
+ value,
+ DC_I2C_SW_STATUS,
+ DC_I2C_SW_STATUS);
+
+ if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
+ return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
+ else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
+ return I2C_CHANNEL_OPERATION_NO_RESPONSE;
+ else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
+ return I2C_CHANNEL_OPERATION_TIMEOUT;
+ else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
+ return I2C_CHANNEL_OPERATION_FAILED;
+ else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
+ return I2C_CHANNEL_OPERATION_SUCCEEDED;
+
+ /*
+ * this is the case when HW used for communication, I2C_SW_STATUS
+ * could be zero
+ */
+ return I2C_CHANNEL_OPERATION_SUCCEEDED;
+}
+
+static uint32_t get_hw_buffer_available_size(
+ const struct i2c_hw_engine *engine)
+{
+ return I2C_HW_BUFFER_SIZE -
+ FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
+}
+
+static uint32_t get_transaction_timeout(
+ const struct i2c_hw_engine *engine,
+ uint32_t length)
+{
+ uint32_t speed = engine->base.funcs->get_speed(&engine->base);
+
+ uint32_t period_timeout;
+ uint32_t num_of_clock_stretches;
+
+ if (!speed)
+ return 0;
+
+ period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
+
+ num_of_clock_stretches = 1 + (length << 3) + 1;
+ num_of_clock_stretches +=
+ (FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
+ (FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
+
+ return period_timeout * num_of_clock_stretches;
+}
+
+/*
+ * @brief
+ * DC_I2C_DDC1_SETUP MM register offsets
+ *
+ * @note
+ * The indices of this offset array are DDC engine IDs
+ */
+static const int32_t ddc_setup_offset[] = {
+
+ mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
+ mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
+ mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
+ mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
+ mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
+ mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
+ mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
+};
+
+/*
+ * @brief
+ * DC_I2C_DDC1_SPEED MM register offsets
+ *
+ * @note
+ * The indices of this offset array are DDC engine IDs
+ */
+static const int32_t ddc_speed_offset[] = {
+ mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
+ mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
+ mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
+ mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
+ mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
+ mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
+ mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
+};
+
+static const struct i2c_engine_funcs i2c_engine_funcs = {
+ .destroy = destroy,
+ .get_speed = get_speed,
+ .set_speed = set_speed,
+ .setup_engine = setup_engine,
+ .submit_channel_request = submit_channel_request,
+ .process_channel_reply = process_channel_reply,
+ .get_channel_status = get_channel_status,
+ .acquire_engine = dal_i2c_hw_engine_acquire_engine,
+};
+
+static const struct engine_funcs engine_funcs = {
+ .release_engine = release_engine,
+ .get_engine_type = dal_i2c_hw_engine_get_engine_type,
+ .acquire = dal_i2c_engine_acquire,
+ .submit_request = dal_i2c_hw_engine_submit_request,
+};
+
+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
+ .get_hw_buffer_available_size =
+ get_hw_buffer_available_size,
+ .get_transaction_timeout =
+ get_transaction_timeout,
+ .wait_on_operation_result =
+ dal_i2c_hw_engine_wait_on_operation_result,
+};
+
+static void construct(
+ struct i2c_hw_engine_dce60 *engine,
+ const struct i2c_hw_engine_dce60_create_arg *arg)
+{
+ dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
+
+ engine->base.base.base.funcs = &engine_funcs;
+ engine->base.base.funcs = &i2c_engine_funcs;
+ engine->base.funcs = &i2c_hw_engine_funcs;
+ engine->base.default_speed = arg->default_speed;
+ engine->addr.DC_I2C_DDCX_SETUP =
+ mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
+ engine->addr.DC_I2C_DDCX_SPEED =
+ mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
+
+ engine->engine_id = arg->engine_id;
+ engine->reference_frequency = arg->reference_frequency;
+ engine->buffer_used_bytes = 0;
+ engine->transaction_count = 0;
+ engine->engine_keep_power_up_count = 1;
+}
+
+struct i2c_engine *dal_i2c_hw_engine_dce60_create(
+ const struct i2c_hw_engine_dce60_create_arg *arg)
+{
+ struct i2c_hw_engine_dce60 *engine;
+
+ if (!arg) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
+ (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
+ !arg->reference_frequency) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ engine = kzalloc(sizeof(struct i2c_hw_engine_dce60), GFP_KERNEL);
+
+ if (!engine) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ construct(engine, arg);
+ return &engine->base.base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
new file mode 100644
index 000000000000..48954265133d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_hw_engine_dce60.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_HW_ENGINE_DCE60_H__
+#define __DAL_I2C_HW_ENGINE_DCE60_H__
+
+struct i2c_hw_engine_dce60 {
+ struct i2c_hw_engine base;
+ struct {
+ uint32_t DC_I2C_DDCX_SETUP;
+ uint32_t DC_I2C_DDCX_SPEED;
+ } addr;
+ uint32_t engine_id;
+ /* expressed in kilohertz */
+ uint32_t reference_frequency;
+ /* number of bytes currently used in HW buffer */
+ uint32_t buffer_used_bytes;
+ /* number of pending transactions (before GO) */
+ uint32_t transaction_count;
+ uint32_t engine_keep_power_up_count;
+};
+
+struct i2c_hw_engine_dce60_create_arg {
+ uint32_t engine_id;
+ uint32_t reference_frequency;
+ uint32_t default_speed;
+ struct dc_context *ctx;
+};
+
+struct i2c_engine *dal_i2c_hw_engine_dce60_create(
+ const struct i2c_hw_engine_dce60_create_arg *arg);
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
new file mode 100644
index 000000000000..9830dc6698e0
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+
+/*
+ * Header of this unit
+ */
+
+#include "i2c_sw_engine_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+/*
+ * This unit
+ */
+
+static const uint32_t ddc_hw_status_addr[] = {
+ mmDC_I2C_DDC1_HW_STATUS,
+ mmDC_I2C_DDC2_HW_STATUS,
+ mmDC_I2C_DDC3_HW_STATUS,
+ mmDC_I2C_DDC4_HW_STATUS,
+ mmDC_I2C_DDC5_HW_STATUS,
+ mmDC_I2C_DDC6_HW_STATUS,
+ mmDC_I2C_DDCVGA_HW_STATUS
+};
+
+/*
+ * @brief
+ * Cast 'struct i2c_sw_engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_I2C_SW_ENGINE(ptr) \
+ container_of((ptr), struct i2c_sw_engine_dce60, base)
+
+/*
+ * @brief
+ * Cast 'struct i2c_engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_I2C_ENGINE(ptr) \
+ FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
+
+/*
+ * @brief
+ * Cast 'struct engine *'
+ * to 'struct i2c_sw_engine_dce60 *'
+ */
+#define FROM_ENGINE(ptr) \
+ FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
+
+static void release_engine(
+ struct engine *engine)
+{
+
+}
+
+static void destruct(
+ struct i2c_sw_engine_dce60 *engine)
+{
+ dal_i2c_sw_engine_destruct(&engine->base);
+}
+
+static void destroy(
+ struct i2c_engine **engine)
+{
+ struct i2c_sw_engine_dce60 *sw_engine = FROM_I2C_ENGINE(*engine);
+
+ destruct(sw_engine);
+
+ kfree(sw_engine);
+
+ *engine = NULL;
+}
+
+static bool acquire_engine(
+ struct i2c_engine *engine,
+ struct ddc *ddc_handle)
+{
+ return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
+}
+
+static const struct i2c_engine_funcs i2c_engine_funcs = {
+ .acquire_engine = acquire_engine,
+ .destroy = destroy,
+ .get_speed = dal_i2c_sw_engine_get_speed,
+ .set_speed = dal_i2c_sw_engine_set_speed,
+ .setup_engine = dal_i2c_engine_setup_i2c_engine,
+ .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
+ .process_channel_reply = dal_i2c_engine_process_channel_reply,
+ .get_channel_status = dal_i2c_sw_engine_get_channel_status,
+};
+
+static const struct engine_funcs engine_funcs = {
+ .release_engine = release_engine,
+ .get_engine_type = dal_i2c_sw_engine_get_engine_type,
+ .acquire = dal_i2c_engine_acquire,
+ .submit_request = dal_i2c_sw_engine_submit_request,
+};
+
+static void construct(
+ struct i2c_sw_engine_dce60 *engine,
+ const struct i2c_sw_engine_dce60_create_arg *arg)
+{
+ struct i2c_sw_engine_create_arg arg_base;
+
+ arg_base.ctx = arg->ctx;
+ arg_base.default_speed = arg->default_speed;
+
+ dal_i2c_sw_engine_construct(&engine->base, &arg_base);
+
+ engine->base.base.base.funcs = &engine_funcs;
+ engine->base.base.funcs = &i2c_engine_funcs;
+ engine->base.default_speed = arg->default_speed;
+ engine->engine_id = arg->engine_id;
+}
+
+struct i2c_engine *dal_i2c_sw_engine_dce60_create(
+ const struct i2c_sw_engine_dce60_create_arg *arg)
+{
+ struct i2c_sw_engine_dce60 *engine;
+
+ if (!arg) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ engine = kzalloc(sizeof(struct i2c_sw_engine_dce60), GFP_KERNEL);
+
+ if (!engine) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ construct(engine, arg);
+ return &engine->base.base;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
new file mode 100644
index 000000000000..5a65a5139e76
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2c_sw_engine_dce60.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_SW_ENGINE_DCE60_H__
+#define __DAL_I2C_SW_ENGINE_DCE60_H__
+
+struct i2c_sw_engine_dce60 {
+ struct i2c_sw_engine base;
+ uint32_t engine_id;
+};
+
+struct i2c_sw_engine_dce60_create_arg {
+ uint32_t engine_id;
+ uint32_t default_speed;
+ struct dc_context *ctx;
+};
+
+struct i2c_engine *dal_i2c_sw_engine_dce60_create(
+ const struct i2c_sw_engine_dce60_create_arg *arg);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
new file mode 100644
index 000000000000..5aaa7cf83807
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+#include "include/i2caux_interface.h"
+#include "../i2caux.h"
+
+/*
+ * Header of this unit
+ */
+
+#include "i2caux_dce60.h"
+
+/*
+ * Post-requisites: headers required by this unit
+ */
+
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+#include "i2c_sw_engine_dce60.h"
+#include "../i2c_hw_engine.h"
+#include "i2c_hw_engine_dce60.h"
+#include "../i2c_generic_hw_engine.h"
+#include "../aux_engine.h"
+
+
+#include "../dce110/aux_engine_dce110.h"
+#include "../dce110/i2caux_dce110.h"
+
+#include "dce/dce_6_0_d.h"
+#include "dce/dce_6_0_sh_mask.h"
+
+
+/* set register offset */
+#define SR(reg_name)\
+ .reg_name = mm ## reg_name
+
+/* set register offset with instance */
+#define SRI(reg_name, block, id)\
+ .reg_name = mm ## block ## id ## _ ## reg_name
+
+#define aux_regs(id)\
+[id] = {\
+ AUX_COMMON_REG_LIST(id), \
+ .AUX_RESET_MASK = 0 \
+}
+
+static const struct dce110_aux_registers dce60_aux_regs[] = {
+ aux_regs(0),
+ aux_regs(1),
+ aux_regs(2),
+ aux_regs(3),
+ aux_regs(4),
+ aux_regs(5)
+};
+
+/*
+ * This unit
+ */
+
+#define FROM_I2C_AUX(ptr) \
+ container_of((ptr), struct i2caux_dce60, base)
+
+static void destruct(
+ struct i2caux_dce60 *i2caux_dce60)
+{
+ dal_i2caux_destruct(&i2caux_dce60->base);
+}
+
+static void destroy(
+ struct i2caux **i2c_engine)
+{
+ struct i2caux_dce60 *i2caux_dce60 = FROM_I2C_AUX(*i2c_engine);
+
+ destruct(i2caux_dce60);
+
+ kfree(i2caux_dce60);
+
+ *i2c_engine = NULL;
+}
+
+static struct i2c_engine *acquire_i2c_hw_engine(
+ struct i2caux *i2caux,
+ struct ddc *ddc)
+{
+ struct i2caux_dce60 *i2caux_dce60 = FROM_I2C_AUX(i2caux);
+
+ struct i2c_engine *engine = NULL;
+ bool non_generic;
+
+ if (!ddc)
+ return NULL;
+
+ if (ddc->hw_info.hw_supported) {
+ enum gpio_ddc_line line = dal_ddc_get_line(ddc);
+
+ if (line < GPIO_DDC_LINE_COUNT) {
+ non_generic = true;
+ engine = i2caux->i2c_hw_engines[line];
+ }
+ }
+
+ if (!engine) {
+ non_generic = false;
+ engine = i2caux->i2c_generic_hw_engine;
+ }
+
+ if (!engine)
+ return NULL;
+
+ if (non_generic) {
+ if (!i2caux_dce60->i2c_hw_buffer_in_use &&
+ engine->base.funcs->acquire(&engine->base, ddc)) {
+ i2caux_dce60->i2c_hw_buffer_in_use = true;
+ return engine;
+ }
+ } else {
+ if (engine->base.funcs->acquire(&engine->base, ddc))
+ return engine;
+ }
+
+ return NULL;
+}
+
+static void release_engine(
+ struct i2caux *i2caux,
+ struct engine *engine)
+{
+ if (engine->funcs->get_engine_type(engine) ==
+ I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
+ FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
+
+ dal_i2caux_release_engine(i2caux, engine);
+}
+
+static const enum gpio_ddc_line hw_ddc_lines[] = {
+ GPIO_DDC_LINE_DDC1,
+ GPIO_DDC_LINE_DDC2,
+ GPIO_DDC_LINE_DDC3,
+ GPIO_DDC_LINE_DDC4,
+ GPIO_DDC_LINE_DDC5,
+ GPIO_DDC_LINE_DDC6,
+ GPIO_DDC_LINE_DDC_VGA
+};
+
+static const enum gpio_ddc_line hw_aux_lines[] = {
+ GPIO_DDC_LINE_DDC1,
+ GPIO_DDC_LINE_DDC2,
+ GPIO_DDC_LINE_DDC3,
+ GPIO_DDC_LINE_DDC4,
+ GPIO_DDC_LINE_DDC5,
+ GPIO_DDC_LINE_DDC6
+};
+
+static const struct i2caux_funcs i2caux_funcs = {
+ .destroy = destroy,
+ .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
+ .release_engine = release_engine,
+ .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
+ .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
+};
+
+static void construct(
+ struct i2caux_dce60 *i2caux_dce60,
+ struct dc_context *ctx)
+{
+ /* Entire family have I2C engine reference clock frequency
+ * changed from XTALIN (27) to XTALIN/2 (13.5) */
+
+ struct i2caux *base = &i2caux_dce60->base;
+
+ uint32_t reference_frequency =
+ dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
+
+ /*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
+ FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
+
+ /* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
+ bool use_i2c_sw_engine = true;
+
+ uint32_t i;
+
+ dal_i2caux_construct(base, ctx);
+
+ i2caux_dce60->base.funcs = &i2caux_funcs;
+ i2caux_dce60->i2c_hw_buffer_in_use = false;
+
+ /* Create I2C HW engines (HW + SW pairs)
+ * for all lines which has assisted HW DDC
+ * 'i' (loop counter) used as DDC/AUX engine_id */
+
+ i = 0;
+
+ do {
+ enum gpio_ddc_line line_id = hw_ddc_lines[i];
+
+ struct i2c_hw_engine_dce60_create_arg hw_arg;
+
+ if (use_i2c_sw_engine) {
+ struct i2c_sw_engine_dce60_create_arg sw_arg;
+
+ sw_arg.engine_id = i;
+ sw_arg.default_speed = base->default_i2c_sw_speed;
+ sw_arg.ctx = ctx;
+ base->i2c_sw_engines[line_id] =
+ dal_i2c_sw_engine_dce60_create(&sw_arg);
+ }
+
+ hw_arg.engine_id = i;
+ hw_arg.reference_frequency = reference_frequency;
+ hw_arg.default_speed = base->default_i2c_hw_speed;
+ hw_arg.ctx = ctx;
+
+ base->i2c_hw_engines[line_id] =
+ dal_i2c_hw_engine_dce60_create(&hw_arg);
+
+ ++i;
+ } while (i < ARRAY_SIZE(hw_ddc_lines));
+
+ /* Create AUX engines for all lines which has assisted HW AUX
+ * 'i' (loop counter) used as DDC/AUX engine_id */
+
+ i = 0;
+
+ do {
+ enum gpio_ddc_line line_id = hw_aux_lines[i];
+
+ struct aux_engine_dce110_init_data arg;
+
+ arg.engine_id = i;
+ arg.timeout_period = base->aux_timeout_period;
+ arg.ctx = ctx;
+ arg.regs = &dce60_aux_regs[i];
+
+ base->aux_engines[line_id] =
+ dal_aux_engine_dce110_create(&arg);
+
+ ++i;
+ } while (i < ARRAY_SIZE(hw_aux_lines));
+
+ /* TODO Generic I2C SW and HW */
+}
+
+struct i2caux *dal_i2caux_dce60_create(
+ struct dc_context *ctx)
+{
+ struct i2caux_dce60 *i2caux_dce60 =
+ kzalloc(sizeof(struct i2caux_dce60), GFP_KERNEL);
+
+ if (!i2caux_dce60) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ construct(i2caux_dce60, ctx);
+ return &i2caux_dce60->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
new file mode 100644
index 000000000000..819b5ccbf977
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce60/i2caux_dce60.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_AUX_DCE60_H__
+#define __DAL_I2C_AUX_DCE60_H__
+
+struct i2caux_dce60 {
+ struct i2caux base;
+ /* indicate the I2C HW circular buffer is in use */
+ bool i2c_hw_buffer_in_use;
+};
+
+struct i2caux *dal_i2caux_dce60_create(
+ struct dc_context *ctx);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index 9b0bcc6b769b..e431624cc755 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -49,6 +49,10 @@
* This unit
*/
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/i2caux_dce60.h"
+#endif
+
#include "dce80/i2caux_dce80.h"
#include "dce100/i2caux_dce100.h"
@@ -78,6 +82,12 @@ struct i2caux *dal_i2caux_create(
}
switch (ctx->dce_version) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case DCE_VERSION_6_0:
+ case DCE_VERSION_6_1:
+ case DCE_VERSION_6_4:
+ return dal_i2caux_dce60_create(ctx);
+#endif
case DCE_VERSION_8_0:
case DCE_VERSION_8_1:
case DCE_VERSION_8_3:
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (5 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 06/10] drm/amd/display: dc/i2caux: " Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support Mauro Rossi
` (4 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h headers were used instead of dce/dce_6_0_{d,sh_mask}.h
but only as exception in dce/irq_service_dce60.c
IMPORTANT: Coding of dce/irq_service_dce60.c requires review to understand
if dce_6_0_{d,sh_mask}.h should be updated with macros/registers/masks
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 11 +
.../display/dc/irq/dce60/irq_service_dce60.c | 303 ++++++++++++++++++
.../display/dc/irq/dce60/irq_service_dce60.h | 35 ++
.../gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
4 files changed, 352 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..e38b6d8d614d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -30,6 +30,17 @@ AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
+###############################################################################
+# DCE 6x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_SI
+IRQ_DCE60 = irq_service_dce60.o
+
+AMD_DAL_IRQ_DCE60 = $(addprefix $(AMDDALPATH)/dc/irq/dce60/,$(IRQ_DCE60))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE60)
+endif
+
###############################################################################
# DCE 8x
###############################################################################
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
new file mode 100644
index 000000000000..107e0dcb5f80
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce60.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "dce/dce_8_0_d.h"
+#include "dce/dce_8_0_sh_mask.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "dc_types.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD1_INT_STATUS,
+ DC_HPD1_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ DC_HPD1_INT_CONTROL,
+ DC_HPD1_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = dce110_vblank_set,
+ .ack = NULL
+};
+
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_INVALID + reg_num] = {\
+ .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
+ .enable_value = {\
+ DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
+ ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
+ },\
+ .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
+ .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
+ .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
+ .funcs = &hpd_irq_info_funcs\
+ }
+
+#define hpd_rx_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
+ .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
+ .enable_value = {\
+ DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
+ ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
+ .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
+ .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
+ .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
+ .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
+ .funcs = &hpd_rx_irq_info_funcs\
+ }
+
+#define pflip_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+ .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
+ .enable_mask =\
+ GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
+ .enable_value = {\
+ GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
+ ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
+ .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
+ .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
+ .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
+ .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
+ .funcs = &pflip_irq_info_funcs\
+ }
+
+#define vupdate_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+ .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
+ .enable_mask =\
+ CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
+ .enable_value = {\
+ CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
+ ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
+ .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
+ .ack_mask =\
+ CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
+ .ack_value =\
+ CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
+ .funcs = &vblank_irq_info_funcs\
+ }
+
+#define vblank_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+ .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+ .enable_mask =\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+ .enable_value = {\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
+ ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
+ .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
+ .ack_mask =\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+ .ack_value =\
+ CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+ .funcs = &vblank_irq_info_funcs,\
+ .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
+ }
+
+#define dummy_irq_entry() \
+ {\
+ .funcs = &dummy_irq_info_funcs\
+ }
+
+#define i2c_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+ .set = dal_irq_service_dummy_set,
+ .ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dce60[DAL_IRQ_SOURCES_NUMBER] = {
+ [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+ hpd_int_entry(1),
+ hpd_int_entry(2),
+ hpd_int_entry(3),
+ hpd_int_entry(4),
+ hpd_int_entry(5),
+ hpd_int_entry(6),
+ hpd_rx_int_entry(1),
+ hpd_rx_int_entry(2),
+ hpd_rx_int_entry(3),
+ hpd_rx_int_entry(4),
+ hpd_rx_int_entry(5),
+ hpd_rx_int_entry(6),
+ i2c_int_entry(1),
+ i2c_int_entry(2),
+ i2c_int_entry(3),
+ i2c_int_entry(4),
+ i2c_int_entry(5),
+ i2c_int_entry(6),
+ dp_sink_int_entry(1),
+ dp_sink_int_entry(2),
+ dp_sink_int_entry(3),
+ dp_sink_int_entry(4),
+ dp_sink_int_entry(5),
+ dp_sink_int_entry(6),
+ [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+ pflip_int_entry(0),
+ pflip_int_entry(1),
+ pflip_int_entry(2),
+ pflip_int_entry(3),
+ pflip_int_entry(4),
+ pflip_int_entry(5),
+ [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+ gpio_pad_int_entry(0),
+ gpio_pad_int_entry(1),
+ gpio_pad_int_entry(2),
+ gpio_pad_int_entry(3),
+ gpio_pad_int_entry(4),
+ gpio_pad_int_entry(5),
+ gpio_pad_int_entry(6),
+ gpio_pad_int_entry(7),
+ gpio_pad_int_entry(8),
+ gpio_pad_int_entry(9),
+ gpio_pad_int_entry(10),
+ gpio_pad_int_entry(11),
+ gpio_pad_int_entry(12),
+ gpio_pad_int_entry(13),
+ gpio_pad_int_entry(14),
+ gpio_pad_int_entry(15),
+ gpio_pad_int_entry(16),
+ gpio_pad_int_entry(17),
+ gpio_pad_int_entry(18),
+ gpio_pad_int_entry(19),
+ gpio_pad_int_entry(20),
+ gpio_pad_int_entry(21),
+ gpio_pad_int_entry(22),
+ gpio_pad_int_entry(23),
+ gpio_pad_int_entry(24),
+ gpio_pad_int_entry(25),
+ gpio_pad_int_entry(26),
+ gpio_pad_int_entry(27),
+ gpio_pad_int_entry(28),
+ gpio_pad_int_entry(29),
+ gpio_pad_int_entry(30),
+ dc_underflow_int_entry(1),
+ dc_underflow_int_entry(2),
+ dc_underflow_int_entry(3),
+ dc_underflow_int_entry(4),
+ dc_underflow_int_entry(5),
+ dc_underflow_int_entry(6),
+ [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+ [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+ vupdate_int_entry(0),
+ vupdate_int_entry(1),
+ vupdate_int_entry(2),
+ vupdate_int_entry(3),
+ vupdate_int_entry(4),
+ vupdate_int_entry(5),
+ vblank_int_entry(0),
+ vblank_int_entry(1),
+ vblank_int_entry(2),
+ vblank_int_entry(3),
+ vblank_int_entry(4),
+ vblank_int_entry(5),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dce60 = {
+ .to_dal_irq_source = to_dal_irq_source_dce110
+};
+
+static void construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+{
+ dal_irq_service_construct(irq_service, init_data);
+
+ irq_service->info = irq_source_info_dce60;
+ irq_service->funcs = &irq_service_funcs_dce60;
+}
+
+struct irq_service *dal_irq_service_dce60_create(
+ struct irq_service_init_data *init_data)
+{
+ struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+ GFP_KERNEL);
+
+ if (!irq_service)
+ return NULL;
+
+ construct(irq_service, init_data);
+ return irq_service;
+}
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
new file mode 100644
index 000000000000..7314268c739c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce60/irq_service_dce60.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCE60_H__
+#define __DAL_IRQ_SERVICE_DCE60_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dce60_create(
+ struct irq_service_init_data *init_data);
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
index 604bea01fc13..190543cdff60 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -30,6 +30,9 @@
#include "dce110/irq_service_dce110.h"
+#if defined(CONFIG_DRM_AMD_DC_SI)
+#include "dce60/irq_service_dce60.h"
+#endif
#include "dce80/irq_service_dce80.h"
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (6 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 07/10] drm/amd/display: dc/irq: " Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 09/10] drm/amdgpu: enable DC support for SI parts Mauro Rossi
` (3 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
This commit adds Display Manager early initialization for SI parts
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ef02d26f7151..e776ac33a857 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1638,6 +1638,13 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
@@ -1782,6 +1789,23 @@ static int dm_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) {
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_HAINAN:
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+ case CHIP_OLAND:
+ adev->mode_info.num_crtc = 2;
+ adev->mode_info.num_hpd = 2;
+ adev->mode_info.num_dig = 2;
+ adev->mode_info.plane_type = dm_plane_type_default;
+ break;
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (7 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 2:23 ` [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig Mauro Rossi
` (2 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
This commit enables DC support and Display Manager IP block
conditionally to CONFIG_DRM_AMD_DC_SI kernel configuration
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
drivers/gpu/drm/amd/amdgpu/si.c | 14 ++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 43c030459af7..f479f7274412 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2250,6 +2250,13 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
{
switch (asic_type) {
#if defined(CONFIG_DRM_AMD_DC)
+#if defined(CONFIG_DRM_AMD_DC_SI)
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c364ef94cc36..f898f548140c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -48,6 +48,8 @@
#include "uvd/uvd_4_0_d.h"
#include "bif/bif_3_0_d.h"
+#include "amdgpu_dm.h"
+
static const u32 tahiti_golden_registers[] =
{
mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
@@ -2060,6 +2062,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
@@ -2074,6 +2080,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
else
amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
@@ -2088,6 +2098,10 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
if (adev->enable_virtual_display)
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
+ else if (amdgpu_device_has_dc_support(adev))
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
break;
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (8 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 09/10] drm/amdgpu: enable DC support for SI parts Mauro Rossi
@ 2018-10-08 2:23 ` Mauro Rossi
2018-10-08 11:00 ` [RFC] drm/amd/display: add SI support to AMD DC Mike Lothian
2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
11 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 2:23 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: harry.wentland-5C7GfCeVMHo
CONFIG_DRM_AMD_DC_SI configuration option is added, default setting is disabled
---
drivers/gpu/drm/amd/display/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index ed654a76c76a..c79afe89e6e2 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -15,6 +15,14 @@ config DRM_AMD_DC_DCN1_0
help
RV family support for display engine
+config DRM_AMD_DC_SI
+ bool "AMD DC support for Southern Islands ASICs"
+ default n
+ help
+ Choose this option to enable new AMD DC support for SI asics
+ by default. This includes Tahiti, Pitcairn, Cape Verde, Oland
+ and Hainan.
+
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (9 preceding siblings ...)
2018-10-08 2:23 ` [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig Mauro Rossi
@ 2018-10-08 11:00 ` Mike Lothian
[not found] ` <CAHbf0-HK4W4xE-hOJPiwr8zhzuuG2GobCTyHHik3mwe1-9_BmQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
11 siblings, 1 reply; 30+ messages in thread
From: Mike Lothian @ 2018-10-08 11:00 UTC (permalink / raw)
To: Mauro Rossi
Cc: harry.wentland-5C7GfCeVMHo, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 4910 bytes --]
Hi Mauro
Do you know if there are any plans to add in UVD support on SI too?
Thanks
Mike
On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> [PATCH 01/10] drm/amd/display: add asics info for SI parts
> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>
> The series adds preliminar SI support as a Proof Of Concept,
> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
>
> Android-x86 need/motivation lies in the following chain of dependencies:
> Vulkan radv requires gbm gralloc prime_fd support,
> gbm gralloc requires drm hwcomposer,
> drm hwcomposer requires Atomic Display Framework,
> Atomic Display Framework requires AMD DC, currently not supporting SI.
>
> So the goals are:
> 1) to get Vulkan radv working on SI parts for android-x86.
> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>
> DCE6 specific code was implemented as a replica of existing DCE8 support
> and based on how DCE8 specific code was added on top of DCE10,11 support
> by adding dce60* sources, functions, macros for each existing in dce80*
>
> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
>
> During this first iteration of review, there are aspects to verify:
> - dce60 code has been added mechanically, so there may be redundancies
> and space for refactoring part of the code
> - dce60_resources was having too many building errors due to missing DCE6
> macros
> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - gfx6 may require some ad hoc initialization, skipped for the moment
> - Hainan specific code requires review, as some documentation and code
> paths
> seem to point that famility may not have DCE6, please confirm
> - video decoding blocks code have not been touched
> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
> - dc/amdgpu_dm/* changes may be incomplete
> - Any other omissis to be reviewed
> - Feedback on best testing strategy required
>
> Review from an expert of the DC impacted modules is recommended
>
> SW Layer
> /===============================================================\
> | DC Display Timing Mode Asic |
> | Interface Service Service Manager Capability* |
> | |
> | Display Topology Display Link Adapter |
> | Path Manager Capability Service Service |
> | Service |
> |---------------------------------------------------------------|
> | GPIO* IRQ I2cAux HW BIOS |
> | Service** Manager* Sequencer* Parser* |
> | |
> | Connector Encoder Audio GPU Controller |
> | |
> \===============================================================/
> HW Layer
>
> Legend:
> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers
>
> Android-x86 preliminary tests results:
>
> [Boots with drm gralloc]
> 3DMark Slingshot
> GFXbench OpenGLES benchmarks OK
> V1 GPU benchmark (OpenGLES) OK
> Regression in Google Chrome, Youtube (app does not show up)
> Regression in Olympus Rising, Chicken Invaders (app does not show up)
>
> [Boots with drm hwcomposer + gbm gralloc]
> Google Chrome, Youtube are OK
> Vulkan radv HAL API becomes available with hwc+gbm gralloc
> V1 GPU benchmark (Vulkan API) OK
> Sacha Willems examples OK
> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
>
> Kind regards
>
> Mauro Rossi
> android-x86 team
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
[-- Attachment #1.2: Type: text/html, Size: 5981 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAHbf0-HK4W4xE-hOJPiwr8zhzuuG2GobCTyHHik3mwe1-9_BmQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-08 11:22 ` Mauro Rossi
[not found] ` <CAEQFVGbWWy7jmcaserbMwANNHei90WX+1AvOfDAY8J=BcsyCrg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 11:22 UTC (permalink / raw)
To: Mike Lothian; +Cc: Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 6049 bytes --]
Hi Mike,
On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian <mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org> wrote:
> Hi Mauro
>
> Do you know if there are any plans to add in UVD support on SI too?
>
> Thanks
>
> Mike
>
At the moment my focus is on getting a conformant, working and stable
implementation of Atomic Display Framework, with the objective to have it
upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged in
linux kernel.
To be honest my attempt is based on code paths inspection and mimicking,
so in this moment I do not even know the state of UVD and what changes are
needed,
but, based on what I saw for DCE6 support addition on top of DCE8,
covering all compatible HW modules makes a lot of sense and it is an
opportunity to exploit,
if feasible.
For this to happen in most complete and reliable way the feedback of staff
who worked on DAL/DC
will be essential, because what I did now was to adapt code for DCE8 to
work for DCE6,
but it was like an "optimistic monkey with a keyboard" approach, with all
due respect for monkeys with keyboards,
:-) I may have missed dozen of changes.
Mauro
>
> On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
>> [PATCH 01/10] drm/amd/display: add asics info for SI parts
>> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
>> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
>> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
>> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
>> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
>> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
>> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
>> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
>> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>>
>> The series adds preliminar SI support as a Proof Of Concept,
>> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
>>
>> Android-x86 need/motivation lies in the following chain of dependencies:
>> Vulkan radv requires gbm gralloc prime_fd support,
>> gbm gralloc requires drm hwcomposer,
>> drm hwcomposer requires Atomic Display Framework,
>> Atomic Display Framework requires AMD DC, currently not supporting SI.
>>
>> So the goals are:
>> 1) to get Vulkan radv working on SI parts for android-x86.
>> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>>
>> DCE6 specific code was implemented as a replica of existing DCE8 support
>> and based on how DCE8 specific code was added on top of DCE10,11 support
>> by adding dce60* sources, functions, macros for each existing in dce80*
>>
>> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
>>
>> During this first iteration of review, there are aspects to verify:
>> - dce60 code has been added mechanically, so there may be redundancies
>> and space for refactoring part of the code
>> - dce60_resources was having too many building errors due to missing DCE6
>> macros
>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>> - gfx6 may require some ad hoc initialization, skipped for the moment
>> - Hainan specific code requires review, as some documentation and code
>> paths
>> seem to point that famility may not have DCE6, please confirm
>> - video decoding blocks code have not been touched
>> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
>> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
>> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
>> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
>> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
>> - dc/amdgpu_dm/* changes may be incomplete
>> - Any other omissis to be reviewed
>> - Feedback on best testing strategy required
>>
>> Review from an expert of the DC impacted modules is recommended
>>
>> SW Layer
>> /===============================================================\
>> | DC Display Timing Mode Asic |
>> | Interface Service Service Manager Capability* |
>> | |
>> | Display Topology Display Link Adapter |
>> | Path Manager Capability Service Service |
>> | Service |
>> |---------------------------------------------------------------|
>> | GPIO* IRQ I2cAux HW BIOS |
>> | Service** Manager* Sequencer* Parser* |
>> | |
>> | Connector Encoder Audio GPU Controller |
>> | |
>> \===============================================================/
>> HW Layer
>>
>> Legend:
>> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
>> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers
>>
>> Android-x86 preliminary tests results:
>>
>> [Boots with drm gralloc]
>> 3DMark Slingshot
>> GFXbench OpenGLES benchmarks OK
>> V1 GPU benchmark (OpenGLES) OK
>> Regression in Google Chrome, Youtube (app does not show up)
>> Regression in Olympus Rising, Chicken Invaders (app does not show up)
>>
>> [Boots with drm hwcomposer + gbm gralloc]
>> Google Chrome, Youtube are OK
>> Vulkan radv HAL API becomes available with hwc+gbm gralloc
>> V1 GPU benchmark (Vulkan API) OK
>> Sacha Willems examples OK
>> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
>>
>> Kind regards
>>
>> Mauro Rossi
>> android-x86 team
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>
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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAEQFVGbWWy7jmcaserbMwANNHei90WX+1AvOfDAY8J=BcsyCrg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-08 11:29 ` Christian König
[not found] ` <7a8b5d6d-82c2-2b98-b2b2-098baf095aef-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Christian König @ 2018-10-08 11:29 UTC (permalink / raw)
To: Mauro Rossi, Mike Lothian
Cc: Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 7355 bytes --]
UVD/VCE on SI with amdgpu would need new firmware.
And so far we never had time to actually look into releasing that firmware.
Regards,
Christian.
Am 08.10.2018 um 13:22 schrieb Mauro Rossi:
> Hi Mike,
> On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian <mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org
> <mailto:mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org>> wrote:
>
> Hi Mauro
>
> Do you know if there are any plans to add in UVD support on SI too?
>
> Thanks
>
> Mike
>
>
> At the moment my focus is on getting a conformant, working and stable
> implementation of Atomic Display Framework, with the objective to have it
> upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged
> in linux kernel.
>
> To be honest my attempt is based on code paths inspection and mimicking,
> so in this moment I do not even know the state of UVD and what changes
> are needed,
> but, based on what I saw for DCE6 support addition on top of DCE8,
> covering all compatible HW modules makes a lot of sense and it is an
> opportunity to exploit,
> if feasible.
>
> For this to happen in most complete and reliable way the feedback of
> staff who worked on DAL/DC
> will be essential, because what I did now was to adapt code for DCE8
> to work for DCE6,
> but it was like an "optimistic monkey with a keyboard" approach, with
> all due respect for monkeys with keyboards,
> :-) I may have missed dozen of changes.
>
> Mauro
>
>
> On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> <mailto:issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>
> [PATCH 01/10] drm/amd/display: add asics info for SI parts
> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>
> The series adds preliminar SI support as a Proof Of Concept,
> based on the idea that DCE6 is similar to DCE8, to be reviewed
> and refined
>
> Android-x86 need/motivation lies in the following chain of
> dependencies:
> Vulkan radv requires gbm gralloc prime_fd support,
> gbm gralloc requires drm hwcomposer,
> drm hwcomposer requires Atomic Display Framework,
> Atomic Display Framework requires AMD DC, currently not
> supporting SI.
>
> So the goals are:
> 1) to get Vulkan radv working on SI parts for android-x86.
> 2) to remove the gap in SI (GCN 1st gen) not having atomic
> support.
>
> DCE6 specific code was implemented as a replica of existing
> DCE8 support
> and based on how DCE8 specific code was added on top of
> DCE10,11 support
> by adding dce60* sources, functions, macros for each existing
> in dce80*
>
> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI
> support in DC
>
> During this first iteration of review, there are aspects to
> verify:
> - dce60 code has been added mechanically, so there may be
> redundancies
> and space for refactoring part of the code
> - dce60_resources was having too many building errors due to
> missing DCE6 macros
> in order to temporarily overcome the problem
> dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
> were used for the PoC
> - gfx6 may require some ad hoc initialization, skipped for the
> moment
> - Hainan specific code requires review, as some documentation
> and code paths
> seem to point that famility may not have DCE6, please confirm
> - video decoding blocks code have not been touched
> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6
> specifics
> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6
> specifics
> - dc/amdgpu_dm/* changes may be incomplete
> - Any other omissis to be reviewed
> - Feedback on best testing strategy required
>
> Review from an expert of the DC impacted modules is recommended
>
> SW Layer
> /===============================================================\
> | DC Display Timing Mode Asic |
> | Interface Service Service Manager Capability* |
> | |
> | Display Topology Display Link Adapter |
> | Path Manager Capability Service Service |
> | Service |
> |---------------------------------------------------------------|
> | GPIO* IRQ I2cAux HW BIOS |
> | Service** Manager* Sequencer* Parser* |
> | |
> | Connector Encoder Audio GPU Controller |
> | |
> \===============================================================/
> HW Layer
>
> Legend:
> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h
> headers
> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers
>
> Android-x86 preliminary tests results:
>
> [Boots with drm gralloc]
> 3DMark Slingshot
> GFXbench OpenGLES benchmarks OK
> V1 GPU benchmark (OpenGLES) OK
> Regression in Google Chrome, Youtube (app does not show up)
> Regression in Olympus Rising, Chicken Invaders (app does not
> show up)
>
> [Boots with drm hwcomposer + gbm gralloc]
> Google Chrome, Youtube are OK
> Vulkan radv HAL API becomes available with hwc+gbm gralloc
> V1 GPU benchmark (Vulkan API) OK
> Sacha Willems examples OK
> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
>
> Kind regards
>
> Mauro Rossi
> android-x86 team
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (10 preceding siblings ...)
2018-10-08 11:00 ` [RFC] drm/amd/display: add SI support to AMD DC Mike Lothian
@ 2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 12:32 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 17:02 ` Mauro Rossi
11 siblings, 2 replies; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-08 12:04 UTC (permalink / raw)
To: Mauro Rossi
Cc: harry.wentland-5C7GfCeVMHo, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
I am currently testing your patch set, on amd-staging-drm-next
(380d480842d584278dba9aa74341017d8c7d8c23) with an AMD tahiti xt part and a
displayport monitor.
patch02 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c did not apply but
seems kind of benign.
It's working out of the box on my AMD tahiti xt part. I did not manage to break
it with aggressive mode programming. Let's see how it goes with my everday
usage.
> The series adds preliminar SI support as a Proof Of Concept,
> based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
Did want to do it, but did drop it due to DC code getting fixed with too much
changes.
Brutally mapping DCE6 to DCE8 is an act of faith... and it's working on my
part.
> Android-x86 need/motivation lies in the following chain of dependencies:
> Vulkan radv requires gbm gralloc prime_fd support,
> gbm gralloc requires drm hwcomposer,
> drm hwcomposer requires Atomic Display Framework,
> Atomic Display Framework requires AMD DC, currently not supporting SI.
>
> So the goals are:
> 1) to get Vulkan radv working on SI parts for android-x86.
AFAIK, Vulkan support is not dependent on the display block. I am running heavy
vulkan games on a custom gnu/linux x86_64 AMD hardware based system, then the
hwcomposer is android only?
> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
I was nearly sure that atomic support was implicitely added for parts
supporting only legacy DRM mode programming interfaces?
--
Sylvain
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <7a8b5d6d-82c2-2b98-b2b2-098baf095aef-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-10-08 12:16 ` Mike Lothian
[not found] ` <CAHbf0-FB2GV18igVo-8MHcVGL89KZoXn+O2B4asoe5R4RbgCVw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Mike Lothian @ 2018-10-08 12:16 UTC (permalink / raw)
To: christian.koenig-5C7GfCeVMHo
Cc: Mauro Rossi, Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 7006 bytes --]
I thought it just required the existing firmware, with padding / extra info
put around it?
On Mon, 8 Oct 2018 at 12:29 Christian König <
ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> UVD/VCE on SI with amdgpu would need new firmware.
>
> And so far we never had time to actually look into releasing that firmware.
>
> Regards,
> Christian.
>
>
> Am 08.10.2018 um 13:22 schrieb Mauro Rossi:
>
> Hi Mike,
> On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian <mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org> wrote:
>
>> Hi Mauro
>>
>> Do you know if there are any plans to add in UVD support on SI too?
>>
>> Thanks
>>
>> Mike
>>
>
> At the moment my focus is on getting a conformant, working and stable
> implementation of Atomic Display Framework, with the objective to have it
> upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged in
> linux kernel.
>
> To be honest my attempt is based on code paths inspection and mimicking,
> so in this moment I do not even know the state of UVD and what changes are
> needed,
> but, based on what I saw for DCE6 support addition on top of DCE8,
> covering all compatible HW modules makes a lot of sense and it is an
> opportunity to exploit,
> if feasible.
>
> For this to happen in most complete and reliable way the feedback of staff
> who worked on DAL/DC
> will be essential, because what I did now was to adapt code for DCE8 to
> work for DCE6,
> but it was like an "optimistic monkey with a keyboard" approach, with all
> due respect for monkeys with keyboards,
> :-) I may have missed dozen of changes.
>
> Mauro
>
>
>>
>> On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>>
>>> [PATCH 01/10] drm/amd/display: add asics info for SI parts
>>> [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
>>> [PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
>>> [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
>>> [PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
>>> [PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
>>> [PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
>>> [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
>>> [PATCH 09/10] drm/amdgpu: enable DC support for SI parts
>>> [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
>>>
>>> The series adds preliminar SI support as a Proof Of Concept,
>>> based on the idea that DCE6 is similar to DCE8, to be reviewed and
>>> refined
>>>
>>> Android-x86 need/motivation lies in the following chain of dependencies:
>>> Vulkan radv requires gbm gralloc prime_fd support,
>>> gbm gralloc requires drm hwcomposer,
>>> drm hwcomposer requires Atomic Display Framework,
>>> Atomic Display Framework requires AMD DC, currently not supporting SI.
>>>
>>> So the goals are:
>>> 1) to get Vulkan radv working on SI parts for android-x86.
>>> 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>>>
>>> DCE6 specific code was implemented as a replica of existing DCE8 support
>>> and based on how DCE8 specific code was added on top of DCE10,11 support
>>> by adding dce60* sources, functions, macros for each existing in dce80*
>>>
>>> CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
>>>
>>> During this first iteration of review, there are aspects to verify:
>>> - dce60 code has been added mechanically, so there may be redundancies
>>> and space for refactoring part of the code
>>> - dce60_resources was having too many building errors due to missing
>>> DCE6 macros
>>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h
>>> headers
>>> were used for the PoC
>>> - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>>> were used for the PoC
>>> - gfx6 may require some ad hoc initialization, skipped for the moment
>>> - Hainan specific code requires review, as some documentation and code
>>> paths
>>> seem to point that famility may not have DCE6, please confirm
>>> - video decoding blocks code have not been touched
>>> - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
>>> - dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
>>> - dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
>>> - dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
>>> - dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
>>> - dc/amdgpu_dm/* changes may be incomplete
>>> - Any other omissis to be reviewed
>>> - Feedback on best testing strategy required
>>>
>>> Review from an expert of the DC impacted modules is recommended
>>>
>>> SW Layer
>>> /===============================================================\
>>> | DC Display Timing Mode Asic |
>>> | Interface Service Service Manager Capability* |
>>> | |
>>> | Display Topology Display Link Adapter |
>>> | Path Manager Capability Service Service |
>>> | Service |
>>> |---------------------------------------------------------------|
>>> | GPIO* IRQ I2cAux HW BIOS |
>>> | Service** Manager* Sequencer* Parser* |
>>> | |
>>> | Connector Encoder Audio GPU Controller |
>>> | |
>>> \===============================================================/
>>> HW Layer
>>>
>>> Legend:
>>> *dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
>>> **dce60 support was added using dce_8_0_{d,sh_mask}.h headers
>>>
>>> Android-x86 preliminary tests results:
>>>
>>> [Boots with drm gralloc]
>>> 3DMark Slingshot
>>> GFXbench OpenGLES benchmarks OK
>>> V1 GPU benchmark (OpenGLES) OK
>>> Regression in Google Chrome, Youtube (app does not show up)
>>> Regression in Olympus Rising, Chicken Invaders (app does not show up)
>>>
>>> [Boots with drm hwcomposer + gbm gralloc]
>>> Google Chrome, Youtube are OK
>>> Vulkan radv HAL API becomes available with hwc+gbm gralloc
>>> V1 GPU benchmark (Vulkan API) OK
>>> Sacha Willems examples OK
>>> Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
>>>
>>> Kind regards
>>>
>>> Mauro Rossi
>>> android-x86 team
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>
>>
>
> _______________________________________________
> amd-gfx mailing listamd-gfx-PD4FTy7X32lNgt0PjOBp934avgP/u3fG0wdF1cv0I5s@public.gmane.org://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-08 12:32 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 17:02 ` Mauro Rossi
1 sibling, 0 replies; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-08 12:32 UTC (permalink / raw)
To: Mauro Rossi
Cc: harry.wentland-5C7GfCeVMHo, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Oct 08, 2018 at 12:04:23PM +0000, sylvain.bertrand@gmail.com wrote:
> I am currently testing your patch set, on amd-staging-drm-next
> (380d480842d584278dba9aa74341017d8c7d8c23) with an AMD tahiti xt part and a
> displayport monitor.
Forgot a very important thing: I run it with the linux tsc fix, or all linux
timings will be wrong and no displayport programing will happen. This fix is
not in current vanilla amd-staging-drm-next.
--
Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAHbf0-FB2GV18igVo-8MHcVGL89KZoXn+O2B4asoe5R4RbgCVw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-08 15:47 ` Deucher, Alexander
0 siblings, 0 replies; 30+ messages in thread
From: Deucher, Alexander @ 2018-10-08 15:47 UTC (permalink / raw)
To: Mike Lothian, Koenig, Christian
Cc: Mauro Rossi, Wentland, Harry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 7438 bytes --]
It's trivial to add the metadata/version headers to the existing firmware, so that is not an issue. The issue is with the firmware itself. If we used the existing firmware, we'd have to add a bunch of really ugly hacks in the driver to work around the current limitations.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Mike Lothian <mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org>
Sent: Monday, October 8, 2018 8:16:01 AM
To: Koenig, Christian
Cc: Mauro Rossi; Wentland, Harry; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [RFC] drm/amd/display: add SI support to AMD DC
I thought it just required the existing firmware, with padding / extra info put around it?
On Mon, 8 Oct 2018 at 12:29 Christian König <ckoenig.leichtzumerken@gmail.com<mailto:ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
UVD/VCE on SI with amdgpu would need new firmware.
And so far we never had time to actually look into releasing that firmware.
Regards,
Christian.
Am 08.10.2018 um 13:22 schrieb Mauro Rossi:
Hi Mike,
On Mon, Oct 8, 2018 at 1:00 PM Mike Lothian <mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org<mailto:mike@fireburn.co.uk>> wrote:
Hi Mauro
Do you know if there are any plans to add in UVD support on SI too?
Thanks
Mike
At the moment my focus is on getting a conformant, working and stable
implementation of Atomic Display Framework, with the objective to have it
upstreamed to amd-gfx branch, then staging (drm-next) and maybe merged in linux kernel.
To be honest my attempt is based on code paths inspection and mimicking,
so in this moment I do not even know the state of UVD and what changes are needed,
but, based on what I saw for DCE6 support addition on top of DCE8,
covering all compatible HW modules makes a lot of sense and it is an opportunity to exploit,
if feasible.
For this to happen in most complete and reliable way the feedback of staff who worked on DAL/DC
will be essential, because what I did now was to adapt code for DCE8 to work for DCE6,
but it was like an "optimistic monkey with a keyboard" approach, with all due respect for monkeys with keyboards,
:-) I may have missed dozen of changes.
Mauro
On Mon, 8 Oct 2018 at 03:24 Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org<mailto:issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
[PATCH 01/10] drm/amd/display: add asics info for SI parts
[PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support
[PATCH 03/10] drm/amd/display: dc/core: add DCE6 support
[PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6
[PATCH 05/10] drm/amd/display: dc/gpio: add support for DCE6
[PATCH 06/10] drm/amd/display: dc/i2caux: add support for DCE6
[PATCH 07/10] drm/amd/display: dc/irq: add support for DCE6
[PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support
[PATCH 09/10] drm/amdgpu: enable DC support for SI parts
[PATCH 10/10] drm/amd/display: enable SI support in the Kconfig
The series adds preliminar SI support as a Proof Of Concept,
based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
Android-x86 need/motivation lies in the following chain of dependencies:
Vulkan radv requires gbm gralloc prime_fd support,
gbm gralloc requires drm hwcomposer,
drm hwcomposer requires Atomic Display Framework,
Atomic Display Framework requires AMD DC, currently not supporting SI.
So the goals are:
1) to get Vulkan radv working on SI parts for android-x86.
2) to remove the gap in SI (GCN 1st gen) not having atomic support.
DCE6 specific code was implemented as a replica of existing DCE8 support
and based on how DCE8 specific code was added on top of DCE10,11 support
by adding dce60* sources, functions, macros for each existing in dce80*
CONFIG_DRM_AMD_DC_SI parameter has been added to control SI support in DC
During this first iteration of review, there are aspects to verify:
- dce60 code has been added mechanically, so there may be redundancies
and space for refactoring part of the code
- dce60_resources was having too many building errors due to missing DCE6 macros
in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
were used for the PoC
- gfx6 may require some ad hoc initialization, skipped for the moment
- Hainan specific code requires review, as some documentation and code paths
seem to point that famility may not have DCE6, please confirm
- video decoding blocks code have not been touched
- dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_dmcu.{c,h} may be missing some SI/DCE6 specifics
- dc/dce/dce_hwseq.h may be missing some SI/DCE6 specifics
- dc/dce/dce_link_encoder.h may be missing some SI/DCE6 specifics
- dc/dce/dce_stream_encoder.h may be missing some SI/DCE6 specifics
- dc/amdgpu_dm/* changes may be incomplete
- Any other omissis to be reviewed
- Feedback on best testing strategy required
Review from an expert of the DC impacted modules is recommended
SW Layer
/===============================================================\
| DC Display Timing Mode Asic |
| Interface Service Service Manager Capability* |
| |
| Display Topology Display Link Adapter |
| Path Manager Capability Service Service |
| Service |
|---------------------------------------------------------------|
| GPIO* IRQ I2cAux HW BIOS |
| Service** Manager* Sequencer* Parser* |
| |
| Connector Encoder Audio GPU Controller |
| |
\===============================================================/
HW Layer
Legend:
*dce60 support was added cleanly with dce_6_0_{d,sh_mask}.h headers
**dce60 support was added using dce_8_0_{d,sh_mask}.h headers
Android-x86 preliminary tests results:
[Boots with drm gralloc]
3DMark Slingshot
GFXbench OpenGLES benchmarks OK
V1 GPU benchmark (OpenGLES) OK
Regression in Google Chrome, Youtube (app does not show up)
Regression in Olympus Rising, Chicken Invaders (app does not show up)
[Boots with drm hwcomposer + gbm gralloc]
Google Chrome, Youtube are OK
Vulkan radv HAL API becomes available with hwc+gbm gralloc
V1 GPU benchmark (Vulkan API) OK
Sacha Willems examples OK
Some glitch/freeze in 3DMark Slingshot Extreeme and API overhead
Kind regards
Mauro Rossi
android-x86 team
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 12:32 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-08 17:02 ` Mauro Rossi
[not found] ` <CAEQFVGahx4U+52uKu20_q0iCPrdzeW8G+viS7p2LJtgF61bf6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
1 sibling, 1 reply; 30+ messages in thread
From: Mauro Rossi @ 2018-10-08 17:02 UTC (permalink / raw)
To: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
Cc: Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi Sylvain,
On Mon, Oct 8, 2018 at 2:04 PM <sylvain.bertrand@gmail.com> wrote:
>
> I am currently testing your patch set, on amd-staging-drm-next
> (380d480842d584278dba9aa74341017d8c7d8c23) with an AMD tahiti xt part and a
> displayport monitor.
> patch02 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c did not apply but
> seems kind of benign.
>
> It's working out of the box on my AMD tahiti xt part. I did not manage to break
> it with aggressive mode programming. Let's see how it goes with my everday
> usage.
Thanks for info, do you have some github or patch to share for
comparison/mutual knowledge?
>
> > The series adds preliminar SI support as a Proof Of Concept,
> > based on the idea that DCE6 is similar to DCE8, to be reviewed and refined
>
> Did want to do it, but did drop it due to DC code getting fixed with too much
> changes.
> Brutally mapping DCE6 to DCE8 is an act of faith... and it's working on my
> part.
Do you mean just pretending SI/DCE6 parts were belonging to CIK/DCE8 family?
That was a doubt for me, because GCN 2nd Generation additions were:
FreeSync support (which should be missing in SI/GCN 1st generation),
AMD TrueAudio (not sure about impacts in DC),
A revised version of AMD PowerTune technology (less states in GCN 1st gen),
GCN 2nd generation introduced an entity called "Shader Engine"
While implementing the DCE6 code paths with 'systematic conservative approach'
I have started to check how/if extend the approach to dce60/resources
and dce60/irq,
I'd like to know if to push further in that direction or if keep the
DCE8 headers/masks "hack"
One problem I see are Mosaic Colored Artifacts on screen surface in
the 3D renders of 3Dmark Slingshot Extreeme,
another visual problem is some imperfection of video sync/buffer swaps
with drm_hwcomposer stack, same as per other GCN families.
It will be interesting to launch some conformance tool like Piglit on
linux, Android CTS dEQP VK tests,
but after having triaged/removed most of the current drm gralloc regressions.
Mauro
>
>
> > Android-x86 need/motivation lies in the following chain of dependencies:
> > Vulkan radv requires gbm gralloc prime_fd support,
> > gbm gralloc requires drm hwcomposer,
> > drm hwcomposer requires Atomic Display Framework,
> > Atomic Display Framework requires AMD DC, currently not supporting SI.
> >
> > So the goals are:
> > 1) to get Vulkan radv working on SI parts for android-x86.
>
> AFAIK, Vulkan support is not dependent on the display block. I am running heavy
> vulkan games on a custom gnu/linux x86_64 AMD hardware based system, then the
> hwcomposer is android only?
Yes, at the moment drm_hwcomposer is used only in Android builds
>
> > 2) to remove the gap in SI (GCN 1st gen) not having atomic support.
>
> I was nearly sure that atomic support was implicitely added for parts
> supporting only legacy DRM mode programming interfaces?
drm_hwcomposer API does not see atomic properties with amdgpu on SI parts.
if Atomic Display Framework available in amdgpu, then hwc, gbm gralloc and radv
would be already working on Android.
Also radeondrmfb does not support Atomic Display Framework and that is a problem
to have one stack for all drivers, becase with AMD DC, radeon r5xx...
r7xx parts will not
work even if OpenGLES supported.
Mauro
>
>
> --
> Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAEQFVGahx4U+52uKu20_q0iCPrdzeW8G+viS7p2LJtgF61bf6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-08 20:17 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 21:22 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
0 siblings, 1 reply; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-08 20:17 UTC (permalink / raw)
To: Mauro Rossi; +Cc: Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Oct 08, 2018 at 07:02:54PM +0200, Mauro Rossi wrote:
> Thanks for info, do you have some github or patch to share for
> comparison/mutual knowledge?
Sorry, I was wrong: I thought your patch set was enabling by default DC for
dce6 (it requires the DC kernel param).
I did force it, and it fails to init the dce6.
:(
--
Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-08 20:17 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-08 21:22 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-14 21:47 ` Mauro Rossi
0 siblings, 1 reply; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-08 21:22 UTC (permalink / raw)
To: Mauro Rossi; +Cc: Harry Wentland, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Oct 08, 2018 at 08:17:06PM +0000, sylvain.bertrand@gmail.com wrote:
> Sorry, I was wrong: I thought your patch set was enabling by default DC for
> dce6 (it requires the DC kernel param).
> I did force it, and it fails to init the dce6.
I did hack a bit your patch set on amd-staging-drm-next to make it go through the
asic init and I managed to get a x11 display with lines kind of garbled, but
you can still understand easily what's on the screen.
I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
invalid powerlevel and atombios/vbios table parsing regarding connectors.
It _seems_ there is not that much additional work to do in order to make it
properly work.
That said, since I am not an android linux dev, I cannot really understand why
the current dce6 implementation in amdgpu is a pb.
AFAIK, the real thing that you additionally get with DC is freesync. But
freesync is actually going to be interesting only if displays are able to
get their sync range lower bound to 0, and get significant power saving
thanks to this. For the use case of very low display refresh rate I don't even
think displayport or hdmi can do that, and be power friendly (you would have
to retrain the link probably each time you send a framebuffer to the display).
I don't know what are the features you have in atomic mode setting and not in
legacy mode setting? You are just setting the same video mode in 2 different
ways.
--
Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-08 21:22 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-14 21:47 ` Mauro Rossi
[not found] ` <CAEQFVGaErupy3y+sKA+uqQPn7x0oL1T9BKWj6y8EC12Ap2-YDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Mauro Rossi @ 2018-10-14 21:47 UTC (permalink / raw)
To: Sylvain Bertrand, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Harry Wentland,
Christian König
Hi,
reporting about some progress made during the weekend,
thanks to Sylvain feedback & suggestions.
I have rebased and updated the series on top of
https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
Here is the amd_dc_si branch:
https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
there, as they are not strictly needed for amd-gfx
Copying also Harry, Alex, Christian and Mike in order to get some
objective and infallible
clues/feedbacks about blocking points and about "no care" items.
Please, also big things I may have missed.
M.
>On Mon, Oct 8, 2018 at 11:23 PM <sylvain.bertrand@gmail.com> wrote:
>
> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it go through the
> asic init and I managed to get a x11 display with lines kind of garbled, but
> you can still understand easily what's on the screen.
I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
Kaveri and older")
because on Mullins I can boot with HDMI and HDMI-to-VGA converter
I was hoping for AMD DC being re-enabled for Kaveri and older,
but I'm available to submit new version of specific patch if required.
> Sylvain - ... The lines may be garbled in your driver code because,
> if I recall properly, "line buffer" programing in dce8 is not
> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
> slight differences in frame buffer tiling.
So the problem could be related to some kind of scan line or tiling
buffer issue,
at the moment the dce_resouces model is grabbed "AS IS" from DCE8
registers/masks
>
> Sylvain - I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
> current SI amdgpu code path should be "copied" in DC. It is related very
> probably to the parsing of VBIOS/ATOMBIOS tables.
10-09 21:10:14.427 0 0 E :
[drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
powerlevel state: 0!
NOTE: the error is the result of Powerplay dependency introduced by
using AMD DC for SI
it's not fatal and it does not seem to affect performance in the Benchmarks
DOUBT: I think that it would make sense to set "power level 0" i.e.
the "lower state" as safe default,
considering that powerplay smu6/hwmgr are not implemented for SI and
smu7 CIK functions do not work,
the AS-IS dpm is the only available option. (and it seams to be
working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
>10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
>10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
NOTE: the warning also appears with Tonga and Vega, it is a Warning
and does not seem to cause issues, so I would assume there is a
default treatment in place,
is this related to missing encoder for drm crtc or to other kind of encoder?
> Sylvain - Did add SI handling in some raven firmware loader function.
> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
> function augmented with SI chip asic_type.
I've merged the change in the (v2) branch
https://github.com/maurossi/linux/tree/amd_dc_si
> Sylvain - AFAIK, the real thing that you additionally get with DC is freesync. But
> freesync is actually going to be interesting only if displays are able to
> get their sync range lower bound to 0, and get significant power saving
> thanks to this. For the use case of very low display refresh rate I don't even
> think displayport or hdmi can do that, and be power friendly (you would have
> to retrain the link probably each time you send a framebuffer to the display).
If freesync is about reducing the framerate rate for power saving,
provided that I've seen it be mentioned the first time for GCN 2nd generation,
I'm not expecting freesync as a mandatory capability for the series.
> Mauro -- dce60_resources was having too many building errors due to missing DCE6 macros
>in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>were used for the PoC
Still to many building errors due to quite different registers naming,
pointers to GPU register info (either in GPUopen or by means of
listing the DCE6 vs DC8 differences),
or keeping the DCE6 is exactly like DCE8 as register changes are
apparently not mission critical.
> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>were used for the PoC
I could not update dc/irq VBI Vertical Blank Interrupt, because i
cannot find the corresponding IRQ register in amdgpu/dce6 registers
headers/mask
-CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
+?seems trivial but who knows what is the corresponding in DCE6?
-CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK
+?seems trivial but who knows what is the corresponding in DCE6?
NOTE: If this is the very basic VBI Vertical Blank Interrupt signal
handling, there should be dce6 registers/masks,
but some hint/documentation is necessary for me to find them.
>Mauro - gfx6 may require some ad hoc initialization, skipped for the moment
Are there ad hoc tiling settings which are necessary?
The OpenGLES and Vulkan radv apps I've tested:
Android CTS dEQP-VK only 85 tests failed over 220'000
Toy Zombies Lite
Sky Force Reloaded
V1 Benchmark Pro
GFXbench
Antutu 3D
Various OpenGLES demos
Here I'm planning to perform also dEQP-EGL, dEQP-GLES2, dEQP-GLES3 soon,
but feedbacks from developers are very welcome and appreciated
> Mauro - Hainan specific code requires review, as some documentation and code paths
>seem to point that famility may not have DCE6, please confirm
Hainan specifics were removed and are unsupported in the new serie
as DCE6 physical module not available in Hainan parts.
Unless the virtual_dce modules supports atomit, but I don't think so.
> Mauro - video decoding blocks code have not been touched
UVD and VCE firmwares and code changes for SI were necessary before the series
and they are unrelated to AMD DC for SI patches.
>Mauro - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
In amd-staging-drm-next dce_clock_source is generic, SI specifics are
not necessary anymore.
> Sylvain - It _seems_ there is not that much additional work to do in order to make it
> properly work.
>
Ok, let's keep the momentum and continue tackle with x11 display problem
and after that I'm runnign piglit no regression with x11 and with wayland too.
> Testing on x11,wayland or other ways
Any other testing tools worth a run?
In case there is some AMD/GPUopen testing tool with unit tests, please
let me know
Kind regards
Mauro
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAEQFVGaErupy3y+sKA+uqQPn7x0oL1T9BKWj6y8EC12Ap2-YDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-15 1:25 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-15 5:28 ` Mauro Rossi
2018-10-15 21:06 ` Harry Wentland
1 sibling, 1 reply; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-15 1:25 UTC (permalink / raw)
To: Mauro Rossi
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian,
Christian-CC+yJ3UmIYqDUpFQwHEjaQ, Harry Wentland,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Sun, Oct 14, 2018 at 11:47:18PM +0200, Mauro Rossi wrote:
> DOUBT: I think that it would make sense to set "power level 0" i.e.
> the "lower state" as safe default,
> considering that powerplay smu6/hwmgr are not implemented for SI and
> smu7 CIK functions do not work,
> the AS-IS dpm is the only available option. (and it seams to be
> working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
dpm not implemented for SI? Are you sure? Because I recall passing "messages"
to the smu6 to switch between major power modes. And currently in amdgpu I
switch back and forth between "high" and "auto". And if I stay on "high" my GPU
fans are going crazy all the time, which forces me to switch back to "auto" in
order to quiet the fans.
Any major state change for any block would have to go through the dpm block
(smu), because it has to be accounted by this block for proper operation. One
of the hard thing to code, coze no proper documentation, was to set the blocks
in an initial state from a poweron/hard reset/etc which the dpm will know
how to start/catch-up its operations from. In a perfect world, the dpm block
would have the knowledge on how to program any block in an initial working
state from any unknown state (and in case of hard block hang, would know how to
hard reset it and set it in a initial state).
> If freesync is about reducing the framerate rate for power saving,
> provided that I've seen it be mentioned the first time for GCN 2nd generation,
> I'm not expecting freesync as a mandatory capability for the series.
Well, there are the low FPS games, and the movies. I am a regular gamer, and I
know that sustained 60 fps is the very lower bound for many games on a desktop
computer display.
It does not apply to mobile size display, and "couch playing" on a TV. The
readibilty of the game depends directly on the amplitude of movements in
physical distance on the display, their speed, the viewing distance, and the
FPS. From my personal comfort point of view and types of games I play, on a
desktop display (dpi, typical viewing distance, typical size), I would target a
minimum of 80-100 fps (120/144 fps seems to be "perfect" targets).
Played rise of the tomb raider (vulkan) on my tahiti part, and even with a blur
effect to "smooth" the perceived fps like in movies, sub-60 fps is really
uncomfortable. I was about to stop playing to this game even though it is a
rather "slow" video game.
> In amd-staging-drm-next dce_clock_source is generic, SI specifics are
> not necessary anymore.
If I recall properly, "bandwidths" and "watermarks" calcs had asic generations
specific code paths. bandwidth is important for displayport programming or
maybe you can presume the maximum all the time (and sacrifice some unkown
amount of power) and watermarks, I know in my old driver I was giving the
highest priority the the dce block anyway (something related to a "memory
aribtrer" and "line buffer").
> Any other testing tools worth a run?
AAA games (vulkan: rize of the tomb raider, GL:bioshock infinite) and AAAA games
(dota2(gl and vulkan), cs:go...)
--
Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-15 1:25 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-15 5:28 ` Mauro Rossi
[not found] ` <CAEQFVGbB_ezGSGwPu2Ka-4rY9RjB_rJvPL8ZCEG-_rfXxOEN-A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 30+ messages in thread
From: Mauro Rossi @ 2018-10-15 5:28 UTC (permalink / raw)
To: Sylvain Bertrand
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Harry Wentland,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 3603 bytes --]
Hi Sylvain,
Il lun 15 ott 2018, 03:25 <sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> ha scritto:
> On Sun, Oct 14, 2018 at 11:47:18PM +0200, Mauro Rossi wrote:
> > DOUBT: I think that it would make sense to set "power level 0" i.e.
> > the "lower state" as safe default,
> > considering that powerplay smu6/hwmgr are not implemented for SI and
> > smu7 CIK functions do not work,
> > the AS-IS dpm is the only available option. (and it seams to be
> > working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
>
> dpm not implemented for SI? Are you sure? Because I recall passing
> "messages"
>
dpm for SI is available, while powerplay for SI is not, but
display/amdgpu_dm uses some powerplay calls, where get_static_clock
functions not available and the *ERROR* DM_PPLIB is due to missing handling
in powerplay
to the smu6 to switch between major power modes. And currently in amdgpu I
> switch back and forth between "high" and "auto". And if I stay on "high"
> my GPU
> fans are going crazy all the time, which forces me to switch back to
> "auto" in
> order to quiet the fans.
> Any major state change for any block would have to go through the dpm block
> (smu), because it has to be accounted by this block for proper operation.
> One
> of the hard thing to code, coze no proper documentation, was to set the
> blocks
> in an initial state from a poweron/hard reset/etc which the dpm will know
> how to start/catch-up its operations from. In a perfect world, the dpm
> block
> would have the knowledge on how to program any block in an initial working
> state from any unknown state (and in case of hard block hang, would know
> how to
> hard reset it and set it in a initial state).
>
> > If freesync is about reducing the framerate rate for power saving,
> > provided that I've seen it be mentioned the first time for GCN 2nd
> generation,
> > I'm not expecting freesync as a mandatory capability for the series.
>
> Well, there are the low FPS games, and the movies. I am a regular gamer,
> and I
> know that sustained 60 fps is the very lower bound for many games on a
> desktop
> computer display.
> It does not apply to mobile size display, and "couch playing" on a TV. The
> readibilty of the game depends directly on the amplitude of movements in
> physical distance on the display, their speed, the viewing distance, and
> the
> FPS. From my personal comfort point of view and types of games I play, on a
> desktop display (dpi, typical viewing distance, typical size), I would
> target a
> minimum of 80-100 fps (120/144 fps seems to be "perfect" targets).
> Played rise of the tomb raider (vulkan) on my tahiti part, and even with a
> blur
> effect to "smooth" the perceived fps like in movies, sub-60 fps is really
> uncomfortable. I was about to stop playing to this game even though it is a
> rather "slow" video game.
>
> > In amd-staging-drm-next dce_clock_source is generic, SI specifics are
> > not necessary anymore.
>
> If I recall properly, "bandwidths" and "watermarks" calcs had asic
> generations
> specific code paths. bandwidth is important for displayport programming or
> maybe you can presume the maximum all the time (and sacrifice some unkown
> amount of power) and watermarks, I know in my old driver I was giving the
> highest priority the the dce block anyway (something related to a "memory
> aribtrer" and "line buffer").
>
> > Any other testing tools worth a run?
>
> AAA games (vulkan: rize of the tomb raider, GL:bioshock infinite) and AAAA
> games
> (dota2(gl and vulkan), cs:go...)
>
> --
> Sylvain
>
Thanks a lot
Mauro
>
[-- Attachment #1.2: Type: text/html, Size: 4683 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAEQFVGbB_ezGSGwPu2Ka-4rY9RjB_rJvPL8ZCEG-_rfXxOEN-A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-10-15 12:45 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-15 17:53 ` Deucher, Alexander
0 siblings, 1 reply; 30+ messages in thread
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w @ 2018-10-15 12:45 UTC (permalink / raw)
To: Mauro Rossi
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Harry Wentland,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Oct 15, 2018 at 07:28:57AM +0200, Mauro Rossi wrote:
> dpm for SI is available, while powerplay for SI is not, but
> display/amdgpu_dm uses some powerplay calls, where get_static_clock
> functions not available and the *ERROR* DM_PPLIB is due to missing handling
> in powerplay
I though powerplay was just more power states for the dpm state machines to
play with. I recall parsing ATOMBIOS pplay tables for records of (voltages/clocks
frequencies).
Maybe the future is to trust the OS kernel and perform all "low speed" 3D asic
functions there and keep only high speed 3D operations in the asic.
--
Sylvain
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
2018-10-15 12:45 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-15 17:53 ` Deucher, Alexander
0 siblings, 0 replies; 30+ messages in thread
From: Deucher, Alexander @ 2018-10-15 17:53 UTC (permalink / raw)
To: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w, Mauro Rossi
Cc: Mike Lothian, Wentland, Harry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 1652 bytes --]
There are two sets of power management code in amdgpu, the older dpm code which was ported from radeon, and the newer powerplay code which was rewritten to align closer with the power management code for other OSes and the hw teams. The "powerplay" code has more features than the older dpm code, but at a fundamental level, they are pretty much the same. Both use the same SMU interfaces to support dynamic clock switching. SI is a bit tricky because it uses and older version of the SMU and an older power management design so it doesn't really match cleanly with the current APIs in the "powerplay" code.
Alex
________________________________
From: sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Monday, October 15, 2018 8:45 AM
To: Mauro Rossi
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Wentland, Harry; Deucher, Alexander; Mike Lothian
Subject: Re: [RFC] drm/amd/display: add SI support to AMD DC
On Mon, Oct 15, 2018 at 07:28:57AM +0200, Mauro Rossi wrote:
> dpm for SI is available, while powerplay for SI is not, but
> display/amdgpu_dm uses some powerplay calls, where get_static_clock
> functions not available and the *ERROR* DM_PPLIB is due to missing handling
> in powerplay
I though powerplay was just more power states for the dpm state machines to
play with. I recall parsing ATOMBIOS pplay tables for records of (voltages/clocks
frequencies).
Maybe the future is to trust the OS kernel and perform all "low speed" 3D asic
functions there and keep only high speed 3D operations in the asic.
--
Sylvain
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_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <CAEQFVGaErupy3y+sKA+uqQPn7x0oL1T9BKWj6y8EC12Ap2-YDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-15 1:25 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
@ 2018-10-15 21:06 ` Harry Wentland
[not found] ` <bef5787e-cc8d-df35-dc55-353ed4443a8c-5C7GfCeVMHo@public.gmane.org>
1 sibling, 1 reply; 30+ messages in thread
From: Harry Wentland @ 2018-10-15 21:06 UTC (permalink / raw)
To: Mauro Rossi, Sylvain Bertrand, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Christian König
On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> Hi,
>
> reporting about some progress made during the weekend,
> thanks to Sylvain feedback & suggestions.
>
> I have rebased and updated the series on top of
> https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
>
> Here is the amd_dc_si branch:
> https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
> NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
> there, as they are not strictly needed for amd-gfx
>
> Copying also Harry, Alex, Christian and Mike in order to get some
> objective and infallible
> clues/feedbacks about blocking points and about "no care" items.
>
> Please, also big things I may have missed.
> M.
>
>> On Mon, Oct 8, 2018 at 11:23 PM <sylvain.bertrand@gmail.com> wrote:
>>
>> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it go through the
>> asic init and I managed to get a x11 display with lines kind of garbled, but
>> you can still understand easily what's on the screen.
>
> I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
> I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
> Kaveri and older")
> because on Mullins I can boot with HDMI and HDMI-to-VGA converter
>
> I was hoping for AMD DC being re-enabled for Kaveri and older,
> but I'm available to submit new version of specific patch if required.
>
I still need to find time to get through your patchset properly. Just a quick note on this. There are Kabini/Kaveri ASICs with VGA connectors in the market, which the DC code doesn't support. If someone writes it we can re-enable it by default.
Either way, you can revert that patch for your tree or use amdgpu.dc=0 as long as you're aware that VGA won't work with amdgpu on such a kernel.
Harry
>> Sylvain - ... The lines may be garbled in your driver code because,
>> if I recall properly, "line buffer" programing in dce8 is not
>> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
>> slight differences in frame buffer tiling.
>
> So the problem could be related to some kind of scan line or tiling
> buffer issue,
> at the moment the dce_resouces model is grabbed "AS IS" from DCE8
> registers/masks
>
>>
>> Sylvain - I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
>> invalid powerlevel and atombios/vbios table parsing regarding connectors.
>> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
>> current SI amdgpu code path should be "copied" in DC. It is related very
>> probably to the parsing of VBIOS/ATOMBIOS tables.
>
> 10-09 21:10:14.427 0 0 E :
> [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
> powerlevel state: 0!
>
> NOTE: the error is the result of Powerplay dependency introduced by
> using AMD DC for SI
> it's not fatal and it does not seem to affect performance in the Benchmarks
>
> DOUBT: I think that it would make sense to set "power level 0" i.e.
> the "lower state" as safe default,
> considering that powerplay smu6/hwmgr are not implemented for SI and
> smu7 CIK functions do not work,
> the AS-IS dpm is the only available option. (and it seams to be
> working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
>
>
>
>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
>
> NOTE: the warning also appears with Tonga and Vega, it is a Warning
> and does not seem to cause issues, so I would assume there is a
> default treatment in place,
> is this related to missing encoder for drm crtc or to other kind of encoder?
>
>> Sylvain - Did add SI handling in some raven firmware loader function.
>> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
>> function augmented with SI chip asic_type.
>
> I've merged the change in the (v2) branch
> https://github.com/maurossi/linux/tree/amd_dc_si
>
>> Sylvain - AFAIK, the real thing that you additionally get with DC is freesync. But
>> freesync is actually going to be interesting only if displays are able to
>> get their sync range lower bound to 0, and get significant power saving
>> thanks to this. For the use case of very low display refresh rate I don't even
>> think displayport or hdmi can do that, and be power friendly (you would have
>> to retrain the link probably each time you send a framebuffer to the display).
>
>
> If freesync is about reducing the framerate rate for power saving,
> provided that I've seen it be mentioned the first time for GCN 2nd generation,
> I'm not expecting freesync as a mandatory capability for the series.
>
>> Mauro -- dce60_resources was having too many building errors due to missing DCE6 macros
>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>
> Still to many building errors due to quite different registers naming,
> pointers to GPU register info (either in GPUopen or by means of
> listing the DCE6 vs DC8 differences),
> or keeping the DCE6 is exactly like DCE8 as register changes are
> apparently not mission critical.
>
>> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>> were used for the PoC
>
> I could not update dc/irq VBI Vertical Blank Interrupt, because i
> cannot find the corresponding IRQ register in amdgpu/dce6 registers
> headers/mask
>
> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
> +?seems trivial but who knows what is the corresponding in DCE6?
>
> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK
> +?seems trivial but who knows what is the corresponding in DCE6?
>
> NOTE: If this is the very basic VBI Vertical Blank Interrupt signal
> handling, there should be dce6 registers/masks,
> but some hint/documentation is necessary for me to find them.
>
>
>> Mauro - gfx6 may require some ad hoc initialization, skipped for the moment
>
> Are there ad hoc tiling settings which are necessary?
>
> The OpenGLES and Vulkan radv apps I've tested:
>
> Android CTS dEQP-VK only 85 tests failed over 220'000
> Toy Zombies Lite
> Sky Force Reloaded
> V1 Benchmark Pro
> GFXbench
> Antutu 3D
> Various OpenGLES demos
>
> Here I'm planning to perform also dEQP-EGL, dEQP-GLES2, dEQP-GLES3 soon,
> but feedbacks from developers are very welcome and appreciated
>
>> Mauro - Hainan specific code requires review, as some documentation and code paths
>> seem to point that famility may not have DCE6, please confirm
>
> Hainan specifics were removed and are unsupported in the new serie
> as DCE6 physical module not available in Hainan parts.
> Unless the virtual_dce modules supports atomit, but I don't think so.
>
>> Mauro - video decoding blocks code have not been touched
>
> UVD and VCE firmwares and code changes for SI were necessary before the series
> and they are unrelated to AMD DC for SI patches.
>
>> Mauro - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
>
> In amd-staging-drm-next dce_clock_source is generic, SI specifics are
> not necessary anymore.
>
>> Sylvain - It _seems_ there is not that much additional work to do in order to make it
>> properly work.
>>
>
> Ok, let's keep the momentum and continue tackle with x11 display problem
> and after that I'm runnign piglit no regression with x11 and with wayland too.
>
>> Testing on x11,wayland or other ways
>
> Any other testing tools worth a run?
> In case there is some AMD/GPUopen testing tool with unit tests, please
> let me know
> Kind regards
>
> Mauro
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <bef5787e-cc8d-df35-dc55-353ed4443a8c-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-15 21:19 ` Harry Wentland
[not found] ` <70b01042-3210-dcce-2b9a-a16754db9f10-5C7GfCeVMHo@public.gmane.org>
2018-10-16 14:48 ` Mauro Rossi
1 sibling, 1 reply; 30+ messages in thread
From: Harry Wentland @ 2018-10-15 21:19 UTC (permalink / raw)
To: Mauro Rossi, Sylvain Bertrand, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Christian König
On 2018-10-15 5:06 p.m., Harry Wentland wrote:
> On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
>> Hi,
>>
>> reporting about some progress made during the weekend,
>> thanks to Sylvain feedback & suggestions.
>>
>> I have rebased and updated the series on top of
>> https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
>>>> Here is the amd_dc_si branch:
>> https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
>> NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
>> there, as they are not strictly needed for amd-gfx
>>
What updates do you have to your original series?
If there are substantial updates can you send a v2 of your series?
If not I'll go through the v1. The branch is great for review but email patches are easier for commenting.
>> Copying also Harry, Alex, Christian and Mike in order to get some
>> objective and infallible
>> clues/feedbacks about blocking points and about "no care" items.
>>
>> Please, also big things I may have missed.
>> M.
>>
>>> On Mon, Oct 8, 2018 at 11:23 PM <sylvain.bertrand@gmail.com> wrote:
>>>
>>> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it go through the
>>> asic init and I managed to get a x11 display with lines kind of garbled, but
>>> you can still understand easily what's on the screen.
>>
>> I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
>> I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
>> Kaveri and older")
>> because on Mullins I can boot with HDMI and HDMI-to-VGA converter
>>
>> I was hoping for AMD DC being re-enabled for Kaveri and older,
>> but I'm available to submit new version of specific patch if required.
>>
>
> I still need to find time to get through your patchset properly. Just a quick note on this. There are Kabini/Kaveri ASICs with VGA connectors in the market, which the DC code doesn't support. If someone writes it we can re-enable it by default.
>
> Either way, you can revert that patch for your tree or use amdgpu.dc=0 as long as you're aware that VGA won't work with amdgpu on such a kernel.
>
> Harry
>
>>> Sylvain - ... The lines may be garbled in your driver code because,
>>> if I recall properly, "line buffer" programing in dce8 is not
>>> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
>>> slight differences in frame buffer tiling.
>>
>> So the problem could be related to some kind of scan line or tiling
>> buffer issue,
>> at the moment the dce_resouces model is grabbed "AS IS" from DCE8
>> registers/masks
>>
We should probably update the DCE6 headers and use those. Sometimes register addresses change in subtle ways and cause problems later on that are hard to spot.
>>>
>>> Sylvain - I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
>>> invalid powerlevel and atombios/vbios table parsing regarding connectors.
>>> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
>>> current SI amdgpu code path should be "copied" in DC. It is related very
>>> probably to the parsing of VBIOS/ATOMBIOS tables.
>>
>> 10-09 21:10:14.427 0 0 E :
>> [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
>> powerlevel state: 0!
>>
>> NOTE: the error is the result of Powerplay dependency introduced by
>> using AMD DC for SI
>> it's not fatal and it does not seem to affect performance in the Benchmarks
>>
>> DOUBT: I think that it would make sense to set "power level 0" i.e.
>> the "lower state" as safe default,
>> considering that powerplay smu6/hwmgr are not implemented for SI and
>> smu7 CIK functions do not work,
>> the AS-IS dpm is the only available option. (and it seams to be
>> working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
>>
I wouldn't worry about this too much for now. DC really just wants powerplay. Might make sense to just silence the error print if things seem to work otherwise.
Great work in getting things up and running with DCE6 and thanks for sending patches to get this work upstreamed.
Harry
>>
>>
>>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
>>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
>>
>> NOTE: the warning also appears with Tonga and Vega, it is a Warning
>> and does not seem to cause issues, so I would assume there is a
>> default treatment in place,
>> is this related to missing encoder for drm crtc or to other kind of encoder?
>>
>>> Sylvain - Did add SI handling in some raven firmware loader function.
>>> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
>>> function augmented with SI chip asic_type.
>>
>> I've merged the change in the (v2) branch
>> https://github.com/maurossi/linux/tree/amd_dc_si
>>
>>> Sylvain - AFAIK, the real thing that you additionally get with DC is freesync. But
>>> freesync is actually going to be interesting only if displays are able to
>>> get their sync range lower bound to 0, and get significant power saving
>>> thanks to this. For the use case of very low display refresh rate I don't even
>>> think displayport or hdmi can do that, and be power friendly (you would have
>>> to retrain the link probably each time you send a framebuffer to the display).
>>
>>
>> If freesync is about reducing the framerate rate for power saving,
>> provided that I've seen it be mentioned the first time for GCN 2nd generation,
>> I'm not expecting freesync as a mandatory capability for the series.
>>
>>> Mauro -- dce60_resources was having too many building errors due to missing DCE6 macros
>>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
>>> were used for the PoC
>>
>> Still to many building errors due to quite different registers naming,
>> pointers to GPU register info (either in GPUopen or by means of
>> listing the DCE6 vs DC8 differences),
>> or keeping the DCE6 is exactly like DCE8 as register changes are
>> apparently not mission critical.
>>
>>> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
>>> were used for the PoC
>>
>> I could not update dc/irq VBI Vertical Blank Interrupt, because i
>> cannot find the corresponding IRQ register in amdgpu/dce6 registers
>> headers/mask
>>
>> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
>> +?seems trivial but who knows what is the corresponding in DCE6?
>>
>> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK
>> +?seems trivial but who knows what is the corresponding in DCE6?
>>
>> NOTE: If this is the very basic VBI Vertical Blank Interrupt signal
>> handling, there should be dce6 registers/masks,
>> but some hint/documentation is necessary for me to find them.
>>
>>
>>> Mauro - gfx6 may require some ad hoc initialization, skipped for the moment
>>
>> Are there ad hoc tiling settings which are necessary?
>>
>> The OpenGLES and Vulkan radv apps I've tested:
>>
>> Android CTS dEQP-VK only 85 tests failed over 220'000
>> Toy Zombies Lite
>> Sky Force Reloaded
>> V1 Benchmark Pro
>> GFXbench
>> Antutu 3D
>> Various OpenGLES demos
>>
>> Here I'm planning to perform also dEQP-EGL, dEQP-GLES2, dEQP-GLES3 soon,
>> but feedbacks from developers are very welcome and appreciated
>>
>>> Mauro - Hainan specific code requires review, as some documentation and code paths
>>> seem to point that famility may not have DCE6, please confirm
>>
>> Hainan specifics were removed and are unsupported in the new serie
>> as DCE6 physical module not available in Hainan parts.
>> Unless the virtual_dce modules supports atomit, but I don't think so.
>>
>>> Mauro - video decoding blocks code have not been touched
>>
>> UVD and VCE firmwares and code changes for SI were necessary before the series
>> and they are unrelated to AMD DC for SI patches.
>>
>>> Mauro - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
>>
>> In amd-staging-drm-next dce_clock_source is generic, SI specifics are
>> not necessary anymore.
>>
>>> Sylvain - It _seems_ there is not that much additional work to do in order to make it
>>> properly work.
>>>
>>
>> Ok, let's keep the momentum and continue tackle with x11 display problem
>> and after that I'm runnign piglit no regression with x11 and with wayland too.
>>
>>> Testing on x11,wayland or other ways
>>
>> Any other testing tools worth a run?
>> In case there is some AMD/GPUopen testing tool with unit tests, please
>> let me know
>> Kind regards
>>
>> Mauro
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <70b01042-3210-dcce-2b9a-a16754db9f10-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-16 12:20 ` Mauro Rossi
0 siblings, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-16 12:20 UTC (permalink / raw)
To: Harry Wentland
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Sylvain Bertrand,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Christian König
Hi Harry,
thanks a lot for response,
On Mon, Oct 15, 2018 at 11:19 PM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2018-10-15 5:06 p.m., Harry Wentland wrote:
> > On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> >> Hi,
> >>
> >> reporting about some progress made during the weekend,
> >> thanks to Sylvain feedback & suggestions.
> >>
> >> I have rebased and updated the series on top of
> >> https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
> >>>> Here is the amd_dc_si branch:
> >> https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
> >> NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
> >> there, as they are not strictly needed for amd-gfx
> >>
>
>
> What updates do you have to your original series?
>
> If there are substantial updates can you send a v2 of your series?
The new v2 series is rebased on amd-staging-drm-next with following benefits:
- dce_clocks chipset families cases are not required anymore
- dcmu fw load for DCN1 has some SI cases added
- it is ready to be applied in amd-staging-drm-next
Not much changes compared to v1, but I'm about to submit v2 very soon.
>
> If not I'll go through the v1. The branch is great for review but email patches are easier for commenting.
This morning I've launched a build on v2 series, on
amd-staging-drm-next branch rebased on top of 4.19rc8
just to test it builds fine.
I'm sending the v2 series this evening and review may proceed on v2
amd-staging-drm-next context.
Mauro
>
>
> >> Copying also Harry, Alex, Christian and Mike in order to get some
> >> objective and infallible
> >> clues/feedbacks about blocking points and about "no care" items.
> >>
> >> Please, also big things I may have missed.
> >> M.
> >>
> >>> On Mon, Oct 8, 2018 at 11:23 PM <sylvain.bertrand@gmail.com> wrote:
> >>>
> >>> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it go through the
> >>> asic init and I managed to get a x11 display with lines kind of garbled, but
> >>> you can still understand easily what's on the screen.
> >>
> >> I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
> >> I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
> >> Kaveri and older")
> >> because on Mullins I can boot with HDMI and HDMI-to-VGA converter
> >>
> >> I was hoping for AMD DC being re-enabled for Kaveri and older,
> >> but I'm available to submit new version of specific patch if required.
> >>
> >
> > I still need to find time to get through your patchset properly. Just a quick note on this. There are Kabini/Kaveri ASICs with VGA connectors in the market, which the DC code doesn't support. If someone writes it we can re-enable it by default.
> >
> > Either way, you can revert that patch for your tree or use amdgpu.dc=0 as long as you're aware that VGA won't work with amdgpu on such a kernel.
> >
> > Harry
> >
> >>> Sylvain - ... The lines may be garbled in your driver code because,
> >>> if I recall properly, "line buffer" programing in dce8 is not
> >>> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
> >>> slight differences in frame buffer tiling.
> >>
> >> So the problem could be related to some kind of scan line or tiling
> >> buffer issue,
> >> at the moment the dce_resouces model is grabbed "AS IS" from DCE8
> >> registers/masks
> >>
>
> We should probably update the DCE6 headers and use those. Sometimes register addresses change in subtle ways and cause problems later on that are hard to spot.
>
> >>>
> >>> Sylvain - I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
> >>> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> >>> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
> >>> current SI amdgpu code path should be "copied" in DC. It is related very
> >>> probably to the parsing of VBIOS/ATOMBIOS tables.
> >>
> >> 10-09 21:10:14.427 0 0 E :
> >> [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
> >> powerlevel state: 0!
> >>
> >> NOTE: the error is the result of Powerplay dependency introduced by
> >> using AMD DC for SI
> >> it's not fatal and it does not seem to affect performance in the Benchmarks
> >>
> >> DOUBT: I think that it would make sense to set "power level 0" i.e.
> >> the "lower state" as safe default,
> >> considering that powerplay smu6/hwmgr are not implemented for SI and
> >> smu7 CIK functions do not work,
> >> the AS-IS dpm is the only available option. (and it seams to be
> >> working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
> >>
>
> I wouldn't worry about this too much for now. DC really just wants powerplay. Might make sense to just silence the error print if things seem to work otherwise.
>
> Great work in getting things up and running with DCE6 and thanks for sending patches to get this work upstreamed.
>
> Harry
>
> >>
> >>
> >>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
> >>> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
> >>
> >> NOTE: the warning also appears with Tonga and Vega, it is a Warning
> >> and does not seem to cause issues, so I would assume there is a
> >> default treatment in place,
> >> is this related to missing encoder for drm crtc or to other kind of encoder?
> >>
> >>> Sylvain - Did add SI handling in some raven firmware loader function.
> >>> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
> >>> function augmented with SI chip asic_type.
> >>
> >> I've merged the change in the (v2) branch
> >> https://github.com/maurossi/linux/tree/amd_dc_si
> >>
> >>> Sylvain - AFAIK, the real thing that you additionally get with DC is freesync. But
> >>> freesync is actually going to be interesting only if displays are able to
> >>> get their sync range lower bound to 0, and get significant power saving
> >>> thanks to this. For the use case of very low display refresh rate I don't even
> >>> think displayport or hdmi can do that, and be power friendly (you would have
> >>> to retrain the link probably each time you send a framebuffer to the display).
> >>
> >>
> >> If freesync is about reducing the framerate rate for power saving,
> >> provided that I've seen it be mentioned the first time for GCN 2nd generation,
> >> I'm not expecting freesync as a mandatory capability for the series.
> >>
> >>> Mauro -- dce60_resources was having too many building errors due to missing DCE6 macros
> >>> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
> >>> were used for the PoC
> >>
> >> Still to many building errors due to quite different registers naming,
> >> pointers to GPU register info (either in GPUopen or by means of
> >> listing the DCE6 vs DC8 differences),
> >> or keeping the DCE6 is exactly like DCE8 as register changes are
> >> apparently not mission critical.
> >>
> >>> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
> >>> were used for the PoC
> >>
> >> I could not update dc/irq VBI Vertical Blank Interrupt, because i
> >> cannot find the corresponding IRQ register in amdgpu/dce6 registers
> >> headers/mask
> >>
> >> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
> >> +?seems trivial but who knows what is the corresponding in DCE6?
> >>
> >> -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK
> >> +?seems trivial but who knows what is the corresponding in DCE6?
> >>
> >> NOTE: If this is the very basic VBI Vertical Blank Interrupt signal
> >> handling, there should be dce6 registers/masks,
> >> but some hint/documentation is necessary for me to find them.
> >>
> >>
> >>> Mauro - gfx6 may require some ad hoc initialization, skipped for the moment
> >>
> >> Are there ad hoc tiling settings which are necessary?
> >>
> >> The OpenGLES and Vulkan radv apps I've tested:
> >>
> >> Android CTS dEQP-VK only 85 tests failed over 220'000
> >> Toy Zombies Lite
> >> Sky Force Reloaded
> >> V1 Benchmark Pro
> >> GFXbench
> >> Antutu 3D
> >> Various OpenGLES demos
> >>
> >> Here I'm planning to perform also dEQP-EGL, dEQP-GLES2, dEQP-GLES3 soon,
> >> but feedbacks from developers are very welcome and appreciated
> >>
> >>> Mauro - Hainan specific code requires review, as some documentation and code paths
> >>> seem to point that famility may not have DCE6, please confirm
> >>
> >> Hainan specifics were removed and are unsupported in the new serie
> >> as DCE6 physical module not available in Hainan parts.
> >> Unless the virtual_dce modules supports atomit, but I don't think so.
> >>
> >>> Mauro - video decoding blocks code have not been touched
> >>
> >> UVD and VCE firmwares and code changes for SI were necessary before the series
> >> and they are unrelated to AMD DC for SI patches.
> >>
> >>> Mauro - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
> >>
> >> In amd-staging-drm-next dce_clock_source is generic, SI specifics are
> >> not necessary anymore.
> >>
> >>> Sylvain - It _seems_ there is not that much additional work to do in order to make it
> >>> properly work.
> >>>
> >>
> >> Ok, let's keep the momentum and continue tackle with x11 display problem
> >> and after that I'm runnign piglit no regression with x11 and with wayland too.
> >>
> >>> Testing on x11,wayland or other ways
> >>
> >> Any other testing tools worth a run?
> >> In case there is some AMD/GPUopen testing tool with unit tests, please
> >> let me know
> >> Kind regards
> >>
> >> Mauro
> >>
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RFC] drm/amd/display: add SI support to AMD DC
[not found] ` <bef5787e-cc8d-df35-dc55-353ed4443a8c-5C7GfCeVMHo@public.gmane.org>
2018-10-15 21:19 ` Harry Wentland
@ 2018-10-16 14:48 ` Mauro Rossi
1 sibling, 0 replies; 30+ messages in thread
From: Mauro Rossi @ 2018-10-16 14:48 UTC (permalink / raw)
To: Harry Wentland
Cc: alexander.deucher-5C7GfCeVMHo, Mike Lothian, Sylvain Bertrand,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Christian König
Hi Harry,
in this thread some of the coding changes with open points,
as a checklist/track for review of upcoming (v2) patches.
M.
On Mon, Oct 15, 2018 at 11:06 PM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2018-10-14 5:47 p.m., Mauro Rossi wrote:
> > Hi,
> >
> > reporting about some progress made during the weekend,
> > thanks to Sylvain feedback & suggestions.
> >
> > I have rebased and updated the series on top of
> > https://cgit.freedesktop.org/~agd5f/linux/?h=amd-staging-drm-next
> >
> > Here is the amd_dc_si branch:
> > https://github.com/maurossi/linux/tree/amd_dc_si (uploading)
> > NOTE: arch/x86/kernel/tsc.c changes for 4K display modes are not
> > there, as they are not strictly needed for amd-gfx
> >
> > Copying also Harry, Alex, Christian and Mike in order to get some
> > objective and infallible
> > clues/feedbacks about blocking points and about "no care" items.
> >
> > Please, also big things I may have missed.
> > M.
> >
> >> On Mon, Oct 8, 2018 at 11:23 PM <sylvain.bertrand@gmail.com> wrote:
> >>
> >> Sylvain - I did hack a bit your patch set on amd-staging-drm-next to make it go through the
> >> asic init and I managed to get a x11 display with lines kind of garbled, but
> >> you can still understand easily what's on the screen.
> >
> > I forgot to mention that since I'm gorgeously trying AMD DC also on Mullins
> > I have reverted d9fda24 (""drm/amdgpu: Don't default to DC support for
> > Kaveri and older")
> > because on Mullins I can boot with HDMI and HDMI-to-VGA converter
> >
> > I was hoping for AMD DC being re-enabled for Kaveri and older,
> > but I'm available to submit new version of specific patch if required.
> >
>
> I still need to find time to get through your patchset properly. Just a quick note on this. There are Kabini/Kaveri ASICs with VGA connectors in the market, which the DC code doesn't support. If someone writes it we can re-enable it by default.
>
> Either way, you can revert that patch for your tree or use amdgpu.dc=0 as long as you're aware that VGA won't work with amdgpu on such a kernel.
>
> Harry
At the moment I have reverted commit disabling DC for Kaveri, as I'm
using Acer ES1-521 which has HDMI output (with an HDMI-to-VGA
converter)
If it's not too complex, I could give it a try to have Kaveri working
for laptops with VGA output,
but from your judgment how complex is this task and which code paths
need to be touched?
If it is achievable by me, why not?
>
> >> Sylvain - ... The lines may be garbled in your driver code because,
> >> if I recall properly, "line buffer" programing in dce8 is not
> >> the same than in dce6 (look for registers with the "LB" abbreviation). Or some
> >> slight differences in frame buffer tiling.
> >
> > So the problem could be related to some kind of scan line or tiling
> > buffer issue,
> > at the moment the dce_resouces model is grabbed "AS IS" from DCE8
> > registers/masks
> >
I will check visually this evening the x11 line artifacts on HD7750 Cape Verde,
do you have any suggestion on top of Sylvain B. analysis?
> >>
> >> Sylvain - I checked the kernel log, and like you said, I got errors in DM_PPLIB due to an
> >> invalid powerlevel and atombios/vbios table parsing regarding connectors.
> >> general dpm is in amdgpu(no DC) for SI, it means the DCE related dpm part in
> >> current SI amdgpu code path should be "copied" in DC. It is related very
> >> probably to the parsing of VBIOS/ATOMBIOS tables.
> >
> > 10-09 21:10:14.427 0 0 E :
> > [drm:dm_pp_get_static_clocks [amdgpu]] *ERROR* DM_PPLIB: invalid
> > powerlevel state: 0!
> >
> > NOTE: the error is the result of Powerplay dependency introduced by
> > using AMD DC for SI
> > it's not fatal and it does not seem to affect performance in the Benchmarks
> >
> > DOUBT: I think that it would make sense to set "power level 0" i.e.
> > the "lower state" as safe default,
> > considering that powerplay smu6/hwmgr are not implemented for SI and
> > smu7 CIK functions do not work,
> > the AS-IS dpm is the only available option. (and it seams to be
> > working, looking at the framerates 250-280 in the V1 Vulkan benchmark)
> >
> >
> >
> >> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
> >> 10-09 21:10:14.427 0 0 W [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4!
> >
> > NOTE: the warning also appears with Tonga and Vega, it is a Warning
> > and does not seem to cause issues, so I would assume there is a
> > default treatment in place,
> > is this related to missing encoder for drm crtc or to other kind of encoder?
> >
Are these Warnings a problem or just Warnings with mid-low severity?
> >> Sylvain - Did add SI handling in some raven firmware loader function.
> >> In drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c, "load_dmcu_fw"
> >> function augmented with SI chip asic_type.
> >
> > I've merged the change in the (v2) branch
> > https://github.com/maurossi/linux/tree/amd_dc_si
> >
> >> Sylvain - AFAIK, the real thing that you additionally get with DC is freesync. But
> >> freesync is actually going to be interesting only if displays are able to
> >> get their sync range lower bound to 0, and get significant power saving
> >> thanks to this. For the use case of very low display refresh rate I don't even
> >> think displayport or hdmi can do that, and be power friendly (you would have
> >> to retrain the link probably each time you send a framebuffer to the display).
> >
> >
> > If freesync is about reducing the framerate rate for power saving,
> > provided that I've seen it be mentioned the first time for GCN 2nd generation,
> > I'm not expecting freesync as a mandatory capability for the series.
> >
> >> Mauro -- dce60_resources was having too many building errors due to missing DCE6 macros
> >> in order to temporarily overcome the problem dce_8_0_{d,sh_mask}.h headers
> >> were used for the PoC
> >
I also think that using and completing the dce_6_0_{d,sh_mask}.h
headers when possible is the best way,
also to be able to control and keep changes separated from dce80 path,
while for unmatching items between DCE8 and DCE6 the dce60_resources.c
code is worth a review to spot
problems.
There are tenths of CRTCx registers named differently between DCE6 and DCE8.
> > Still to many building errors due to quite different registers naming,
> > pointers to GPU register info (either in GPUopen or by means of
> > listing the DCE6 vs DC8 differences),
> > or keeping the DCE6 is exactly like DCE8 as register changes are
> > apparently not mission critical.
> >
> >> Mauro - dc/irq suffered the same problem dce_8_0_{d,sh_mask}.h headers
> >> were used for the PoC
> >
> > I could not update dc/irq VBI Vertical Blank Interrupt, because i
> > cannot find the corresponding IRQ register in amdgpu/dce6 registers
> > headers/mask
> >
> > -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
> > +?seems trivial but who knows what is the corresponding in DCE6?
> >
> > -CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK
> > +?seems trivial but who knows what is the corresponding in DCE6?
> >
> > NOTE: If this is the very basic VBI Vertical Blank Interrupt signal
> > handling, there should be dce6 registers/masks,
> > but some hint/documentation is necessary for me to find them.
> >
The identification of the vblank interrupt register to be used in DCE6
should suffice to use the dce_6_0_{d,sh_mask}.h headers,
this should solve the dc/irq buidling errors.
> >
> >> Mauro - gfx6 may require some ad hoc initialization, skipped for the moment
> >
> > Are there ad hoc tiling settings which are necessary?
This part is way beyond my knowledge, as it involves the OpenGL
implementation and compliance,
may we skip gfx6 specifics or are there changes necessary?
> >
> > The OpenGLES and Vulkan radv apps I've tested:
> >
> > Android CTS dEQP-VK only 85 tests failed over 220'000
> > Toy Zombies Lite
> > Sky Force Reloaded
> > V1 Benchmark Pro
> > GFXbench
> > Antutu 3D
> > Various OpenGLES demos
> >
> > Here I'm planning to perform also dEQP-EGL, dEQP-GLES2, dEQP-GLES3 soon,
> > but feedbacks from developers are very welcome and appreciated
> >
> >> Mauro - Hainan specific code requires review, as some documentation and code paths
> >> seem to point that famility may not have DCE6, please confirm
> >
> > Hainan specifics were removed and are unsupported in the new serie
> > as DCE6 physical module not available in Hainan parts.
> > Unless the virtual_dce modules supports atomit, but I don't think so.
> >
Is it correct that even with virtual DCE block we would not get
atomic, so Hainan is to be skipped?
I forgot to say this before, Hainan is not supported in (v2) patches
and the commit messages for (v2) patches have been updated
accordingly.
> >> Mauro - video decoding blocks code have not been touched
> >
> > UVD and VCE firmwares and code changes for SI were necessary before the series
> > and they are unrelated to AMD DC for SI patches.
For Harry, Alex, do you have plans to add support to UVD, VCE firmware for SI?
In any case they seem unrelated to DC code paths.
> >
> >> Mauro - dc/dce/dce_clock_source.{c,h} may be missing some SI/DCE6 specifics
> >
> > In amd-staging-drm-next dce_clock_source is generic, SI specifics are
> > not necessary anymore.
> >
> >> Sylvain - It _seems_ there is not that much additional work to do in order to make it
> >> properly work.
> >>
> >
> > Ok, let's keep the momentum and continue tackle with x11 display problem
> > and after that I'm runnign piglit no regression with x11 and with wayland too.
> >
> >> Testing on x11,wayland or other ways
> >
> > Any other testing tools worth a run?
> > In case there is some AMD/GPUopen testing tool with unit tests, please
> > let me know
> > Kind regards
> >
> > Mauro
> >
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2018-10-16 14:48 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-08 2:23 [RFC] drm/amd/display: add SI support to AMD DC Mauro Rossi
[not found] ` <20181008022344.10247-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-08 2:23 ` [PATCH 01/10] drm/amd/display: add asics info for SI parts Mauro Rossi
2018-10-08 2:23 ` [PATCH 02/10] drm/amd/display: dc/dce: add DCE6 support Mauro Rossi
2018-10-08 2:23 ` [PATCH 03/10] drm/amd/display: dc/core: " Mauro Rossi
2018-10-08 2:23 ` [PATCH 04/10] drm/amd/display: dc/bios: add support for DCE6 Mauro Rossi
2018-10-08 2:23 ` [PATCH 05/10] drm/amd/display: dc/gpio: " Mauro Rossi
2018-10-08 2:23 ` [PATCH 06/10] drm/amd/display: dc/i2caux: " Mauro Rossi
2018-10-08 2:23 ` [PATCH 07/10] drm/amd/display: dc/irq: " Mauro Rossi
2018-10-08 2:23 ` [PATCH 08/10] drm/amd/display: amdgpu_dm: add SI support Mauro Rossi
2018-10-08 2:23 ` [PATCH 09/10] drm/amdgpu: enable DC support for SI parts Mauro Rossi
2018-10-08 2:23 ` [PATCH 10/10] drm/amd/display: enable SI support in the Kconfig Mauro Rossi
2018-10-08 11:00 ` [RFC] drm/amd/display: add SI support to AMD DC Mike Lothian
[not found] ` <CAHbf0-HK4W4xE-hOJPiwr8zhzuuG2GobCTyHHik3mwe1-9_BmQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-08 11:22 ` Mauro Rossi
[not found] ` <CAEQFVGbWWy7jmcaserbMwANNHei90WX+1AvOfDAY8J=BcsyCrg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-08 11:29 ` Christian König
[not found] ` <7a8b5d6d-82c2-2b98-b2b2-098baf095aef-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-10-08 12:16 ` Mike Lothian
[not found] ` <CAHbf0-FB2GV18igVo-8MHcVGL89KZoXn+O2B4asoe5R4RbgCVw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-08 15:47 ` Deucher, Alexander
2018-10-08 12:04 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 12:32 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 17:02 ` Mauro Rossi
[not found] ` <CAEQFVGahx4U+52uKu20_q0iCPrdzeW8G+viS7p2LJtgF61bf6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-08 20:17 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-08 21:22 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-14 21:47 ` Mauro Rossi
[not found] ` <CAEQFVGaErupy3y+sKA+uqQPn7x0oL1T9BKWj6y8EC12Ap2-YDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-15 1:25 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-15 5:28 ` Mauro Rossi
[not found] ` <CAEQFVGbB_ezGSGwPu2Ka-4rY9RjB_rJvPL8ZCEG-_rfXxOEN-A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-10-15 12:45 ` sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w
2018-10-15 17:53 ` Deucher, Alexander
2018-10-15 21:06 ` Harry Wentland
[not found] ` <bef5787e-cc8d-df35-dc55-353ed4443a8c-5C7GfCeVMHo@public.gmane.org>
2018-10-15 21:19 ` Harry Wentland
[not found] ` <70b01042-3210-dcce-2b9a-a16754db9f10-5C7GfCeVMHo@public.gmane.org>
2018-10-16 12:20 ` Mauro Rossi
2018-10-16 14:48 ` Mauro Rossi
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