* [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
@ 2018-10-16 22:46 Daniele Ceraolo Spurio
2018-10-16 22:46 ` [PATCH v2 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-16 22:46 UTC (permalink / raw)
To: intel-gfx
The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
FW and then return, so waiting on the H2G is not enough to guarantee
GuC is done.
When all the processing is done, GuC writes 0 to scratch register 14,
so we can poll on that. Note that GuC does not ensure that the value
in the register is different from 0 while the action is in progress
so we need to take care of that ourselves as well.
v2: improve comment, return early on GuC error and improve error
message (Michal)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_guc.c | 42 +++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++++
2 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 230aea69385d..4c61eb94527a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -521,6 +521,44 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
+/*
+ * The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC FW and
+ * then return, so waiting on the H2G is not enough to guarantee GuC is done.
+ * When all the processing is done, GuC writes INTEL_GUC_SLEEP_STATE_SUCCESS to
+ * scratch register 14, so we can poll on that. Note that GuC does not ensure
+ * that the value in the register is different from
+ * INTEL_GUC_SLEEP_STATE_SUCCESS while the action is in progress so we need to
+ * take care of that ourselves as well.
+ */
+static int guc_sleep_state_action(struct intel_guc *guc,
+ const u32 *action, u32 len)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret;
+ u32 status;
+
+ I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
+
+ ret = intel_guc_send(guc, action, len);
+ if (ret)
+ return ret;
+
+ ret = __intel_wait_for_register(dev_priv, SOFT_SCRATCH(14),
+ INTEL_GUC_SLEEP_STATE_INVALID_MASK,
+ 0, 0, 10, &status);
+ if (ret)
+ return ret;
+
+ if (status != INTEL_GUC_SLEEP_STATE_SUCCESS) {
+ DRM_ERROR("GuC failed to change sleep state. "
+ "action=0x%x, err=%u\n",
+ action[0], status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
/**
* intel_guc_suspend() - notify GuC entering suspend state
* @guc: the guc
@@ -533,7 +571,7 @@ int intel_guc_suspend(struct intel_guc *guc)
intel_guc_ggtt_offset(guc, guc->shared_data)
};
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
+ return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
}
/**
@@ -571,7 +609,7 @@ int intel_guc_resume(struct intel_guc *guc)
intel_guc_ggtt_offset(guc, guc->shared_data)
};
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
+ return guc_sleep_state_action(guc, data, ARRAY_SIZE(data));
}
/**
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..1a853cc627e3 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -687,6 +687,13 @@ enum intel_guc_report_status {
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
};
+enum intel_guc_sleep_state_status {
+ INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
+ INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
+ INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
+};
+#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
+
#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
--
2.19.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX enable GuC for CI
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
@ 2018-10-16 22:46 ` Daniele Ceraolo Spurio
2018-10-16 23:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-16 22:46 UTC (permalink / raw)
To: intel-gfx
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..c681537bcb92 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
2.19.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
2018-10-16 22:46 ` [PATCH v2 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
@ 2018-10-16 23:28 ` Patchwork
2018-10-16 23:53 ` ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-10-16 23:28 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51088/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8971200da2a4 drm/i915/guc: fix GuC suspend/resume
-:102: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#102: FILE: drivers/gpu/drm/i915/intel_guc_fwif.h:695:
+};
+#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
total: 0 errors, 0 warnings, 1 checks, 73 lines checked
6e16f86cee15 HAX enable GuC for CI
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
2018-10-16 22:46 ` [PATCH v2 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
2018-10-16 23:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume Patchwork
@ 2018-10-16 23:53 ` Patchwork
2018-10-17 16:40 ` [PATCH v2 1/2] " Michal Wajdeczko
2018-11-26 14:51 ` Michal Wajdeczko
4 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2018-10-16 23:53 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume
URL : https://patchwork.freedesktop.org/series/51088/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4991 -> Patchwork_10482 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10482 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10482, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51088/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10482:
=== IGT changes ===
==== Possible regressions ====
igt@drv_selftest@live_guc:
fi-kbl-7567u: PASS -> DMESG-WARN
fi-skl-gvtdvm: PASS -> DMESG-WARN
fi-skl-iommu: PASS -> DMESG-WARN
fi-skl-6260u: PASS -> DMESG-WARN
fi-bxt-dsi: PASS -> DMESG-WARN
fi-skl-6700k2: PASS -> DMESG-WARN
fi-whl-u: PASS -> DMESG-WARN
fi-skl-6770hq: PASS -> DMESG-WARN
fi-kbl-8809g: PASS -> DMESG-WARN
fi-kbl-x1275: PASS -> DMESG-WARN
fi-bxt-j4205: PASS -> DMESG-WARN
fi-skl-6700hq: PASS -> DMESG-WARN
fi-cfl-s3: PASS -> DMESG-WARN
fi-cfl-8109u: PASS -> DMESG-WARN
fi-kbl-7500u: PASS -> DMESG-WARN
fi-cfl-8700k: PASS -> DMESG-WARN
igt@drv_selftest@live_hangcheck:
fi-kbl-r: PASS -> INCOMPLETE
fi-whl-u: PASS -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10482 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-ilk-650: PASS -> DMESG-WARN (fdo#106387)
igt@pm_rpm@module-reload:
fi-skl-6600u: PASS -> INCOMPLETE (fdo#107807)
==== Possible fixes ====
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS
fi-icl-u2: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS +1
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
== Participating hosts (40 -> 37) ==
Additional (1): fi-kbl-guc
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-snb-2520m
== Build changes ==
* Linux: CI_DRM_4991 -> Patchwork_10482
CI_DRM_4991: c4fc9e99d838c9b9a3f6bdb6e609b0cf820f9aef @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4682: 0ac43db33e116b546e5704fe0b4dde21f391e09c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10482: 6e16f86cee15acffb8e4e2cba6abedbca631630b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6e16f86cee15 HAX enable GuC for CI
8971200da2a4 drm/i915/guc: fix GuC suspend/resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10482/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2018-10-16 23:53 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-10-17 16:40 ` Michal Wajdeczko
2018-10-17 20:32 ` Chris Wilson
2018-11-26 14:51 ` Michal Wajdeczko
4 siblings, 1 reply; 15+ messages in thread
From: Michal Wajdeczko @ 2018-10-17 16:40 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
> FW and then return, so waiting on the H2G is not enough to guarantee
> GuC is done.
> When all the processing is done, GuC writes 0 to scratch register 14,
> so we can poll on that. Note that GuC does not ensure that the value
> in the register is different from 0 while the action is in progress
> so we need to take care of that ourselves as well.
>
> v2: improve comment, return early on GuC error and improve error
> message (Michal)
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Michal
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
2018-10-17 16:40 ` [PATCH v2 1/2] " Michal Wajdeczko
@ 2018-10-17 20:32 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2018-10-17 20:32 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Michal Wajdeczko, intel-gfx
Quoting Michal Wajdeczko (2018-10-17 17:40:50)
> On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
> > The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
> > FW and then return, so waiting on the H2G is not enough to guarantee
> > GuC is done.
> > When all the processing is done, GuC writes 0 to scratch register 14,
> > so we can poll on that. Note that GuC does not ensure that the value
> > in the register is different from 0 while the action is in progress
> > so we need to take care of that ourselves as well.
> >
> > v2: improve comment, return early on GuC error and improve error
> > message (Michal)
> >
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
>
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Applied, thanks for the fix and review.
-Chris
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2018-10-17 16:40 ` [PATCH v2 1/2] " Michal Wajdeczko
@ 2018-11-26 14:51 ` Michal Wajdeczko
2018-11-27 19:34 ` Daniele Ceraolo Spurio
4 siblings, 1 reply; 15+ messages in thread
From: Michal Wajdeczko @ 2018-11-26 14:51 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
/snip/
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 8382d591c784..1a853cc627e3 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -687,6 +687,13 @@ enum intel_guc_report_status {
> INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
> };
> +enum intel_guc_sleep_state_status {
> + INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
> + INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
> + INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
> +};
btw, it used to be 0,1,2 but from some time fw defines above as:
INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3,
Michal
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
2018-11-26 14:51 ` Michal Wajdeczko
@ 2018-11-27 19:34 ` Daniele Ceraolo Spurio
2018-11-28 19:55 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 15+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-11-27 19:34 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 26/11/2018 06:51, Michal Wajdeczko wrote:
> On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
> /snip/
>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 8382d591c784..1a853cc627e3 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -687,6 +687,13 @@ enum intel_guc_report_status {
>> INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
>> };
>> +enum intel_guc_sleep_state_status {
>> + INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
>> + INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
>> + INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
>> +};
>
> btw, it used to be 0,1,2 but from some time fw defines above as:
>
> INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
> INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
> INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3,
>
> Michal
Yeah, I think I had already mentioned in some reply that the newer
firmware does suspend/resume differently, but I haven't looked at the
details. I'm not even sure if polling the register will still be required.
Daniele
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume
2018-11-27 19:34 ` Daniele Ceraolo Spurio
@ 2018-11-28 19:55 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 15+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-11-28 19:55 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 27/11/2018 11:34, Daniele Ceraolo Spurio wrote:
>
>
> On 26/11/2018 06:51, Michal Wajdeczko wrote:
>> On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
>> <daniele.ceraolospurio@intel.com> wrote:
>>
>> /snip/
>>
>>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>>> index 8382d591c784..1a853cc627e3 100644
>>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>>> @@ -687,6 +687,13 @@ enum intel_guc_report_status {
>>> INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
>>> };
>>> +enum intel_guc_sleep_state_status {
>>> + INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
>>> + INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
>>> + INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
>>> +};
>>
>> btw, it used to be 0,1,2 but from some time fw defines above as:
>>
>> INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
>> INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
>> INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3,
>>
>> Michal
>
> Yeah, I think I had already mentioned in some reply that the newer
> firmware does suspend/resume differently, but I haven't looked at the
> details. I'm not even sure if polling the register will still be required.
>
> Daniele
I've confirmed with the GuC team that the differences are mostly
internal to GuC and the only change from the kernel perspective is that
the enum values have changed. We still need to do the polling, but I
guess we'll be able to init the register to zero since all the return
values are > 0.
Daniele
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX: Enable GuC for CI
2018-10-17 20:05 [PATCH v2 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
@ 2018-10-17 20:05 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-10-17 20:05 UTC (permalink / raw)
To: intel-gfx
GuC is disabled by default. Enable it.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX enable GuC for CI
2018-06-18 11:18 [PATCH v2 1/2] drm/i915/guc: Print CTL params passed to Guc Michal Wajdeczko
@ 2018-06-18 11:18 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-06-18 11:18 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe046..3e4e128 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX enable GuC for CI
2018-06-18 10:39 [PATCH v2 1/2] drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init Michal Wajdeczko
@ 2018-06-18 10:39 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-06-18 10:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe046..3e4e128 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX: Enable GuC for CI
2018-03-02 13:37 [PATCH v2 1/2] drm/i915/huc: Mark firmware as failed on auth failure Michal Wajdeczko
@ 2018-03-02 13:37 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-03-02 13:37 UTC (permalink / raw)
To: intel-gfx
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8e25474..fb80e86 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX: Enable GuC for CI
2018-03-02 11:15 [PATCH v2 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
@ 2018-03-02 11:15 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-03-02 11:15 UTC (permalink / raw)
To: intel-gfx
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e5bf0d3..b57c415 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/2] HAX: Enable GuC for CI
2018-02-20 22:57 [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure Michal Wajdeczko
@ 2018-02-20 22:57 ` Michal Wajdeczko
0 siblings, 0 replies; 15+ messages in thread
From: Michal Wajdeczko @ 2018-02-20 22:57 UTC (permalink / raw)
To: intel-gfx
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 75d0eb9..c577193 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-11-28 19:55 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-16 22:46 [PATCH v2 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
2018-10-16 22:46 ` [PATCH v2 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
2018-10-16 23:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/i915/guc: fix GuC suspend/resume Patchwork
2018-10-16 23:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-10-17 16:40 ` [PATCH v2 1/2] " Michal Wajdeczko
2018-10-17 20:32 ` Chris Wilson
2018-11-26 14:51 ` Michal Wajdeczko
2018-11-27 19:34 ` Daniele Ceraolo Spurio
2018-11-28 19:55 ` Daniele Ceraolo Spurio
-- strict thread matches above, loose matches on Subject: below --
2018-10-17 20:05 [PATCH v2 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-17 20:05 ` [PATCH v2 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-06-18 11:18 [PATCH v2 1/2] drm/i915/guc: Print CTL params passed to Guc Michal Wajdeczko
2018-06-18 11:18 ` [PATCH v2 2/2] HAX enable GuC for CI Michal Wajdeczko
2018-06-18 10:39 [PATCH v2 1/2] drm/i915/uc: Fetch GuC/HuC firmwares from guc/huc specific init Michal Wajdeczko
2018-06-18 10:39 ` [PATCH v2 2/2] HAX enable GuC for CI Michal Wajdeczko
2018-03-02 13:37 [PATCH v2 1/2] drm/i915/huc: Mark firmware as failed on auth failure Michal Wajdeczko
2018-03-02 13:37 ` [PATCH v2 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-03-02 11:15 [PATCH v2 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
2018-03-02 11:15 ` [PATCH v2 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-02-20 22:57 [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure Michal Wajdeczko
2018-02-20 22:57 ` [PATCH v2 2/2] HAX: Enable GuC for CI Michal Wajdeczko
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