All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bjorn Helgaas <helgaas@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: honghui.zhang@mediatek.com, youlin.pei@mediatek.com,
	devicetree@vger.kernel.org, ulf.hansson@linaro.org,
	ryder.lee@mediatek.com, marc.zyngier@arm.com,
	linux-pci@vger.kernel.org, jianjun.wang@mediatek.com,
	linux-kernel@vger.kernel.org, yt.shen@mediatek.com,
	matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org,
	bhelgaas@google.com, yingjoe.chen@mediatek.com,
	eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 2/9] PCI: Using PCI configuration space header type instead of class type to assign resource
Date: Wed, 17 Oct 2018 08:22:51 -0500	[thread overview]
Message-ID: <20181017132251.GG5906@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <20181016145355.GB16390@e107981-ln.cambridge.arm.com>

On Tue, Oct 16, 2018 at 03:53:55PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zhang@mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > 
> > The PCI configuration space header type defines the layout of the rest
> > of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9) while the
> > resource assignment is based on the configuration space layout instead
> > of its class type. Using configuration space header type instead of
> > class type for the resource assignment.
> > 
> > Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> >  drivers/pci/pci.c       |  3 +--
> >  drivers/pci/probe.c     |  3 ---
> >  drivers/pci/setup-bus.c | 20 ++++++++++----------
> >  3 files changed, 11 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index 29ff961..7d379ca 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -5908,8 +5908,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
> >  	 * to enable the kernel to reassign new resource
> >  	 * window later on.
> >  	 */
> > -	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
> > -	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
> > +	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
> >  		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
> >  			r = &dev->resource[i];
> >  			if (!(r->flags & IORESOURCE_MEM))
> > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> > index ec78400..29a35c1 100644
> > --- a/drivers/pci/probe.c
> > +++ b/drivers/pci/probe.c
> > @@ -1695,9 +1695,6 @@ int pci_setup_device(struct pci_dev *dev)
> >  		break;
> >  
> >  	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
> > -		if (class != PCI_CLASS_BRIDGE_PCI)
> > -			goto bad;
> > -
> >  		/*
> >  		 * The PCI-to-PCI bridge spec requires that subtractive
> >  		 * decoding (i.e. transparent) bridge must have programming
> > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> > index 79b1824..69f90f4 100644
> > --- a/drivers/pci/setup-bus.c
> > +++ b/drivers/pci/setup-bus.c
> > @@ -182,7 +182,7 @@ static void __dev_sort_resources(struct pci_dev *dev,
> >  	u16 class = dev->class >> 8;
> >  
> >  	/* Don't touch classless devices or host bridges or ioapics.  */
> > -	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
> > +	if (class == PCI_CLASS_NOT_DEFINED)
> 
> I think this check has been there since the first initial git commit,
> whether that's _really_ needed or not in the current kernel it is very
> hard to say.
> 
> I am not that sure it is safe to remove it, especially given that we are at
> -rc8 and close to a release, it would be good if this patch could sit in
> next to give it some exposure to testing before merging it upstream.

Yes, you're right; I think I think this is a little too risky at this
point.  I'll pull this patch out and queue it up for the next cycle
(v4.21).

For v4.20, I think you should resurrect the class code patch [1].  That
should be enough to make things work in v4.20, even without this hdr_type
patch.  It will also improve the lspci output, because I think it uses the
class code to look up the generic description, e.g., in this output:

  00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port (rev f1)

I think the "PCI bridge" part is based on the class code.

Bjorn

[1] https://lore.kernel.org/linux-pci/1539590940-13355-3-git-send-email-honghui.zhang@mediatek.com

> >  		return;
> >  
> >  	/* Don't touch ioapic devices already enabled by firmware */
> > @@ -1221,12 +1221,12 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
> >  		if (!b)
> >  			continue;
> >  
> > -		switch (dev->class >> 8) {
> > -		case PCI_CLASS_BRIDGE_CARDBUS:
> > +		switch (dev->hdr_type) {
> > +		case PCI_HEADER_TYPE_CARDBUS:
> >  			pci_bus_size_cardbus(b, realloc_head);
> >  			break;
> >  
> > -		case PCI_CLASS_BRIDGE_PCI:
> > +		case PCI_HEADER_TYPE_BRIDGE:
> >  		default:
> >  			__pci_bus_size_bridges(b, realloc_head);
> >  			break;
> > @@ -1237,12 +1237,12 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
> >  	if (pci_is_root_bus(bus))
> >  		return;
> >  
> > -	switch (bus->self->class >> 8) {
> > -	case PCI_CLASS_BRIDGE_CARDBUS:
> > +	switch (bus->self->hdr_type) {
> > +	case PCI_HEADER_TYPE_CARDBUS:
> >  		/* don't size cardbuses yet. */
> >  		break;
> >  
> > -	case PCI_CLASS_BRIDGE_PCI:
> > +	case PCI_HEADER_TYPE_BRIDGE:
> >  		pci_bridge_check_ranges(bus);
> >  		if (bus->self->is_hotplug_bridge) {
> >  			additional_io_size  = pci_hotplug_io_size;
> > @@ -1391,13 +1391,13 @@ void __pci_bus_assign_resources(const struct pci_bus *bus,
> >  
> >  		__pci_bus_assign_resources(b, realloc_head, fail_head);
> >  
> > -		switch (dev->class >> 8) {
> > -		case PCI_CLASS_BRIDGE_PCI:
> > +		switch (dev->hdr_type) {
> > +		case PCI_HEADER_TYPE_BRIDGE:
> >  			if (!pci_is_enabled(dev))
> >  				pci_setup_bridge(b);
> >  			break;
> >  
> > -		case PCI_CLASS_BRIDGE_CARDBUS:
> > +		case PCI_HEADER_TYPE_CARDBUS:
> >  			pci_setup_cardbus(b);
> >  			break;
> >  
> > -- 
> > 2.6.4
> > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: helgaas@kernel.org (Bjorn Helgaas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 2/9] PCI: Using PCI configuration space header type instead of class type to assign resource
Date: Wed, 17 Oct 2018 08:22:51 -0500	[thread overview]
Message-ID: <20181017132251.GG5906@bhelgaas-glaptop.roam.corp.google.com> (raw)
In-Reply-To: <20181016145355.GB16390@e107981-ln.cambridge.arm.com>

On Tue, Oct 16, 2018 at 03:53:55PM +0100, Lorenzo Pieralisi wrote:
> On Tue, Oct 16, 2018 at 06:44:43PM +0800, honghui.zhang at mediatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> > 
> > The PCI configuration space header type defines the layout of the rest
> > of the header (PCI r3.0 sec 6.1, PCIe r4.0 sec 7.5.1.1.9) while the
> > resource assignment is based on the configuration space layout instead
> > of its class type. Using configuration space header type instead of
> > class type for the resource assignment.
> > 
> > Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > ---
> >  drivers/pci/pci.c       |  3 +--
> >  drivers/pci/probe.c     |  3 ---
> >  drivers/pci/setup-bus.c | 20 ++++++++++----------
> >  3 files changed, 11 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index 29ff961..7d379ca 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -5908,8 +5908,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
> >  	 * to enable the kernel to reassign new resource
> >  	 * window later on.
> >  	 */
> > -	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
> > -	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
> > +	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
> >  		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
> >  			r = &dev->resource[i];
> >  			if (!(r->flags & IORESOURCE_MEM))
> > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> > index ec78400..29a35c1 100644
> > --- a/drivers/pci/probe.c
> > +++ b/drivers/pci/probe.c
> > @@ -1695,9 +1695,6 @@ int pci_setup_device(struct pci_dev *dev)
> >  		break;
> >  
> >  	case PCI_HEADER_TYPE_BRIDGE:		    /* bridge header */
> > -		if (class != PCI_CLASS_BRIDGE_PCI)
> > -			goto bad;
> > -
> >  		/*
> >  		 * The PCI-to-PCI bridge spec requires that subtractive
> >  		 * decoding (i.e. transparent) bridge must have programming
> > diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
> > index 79b1824..69f90f4 100644
> > --- a/drivers/pci/setup-bus.c
> > +++ b/drivers/pci/setup-bus.c
> > @@ -182,7 +182,7 @@ static void __dev_sort_resources(struct pci_dev *dev,
> >  	u16 class = dev->class >> 8;
> >  
> >  	/* Don't touch classless devices or host bridges or ioapics.  */
> > -	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
> > +	if (class == PCI_CLASS_NOT_DEFINED)
> 
> I think this check has been there since the first initial git commit,
> whether that's _really_ needed or not in the current kernel it is very
> hard to say.
> 
> I am not that sure it is safe to remove it, especially given that we are at
> -rc8 and close to a release, it would be good if this patch could sit in
> next to give it some exposure to testing before merging it upstream.

Yes, you're right; I think I think this is a little too risky at this
point.  I'll pull this patch out and queue it up for the next cycle
(v4.21).

For v4.20, I think you should resurrect the class code patch [1].  That
should be enough to make things work in v4.20, even without this hdr_type
patch.  It will also improve the lspci output, because I think it uses the
class code to look up the generic description, e.g., in this output:

  00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port (rev f1)

I think the "PCI bridge" part is based on the class code.

Bjorn

[1] https://lore.kernel.org/linux-pci/1539590940-13355-3-git-send-email-honghui.zhang at mediatek.com

> >  		return;
> >  
> >  	/* Don't touch ioapic devices already enabled by firmware */
> > @@ -1221,12 +1221,12 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
> >  		if (!b)
> >  			continue;
> >  
> > -		switch (dev->class >> 8) {
> > -		case PCI_CLASS_BRIDGE_CARDBUS:
> > +		switch (dev->hdr_type) {
> > +		case PCI_HEADER_TYPE_CARDBUS:
> >  			pci_bus_size_cardbus(b, realloc_head);
> >  			break;
> >  
> > -		case PCI_CLASS_BRIDGE_PCI:
> > +		case PCI_HEADER_TYPE_BRIDGE:
> >  		default:
> >  			__pci_bus_size_bridges(b, realloc_head);
> >  			break;
> > @@ -1237,12 +1237,12 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
> >  	if (pci_is_root_bus(bus))
> >  		return;
> >  
> > -	switch (bus->self->class >> 8) {
> > -	case PCI_CLASS_BRIDGE_CARDBUS:
> > +	switch (bus->self->hdr_type) {
> > +	case PCI_HEADER_TYPE_CARDBUS:
> >  		/* don't size cardbuses yet. */
> >  		break;
> >  
> > -	case PCI_CLASS_BRIDGE_PCI:
> > +	case PCI_HEADER_TYPE_BRIDGE:
> >  		pci_bridge_check_ranges(bus);
> >  		if (bus->self->is_hotplug_bridge) {
> >  			additional_io_size  = pci_hotplug_io_size;
> > @@ -1391,13 +1391,13 @@ void __pci_bus_assign_resources(const struct pci_bus *bus,
> >  
> >  		__pci_bus_assign_resources(b, realloc_head, fail_head);
> >  
> > -		switch (dev->class >> 8) {
> > -		case PCI_CLASS_BRIDGE_PCI:
> > +		switch (dev->hdr_type) {
> > +		case PCI_HEADER_TYPE_BRIDGE:
> >  			if (!pci_is_enabled(dev))
> >  				pci_setup_bridge(b);
> >  			break;
> >  
> > -		case PCI_CLASS_BRIDGE_CARDBUS:
> > +		case PCI_HEADER_TYPE_CARDBUS:
> >  			pci_setup_cardbus(b);
> >  			break;
> >  
> > -- 
> > 2.6.4
> > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2018-10-17 13:22 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-16 10:44 [PATCH v9 0/9] PCI: mediatek: fixup find_port, enable_msi and add PM, module support honghui.zhang
2018-10-16 10:44 ` honghui.zhang at mediatek.com
2018-10-16 10:44 ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 1/9] PCI: mediatek: Using slot's devfn for compare to fix mtk_pcie_find_port logic honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 2/9] PCI: Using PCI configuration space header type instead of class type to assign resource honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 14:53   ` Lorenzo Pieralisi
2018-10-16 14:53     ` Lorenzo Pieralisi
2018-10-17 13:22     ` Bjorn Helgaas [this message]
2018-10-17 13:22       ` Bjorn Helgaas
2018-10-18  1:25       ` Honghui Zhang
2018-10-18  1:25         ` Honghui Zhang
2018-10-18  1:25         ` Honghui Zhang
2019-01-30 17:06   ` Bjorn Helgaas
2019-01-30 17:06     ` Bjorn Helgaas
2018-10-16 10:44 ` [PATCH v9 3/9] PCI: mediatek: Remove the redundant dev->pm_domain check honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 4/9] PCI: mediatek: Convert to use pci_host_probe() honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 5/9] PCI: mediatek: Move the mtk_pcie_startup_port_v2 function's define after mtk_pcie_setup_irq honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 6/9] PCI: mediatek: Fixup enable MSI logic by enable MSI after clock enabled honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 7/9] PCI: mediatek: Add system PM support for MT2712 and MT7622 honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 8/9] PCI: mediatek: Save the GIC IRQ in mtk_pcie_port honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang
2018-10-16 10:44 ` [PATCH v9 9/9] PCI: mediatek: Add loadable kernel module support honghui.zhang
2018-10-16 10:44   ` honghui.zhang at mediatek.com
2018-10-16 10:44   ` honghui.zhang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181017132251.GG5906@bhelgaas-glaptop.roam.corp.google.com \
    --to=helgaas@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=eddie.huang@mediatek.com \
    --cc=honghui.zhang@mediatek.com \
    --cc=jianjun.wang@mediatek.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=marc.zyngier@arm.com \
    --cc=matthias.bgg@gmail.com \
    --cc=ryder.lee@mediatek.com \
    --cc=ulf.hansson@linaro.org \
    --cc=yingjoe.chen@mediatek.com \
    --cc=youlin.pei@mediatek.com \
    --cc=yt.shen@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.