[PATCH v2 1/2] drm/i915/guc: Limit number of scratch registers used for H2G

[PATCH v2 1/2] drm/i915/guc: Limit number of scratch registers used for H2G

[Michal Wajdeczko]

We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.

v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_guc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 4c61eb9..390ae7e 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 	unsigned int i;
 
 	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
-	guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
+	guc->send_regs.count = 8;
+	GEM_BUG_ON(guc->send_regs.count > SOFT_SCRATCH_COUNT);
 
 	for (i = 0; i < guc->send_regs.count; i++) {
 		fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
-- 
1.9.1

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[PATCH v2 2/2] HAX: Enable GuC for CI

[Michal Wajdeczko]

GuC is disabled by default. Enable it.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
1.9.1

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✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/guc: Limit number of scratch registers used for H2G

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/guc: Limit number of scratch registers used for H2G
URL   : https://patchwork.freedesktop.org/series/51137/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5000 -> Patchwork_10494 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10494 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10494, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51137/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10494:

  === IGT changes ===

    ==== Possible regressions ====

    igt@drv_selftest@live_guc:
      fi-kbl-7567u:       PASS -> DMESG-WARN
      fi-skl-6600u:       PASS -> DMESG-WARN
      fi-skl-gvtdvm:      PASS -> DMESG-WARN
      fi-skl-iommu:       PASS -> DMESG-WARN
      fi-skl-6260u:       PASS -> DMESG-WARN
      fi-bxt-dsi:         PASS -> DMESG-WARN
      fi-skl-6700k2:      PASS -> DMESG-WARN
      fi-whl-u:           PASS -> DMESG-WARN
      fi-skl-6770hq:      PASS -> DMESG-WARN
      fi-kbl-8809g:       PASS -> DMESG-WARN
      fi-kbl-x1275:       PASS -> DMESG-WARN
      fi-bxt-j4205:       PASS -> DMESG-WARN
      fi-skl-6700hq:      PASS -> DMESG-WARN
      fi-cfl-8109u:       PASS -> DMESG-WARN
      fi-kbl-7500u:       PASS -> DMESG-WARN
      fi-cfl-8700k:       PASS -> DMESG-WARN

    igt@drv_selftest@live_hangcheck:
      fi-kbl-r:           PASS -> INCOMPLETE
      fi-cfl-s3:          PASS -> INCOMPLETE

    
== Known issues ==

  Here are the changes found in Patchwork_10494 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (47 -> 39) ==

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-icl-u fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-kbl-7560u 


== Build changes ==

    * Linux: CI_DRM_5000 -> Patchwork_10494

  CI_DRM_5000: b9543c130d4f6edd76ec98090c46044ba6d9493e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4683: 7766b1e2348b32cc8ed58a972c6fd53b20279549 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10494: 4d93c7675bc7d5ba85123b68c00f253ec6aa133f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4d93c7675bc7 HAX: Enable GuC for CI
0a7c2abb67b7 drm/i915/guc: Limit number of scratch registers used for H2G

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10494/issues.html
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Re: [PATCH v2 1/2] drm/i915/guc: Limit number of scratch registers used for H2G

[Daniele Ceraolo Spurio]

On 17/10/18 13:05, Michal Wajdeczko wrote:
> We wrongly assumed that GuC is only using last scratch register
> for G2H messages, but in fact it is also using register [14] to
> report sleep state status. Remove that register from our H2G
> send registers pool.
> 
> v2: No message from host to GuC uses more than 8 registers and
> the GuC FW itself uses an 8-element array to store the H2G message,
> so we may reduce our send array to just 8 registers (Daniele)
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/intel_guc.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 4c61eb9..390ae7e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>   	unsigned int i;
>   
>   	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> -	guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
> +	guc->send_regs.count = 8;
> +	GEM_BUG_ON(guc->send_regs.count > SOFT_SCRATCH_COUNT);

With the info about no command using more than 8 regs added to the code 
as a comment:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

nitpick: if we add a define instead of using "8" directly we can ditch 
the GEM_BUG_ON in favor of a BUILD_BUG_ON. If you do that, the comment 
probably belongs with the define.

Thanks,
Daniele

>   
>   	for (i = 0; i < guc->send_regs.count; i++) {
>   		fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> 
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