[Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze

[Palmer Dabbelt <palmer@sifive.com>]

The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging (2018-10-16 17:42:56 +0100)

are available in the Git repository at:

  git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-sf0

for you to fetch changes up to 7c28f4da20e5585dce7d575691dac5392b7c6f78:

  RISC-V: Don't add NULL bootargs to device-tree (2018-10-17 13:02:30 -0700)

----------------------------------------------------------------
First RISC-V Patch Set for the 3.1 Soft Freeze

This pull request contains a handful of patches that have been floating
around various trees for a while but haven't made it upstream.  These
patches all appear quite safe.  They're all somewhat independent from
each other:

* One refactors our IRQ management function to allow multiple interrupts
  to be raised an once.  This patch has no functional difference.
* Cleaning up the op_helper/cpu_helper split.  This patch has no
  functional difference.
* Updates to various constants to keep them in sync with the latest ISA
  specification and to remove some non-standard bits that snuck in.
* A fix for a memory leak in the PLIC driver.
* A fix to our device tree handling to avoid provinging a NULL string.

I've given this my standard test: building the port, booting a Fedora
root filesytem on the latest Linux tag, and then shutting down that
image.  Essentially I'm just following the QEMU RISC-V wiki page's
instructions.  Everything looks fine here.

We have a lot more outstanding patches so I'll definately be submitting
another PR for the soft freeze.

----------------------------------------------------------------
Michael Clark (5):
      RISC-V: Allow setting and clearing multiple irqs
      RISC-V: Move non-ops from op_helper to cpu_helper
      RISC-V: Update CSR and interrupt definitions
      RISC-V: Add missing free for plic_hart_config
      RISC-V: Don't add NULL bootargs to device-tree

 hw/riscv/sifive_clint.c                 |   8 +-
 hw/riscv/sifive_plic.c                  |   4 +-
 hw/riscv/sifive_u.c                     |   4 +-
 hw/riscv/spike.c                        |   6 +-
 hw/riscv/virt.c                         |   6 +-
 target/riscv/Makefile.objs              |   2 +-
 target/riscv/cpu.c                      |   6 +-
 target/riscv/cpu.h                      |  22 +-
 target/riscv/cpu_bits.h                 | 683 +++++++++++++++++---------------
 target/riscv/{helper.c => cpu_helper.c} |  35 +-
 target/riscv/op_helper.c                |  34 +-
 11 files changed, 438 insertions(+), 372 deletions(-)
 rename target/riscv/{helper.c => cpu_helper.c} (95%)