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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	Michael Clark <mjc@sifive.com>,
	qemu-devel@nongnu.orgMichael Clark <mjc@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 4/5] RISC-V: Add missing free for plic_hart_config
Date: Wed, 17 Oct 2018 14:54:21 -0700	[thread overview]
Message-ID: <20181017215422.3973-5-palmer@sifive.com> (raw)
In-Reply-To: <20181017215422.3973-1-palmer@sifive.com>

From: Michael Clark <mjc@sifive.com>

Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 005169eabcb4..6bd723dc3ad9 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -385,6 +385,8 @@ static void riscv_virt_board_init(MachineState *machine)
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+    g_free(plic_hart_config);
 }
 
 static void riscv_virt_board_machine_init(MachineClass *mc)
-- 
2.18.1

  parent reply	other threads:[~2018-10-17 22:02 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-17 21:54 [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze Palmer Dabbelt
2018-10-17 21:54 ` [Qemu-devel] [PULL 1/5] RISC-V: Allow setting and clearing multiple irqs Palmer Dabbelt
2018-10-17 21:54 ` [Qemu-devel] [PULL 2/5] RISC-V: Move non-ops from op_helper to cpu_helper Palmer Dabbelt
2018-10-17 21:54 ` [Qemu-devel] [PULL 3/5] RISC-V: Update CSR and interrupt definitions Palmer Dabbelt
2018-10-17 21:54 ` Palmer Dabbelt [this message]
2018-10-17 21:54 ` [Qemu-devel] [PULL 5/5] RISC-V: Don't add NULL bootargs to device-tree Palmer Dabbelt
2018-10-17 23:32 ` [Qemu-devel] [PULL] First RISC-V Patch Set for the 3.1 Soft Freeze Eric Blake
2018-10-18  0:01   ` Palmer Dabbelt
2018-10-18 12:54     ` Michael Clark
2018-10-18 18:26       ` Palmer Dabbelt
2018-10-25 18:34 ` Peter Maydell

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