From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 00/45] target-arm queue
Date: Fri, 19 Oct 2018 17:56:50 +0100 [thread overview]
Message-ID: <20181019165735.22511-1-peter.maydell@linaro.org> (raw)
As promised, another pullreq... This one's mostly RTH's patches.
thanks
-- PMM
The following changes since commit 784c2e4f232adf5ef47a84a262ec72a07d068d6a:
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2018-10-19 15:30:40 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181019
for you to fetch changes up to 88c9add25e7120e8622796c81ad3f3fb7f8d40e7:
target/arm: Only flush tlb if ASID changes (2018-10-19 17:38:48 +0100)
----------------------------------------------------------------
target-arm queue:
* ssi-sd: Make devices picking up backends unavailable with -device
* Add support for VCPU event states
* Move towards making ID registers the source of truth for
whether a guest CPU implements a feature, rather than having
parallel ID registers and feature bit flags
* Implement various HCR hypervisor trap/config bits
* Get IL bit correct for v7 syndrome values
* Report correct syndrome for FP/SIMD traps to Hyp mode
* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
* Refactor A32 Neon to use generic vector infrastructure
* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
* net: cadence_gem: Report features correctly in ID register
* Avoid some unnecessary TLB flushes on TTBR register writes
----------------------------------------------------------------
Dongjiu Geng (1):
target/arm: Add support for VCPU event states
Edgar E. Iglesias (2):
net: cadence_gem: Announce availability of priority queues
net: cadence_gem: Announce 64bit addressing support
Markus Armbruster (1):
ssi-sd: Make devices picking up backends unavailable with -device
Peter Maydell (10):
target/arm: Improve debug logging of AArch32 exception return
target/arm: Make switch_mode() file-local
target/arm: Implement HCR.FB
target/arm: Implement HCR.DC
target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
target/arm: Implement HCR.VI and VF
target/arm: Implement HCR.PTW
target/arm: New utility function to extract EC from syndrome
target/arm: Get IL bit correct for v7 syndrome values
target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
Richard Henderson (30):
target/arm: Move some system registers into a substructure
target/arm: V8M should not imply V7VE
target/arm: Convert v8 extensions from feature bits to isar tests
target/arm: Convert division from feature bits to isar0 tests
target/arm: Convert jazelle from feature bit to isar1 test
target/arm: Convert t32ee from feature bit to isar3 test
target/arm: Convert sve from feature bit to aa64pfr0 test
target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
target/arm: Hoist address increment for vector memory ops
target/arm: Don't call tcg_clear_temp_count
target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
target/arm: Promote consecutive memory ops for aa64
target/arm: Mark some arrays const
target/arm: Use gvec for NEON VDUP
target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
target/arm: Use gvec for NEON_3R_LOGIC insns
target/arm: Use gvec for NEON_3R_VADD_VSUB insns
target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
target/arm: Use gvec for NEON_3R_VMUL
target/arm: Use gvec for VSHR, VSHL
target/arm: Use gvec for VSRA
target/arm: Use gvec for VSRI, VSLI
target/arm: Use gvec for NEON_3R_VML
target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
target/arm: Use gvec for NEON VLD all lanes
target/arm: Reorg NEON VLD/VST all elements
target/arm: Promote consecutive memory ops for aa32
target/arm: Reorg NEON VLD/VST single element to one lane
target/arm: Remove writefn from TTBR0_EL3
target/arm: Only flush tlb if ASID changes
Stewart Hildebrand (1):
hw/arm/boot: Increase compliance with kernel arm64 boot protocol
target/arm/cpu.h | 227 ++++++-
target/arm/internals.h | 45 +-
target/arm/kvm_arm.h | 24 +
target/arm/translate.h | 21 +
hw/arm/boot.c | 18 +
hw/intc/armv7m_nvic.c | 12 +-
hw/net/cadence_gem.c | 9 +-
hw/sd/ssi-sd.c | 2 +
linux-user/aarch64/signal.c | 4 +-
linux-user/elfload.c | 60 +-
linux-user/syscall.c | 10 +-
target/arm/cpu.c | 242 ++++----
target/arm/cpu64.c | 148 +++--
target/arm/helper.c | 397 ++++++++----
target/arm/kvm.c | 60 ++
target/arm/kvm32.c | 13 +
target/arm/kvm64.c | 15 +-
target/arm/machine.c | 28 +-
target/arm/op_helper.c | 2 +-
target/arm/translate-a64.c | 715 ++++-----------------
target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
21 files changed, 2021 insertions(+), 1482 deletions(-)
next reply other threads:[~2018-10-19 16:57 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-19 16:56 Peter Maydell [this message]
2018-10-19 16:56 ` [Qemu-devel] [PULL 01/45] ssi-sd: Make devices picking up backends unavailable with -device Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 04/45] target/arm: V8M should not imply V7VE Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 " Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 12/45] target/arm: Make switch_mode() file-local Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 13/45] target/arm: Implement HCR.FB Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 14/45] target/arm: Implement HCR.DC Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 15/45] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 16/45] target/arm: Implement HCR.VI and VF Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 17/45] target/arm: Implement HCR.PTW Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 18/45] target/arm: New utility function to extract EC from syndrome Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 19/45] target/arm: Get IL bit correct for v7 syndrome values Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 25/45] target/arm: Promote consecutive memory ops for aa64 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 26/45] target/arm: Mark some arrays const Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 27/45] target/arm: Use gvec for NEON VDUP Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 29/45] target/arm: Use gvec for NEON_3R_LOGIC insns Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 32/45] target/arm: Use gvec for NEON_3R_VMUL Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 34/45] target/arm: Use gvec for VSRA Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 37/45] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all elements Peter Maydell
2018-11-02 16:31 ` Laurent Vivier
2018-10-19 16:57 ` [Qemu-devel] [PULL 40/45] target/arm: Promote consecutive memory ops for aa32 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-08-14 18:17 [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
2018-08-15 12:29 ` Peter Maydell
2014-02-26 18:01 Peter Maydell
2014-02-27 11:33 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181019165735.22511-1-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.