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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states
Date: Fri, 19 Oct 2018 17:56:52 +0100	[thread overview]
Message-ID: <20181019165735.22511-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20181019165735.22511-1-peter.maydell@linaro.org>

From: Dongjiu Geng <gengdongjiu@huawei.com>

This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
And also it can support the exception state migration.

The SError exception states include SError pending state and ESR value,
the kvm_put/get_vcpu_events() will be called when set or get system
registers. When do migration, if source machine has SError pending,
QEMU will do this migration regardless whether the target machine supports
to specify guest ESR value, because if target machine does not support that,
it can also inject the SError with zero ESR value.

Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1538067351-23931-3-git-send-email-gengdongjiu@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  7 ++++++
 target/arm/kvm_arm.h | 24 ++++++++++++++++++
 target/arm/kvm.c     | 60 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/kvm32.c   | 13 ++++++++++
 target/arm/kvm64.c   | 13 ++++++++++
 target/arm/machine.c | 22 ++++++++++++++++
 6 files changed, 139 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f00c0444c48..a314e557ac0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -531,6 +531,13 @@ typedef struct CPUARMState {
          */
     } exception;
 
+    /* Information associated with an SError */
+    struct {
+        uint8_t pending;
+        uint8_t has_esr;
+        uint64_t esr;
+    } serror;
+
     /* Thumb-2 EE state.  */
     uint32_t teecr;
     uint32_t teehbr;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 5948e8b5602..21c0129da24 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -121,6 +121,30 @@ bool write_kvmstate_to_list(ARMCPU *cpu);
  */
 void kvm_arm_reset_vcpu(ARMCPU *cpu);
 
+/**
+ * kvm_arm_init_serror_injection:
+ * @cs: CPUState
+ *
+ * Check whether KVM can set guest SError syndrome.
+ */
+void kvm_arm_init_serror_injection(CPUState *cs);
+
+/**
+ * kvm_get_vcpu_events:
+ * @cpu: ARMCPU
+ *
+ * Get VCPU related state from kvm.
+ */
+int kvm_get_vcpu_events(ARMCPU *cpu);
+
+/**
+ * kvm_put_vcpu_events:
+ * @cpu: ARMCPU
+ *
+ * Put VCPU related state to kvm.
+ */
+int kvm_put_vcpu_events(ARMCPU *cpu);
+
 #ifdef CONFIG_KVM
 /**
  * kvm_arm_create_scratch_host_vcpu:
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 54ef5f711b8..09a86e2820b 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -34,6 +34,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
 };
 
 static bool cap_has_mp_state;
+static bool cap_has_inject_serror_esr;
 
 static ARMHostCPUFeatures arm_host_cpu_features;
 
@@ -48,6 +49,12 @@ int kvm_arm_vcpu_init(CPUState *cs)
     return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
 }
 
+void kvm_arm_init_serror_injection(CPUState *cs)
+{
+    cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
+                                    KVM_CAP_ARM_INJECT_SERROR_ESR);
+}
+
 bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
                                       int *fdarray,
                                       struct kvm_vcpu_init *init)
@@ -522,6 +529,59 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
     return 0;
 }
 
+int kvm_put_vcpu_events(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    struct kvm_vcpu_events events;
+    int ret;
+
+    if (!kvm_has_vcpu_events()) {
+        return 0;
+    }
+
+    memset(&events, 0, sizeof(events));
+    events.exception.serror_pending = env->serror.pending;
+
+    /* Inject SError to guest with specified syndrome if host kernel
+     * supports it, otherwise inject SError without syndrome.
+     */
+    if (cap_has_inject_serror_esr) {
+        events.exception.serror_has_esr = env->serror.has_esr;
+        events.exception.serror_esr = env->serror.esr;
+    }
+
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
+    if (ret) {
+        error_report("failed to put vcpu events");
+    }
+
+    return ret;
+}
+
+int kvm_get_vcpu_events(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    struct kvm_vcpu_events events;
+    int ret;
+
+    if (!kvm_has_vcpu_events()) {
+        return 0;
+    }
+
+    memset(&events, 0, sizeof(events));
+    ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
+    if (ret) {
+        error_report("failed to get vcpu events");
+        return ret;
+    }
+
+    env->serror.pending = events.exception.serror_pending;
+    env->serror.has_esr = events.exception.serror_has_esr;
+    env->serror.esr = events.exception.serror_esr;
+
+    return 0;
+}
+
 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
 {
 }
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 4e91c11796b..0f1e94c7b5e 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -217,6 +217,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
     }
     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 
+    /* Check whether userspace can specify guest syndrome value */
+    kvm_arm_init_serror_injection(cs);
+
     return kvm_arm_init_cpreg_list(cpu);
 }
 
@@ -358,6 +361,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    ret = kvm_put_vcpu_events(cpu);
+    if (ret) {
+        return ret;
+    }
+
     /* Note that we do not call write_cpustate_to_list()
      * here, so we are only writing the tuple list back to
      * KVM. This is safe because nothing can change the
@@ -445,6 +453,11 @@ int kvm_arch_get_registers(CPUState *cs)
     }
     vfp_set_fpscr(env, fpscr);
 
+    ret = kvm_get_vcpu_events(cpu);
+    if (ret) {
+        return ret;
+    }
+
     if (!write_kvmstate_to_list(cpu)) {
         return EINVAL;
     }
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index e0b82462838..5411486491a 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -546,6 +546,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
 
     kvm_arm_init_debug(cs);
 
+    /* Check whether user space can specify guest syndrome value */
+    kvm_arm_init_serror_injection(cs);
+
     return kvm_arm_init_cpreg_list(cpu);
 }
 
@@ -727,6 +730,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
+    ret = kvm_put_vcpu_events(cpu);
+    if (ret) {
+        return ret;
+    }
+
     if (!write_list_to_kvmstate(cpu, level)) {
         return EINVAL;
     }
@@ -863,6 +871,11 @@ int kvm_arch_get_registers(CPUState *cs)
     }
     vfp_set_fpcr(env, fpr);
 
+    ret = kvm_get_vcpu_events(cpu);
+    if (ret) {
+        return ret;
+    }
+
     if (!write_kvmstate_to_list(cpu)) {
         return EINVAL;
     }
diff --git a/target/arm/machine.c b/target/arm/machine.c
index ff4ec22bf75..32bcde070a0 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -172,6 +172,27 @@ static const VMStateDescription vmstate_sve = {
 };
 #endif /* AARCH64 */
 
+static bool serror_needed(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+
+    return env->serror.pending != 0;
+}
+
+static const VMStateDescription vmstate_serror = {
+    .name = "cpu/serror",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = serror_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(env.serror.pending, ARMCPU),
+        VMSTATE_UINT8(env.serror.has_esr, ARMCPU),
+        VMSTATE_UINT64(env.serror.esr, ARMCPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool m_needed(void *opaque)
 {
     ARMCPU *cpu = opaque;
@@ -726,6 +747,7 @@ const VMStateDescription vmstate_arm_cpu = {
 #ifdef TARGET_AARCH64
         &vmstate_sve,
 #endif
+        &vmstate_serror,
         NULL
     }
 };
-- 
2.19.1

  parent reply	other threads:[~2018-10-19 16:57 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-19 16:56 [Qemu-devel] [PULL 00/45] target-arm queue Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 01/45] ssi-sd: Make devices picking up backends unavailable with -device Peter Maydell
2018-10-19 16:56 ` Peter Maydell [this message]
2018-10-19 16:56 ` [Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 04/45] target/arm: V8M should not imply V7VE Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test Peter Maydell
2018-10-19 16:56 ` [Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 " Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 12/45] target/arm: Make switch_mode() file-local Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 13/45] target/arm: Implement HCR.FB Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 14/45] target/arm: Implement HCR.DC Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 15/45] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 16/45] target/arm: Implement HCR.VI and VF Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 17/45] target/arm: Implement HCR.PTW Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 18/45] target/arm: New utility function to extract EC from syndrome Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 19/45] target/arm: Get IL bit correct for v7 syndrome values Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 25/45] target/arm: Promote consecutive memory ops for aa64 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 26/45] target/arm: Mark some arrays const Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 27/45] target/arm: Use gvec for NEON VDUP Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 29/45] target/arm: Use gvec for NEON_3R_LOGIC insns Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 32/45] target/arm: Use gvec for NEON_3R_VMUL Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 34/45] target/arm: Use gvec for VSRA Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 37/45] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all elements Peter Maydell
2018-11-02 16:31   ` Laurent Vivier
2018-10-19 16:57 ` [Qemu-devel] [PULL 40/45] target/arm: Promote consecutive memory ops for aa32 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3 Peter Maydell
2018-10-19 16:57 ` [Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes Peter Maydell

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