* [PATCH 0/3] ICL DSI PLL enable
@ 2018-10-23 11:09 Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi Vandita Kulkarni
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Vandita Kulkarni @ 2018-10-23 11:09 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
ICL DSI uses DPLL.
As per the discussion with hw team, the same
sequence can be used for enabling DPLL for mipi dsi
as well. Hence reusing the dpll functions from icl pll manager.
In addition to that we need to program
the esc clock register before enabling dsi.
This has been tested with other power-on related patches
present at https://github.com/madhavchauhan/Intel-DSI-Driver
Madhav Chauhan (2):
drm/i915/icl: Calculate DPLL params for DSI
drm/i915/icl: Add get_config functionality for dsi
Vandita Kulkarni (1):
drm/i915/icl: Use the same pll functions for dsi
drivers/gpu/drm/i915/icl_dsi.c | 30 ++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_display.c | 4 +++-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 ++
3 files changed, 31 insertions(+), 5 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
@ 2018-10-23 11:09 ` Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI Vandita Kulkarni
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Vandita Kulkarni @ 2018-10-23 11:09 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The same pll manager functions can be used to enable
dpll for mipi. Hence enabling the IO power and
esc clock as part of pre pll enable call.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a175..d2bb369 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -637,16 +637,25 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
}
static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
- const struct drm_connector_state *conn_state)
+gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
{
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
- /* step3: enable DSI PLL */
+ /*
+ * step3: DSI uses DPLL, can use the respective pll
+ * manager enable func, just program esc clock here.
+ */
gen11_dsi_program_esc_clk_div(encoder);
+}
+static void __attribute__((unused))
+gen11_dsi_pre_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
+{
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
--
1.9.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi Vandita Kulkarni
@ 2018-10-23 11:09 ` Vandita Kulkarni
2018-10-23 16:22 ` Ville Syrjälä
2018-10-23 11:09 ` [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi Vandita Kulkarni
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Vandita Kulkarni @ 2018-10-23 11:09 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch calculate various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.
v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
v3: Rebase
v4: use port clock instead of bitrate.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 +++-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc7e3b0..ddbba92 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9250,10 +9250,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_atomic_state *state =
to_intel_atomic_state(crtc_state->base.state);
- if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
+ IS_ICELAKE(dev_priv)) {
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7bdff5b..f31acf1 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2525,6 +2525,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
+ else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+ ret = cnl_ddi_calculate_wrpll(clock/5, dev_priv, &pll_params);
else
ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI Vandita Kulkarni
@ 2018-10-23 11:09 ` Vandita Kulkarni
2018-10-23 12:09 ` Ville Syrjälä
2018-10-23 12:04 ` ✗ Fi.CI.CHECKPATCH: warning for ICL DSI PLL enable Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Vandita Kulkarni @ 2018-10-23 11:09 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.
v2: use intel_dsi_bitrate instead of intel_dsi->pclk
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d2bb369..6cb3bf8 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -665,3 +665,16 @@ static void __attribute__((unused))
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
}
+
+static void __attribute__((unused))
+gen11_dsi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ u32 pixel_clk;
+
+ pixel_clk = intel_dsi_bitrate(intel_dsi);
+ pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
+ pipe_config->port_clock = pixel_clk;
+}
--
1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for ICL DSI PLL enable
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
` (2 preceding siblings ...)
2018-10-23 11:09 ` [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi Vandita Kulkarni
@ 2018-10-23 12:04 ` Patchwork
2018-10-23 12:12 ` [PATCH 0/3] " Jani Nikula
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-10-23 12:04 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: ICL DSI PLL enable
URL : https://patchwork.freedesktop.org/series/51373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ab5b10e0ce6a drm/i915/icl: Use the same pll functions for dsi
c36b32e74d2c drm/i915/icl: Calculate DPLL params for DSI
-:33: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/i915/intel_display.c:9258:
+ if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
+ IS_ICELAKE(dev_priv)) {
-:46: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2529:
+ ret = cnl_ddi_calculate_wrpll(clock/5, dev_priv, &pll_params);
^
total: 0 errors, 0 warnings, 2 checks, 21 lines checked
7b5e549878d4 drm/i915/icl: Add get_config functionality for dsi
-:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#26: FILE: drivers/gpu/drm/i915/icl_dsi.c:671:
+gen11_dsi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
total: 0 errors, 0 warnings, 1 checks, 16 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi
2018-10-23 11:09 ` [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi Vandita Kulkarni
@ 2018-10-23 12:09 ` Ville Syrjälä
2018-10-24 4:48 ` Kulkarni, Vandita
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-23 12:09 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: jani.nikula, intel-gfx
On Tue, Oct 23, 2018 at 04:39:14PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch implements the functionality for getting PIPE
> configuration to which DSI encoder is connected. Used during
> the atomic modeset.
>
> v2: use intel_dsi_bitrate instead of intel_dsi->pclk
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index d2bb369..6cb3bf8 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -665,3 +665,16 @@ static void __attribute__((unused))
> /* step6d: enable dsi transcoder */
> gen11_dsi_enable_transcoder(encoder);
> }
> +
> +static void __attribute__((unused))
> +gen11_dsi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> + base);
> + u32 pixel_clk;
> +
> + pixel_clk = intel_dsi_bitrate(intel_dsi);
> + pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
> + pipe_config->port_clock = pixel_clk;
We're supposed to read the state from the hardware here. See how other
DDI encoders do it.
> +}
> --
> 1.9.1
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/3] ICL DSI PLL enable
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
` (3 preceding siblings ...)
2018-10-23 12:04 ` ✗ Fi.CI.CHECKPATCH: warning for ICL DSI PLL enable Patchwork
@ 2018-10-23 12:12 ` Jani Nikula
2018-10-23 12:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-10-23 15:40 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2018-10-23 12:12 UTC (permalink / raw)
To: Vandita Kulkarni, intel-gfx
On Tue, 23 Oct 2018, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> This has been tested with other power-on related patches
> present at https://github.com/madhavchauhan/Intel-DSI-Driver
Please rebase on top of icl-dsi-2018-10-23 branch of
https://cgit.freedesktop.org/~jani/drm/
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for ICL DSI PLL enable
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
` (4 preceding siblings ...)
2018-10-23 12:12 ` [PATCH 0/3] " Jani Nikula
@ 2018-10-23 12:22 ` Patchwork
2018-10-23 15:40 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-10-23 12:22 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: ICL DSI PLL enable
URL : https://patchwork.freedesktop.org/series/51373/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5020 -> Patchwork_10543 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51373/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10543 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107774, fdo#107859, fdo#107556)
==== Possible fixes ====
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN (fdo#102614) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS +1
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-cfl-8700k: FAIL (fdo#104008) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
== Participating hosts (47 -> 44) ==
Additional (3): fi-kbl-soraka fi-icl-u fi-cfl-8109u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005
== Build changes ==
* Linux: CI_DRM_5020 -> Patchwork_10543
CI_DRM_5020: 95151c25e0433a2fe771b8bc272f3f8fb54a7e27 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4686: 741bf7064c467df725c14cc0b3b8b50436f9ee09 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10543: 7b5e549878d4f614eff9c6d09513973ff365ccc1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7b5e549878d4 drm/i915/icl: Add get_config functionality for dsi
c36b32e74d2c drm/i915/icl: Calculate DPLL params for DSI
ab5b10e0ce6a drm/i915/icl: Use the same pll functions for dsi
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10543/issues.html
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for ICL DSI PLL enable
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
` (5 preceding siblings ...)
2018-10-23 12:22 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-10-23 15:40 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-10-23 15:40 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: ICL DSI PLL enable
URL : https://patchwork.freedesktop.org/series/51373/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5020_full -> Patchwork_10543_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10543_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_await@wide-contexts:
shard-glk: PASS -> FAIL (fdo#106680)
igt@gem_exec_schedule@pi-ringfull-render:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-snb: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
shard-hsw: PASS -> DMESG-WARN (fdo#107956)
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1
igt@kms_color@pipe-a-legacy-gamma:
shard-skl: PASS -> FAIL (fdo#104782, fdo#108145)
igt@kms_color@pipe-c-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-256x256-random:
shard-apl: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538)
igt@kms_draw_crc@draw-method-xrgb2101010-render-ytiled:
shard-skl: PASS -> FAIL (fdo#103184)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167) +1
igt@kms_plane@pixel-format-pipe-b-planes:
shard-skl: NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166)
igt@kms_plane@plane-position-covered-pipe-b-planes:
shard-glk: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#108146)
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-apl: PASS -> FAIL (fdo#103166)
igt@perf@blocking:
shard-hsw: PASS -> FAIL (fdo#102252)
igt@pm_rpm@cursor:
shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) +1
igt@syncobj_wait@wait-for-submit-delayed-submit:
shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) +4
shard-skl: NOTRUN -> INCOMPLETE (fdo#108490) +2
==== Possible fixes ====
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: FAIL (fdo#106641) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
shard-glk: DMESG-WARN (fdo#107956) -> PASS
igt@kms_chv_cursor_fail@pipe-b-256x256-top-edge:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS +2
igt@kms_cursor_crc@cursor-256x256-sliding:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_flip@flip-vs-expired-vblank:
shard-skl: FAIL (fdo#105363) -> PASS
igt@kms_flip@modeset-vs-vblank-race:
shard-kbl: FAIL (fdo#103060) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
shard-apl: FAIL (fdo#103167) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-apl: FAIL (fdo#103166) -> PASS +1
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
fdo#108490 https://bugs.freedesktop.org/show_bug.cgi?id=108490
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5020 -> Patchwork_10543
CI_DRM_5020: 95151c25e0433a2fe771b8bc272f3f8fb54a7e27 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4686: 741bf7064c467df725c14cc0b3b8b50436f9ee09 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10543: 7b5e549878d4f614eff9c6d09513973ff365ccc1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10543/shards.html
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI
2018-10-23 11:09 ` [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI Vandita Kulkarni
@ 2018-10-23 16:22 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-23 16:22 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: jani.nikula, intel-gfx
On Tue, Oct 23, 2018 at 04:39:13PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch calculate various DPLL dividers and
> parameters for DSI encoder and adjust AFE clock
> for DSI. For DSI, 8x clock is AFE clock.
>
> v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
>
> v3: Rebase
>
> v4: use port clock instead of bitrate.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 ++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fc7e3b0..ddbba92 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9250,10 +9250,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->base.state);
>
> - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
> + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
> + IS_ICELAKE(dev_priv)) {
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7bdff5b..f31acf1 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2525,6 +2525,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
> + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> + ret = cnl_ddi_calculate_wrpll(clock/5, dev_priv, &pll_params);
That /5 could be eliminated in .compute_config(). Not that we seem to
have a full .compute_config() yet.
> else
> ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
>
> --
> 1.9.1
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi
2018-10-23 12:09 ` Ville Syrjälä
@ 2018-10-24 4:48 ` Kulkarni, Vandita
0 siblings, 0 replies; 11+ messages in thread
From: Kulkarni, Vandita @ 2018-10-24 4:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, October 23, 2018 5:39 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi
>
> On Tue, Oct 23, 2018 at 04:39:14PM +0530, Vandita Kulkarni wrote:
> > From: Madhav Chauhan <madhav.chauhan@intel.com>
> >
> > This patch implements the functionality for getting PIPE configuration
> > to which DSI encoder is connected. Used during the atomic modeset.
> >
> > v2: use intel_dsi_bitrate instead of intel_dsi->pclk
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/icl_dsi.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index d2bb369..6cb3bf8 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -665,3 +665,16 @@ static void __attribute__((unused))
> > /* step6d: enable dsi transcoder */
> > gen11_dsi_enable_transcoder(encoder);
> > }
> > +
> > +static void __attribute__((unused))
> > +gen11_dsi_get_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config) {
> > + struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> > + base);
> > + u32 pixel_clk;
> > +
> > + pixel_clk = intel_dsi_bitrate(intel_dsi);
> > + pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
> > + pipe_config->port_clock = pixel_clk;
>
> We're supposed to read the state from the hardware here. See how other DDI
> encoders do it.
Ok.
Thanks,
Vandita
>
> > +}
> > --
> > 1.9.1
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-10-24 4:49 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-23 11:09 [PATCH 0/3] ICL DSI PLL enable Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 1/3] drm/i915/icl: Use the same pll functions for dsi Vandita Kulkarni
2018-10-23 11:09 ` [PATCH 2/3] drm/i915/icl: Calculate DPLL params for DSI Vandita Kulkarni
2018-10-23 16:22 ` Ville Syrjälä
2018-10-23 11:09 ` [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi Vandita Kulkarni
2018-10-23 12:09 ` Ville Syrjälä
2018-10-24 4:48 ` Kulkarni, Vandita
2018-10-23 12:04 ` ✗ Fi.CI.CHECKPATCH: warning for ICL DSI PLL enable Patchwork
2018-10-23 12:12 ` [PATCH 0/3] " Jani Nikula
2018-10-23 12:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-10-23 15:40 ` ✓ Fi.CI.IGT: " Patchwork
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