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From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/3] pci: layerscape: Modify the EP and RC mode judge method
Date: Fri, 26 Oct 2018 09:56:24 +0800	[thread overview]
Message-ID: <20181026015626.40131-1-xiaowei.bao@nxp.com> (raw)

Modify the RC and EP mode judge method, save the mode as a variable,
the variable will be used by other function.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
 drivers/pci/pcie_layerscape.c |   18 ++++++++----------
 drivers/pci/pcie_layerscape.h |    1 +
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 3b7377a..17cba46 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -438,9 +438,7 @@ static int ls_pcie_probe(struct udevice *dev)
 	struct ls_pcie *pcie = dev_get_priv(dev);
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
-	u8 header_type;
 	u16 link_sta;
-	bool ep_mode;
 	uint svr;
 	int ret;
 	fdt_size_t cfg_size;
@@ -524,15 +522,15 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
 	      pcie->big_endian);
 
-	header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
-	ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
-	printf("PCIe%u: %s %s", pcie->idx, dev->name,
-	       ep_mode ? "Endpoint" : "Root Complex");
+	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
 
-	if (ep_mode)
-		ls_pcie_setup_ep(pcie);
-	else
-		ls_pcie_setup_ctrl(pcie);
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+			ls_pcie_setup_ep(pcie);
+	} else {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+			ls_pcie_setup_ctrl(pcie);
+	}
 
 	if (!ls_pcie_link_up(pcie)) {
 		/* Let the user know there's no PCIe link */
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 8770b44..ddfbba6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -144,6 +144,7 @@ struct ls_pcie {
 	bool big_endian;
 	bool enabled;
 	int next_lut_index;
+	int mode;
 };
 
 extern struct list_head ls_pcie_list;
-- 
1.7.1

             reply	other threads:[~2018-10-26  1:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-26  1:56 Xiaowei Bao [this message]
2018-10-26  1:56 ` [U-Boot] [PATCH 2/3] pci: layerscape: Do not scan when PEX work in EP mode Xiaowei Bao
2018-10-26  1:56 ` [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC Xiaowei Bao
2018-11-02 14:52   ` York Sun
2018-11-04  5:34     ` Xiaowei Bao

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