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* [U-Boot] [PATCH 1/3] pci: layerscape: Modify the EP and RC mode judge method
@ 2018-10-26  1:56 Xiaowei Bao
  2018-10-26  1:56 ` [U-Boot] [PATCH 2/3] pci: layerscape: Do not scan when PEX work in EP mode Xiaowei Bao
  2018-10-26  1:56 ` [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC Xiaowei Bao
  0 siblings, 2 replies; 5+ messages in thread
From: Xiaowei Bao @ 2018-10-26  1:56 UTC (permalink / raw)
  To: u-boot

Modify the RC and EP mode judge method, save the mode as a variable,
the variable will be used by other function.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
 drivers/pci/pcie_layerscape.c |   18 ++++++++----------
 drivers/pci/pcie_layerscape.h |    1 +
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 3b7377a..17cba46 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -438,9 +438,7 @@ static int ls_pcie_probe(struct udevice *dev)
 	struct ls_pcie *pcie = dev_get_priv(dev);
 	const void *fdt = gd->fdt_blob;
 	int node = dev_of_offset(dev);
-	u8 header_type;
 	u16 link_sta;
-	bool ep_mode;
 	uint svr;
 	int ret;
 	fdt_size_t cfg_size;
@@ -524,15 +522,15 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
 	      pcie->big_endian);
 
-	header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
-	ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
-	printf("PCIe%u: %s %s", pcie->idx, dev->name,
-	       ep_mode ? "Endpoint" : "Root Complex");
+	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
 
-	if (ep_mode)
-		ls_pcie_setup_ep(pcie);
-	else
-		ls_pcie_setup_ctrl(pcie);
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+			ls_pcie_setup_ep(pcie);
+	} else {
+		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+			ls_pcie_setup_ctrl(pcie);
+	}
 
 	if (!ls_pcie_link_up(pcie)) {
 		/* Let the user know there's no PCIe link */
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 8770b44..ddfbba6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -144,6 +144,7 @@ struct ls_pcie {
 	bool big_endian;
 	bool enabled;
 	int next_lut_index;
+	int mode;
 };
 
 extern struct list_head ls_pcie_list;
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/3] pci: layerscape: Do not scan when PEX work in EP mode
  2018-10-26  1:56 [U-Boot] [PATCH 1/3] pci: layerscape: Modify the EP and RC mode judge method Xiaowei Bao
@ 2018-10-26  1:56 ` Xiaowei Bao
  2018-10-26  1:56 ` [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC Xiaowei Bao
  1 sibling, 0 replies; 5+ messages in thread
From: Xiaowei Bao @ 2018-10-26  1:56 UTC (permalink / raw)
  To: u-boot

Don't scan the bus when the PEX work in EP mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
 drivers/pci/pcie_layerscape.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 17cba46..db1375a 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -225,6 +225,9 @@ static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
 {
 	struct udevice *bus = pcie->bus;
 
+	if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
+		return -ENODEV;
+
 	if (!pcie->enabled)
 		return -ENXIO;
 
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC
  2018-10-26  1:56 [U-Boot] [PATCH 1/3] pci: layerscape: Modify the EP and RC mode judge method Xiaowei Bao
  2018-10-26  1:56 ` [U-Boot] [PATCH 2/3] pci: layerscape: Do not scan when PEX work in EP mode Xiaowei Bao
@ 2018-10-26  1:56 ` Xiaowei Bao
  2018-11-02 14:52   ` York Sun
  1 sibling, 1 reply; 5+ messages in thread
From: Xiaowei Bao @ 2018-10-26  1:56 UTC (permalink / raw)
  To: u-boot

Add the dts fixup when PCI controller work diffferent mode.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
 drivers/pci/pcie_layerscape_fixup.c |   25 +++++++++++++++++++++++--
 1 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 1a17bd9..089e031 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -218,7 +218,7 @@ static void fdt_fixup_pcie(void *blob)
 }
 #endif
 
-static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
 {
 	int off;
 	uint svr;
@@ -243,12 +243,33 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 			return;
 	}
 
-	if (pcie->enabled)
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
+		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+	else
+		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
+{
+	int off;
+
+	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+					    pcie->dbi_res.start);
+	if (off < 0)
+		return;
+
+	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
 		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 	else
 		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 }
 
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
+{
+	ft_pcie_ep_fix(blob, pcie);
+	ft_pcie_rc_fix(blob, pcie);
+}
+
 /* Fixup Kernel DT for PCIe */
 void ft_pci_setup(void *blob, bd_t *bd)
 {
-- 
1.7.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC
  2018-10-26  1:56 ` [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC Xiaowei Bao
@ 2018-11-02 14:52   ` York Sun
  2018-11-04  5:34     ` Xiaowei Bao
  0 siblings, 1 reply; 5+ messages in thread
From: York Sun @ 2018-11-02 14:52 UTC (permalink / raw)
  To: u-boot

On 10/25/18 7:01 PM, Xiaowei Bao wrote:
> Add the dts fixup when PCI controller work diffferent mode.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
>  drivers/pci/pcie_layerscape_fixup.c |   25 +++++++++++++++++++++++--
>  1 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
> index 1a17bd9..089e031 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -218,7 +218,7 @@ static void fdt_fixup_pcie(void *blob)
>  }
>  #endif
>  
> -static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
> +static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
>  {
>  	int off;
>  	uint svr;
> @@ -243,12 +243,33 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
>  			return;
>  	}
>  
> -	if (pcie->enabled)
> +	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
> +		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
> +	else
> +		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
> +}
> +
> +static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
> +{
> +	int off;
> +
> +	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
> +					    pcie->dbi_res.start);
> +	if (off < 0)
> +		return;
> +
> +	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
>  		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
>  	else
>  		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
>  }
>  
> +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
> +{
> +	ft_pcie_ep_fix(blob, pcie);
> +	ft_pcie_rc_fix(blob, pcie);
> +}

Wouldn't it be faster to check the result of first call before entering
the second function? One cannot be both EP and RC, right?

York

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC
  2018-11-02 14:52   ` York Sun
@ 2018-11-04  5:34     ` Xiaowei Bao
  0 siblings, 0 replies; 5+ messages in thread
From: Xiaowei Bao @ 2018-11-04  5:34 UTC (permalink / raw)
  To: u-boot



-----Original Message-----
From: York Sun 
Sent: 2018年11月2日 22:53
To: Xiaowei Bao <xiaowei.bao@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; bmeng.cn at gmail.com; yamada.masahiro at socionext.com; u-boot at lists.denx.de
Cc: Jiafei Pan <jiafei.pan@nxp.com>
Subject: Re: [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC

On 10/25/18 7:01 PM, Xiaowei Bao wrote:
> Add the dts fixup when PCI controller work diffferent mode.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
>  drivers/pci/pcie_layerscape_fixup.c |   25 +++++++++++++++++++++++--
>  1 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/pcie_layerscape_fixup.c 
> b/drivers/pci/pcie_layerscape_fixup.c
> index 1a17bd9..089e031 100644
> --- a/drivers/pci/pcie_layerscape_fixup.c
> +++ b/drivers/pci/pcie_layerscape_fixup.c
> @@ -218,7 +218,7 @@ static void fdt_fixup_pcie(void *blob)  }  #endif
>  
> -static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
> +static void ft_pcie_rc_fix(void *blob, struct ls_pcie *pcie)
>  {
>  	int off;
>  	uint svr;
> @@ -243,12 +243,33 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
>  			return;
>  	}
>  
> -	if (pcie->enabled)
> +	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
> +		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
> +	else
> +		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); }
> +
> +static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie) {
> +	int off;
> +
> +	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
> +					    pcie->dbi_res.start);
> +	if (off < 0)
> +		return;
> +
> +	if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
>  		fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
>  	else
>  		fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);  } 
>  
> +static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) {
> +	ft_pcie_ep_fix(blob, pcie);
> +	ft_pcie_rc_fix(blob, pcie);
> +}

Wouldn't it be faster to check the result of first call before entering the second function? One cannot be both EP and RC, right?

York
[Xiaowei Bao] Hi York, we add the different note in DTS for RC mode and EP mode of one controller, and the compatible also difference, and the status is disabled in default, so we check the it separately. 

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-11-04  5:34 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-26  1:56 [U-Boot] [PATCH 1/3] pci: layerscape: Modify the EP and RC mode judge method Xiaowei Bao
2018-10-26  1:56 ` [U-Boot] [PATCH 2/3] pci: layerscape: Do not scan when PEX work in EP mode Xiaowei Bao
2018-10-26  1:56 ` [U-Boot] [PATCH 3/3] pci: layerscape: Add the dts fixup for EP and RC Xiaowei Bao
2018-11-02 14:52   ` York Sun
2018-11-04  5:34     ` Xiaowei Bao

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