[v4 0/2] Enable Plane Input CSC for ICL

[v4 0/2] Enable Plane Input CSC for ICL

[Uma Shankar]

This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.

This series enables color conversion for Full Range YUV data,
limited range handling will be done as a separate patch.

v2: Separated the patch into 2 parts as per Maarten's comments.
Addressed Ville and Maarten's review comment.

v3: Redesigned the register macro definition as per Matt's comment.
Addressed Maarten's review comment.

v4: Added support for Limited Range Color Handling.

Note: This is currently untested and floated to get feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.

Uma Shankar (2):
  drm/i915/icl: Define Plane Input CSC Coefficient Registers
  drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

 drivers/gpu/drm/i915/i915_reg.h      | 50 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_color.c   | 79 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 23 ++++++++---
 drivers/gpu/drm/i915/intel_drv.h     |  2 +
 4 files changed, 148 insertions(+), 6 deletions(-)

-- 
1.9.1

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[v4 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers

[Uma Shankar]

Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.

v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.

v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.

v4: No Change

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..d806e6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
+#define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
@@ -6585,6 +6586,55 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
 
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+	     _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+	     _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
+	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
 
 #define _PLANE_CTL_1_B				0x71180
 #define _PLANE_CTL_2_B				0x71280
-- 
1.9.1

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[v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

[Uma Shankar]

Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.

This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.

Note: This is currently untested and floated to get an early feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.

v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.

v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.

v4: Added support for Limited Range Color Handling

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 79 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 23 ++++++++---
 drivers/gpu/drm/i915/intel_drv.h     |  2 +
 3 files changed, 98 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..3a52d92 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
 #define CSC_RGB_TO_YUV_BV 0x1e080000
 
+#define  ROFF(x)          (((x) & 0xffff) << 16)
+#define  GOFF(x)          (((x) & 0xffff) << 0)
+#define  BOFF(x)          (((x) & 0xffff) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI		0x800
+#define PREOFF_YUV_TO_RGB_ME		0xF00
+#define PREOFF_YUV_TO_RGB_LO		0x800
+
 /*
  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  * format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
 	return -EINVAL;
 }
 
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv =
+		to_i915(plane_state->base.plane->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	enum pipe pipe = crtc->pipe;
+	struct intel_plane *intel_plane =
+		to_intel_plane(plane_state->base.plane);
+	enum plane_id plane = intel_plane->id;
+
+	static const u16 input_csc_matrix[][9] = {
+		/* BT.601 full range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x7AF8, 7800, 0x0,
+			0x8B28, 7800, 0x9AC0,
+			0x0, 7800, 0x7DD8,
+		},
+		/* BT.709 full range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x7C98, 7800, 0x0,
+			0x9EF8, 7800, 0xABF8,
+			0x0, 0x7800,  0x7ED8,
+		},
+	};
+
+	/* Matrix for Limited Range to Full Range Conversion */
+	static const u16 input_csc_matrix_lr[][9] = {
+		/* BT.601 Limted range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x7CC8, 7950, 0x0,
+			0x8CB8, 7918, 0x9C40,
+			0x0, 7918, 0x7FC8,
+		},
+		/* BT.709 Limited range YCbCr -> full range RGB */
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x7EA8, 7950, 0x0,
+			0x8888, 7918, 0xADA8,
+			0x0, 0x7918,  0x6870,
+		},
+	};
+	const u16 *csc;
+
+	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+		csc = input_csc_matrix[plane_state->base.color_encoding];
+	else
+		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
+
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
+		   GOFF(csc[1]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
+		   GOFF(csc[4]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
+		   GOFF(csc[7]));
+	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
+
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
+		   PREOFF_YUV_TO_RGB_HI);
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
+		   PREOFF_YUV_TO_RGB_ME);
+	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
+		   PREOFF_YUV_TO_RGB_LO);
+
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
+	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0);
+}
+
 void intel_color_init(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fe045ab..d16a064 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	struct drm_i915_private *dev_priv =
 		to_i915(plane_state->base.plane->dev);
 	const struct drm_framebuffer *fb = plane_state->base.fb;
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 	u32 plane_color_ctl = 0;
 
 	if (INTEL_GEN(dev_priv) < 11) {
@@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 
 	if (fb->format->is_yuv) {
-		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
-			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
-		else
-			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+		if (!icl_is_hdr_plane(plane)) {
+			if (plane_state->base.color_encoding ==
+					DRM_COLOR_YCBCR_BT709)
+				plane_color_ctl |=
+					PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
+			else
+				plane_color_ctl |=
+					PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
 
-		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
-			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+			if (plane_state->base.color_range ==
+					DRM_COLOR_YCBCR_FULL_RANGE)
+				plane_color_ctl |=
+				PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+		} else {
+			icl_program_input_csc_coeff(crtc_state, plane_state);
+			plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
+		}
 	}
 
 	return plane_color_ctl;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308..bd9e946 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+				 const struct intel_plane_state *plane_state);
 
 /* intel_lspcon.c */
 bool lspcon_init(struct intel_digital_port *intel_dig_port);
-- 
1.9.1

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Re: [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

[Matt Roper]

On Fri, Oct 26, 2018 at 03:33:38AM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
> 
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
> 
> Note: This is currently untested and floated to get an early feedback
> on the design and implementation for this feature. In parallel,
> I will test this on actual ICL hardware and confirm with planar
> formats.
> 
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
> 
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
> 
> v4: Added support for Limited Range Color Handling
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c   | 79 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 23 ++++++++---
>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
>  3 files changed, 98 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..3a52d92 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
>  #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
>  #define CSC_RGB_TO_YUV_BV 0x1e080000
>  
> +#define  ROFF(x)          (((x) & 0xffff) << 16)
> +#define  GOFF(x)          (((x) & 0xffff) << 0)
> +#define  BOFF(x)          (((x) & 0xffff) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI		0x800
> +#define PREOFF_YUV_TO_RGB_ME		0xF00
> +#define PREOFF_YUV_TO_RGB_LO		0x800

Doesn't bit #12 need to be set for each of these values (0x1800, 0x1F00,
0x1800)?  At least that's what I came up with based on the assumption
that input CSC is programmed the same way as pipe CSC, but I might be
overlooking or miscalculating something.

The pipe CSC page gives an example of converting YUV to RGB with a table
that matches your csc matrix below, and a note "Program the CSC
Pre-Offsets to -1/2, -1/16, and -1/2."

The bspec indicates the register values here are 13-bits (12:0 in the
register dword) and are 2's complement fractions allowing values between
-1 and 1 (exclusive).  So I take that to mean:

    1/2                     = 0 1000 0000 0000
    -1/2 (one's complement) = 1 0111 1111 1111
    -1/2 (two's complement) = 1 1000 0000 0000 = 0x1800

and

    1/16                     = 0 0001 0000 0000
    -1/16 (one's complement) = 1 1110 1111 1111
    -1/16 (two's complement) = 1 1111 0000 0000 = 0x1F00

Anyway, it would probably be good to give a comment indicating what the
human-readable values you're using are supposed to be and an indication
of how the register is programmed to represent those values.


Matt

> +
>  /*
>   * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>   * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
>  	return -EINVAL;
>  }
>  
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> +				 const struct intel_plane_state *plane_state)
> +{
> +	struct drm_i915_private *dev_priv =
> +		to_i915(plane_state->base.plane->dev);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	struct intel_plane *intel_plane =
> +		to_intel_plane(plane_state->base.plane);
> +	enum plane_id plane = intel_plane->id;
> +
> +	static const u16 input_csc_matrix[][9] = {
> +		/* BT.601 full range YCbCr -> full range RGB */
> +		[DRM_COLOR_YCBCR_BT601] = {
> +			0x7AF8, 7800, 0x0,
> +			0x8B28, 7800, 0x9AC0,
> +			0x0, 7800, 0x7DD8,
> +		},
> +		/* BT.709 full range YCbCr -> full range RGB */
> +		[DRM_COLOR_YCBCR_BT709] = {
> +			0x7C98, 7800, 0x0,
> +			0x9EF8, 7800, 0xABF8,
> +			0x0, 0x7800,  0x7ED8,
> +		},
> +	};
> +
> +	/* Matrix for Limited Range to Full Range Conversion */
> +	static const u16 input_csc_matrix_lr[][9] = {
> +		/* BT.601 Limted range YCbCr -> full range RGB */
> +		[DRM_COLOR_YCBCR_BT601] = {
> +			0x7CC8, 7950, 0x0,
> +			0x8CB8, 7918, 0x9C40,
> +			0x0, 7918, 0x7FC8,
> +		},
> +		/* BT.709 Limited range YCbCr -> full range RGB */
> +		[DRM_COLOR_YCBCR_BT709] = {
> +			0x7EA8, 7950, 0x0,
> +			0x8888, 7918, 0xADA8,
> +			0x0, 0x7918,  0x6870,
> +		},
> +	};
> +	const u16 *csc;
> +
> +	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> +		csc = input_csc_matrix[plane_state->base.color_encoding];
> +	else
> +		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> +
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
> +		   GOFF(csc[1]));
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
> +		   GOFF(csc[4]));
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
> +		   GOFF(csc[7]));
> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
> +
> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
> +		   PREOFF_YUV_TO_RGB_HI);
> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
> +		   PREOFF_YUV_TO_RGB_ME);
> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
> +		   PREOFF_YUV_TO_RGB_LO);
> +
> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0);
> +}
> +
>  void intel_color_init(struct drm_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fe045ab..d16a064 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  	struct drm_i915_private *dev_priv =
>  		to_i915(plane_state->base.plane->dev);
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
> +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>  	u32 plane_color_ctl = 0;
>  
>  	if (INTEL_GEN(dev_priv) < 11) {
> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>  
>  	if (fb->format->is_yuv) {
> -		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> -			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> -		else
> -			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> +		if (!icl_is_hdr_plane(plane)) {
> +			if (plane_state->base.color_encoding ==
> +					DRM_COLOR_YCBCR_BT709)
> +				plane_color_ctl |=
> +					PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> +			else
> +				plane_color_ctl |=
> +					PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>  
> -		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> -			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> +			if (plane_state->base.color_range ==
> +					DRM_COLOR_YCBCR_FULL_RANGE)
> +				plane_color_ctl |=
> +				PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> +		} else {
> +			icl_program_input_csc_coeff(crtc_state, plane_state);
> +			plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> +		}
>  	}
>  
>  	return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index db24308..bd9e946 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
>  void intel_color_set_csc(struct drm_crtc_state *crtc_state);
>  void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> +				 const struct intel_plane_state *plane_state);
>  
>  /* intel_lspcon.c */
>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [v4 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers

[Matt Roper]

On Fri, Oct 26, 2018 at 03:33:37AM +0530, Uma Shankar wrote:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3 planes
> have this capability.
> 
> v2: Segregated the register macro definition as separate patch
> as per Maarten's suggestion.
> 
> v3: Removed a redundant 3rd Pipe register definition and
> simplified the equally spaced register definition by adding an
> offset as per Matt's comment.
> 
> v4: No Change
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 69eb573..d806e6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6569,6 +6569,7 @@ enum {
>  #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
>  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30) /* Pre-ICL */
>  #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE	(1 << 28)
> +#define   PLANE_COLOR_INPUT_CSC_ENABLE		(1 << 20) /* ICL+ */
>  #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23) /* Pre-ICL */
>  #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
>  #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709		(1 << 17)
> @@ -6585,6 +6586,55 @@ enum {
>  #define _PLANE_NV12_BUF_CFG_1_A		0x70278
>  #define _PLANE_NV12_BUF_CFG_2_A		0x70378
>  
> +/* Input CSC Register Definitions */
> +#define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> +	     _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> +	     _PLANE_INPUT_CSC_RY_GY_2_B)
> +
> +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\

The _REG suffix on these names could probably be dropped to make them a
bit shorter.  But otherwise, these match all the offsets I see in the
bspec, so

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> +	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
> +		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> +	     _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> +	     _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
> +	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> +		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> +	     _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)	\
> +	_PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> +	     _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
> +	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> +		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>  
>  #define _PLANE_CTL_1_B				0x71180
>  #define _PLANE_CTL_2_B				0x71280
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev3)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev3)
URL   : https://patchwork.freedesktop.org/series/51463/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
99febf0a6212 drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:6603:
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)

-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:6603:
+#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+		    _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)

-:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:6619:
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)

-:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:6619:
+#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)

-:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#86: FILE: drivers/gpu/drm/i915/i915_reg.h:6635:
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)

-:86: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#86: FILE: drivers/gpu/drm/i915/i915_reg.h:6635:
+#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index)	\
+	_MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+		    _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)

total: 0 errors, 0 warnings, 6 checks, 62 lines checked
ca48ad67d283 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

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✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev3)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev3)
URL   : https://patchwork.freedesktop.org/series/51463/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!

Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev3)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev3)
URL   : https://patchwork.freedesktop.org/series/51463/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5038 -> Patchwork_10587 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/3/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10587 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-modeset:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106000)

    igt@kms_flip@basic-plain-flip:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-skl-6700k2:      PASS -> INCOMPLETE (fdo#104108, k.org#199541, fdo#105524)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-icl-u:           NOTRUN -> FAIL (fdo#103375) +1

    
    ==== Possible fixes ====

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-WARN (fdo#102614) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
      fi-glk-j4005:       DMESG-WARN (fdo#106000) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541


== Participating hosts (46 -> 44) ==

  Additional (1): fi-icl-u 
  Missing    (3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_5038 -> Patchwork_10587

  CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10587: ca48ad67d283f6b861e6acfbe8ba7b6cfba5ebae @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ca48ad67d283 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
99febf0a6212 drm/i915/icl: Define Plane Input CSC Coefficient Registers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10587/issues.html
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✗ Fi.CI.IGT: failure for Enable Plane Input CSC for ICL (rev3)

[Patchwork]

== Series Details ==

Series: Enable Plane Input CSC for ICL (rev3)
URL   : https://patchwork.freedesktop.org/series/51463/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5038_full -> Patchwork_10587_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10587_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10587_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10587_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_busy@close-race:
      shard-apl:          PASS -> DMESG-FAIL

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          PASS -> SKIP
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10587_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411, fdo#106886)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956) +2

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          PASS -> FAIL (fdo#108147)

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +2

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#103191)

    igt@kms_cursor_crc@cursor-256x256-onscreen:
      shard-skl:          NOTRUN -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-64x64-dpms:
      shard-glk:          PASS -> FAIL (fdo#103232) +1

    igt@kms_fbcon_fbt@psr-suspend:
      shard-skl:          NOTRUN -> FAIL (fdo#107882) +1

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
      shard-glk:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
      shard-skl:          NOTRUN -> FAIL (fdo#105683)

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-apl:          PASS -> FAIL (fdo#103166) +1

    igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
      shard-skl:          NOTRUN -> FAIL (fdo#107815, fdo#108145) +1

    igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +3

    igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
      shard-glk:          PASS -> FAIL (fdo#108145) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@gem_busy@close-race:
      shard-glk:          DMESG-FAIL -> PASS

    igt@kms_cursor_crc@cursor-128x128-onscreen:
      shard-glk:          FAIL (fdo#103232) -> PASS +1

    igt@kms_cursor_crc@cursor-128x128-sliding:
      shard-apl:          FAIL (fdo#103232) -> PASS +1

    igt@kms_cursor_crc@cursor-256x256-dpms:
      shard-skl:          FAIL (fdo#103232) -> PASS

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-skl:          INCOMPLETE (fdo#104108) -> PASS

    igt@kms_draw_crc@fill-fb:
      shard-skl:          FAIL (fdo#103184) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-rte:
      shard-glk:          FAIL (fdo#103167, fdo#105682) -> PASS

    igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
      shard-skl:          FAIL (fdo#107815, fdo#108145) -> PASS

    igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-glk:          FAIL (fdo#103166) -> PASS

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@perf@polling:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
    ==== Warnings ====

    igt@kms_cursor_crc@cursor-64x64-sliding:
      shard-apl:          FAIL (fdo#103232) -> DMESG-WARN (fdo#108549)

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          DMESG-FAIL (fdo#103167, fdo#108549) -> DMESG-WARN (fdo#108549)

    
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#108549 https://bugs.freedesktop.org/show_bug.cgi?id=108549
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5038 -> Patchwork_10587

  CI_DRM_5038: 96ecfb04d5acfcc565068c09afd6d0d713b2ddef @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4695: 81b66cf2806d6a8e9516580fb31879677487d32b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10587: ca48ad67d283f6b861e6acfbe8ba7b6cfba5ebae @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10587/shards.html
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Re: [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

[Maarten Lankhorst]

Op 26-10-18 om 00:11 schreef Matt Roper:
> On Fri, Oct 26, 2018 at 03:33:38AM +0530, Uma Shankar wrote:
>> Plane input CSC needs to be enabled to convert frambuffers from
>> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
>> the planes have hardcoded conversion and taken care by the legacy
>> code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> Note: This is currently untested and floated to get an early feedback
>> on the design and implementation for this feature. In parallel,
>> I will test this on actual ICL hardware and confirm with planar
>> formats.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift
>> issue with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_color.c   | 79 ++++++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_display.c | 23 ++++++++---
>>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
>>  3 files changed, 98 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..3a52d92 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>>  #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
>>  #define CSC_RGB_TO_YUV_BV 0x1e080000
>>  
>> +#define  ROFF(x)          (((x) & 0xffff) << 16)
>> +#define  GOFF(x)          (((x) & 0xffff) << 0)
>> +#define  BOFF(x)          (((x) & 0xffff) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI		0x800
>> +#define PREOFF_YUV_TO_RGB_ME		0xF00
>> +#define PREOFF_YUV_TO_RGB_LO		0x800
> Doesn't bit #12 need to be set for each of these values (0x1800, 0x1F00,
> 0x1800)?  At least that's what I came up with based on the assumption
> that input CSC is programmed the same way as pipe CSC, but I might be
> overlooking or miscalculating something.
>
> The pipe CSC page gives an example of converting YUV to RGB with a table
> that matches your csc matrix below, and a note "Program the CSC
> Pre-Offsets to -1/2, -1/16, and -1/2."
>
> The bspec indicates the register values here are 13-bits (12:0 in the
> register dword) and are 2's complement fractions allowing values between
> -1 and 1 (exclusive).  So I take that to mean:
>
>     1/2                     = 0 1000 0000 0000
>     -1/2 (one's complement) = 1 0111 1111 1111
>     -1/2 (two's complement) = 1 1000 0000 0000 = 0x1800
>
> and
>
>     1/16                     = 0 0001 0000 0000
>     -1/16 (one's complement) = 1 1110 1111 1111
>     -1/16 (two's complement) = 1 1111 0000 0000 = 0x1F00
>
> Anyway, it would probably be good to give a comment indicating what the
> human-readable values you're using are supposed to be and an indication
> of how the register is programmed to represent those values.
>
>
> Matt
>
>> +
>>  /*
>>   * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>>   * format). This macro takes the coefficient we want transformed and the
>> @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
>>  	return -EINVAL;
>>  }
>>  
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> +				 const struct intel_plane_state *plane_state)
>> +{
>> +	struct drm_i915_private *dev_priv =
>> +		to_i915(plane_state->base.plane->dev);
>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> +	enum pipe pipe = crtc->pipe;
>> +	struct intel_plane *intel_plane =
>> +		to_intel_plane(plane_state->base.plane);
>> +	enum plane_id plane = intel_plane->id;
>> +
>> +	static const u16 input_csc_matrix[][9] = {
>> +		/* BT.601 full range YCbCr -> full range RGB */
>> +		[DRM_COLOR_YCBCR_BT601] = {
>> +			0x7AF8, 7800, 0x0,
>> +			0x8B28, 7800, 0x9AC0,
>> +			0x0, 7800, 0x7DD8,
>> +		},
>> +		/* BT.709 full range YCbCr -> full range RGB */
>> +		[DRM_COLOR_YCBCR_BT709] = {
>> +			0x7C98, 7800, 0x0,
>> +			0x9EF8, 7800, 0xABF8,
>> +			0x0, 0x7800,  0x7ED8,
>> +		},
>> +	};
>> +
>> +	/* Matrix for Limited Range to Full Range Conversion */
>> +	static const u16 input_csc_matrix_lr[][9] = {
>> +		/* BT.601 Limted range YCbCr -> full range RGB */
>> +		[DRM_COLOR_YCBCR_BT601] = {
>> +			0x7CC8, 7950, 0x0,
>> +			0x8CB8, 7918, 0x9C40,
>> +			0x0, 7918, 0x7FC8,
I think you forgot to add 0x to the second value, resulting in part hex, part numeric.

~Maarten
>> +		},
>> +		/* BT.709 Limited range YCbCr -> full range RGB */
>> +		[DRM_COLOR_YCBCR_BT709] = {
>> +			0x7EA8, 7950, 0x0,
>> +			0x8888, 7918, 0xADA8,
>> +			0x0, 0x7918,  0x6870,
>> +		},
>> +	};
>> +	const u16 *csc;
>> +
>> +	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
>> +		csc = input_csc_matrix[plane_state->base.color_encoding];
>> +	else
>> +		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>> +
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0), ROFF(csc[0]) |
>> +		   GOFF(csc[1]));
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1), BOFF(csc[2]));
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2), ROFF(csc[3]) |
>> +		   GOFF(csc[4]));
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3), BOFF(csc[5]));
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4), ROFF(csc[6]) |
>> +		   GOFF(csc[7]));
>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5), BOFF(csc[8]));
>> +
>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
>> +		   PREOFF_YUV_TO_RGB_HI);
>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
>> +		   PREOFF_YUV_TO_RGB_ME);
>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
>> +		   PREOFF_YUV_TO_RGB_LO);
>> +
>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0);
>> +}
>> +
>>  void intel_color_init(struct drm_crtc *crtc)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index fe045ab..d16a064 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>>  	struct drm_i915_private *dev_priv =
>>  		to_i915(plane_state->base.plane->dev);
>>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>> +	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>>  	u32 plane_color_ctl = 0;
>>  
>>  	if (INTEL_GEN(dev_priv) < 11) {
>> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>>  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>>  
>>  	if (fb->format->is_yuv) {
>> -		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
>> -			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> -		else
>> -			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>> +		if (!icl_is_hdr_plane(plane)) {
>> +			if (plane_state->base.color_encoding ==
>> +					DRM_COLOR_YCBCR_BT709)
>> +				plane_color_ctl |=
>> +					PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> +			else
>> +				plane_color_ctl |=
>> +					PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>  
>> -		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
>> -			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> +			if (plane_state->base.color_range ==
>> +					DRM_COLOR_YCBCR_FULL_RANGE)
>> +				plane_color_ctl |=
>> +				PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> +		} else {
>> +			icl_program_input_csc_coeff(crtc_state, plane_state);
>> +			plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
>> +		}
>>  	}
>>  
>>  	return plane_color_ctl;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index db24308..bd9e946 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>>  int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
>>  void intel_color_set_csc(struct drm_crtc_state *crtc_state);
>>  void intel_color_load_luts(struct drm_crtc_state *crtc_state);
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> +				 const struct intel_plane_state *plane_state);
>>  
>>  /* intel_lspcon.c */
>>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


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Re: [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion

[Shankar, Uma]

>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Friday, October 26, 2018 2:11 PM
>To: Roper, Matthew D <matthew.d.roper@intel.com>; Shankar, Uma
><uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
>Lankhorst, Maarten <maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v4 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to
>RGB Conversion
>
>Op 26-10-18 om 00:11 schreef Matt Roper:
>> On Fri, Oct 26, 2018 at 03:33:38AM +0530, Uma Shankar wrote:
>>> Plane input CSC needs to be enabled to convert frambuffers from YUV
>>> to RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>>> have hardcoded conversion and taken care by the legacy code.
>>>
>>> This patch defines the co-efficient values for YUV to RGB conversion
>>> in BT709 and BT601 formats. It programs the coefficients and enables
>>> the plane input csc unit in hardware.
>>>
>>> Note: This is currently untested and floated to get an early feedback
>>> on the design and implementation for this feature. In parallel, I
>>> will test this on actual ICL hardware and confirm with planar
>>> formats.
>>>
>>> v2: Addressed Maarten's and Ville's review comments and added the
>>> coefficients in a 2D array instead of independent Macros.
>>>
>>> v3: Added individual coefficient matrix (9 values) instead of 6
>>> register values as per Maarten's comment. Also addresed a shift issue
>>> with B channel coefficient.
>>>
>>> v4: Added support for Limited Range Color Handling
>>>
>>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_color.c   | 79
>++++++++++++++++++++++++++++++++++++
>>>  drivers/gpu/drm/i915/intel_display.c | 23 ++++++++---
>>>  drivers/gpu/drm/i915/intel_drv.h     |  2 +
>>>  3 files changed, 98 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>>> b/drivers/gpu/drm/i915/intel_color.c
>>> index 5127da2..3a52d92 100644
>>> --- a/drivers/gpu/drm/i915/intel_color.c
>>> +++ b/drivers/gpu/drm/i915/intel_color.c
>>> @@ -57,6 +57,15 @@
>>>  #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8  #define
>CSC_RGB_TO_YUV_BV
>>> 0x1e080000
>>>
>>> +#define  ROFF(x)          (((x) & 0xffff) << 16)
>>> +#define  GOFF(x)          (((x) & 0xffff) << 0)
>>> +#define  BOFF(x)          (((x) & 0xffff) << 16)
>>> +
>>> +/* Preoffset values for YUV to RGB Conversion */
>>> +#define PREOFF_YUV_TO_RGB_HI		0x800
>>> +#define PREOFF_YUV_TO_RGB_ME		0xF00
>>> +#define PREOFF_YUV_TO_RGB_LO		0x800
>> Doesn't bit #12 need to be set for each of these values (0x1800,
>> 0x1F00, 0x1800)?  At least that's what I came up with based on the
>> assumption that input CSC is programmed the same way as pipe CSC, but
>> I might be overlooking or miscalculating something.
>>
>> The pipe CSC page gives an example of converting YUV to RGB with a
>> table that matches your csc matrix below, and a note "Program the CSC
>> Pre-Offsets to -1/2, -1/16, and -1/2."
>>
>> The bspec indicates the register values here are 13-bits (12:0 in the
>> register dword) and are 2's complement fractions allowing values
>> between
>> -1 and 1 (exclusive).  So I take that to mean:
>>
>>     1/2                     = 0 1000 0000 0000
>>     -1/2 (one's complement) = 1 0111 1111 1111
>>     -1/2 (two's complement) = 1 1000 0000 0000 = 0x1800
>>
>> and
>>
>>     1/16                     = 0 0001 0000 0000
>>     -1/16 (one's complement) = 1 1110 1111 1111
>>     -1/16 (two's complement) = 1 1111 0000 0000 = 0x1F00
>>
>> Anyway, it would probably be good to give a comment indicating what
>> the human-readable values you're using are supposed to be and an
>> indication of how the register is programmed to represent those values.

Yes, You are right here. Will correct it. Thanks Matt !!

>> Matt
>>
>>> +
>>>  /*
>>>   * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>>>   * format). This macro takes the coefficient we want transformed and
>>> the @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
>>>  	return -EINVAL;
>>>  }
>>>
>>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>>> +				 const struct intel_plane_state *plane_state) {
>>> +	struct drm_i915_private *dev_priv =
>>> +		to_i915(plane_state->base.plane->dev);
>>> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>>> +	enum pipe pipe = crtc->pipe;
>>> +	struct intel_plane *intel_plane =
>>> +		to_intel_plane(plane_state->base.plane);
>>> +	enum plane_id plane = intel_plane->id;
>>> +
>>> +	static const u16 input_csc_matrix[][9] = {
>>> +		/* BT.601 full range YCbCr -> full range RGB */
>>> +		[DRM_COLOR_YCBCR_BT601] = {
>>> +			0x7AF8, 7800, 0x0,
>>> +			0x8B28, 7800, 0x9AC0,
>>> +			0x0, 7800, 0x7DD8,
>>> +		},
>>> +		/* BT.709 full range YCbCr -> full range RGB */
>>> +		[DRM_COLOR_YCBCR_BT709] = {
>>> +			0x7C98, 7800, 0x0,
>>> +			0x9EF8, 7800, 0xABF8,
>>> +			0x0, 0x7800,  0x7ED8,
>>> +		},
>>> +	};
>>> +
>>> +	/* Matrix for Limited Range to Full Range Conversion */
>>> +	static const u16 input_csc_matrix_lr[][9] = {
>>> +		/* BT.601 Limted range YCbCr -> full range RGB */
>>> +		[DRM_COLOR_YCBCR_BT601] = {
>>> +			0x7CC8, 7950, 0x0,
>>> +			0x8CB8, 7918, 0x9C40,
>>> +			0x0, 7918, 0x7FC8,
>I think you forgot to add 0x to the second value, resulting in part hex, part
>numeric.

Oh :( , Yes my bad. Will rectify the error. Thanks

Regards,
Uma Shankar

>~Maarten
>>> +		},
>>> +		/* BT.709 Limited range YCbCr -> full range RGB */
>>> +		[DRM_COLOR_YCBCR_BT709] = {
>>> +			0x7EA8, 7950, 0x0,
>>> +			0x8888, 7918, 0xADA8,
>>> +			0x0, 0x7918,  0x6870,
>>> +		},
>>> +	};
>>> +	const u16 *csc;
>>> +
>>> +	if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>>> +		csc = input_csc_matrix[plane_state->base.color_encoding];
>>> +	else
>>> +		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>>> +
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 0),
>ROFF(csc[0]) |
>>> +		   GOFF(csc[1]));
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 1),
>BOFF(csc[2]));
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 2),
>ROFF(csc[3]) |
>>> +		   GOFF(csc[4]));
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 3),
>BOFF(csc[5]));
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 4),
>ROFF(csc[6]) |
>>> +		   GOFF(csc[7]));
>>> +	I915_WRITE(PLANE_INPUT_CSC_COEFF_REG(pipe, plane, 5),
>>> +BOFF(csc[8]));
>>> +
>>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 0),
>>> +		   PREOFF_YUV_TO_RGB_HI);
>>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 1),
>>> +		   PREOFF_YUV_TO_RGB_ME);
>>> +	I915_WRITE(PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, 2),
>>> +		   PREOFF_YUV_TO_RGB_LO);
>>> +
>>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 0), 0x0);
>>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 1), 0x0);
>>> +	I915_WRITE(PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, 2), 0x0); }
>>> +
>>>  void intel_color_init(struct drm_crtc *crtc)  {
>>>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git
>>> a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index fe045ab..d16a064 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct
>intel_crtc_state *crtc_state,
>>>  	struct drm_i915_private *dev_priv =
>>>  		to_i915(plane_state->base.plane->dev);
>>>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>>> +	struct intel_plane *plane =
>>> +to_intel_plane(plane_state->base.plane);
>>>  	u32 plane_color_ctl = 0;
>>>
>>>  	if (INTEL_GEN(dev_priv) < 11) {
>>> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct
>intel_crtc_state *crtc_state,
>>>  	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>>>
>>>  	if (fb->format->is_yuv) {
>>> -		if (plane_state->base.color_encoding ==
>DRM_COLOR_YCBCR_BT709)
>>> -			plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>>> -		else
>>> -			plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>> +		if (!icl_is_hdr_plane(plane)) {
>>> +			if (plane_state->base.color_encoding ==
>>> +					DRM_COLOR_YCBCR_BT709)
>>> +				plane_color_ctl |=
>>> +
>	PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>>> +			else
>>> +				plane_color_ctl |=
>>> +
>	PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>>
>>> -		if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>>> -			plane_color_ctl |=
>PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>>> +			if (plane_state->base.color_range ==
>>> +					DRM_COLOR_YCBCR_FULL_RANGE)
>>> +				plane_color_ctl |=
>>> +
>	PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>>> +		} else {
>>> +			icl_program_input_csc_coeff(crtc_state, plane_state);
>>> +			plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
>>> +		}
>>>  	}
>>>
>>>  	return plane_color_ctl;
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>>> b/drivers/gpu/drm/i915/intel_drv.h
>>> index db24308..bd9e946 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const
>>> struct intel_crtc_state *old_crtc_  int intel_color_check(struct
>>> drm_crtc *crtc, struct drm_crtc_state *state);  void
>>> intel_color_set_csc(struct drm_crtc_state *crtc_state);  void
>>> intel_color_load_luts(struct drm_crtc_state *crtc_state);
>>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>>> +				 const struct intel_plane_state *plane_state);
>>>
>>>  /* intel_lspcon.c */
>>>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
>>> --
>>> 1.9.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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