[PATCH 1/3] drm/i915: Make number of ddi ports explicit.

* [PATCH 1/3] drm/i915: Make number of ddi ports explicit.
@ 2018-10-26 23:15 Rodrigo Vivi
  2018-10-26 23:15 ` [PATCH 2/3] drm/i915: Prefer direct IS_CANNONLAKE over IS_CNL_WITH_PORT_F Rodrigo Vivi
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2018-10-26 23:15 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Instead of a simple bool that shows if we have ddi ports
or not, let's highlight the number of ddi ports.

So we can use this information to determine the code
path instead of using platforms codenames.

v2: s/ddi_ports/num_ddi_ports (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 5 +++--
 drivers/gpu/drm/i915/intel_device_info.h | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..89f695fb8668 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2629,7 +2629,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
 
-#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
+#define HAS_DDI(dev_priv)		 ((dev_priv)->info.num_ddi_ports > 0)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..da5ca27a976d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -363,7 +363,7 @@ static const struct intel_device_info intel_valleyview_info = {
 #define G75_FEATURES  \
 	GEN7_FEATURES, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
-	.has_ddi = 1, \
+	.num_ddi_ports = 5, \
 	.has_fpga_dbg = 1, \
 	.has_psr = 1, \
 	.has_dp_mst = 1, \
@@ -505,7 +505,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 	.num_pipes = 3, \
 	.has_64bit_reloc = 1, \
-	.has_ddi = 1, \
+	.num_ddi_ports = 3, \
 	.has_fpga_dbg = 1, \
 	.has_fbc = 1, \
 	.has_psr = 1, \
@@ -602,6 +602,7 @@ static const struct intel_device_info intel_cannonlake_info = {
 			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
 			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
 	GEN(11), \
+	.num_ddi_ports = 6, \
 	.ddb_size = 2048, \
 	.has_logical_ring_elsq = 1
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4eae78b..2755d500cf27 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -90,7 +90,6 @@ enum intel_ppgtt {
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
 	func(has_csr); \
-	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_reset_engine); \
 	func(has_fbc); \
@@ -165,6 +164,7 @@ struct intel_device_info {
 
 	u32 display_mmio_offset;
 
+	u8 num_ddi_ports;
 	u8 num_pipes;
 	u8 num_sprites[I915_MAX_PIPES];
 	u8 num_scalers[I915_MAX_PIPES];
-- 
2.19.1

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