* [Qemu-devel] [PATCH v5 01/11] hw/m68k: add via support
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:46 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 02/11] hw/m68k: implement ADB bus support for via Mark Cave-Ayland
` (10 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/misc/Makefile.objs | 1 +
hw/misc/mac_via.c | 666 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/mac_via.h | 107 ++++++++
3 files changed, 774 insertions(+)
create mode 100644 hw/misc/mac_via.c
create mode 100644 include/hw/misc/mac_via.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 680350b3c3..9417bff296 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -73,4 +73,5 @@ obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
+obj-$(CONFIG_MAC_VIA) += mac_via.o
obj-$(CONFIG_MSF2) += msf2-sysreg.o
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
new file mode 100644
index 0000000000..d6d6b86e1a
--- /dev/null
+++ b/hw/misc/mac_via.c
@@ -0,0 +1,666 @@
+/*
+ * QEMU m68k Macintosh VIA device support
+ *
+ * Copyright (c) 2011-2018 Laurent Vivier
+ * Copyright (c) 2018 Mark Cave-Ayland
+ *
+ * Some parts from hw/misc/macio/cuda.c
+ *
+ * Copyright (c) 2004-2007 Fabrice Bellard
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * some parts from linux-2.6.29, arch/m68k/include/asm/mac_via.h
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/misc/mac_via.h"
+#include "hw/misc/mos6522.h"
+#include "hw/input/adb.h"
+#include "sysemu/sysemu.h"
+#include "qapi/error.h"
+#include "qemu/cutils.h"
+
+
+/*
+ * VIAs: There are two in every machine,
+ */
+
+#define VIA_SIZE (0x2000)
+
+/*
+ * Not all of these are true post MacII I think.
+ * CSA: probably the ones CHRP marks as 'unused' change purposes
+ * when the IWM becomes the SWIM.
+ * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
+ * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
+ *
+ * also, http://developer.apple.com/technotes/hw/hw_09.html claims the
+ * following changes for IIfx:
+ * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
+ * Also, "All of the functionality of VIA2 has been moved to other chips".
+ */
+
+#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
+ * [CHRP] SCC WREQ: Reflects the state of the
+ * Wait/Request pins from the SCC.
+ * [Macintosh Family Hardware]
+ * as CHRP on SE/30,II,IIx,IIcx,IIci.
+ * on IIfx, "0 means an active request"
+ */
+#define VIA1A_vRev8 0x40 /* Revision 8 board ???
+ * [CHRP] En WaitReqB: Lets the WaitReq_L
+ * signal from port B of the SCC appear on
+ * the PA7 input pin. Output.
+ * [Macintosh Family] On the SE/30, this
+ * is the bit to flip screen buffers.
+ * 0=alternate, 1=main.
+ * on II,IIx,IIcx,IIci,IIfx this is a bit
+ * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
+ */
+#define VIA1A_vHeadSel 0x20 /* Head select for IWM.
+ * [CHRP] unused.
+ * [Macintosh Family] "Floppy disk
+ * state-control line SEL" on all but IIfx
+ */
+#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
+ * this bit enables the "Overlay" address
+ * map in the address decoders as it is on
+ * reset for mapping the ROM over the reset
+ * vector. 1=use overlay map.
+ * On the IIci,IIfx it is another bit of the
+ * CPU ID: 0=normal IIci, 1=IIci with parity
+ * feature or IIfx.
+ * [CHRP] En WaitReqA: Lets the WaitReq_L
+ * signal from port A of the SCC appear
+ * on the PA7 input pin (CHRP). Output.
+ * [MkLinux] "Drive Select"
+ * (with 0x20 being 'disk head select')
+ */
+#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
+ * 1: select the external serial clock to
+ * drive the SCC's /RTxCA pin.
+ * 0: Select the 3.6864MHz clock to drive
+ * the SCC cell.
+ * [Macintosh Family] Correct on all but IIfx
+ */
+
+/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
+ * on Macs which had the PWM sound hardware. Reserved on newer models.
+ * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
+ * bit 2: 1=IIci, 0=IIfx
+ * bit 1: 1 on both IIci and IIfx.
+ * MkLinux sez bit 0 is 'burnin flag' in this case.
+ * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
+ * inputs, these bits will read 0.
+ */
+#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
+#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
+
+/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
+ * CHRP offers no info. */
+#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
+ * PWM hardware) 0=enabled.
+ * Also, on IIci w/parity, shows parity error
+ * 0=error, 1=OK. */
+#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
+ * On SE/30, vertical sync interrupt enable.
+ * 0=enabled. This vSync interrupt shows up
+ * as a slot $E interrupt. */
+#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
+#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
+#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
+#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
+#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
+#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
+
+/*
+ * VIA2 A register is the interrupt lines raised off the nubus
+ * slots.
+ * The below info is from 'Macintosh Family Hardware.'
+ * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
+ * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
+ * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
+ * Perhaps OSS uses vRAM1 and vRAM2 for ADB.
+ */
+
+#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
+#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
+#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
+#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
+#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
+#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
+#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
+#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
+
+/* RAM size bits decoded as follows:
+ * bit1 bit0 size of ICs in bank A
+ * 0 0 256 kbit
+ * 0 1 1 Mbit
+ * 1 0 4 Mbit
+ * 1 1 16 Mbit
+ */
+
+/*
+ * Register B has the fun stuff in it
+ */
+
+#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
+ * timer T1.
+ * on IIci, parity test: 0=test mode.
+ * [MkLinux] RBV_PARODD: 1=odd,0=even. */
+#define VIA2B_vSndJck 0x40 /* External sound jack status.
+ * 0=plug is inserted. On SE/30, always 0 */
+#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
+#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
+#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
+ * on II, AMU/PMMU control.
+ * if AMU, 0=24bit to 32bit translation
+ * if PMMU, 1=PMMU is accessing page table.
+ * on SE/30 tied low.
+ * on IIx,IIcx,IIfx, unused.
+ * on IIci/RBV, cache control. 0=flush cache.
+ */
+#define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
+ * on SE/30 this signal sent to PDS card.
+ */
+#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
+ * on SE/30 sent to PDS card.
+ */
+#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
+ * on others, 0=disable processor's instruction
+ * and data caches.
+ */
+
+/* interrupt flags */
+
+#define IRQ_SET 0x80
+
+/* common */
+
+#define VIA_IRQ_TIMER1 0x40
+#define VIA_IRQ_TIMER2 0x20
+
+/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
+ * Another example of a valid function that has no ROM support is the use
+ * of the alternate video page for page-flipping animation. Since there
+ * is no ROM call to flip pages, it is necessary to go play with the
+ * right bit in the VIA chip (6522 Versatile Interface Adapter).
+ * [CSA: don't know which one this is, but it's one of 'em!]
+ */
+
+/*
+ * 6522 registers - see databook.
+ * CSA: Assignments for VIA1 confirmed from CHRP spec.
+ */
+
+/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
+/* Note: 15 VIA regs, 8 RBV regs */
+
+#define vBufB 0x0000 /* [VIA/RBV] Register B */
+#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
+#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
+#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
+#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
+#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
+#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
+#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
+#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
+#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
+#define vSR 0x1400 /* [VIA only] Shift register. */
+#define vACR 0x1600 /* [VIA only] Auxilary control register. */
+#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
+ /* CHRP sez never ever to *write* this.
+ * Mac family says never to *change* this.
+ * In fact we need to initialize it once at start.
+ */
+#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
+#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
+#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
+
+/* from linux 2.6 drivers/macintosh/via-macii.c */
+
+/* Bits in ACR */
+
+#define VIA1ACR_vShiftCtrl 0x1c /* Shift register control bits */
+#define VIA1ACR_vShiftExtClk 0x0c /* Shift on external clock */
+#define VIA1ACR_vShiftOut 0x10 /* Shift out if 1 */
+
+/* Apple Macintosh Family Hardware Refenece
+ * Table 19-10 ADB transaction states
+ */
+
+#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2)
+#define VIA1B_vADB_StateShift 4
+
+#define VIA_TIMER_FREQ (783360)
+
+/* VIA returns time offset from Jan 1, 1904, not 1970 */
+#define RTC_OFFSET 2082844800
+
+
+static void via1_VBL(void *opaque)
+{
+ MacVIAState *m = opaque;
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1);
+ MOS6522State *s = MOS6522(v1s);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
+
+ s->ifr |= VIA1_IRQ_VBLANK;
+ mdc->update_irq(s);
+
+ timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630)
+ / 16630 * 16630);
+}
+
+static void via1_one_second(void *opaque)
+{
+ MacVIAState *m = opaque;
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1);
+ MOS6522State *s = MOS6522(v1s);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
+
+ s->ifr |= VIA1_IRQ_ONE_SECOND;
+ mdc->update_irq(s);
+
+ timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL)
+ + 1000) / 1000 * 1000);
+}
+
+static void via1_irq_request(void *opaque, int irq, int level)
+{
+ MOS6522Q800VIA1State *v1s = opaque;
+ MOS6522State *s = MOS6522(v1s);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
+
+ if (level) {
+ s->ifr |= 1 << irq;
+ } else {
+ s->ifr &= ~(1 << irq);
+ }
+
+ mdc->update_irq(s);
+}
+
+static void via2_irq_request(void *opaque, int irq, int level)
+{
+ MOS6522Q800VIA2State *v2s = opaque;
+ MOS6522State *s = MOS6522(v2s);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
+
+ if (level) {
+ s->ifr |= 1 << irq;
+ } else {
+ s->ifr &= ~(1 << irq);
+ }
+
+ mdc->update_irq(s);
+}
+
+static void via1_rtc_update(MacVIAState *m)
+{
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1);
+ MOS6522State *s = MOS6522(v1s);
+
+ if (s->b & VIA1B_vRTCEnb) {
+ return;
+ }
+
+ if (s->dirb & VIA1B_vRTCData) {
+ /* send bits to the RTC */
+ if (!(v1s->last_b & VIA1B_vRTCClk) && (s->b & VIA1B_vRTCClk)) {
+ m->data_out <<= 1;
+ m->data_out |= s->b & VIA1B_vRTCData;
+ m->data_out_cnt++;
+ }
+ } else {
+ /* receive bits from the RTC */
+ if ((v1s->last_b & VIA1B_vRTCClk) &&
+ !(s->b & VIA1B_vRTCClk) &&
+ m->data_in_cnt) {
+ s->b = (s->b & ~VIA1B_vRTCData) |
+ ((m->data_in >> 7) & VIA1B_vRTCData);
+ m->data_in <<= 1;
+ m->data_in_cnt--;
+ }
+ }
+
+ if (m->data_out_cnt == 8) {
+ m->data_out_cnt = 0;
+
+ if (m->cmd == 0) {
+ if (m->data_out & 0x80) {
+ /* this is a read command */
+ uint32_t time = m->tick_offset +
+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
+ NANOSECONDS_PER_SECOND);
+ if (m->data_out == 0x81) { /* seconds register 0 */
+ m->data_in = time & 0xff;
+ m->data_in_cnt = 8;
+ } else if (m->data_out == 0x85) { /* seconds register 1 */
+ m->data_in = (time >> 8) & 0xff;
+ m->data_in_cnt = 8;
+ } else if (m->data_out == 0x89) { /* seconds register 2 */
+ m->data_in = (time >> 16) & 0xff;
+ m->data_in_cnt = 8;
+ } else if (m->data_out == 0x8d) { /* seconds register 3 */
+ m->data_in = (time >> 24) & 0xff;
+ m->data_in_cnt = 8;
+ } else if ((m->data_out & 0xf3) == 0xa1) {
+ /* PRAM address 0x10 -> 0x13 */
+ int addr = (m->data_out >> 2) & 0x03;
+ m->data_in = v1s->PRAM[addr];
+ m->data_in_cnt = 8;
+ } else if ((m->data_out & 0xf3) == 0xa1) {
+ /* PRAM address 0x00 -> 0x0f */
+ int addr = (m->data_out >> 2) & 0x0f;
+ m->data_in = v1s->PRAM[addr];
+ m->data_in_cnt = 8;
+ } else if ((m->data_out & 0xf8) == 0xb8) {
+ /* extended memory designator and sector number */
+ m->cmd = m->data_out;
+ }
+ } else {
+ /* this is a write command */
+ m->cmd = m->data_out;
+ }
+ } else {
+ if (m->cmd & 0x80) {
+ if ((m->cmd & 0xf8) == 0xb8) {
+ /* extended memory designator and sector number */
+ int sector = m->cmd & 0x07;
+ int addr = (m->data_out >> 2) & 0x1f;
+
+ m->data_in = v1s->PRAM[sector * 8 + addr];
+ m->data_in_cnt = 8;
+ }
+ } else if (!m->wprotect) {
+ /* this is a write command */
+ if (m->alt != 0) {
+ /* extended memory designator and sector number */
+ int sector = m->cmd & 0x07;
+ int addr = (m->alt >> 2) & 0x1f;
+
+ v1s->PRAM[sector * 8 + addr] = m->data_out;
+
+ m->alt = 0;
+ } else if (m->cmd == 0x01) { /* seconds register 0 */
+ /* FIXME */
+ } else if (m->cmd == 0x05) { /* seconds register 1 */
+ /* FIXME */
+ } else if (m->cmd == 0x09) { /* seconds register 2 */
+ /* FIXME */
+ } else if (m->cmd == 0x0d) { /* seconds register 3 */
+ /* FIXME */
+ } else if (m->cmd == 0x31) {
+ /* Test Register */
+ } else if (m->cmd == 0x35) {
+ /* Write Protect register */
+ m->wprotect = m->data_out & 1;
+ } else if ((m->cmd & 0xf3) == 0xa1) {
+ /* PRAM address 0x10 -> 0x13 */
+ int addr = (m->cmd >> 2) & 0x03;
+ v1s->PRAM[addr] = m->data_out;
+ } else if ((m->cmd & 0xf3) == 0xa1) {
+ /* PRAM address 0x00 -> 0x0f */
+ int addr = (m->cmd >> 2) & 0x0f;
+ v1s->PRAM[addr] = m->data_out;
+ } else if ((m->cmd & 0xf8) == 0xb8) {
+ /* extended memory designator and sector number */
+ m->alt = m->cmd;
+ }
+ }
+ }
+ m->data_out = 0;
+ }
+}
+
+static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
+{
+ MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
+ MOS6522State *ms = MOS6522(s);
+
+ addr = (addr >> 9) & 0xf;
+ return mos6522_read(ms, addr, size);
+}
+
+static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
+ MOS6522State *ms = MOS6522(s);
+
+ addr = (addr >> 9) & 0xf;
+ mos6522_write(ms, addr, val, size);
+}
+
+static const MemoryRegionOps mos6522_q800_via1_ops = {
+ .read = mos6522_q800_via1_read,
+ .write = mos6522_q800_via1_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size)
+{
+ MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque);
+ MOS6522State *ms = MOS6522(s);
+
+ addr = (addr >> 9) & 0xf;
+ return mos6522_read(ms, addr, size);
+}
+
+static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque);
+ MOS6522State *ms = MOS6522(s);
+
+ addr = (addr >> 9) & 0xf;
+ mos6522_write(ms, addr, val, size);
+}
+
+static const MemoryRegionOps mos6522_q800_via2_ops = {
+ .read = mos6522_q800_via2_read,
+ .write = mos6522_q800_via2_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void mac_via_reset(DeviceState *dev)
+{
+ MacVIAState *m = MAC_VIA(dev);
+
+ timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630)
+ / 16630 * 16630);
+
+ timer_mod(m->one_second_timer, (qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL)
+ + 1000) / 1000 * 1000);
+}
+
+static void mac_via_realize(DeviceState *dev, Error **errp)
+{
+ MacVIAState *m = MAC_VIA(dev);
+ MOS6522State *ms;
+ struct tm tm;
+
+ /* Init VIAs 1 and 2 */
+ sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1,
+ sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1);
+
+ sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2,
+ sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2);
+
+ /* Pass through mos6522 output IRQs */
+ ms = MOS6522(&m->mos6522_via1);
+ object_property_add_alias(OBJECT(dev), "irq[0]", OBJECT(ms),
+ SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort);
+ ms = MOS6522(&m->mos6522_via2);
+ object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms),
+ SYSBUS_DEVICE_GPIO_IRQ "[0]", &error_abort);
+
+ /* Pass through mos6522 input IRQs */
+ qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq");
+ qdev_pass_gpios(DEVICE(&m->mos6522_via2), dev, "via2-irq");
+
+ /* VIA 1 */
+ m->one_second_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, via1_one_second, m);
+ m->VBL_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via1_VBL, m);
+
+ qemu_get_timedate(&tm, 0);
+ m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
+}
+
+static void mac_via_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ MacVIAState *m = MAC_VIA(obj);
+
+ /* MMIO */
+ memory_region_init(&m->mmio, obj, "mac-via", 2 * VIA_SIZE);
+ sysbus_init_mmio(sbd, &m->mmio);
+
+ memory_region_init_io(&m->via1mem, obj, &mos6522_q800_via1_ops,
+ &m->mos6522_via1, "via1", VIA_SIZE);
+ memory_region_add_subregion(&m->mmio, 0x0, &m->via1mem);
+
+ memory_region_init_io(&m->via2mem, obj, &mos6522_q800_via2_ops,
+ &m->mos6522_via2, "via2", VIA_SIZE);
+ memory_region_add_subregion(&m->mmio, VIA_SIZE, &m->via2mem);
+
+ /* ADB */
+ qbus_create_inplace((BusState *)&m->adb_bus, sizeof(m->adb_bus),
+ TYPE_ADB_BUS, DEVICE(obj), "adb.0");
+}
+
+static void mac_via_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = mac_via_realize;
+ dc->reset = mac_via_reset;
+}
+
+static TypeInfo mac_via_info = {
+ .name = TYPE_MAC_VIA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MacVIAState),
+ .instance_init = mac_via_init,
+ .class_init = mac_via_class_init,
+};
+
+/* VIA 1 */
+static void mos6522_q800_via1_portB_write(MOS6522State *s)
+{
+ MOS6522Q800VIA1State *v1s = container_of(s, MOS6522Q800VIA1State,
+ parent_obj);
+ MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1);
+
+ via1_rtc_update(m);
+
+ v1s->last_b = s->b;
+}
+
+static void mos6522_q800_via1_reset(DeviceState *dev)
+{
+ MOS6522State *ms = MOS6522(dev);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
+
+ mdc->parent_reset(dev);
+
+ ms->timers[0].frequency = VIA_TIMER_FREQ;
+ ms->timers[1].frequency = VIA_TIMER_FREQ;
+
+ ms->b = VIA1B_vADB_StateMask | VIA1B_vADBInt | VIA1B_vRTCEnb;
+}
+
+static void mos6522_q800_via1_init(Object *obj)
+{
+ qdev_init_gpio_in_named(DEVICE(obj), via1_irq_request, "via1-irq",
+ VIA1_IRQ_NB);
+}
+
+static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
+
+ dc->reset = mos6522_q800_via1_reset;
+ mdc->portB_write = mos6522_q800_via1_portB_write;
+}
+
+static const TypeInfo mos6522_q800_via1_type_info = {
+ .name = TYPE_MOS6522_Q800_VIA1,
+ .parent = TYPE_MOS6522,
+ .instance_size = sizeof(MOS6522Q800VIA1State),
+ .instance_init = mos6522_q800_via1_init,
+ .class_init = mos6522_q800_via1_class_init,
+};
+
+/* VIA 2 */
+static void mos6522_q800_via2_portB_write(MOS6522State *s)
+{
+ if (s->dirb & VIA2B_vPower && (s->b & VIA2B_vPower) == 0) {
+ /* shutdown */
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ }
+}
+
+static void mos6522_q800_via2_reset(DeviceState *dev)
+{
+ MOS6522State *ms = MOS6522(dev);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
+
+ mdc->parent_reset(dev);
+
+ ms->timers[0].frequency = VIA_TIMER_FREQ;
+ ms->timers[1].frequency = VIA_TIMER_FREQ;
+
+ ms->dirb = 0;
+ ms->b = 0;
+}
+
+static void mos6522_q800_via2_init(Object *obj)
+{
+ qdev_init_gpio_in_named(DEVICE(obj), via2_irq_request, "via2-irq",
+ VIA2_IRQ_NB);
+}
+
+static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
+
+ dc->reset = mos6522_q800_via2_reset;
+ mdc->portB_write = mos6522_q800_via2_portB_write;
+}
+
+static const TypeInfo mos6522_q800_via2_type_info = {
+ .name = TYPE_MOS6522_Q800_VIA2,
+ .parent = TYPE_MOS6522,
+ .instance_size = sizeof(MOS6522Q800VIA2State),
+ .instance_init = mos6522_q800_via2_init,
+ .class_init = mos6522_q800_via2_class_init,
+};
+
+static void mac_via_register_types(void)
+{
+ type_register_static(&mos6522_q800_via1_type_info);
+ type_register_static(&mos6522_q800_via2_type_info);
+ type_register_static(&mac_via_info);
+}
+
+type_init(mac_via_register_types);
diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h
new file mode 100644
index 0000000000..69bdecabb0
--- /dev/null
+++ b/include/hw/misc/mac_via.h
@@ -0,0 +1,107 @@
+/*
+ *
+ * Copyright (c) 2011-2018 Laurent Vivier
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef HW_MISC_MAC_VIA_H
+#define HW_MISC_MAC_VIA_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mos6522.h"
+
+
+/* VIA 1 */
+#define VIA1_IRQ_ONE_SECOND_BIT 0
+#define VIA1_IRQ_VBLANK_BIT 1
+#define VIA1_IRQ_ADB_READY_BIT 2
+#define VIA1_IRQ_ADB_DATA_BIT 3
+#define VIA1_IRQ_ADB_CLOCK_BIT 4
+
+#define VIA1_IRQ_NB 8
+
+#define VIA1_IRQ_ONE_SECOND (1 << VIA1_IRQ_ONE_SECOND_BIT)
+#define VIA1_IRQ_VBLANK (1 << VIA1_IRQ_VBLANK_BIT)
+#define VIA1_IRQ_ADB_READY (1 << VIA1_IRQ_ADB_READY_BIT)
+#define VIA1_IRQ_ADB_DATA (1 << VIA1_IRQ_ADB_DATA_BIT)
+#define VIA1_IRQ_ADB_CLOCK (1 << VIA1_IRQ_ADB_CLOCK_BIT)
+
+
+#define TYPE_MOS6522_Q800_VIA1 "mos6522-q800-via1"
+#define MOS6522_Q800_VIA1(obj) OBJECT_CHECK(MOS6522Q800VIA1State, (obj), \
+ TYPE_MOS6522_Q800_VIA1)
+
+typedef struct MOS6522Q800VIA1State {
+ /*< private >*/
+ MOS6522State parent_obj;
+
+ qemu_irq irqs[VIA1_IRQ_NB];
+ uint8_t last_b;
+ uint8_t PRAM[256];
+} MOS6522Q800VIA1State;
+
+
+/* VIA 2 */
+#define VIA2_IRQ_SCSI_DATA_BIT 0
+#define VIA2_IRQ_SLOT_BIT 1
+#define VIA2_IRQ_UNUSED_BIT 2
+#define VIA2_IRQ_SCSI_BIT 3
+#define VIA2_IRQ_ASC_BIT 4
+
+#define VIA2_IRQ_NB 8
+
+#define VIA2_IRQ_SCSI_DATA (1 << VIA2_IRQ_SCSI_DATA_BIT)
+#define VIA2_IRQ_SLOT (1 << VIA2_IRQ_SLOT_BIT)
+#define VIA2_IRQ_UNUSED (1 << VIA2_IRQ_SCSI_BIT)
+#define VIA2_IRQ_SCSI (1 << VIA2_IRQ_UNUSED_BIT)
+#define VIA2_IRQ_ASC (1 << VIA2_IRQ_ASC_BIT)
+
+#define TYPE_MOS6522_Q800_VIA2 "mos6522-q800-via2"
+#define MOS6522_Q800_VIA2(obj) OBJECT_CHECK(MOS6522Q800VIA2State, (obj), \
+ TYPE_MOS6522_Q800_VIA2)
+
+typedef struct MOS6522Q800VIA2State {
+ /*< private >*/
+ MOS6522State parent_obj;
+} MOS6522Q800VIA2State;
+
+
+#define TYPE_MAC_VIA "mac_via"
+#define MAC_VIA(obj) OBJECT_CHECK(MacVIAState, (obj), TYPE_MAC_VIA)
+
+typedef struct MacVIAState {
+ SysBusDevice busdev;
+
+ /* MMIO */
+ MemoryRegion mmio;
+ MemoryRegion via1mem;
+ MemoryRegion via2mem;
+
+ /* VIAs */
+ MOS6522Q800VIA1State mos6522_via1;
+ MOS6522Q800VIA2State mos6522_via2;
+
+ /* RTC */
+ uint32_t tick_offset;
+
+ uint8_t data_out;
+ int data_out_cnt;
+ uint8_t data_in;
+ uint8_t data_in_cnt;
+ uint8_t cmd;
+ int wprotect;
+ int alt;
+
+ /* ADB */
+ ADBBusState adb_bus;
+
+ /* external timers */
+ QEMUTimer *one_second_timer;
+ QEMUTimer *VBL_timer;
+
+} MacVIAState;
+
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 01/11] hw/m68k: add via support
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 01/11] hw/m68k: add via support Mark Cave-Ayland
@ 2018-10-30 6:46 ` Hervé Poussineau
0 siblings, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:46 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/misc/Makefile.objs | 1 +
> hw/misc/mac_via.c | 666 ++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/misc/mac_via.h | 107 ++++++++
> 3 files changed, 774 insertions(+)
> create mode 100644 hw/misc/mac_via.c
> create mode 100644 include/hw/misc/mac_via.h
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 02/11] hw/m68k: implement ADB bus support for via
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 01/11] hw/m68k: add via support Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:46 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit Mark Cave-Ayland
` (9 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/misc/mac_via.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/mac_via.h | 7 ++
2 files changed, 197 insertions(+)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index d6d6b86e1a..0fc8d0a038 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -237,10 +237,16 @@
* Table 19-10 ADB transaction states
*/
+#define ADB_STATE_NEW 0
+#define ADB_STATE_EVEN 1
+#define ADB_STATE_ODD 2
+#define ADB_STATE_IDLE 3
+
#define VIA1B_vADB_StateMask (VIA1B_vADBS1 | VIA1B_vADBS2)
#define VIA1B_vADB_StateShift 4
#define VIA_TIMER_FREQ (783360)
+#define VIA_ADB_POLL_FREQ 50 /* XXX: not real */
/* VIA returns time offset from Jan 1, 1904, not 1970 */
#define RTC_OFFSET 2082844800
@@ -422,6 +428,181 @@ static void via1_rtc_update(MacVIAState *m)
}
}
+static int adb_via_poll(MacVIAState *s, int state, uint8_t *data)
+{
+ if (state != ADB_STATE_IDLE) {
+ return 0;
+ }
+
+ if (s->adb_data_in_size < s->adb_data_in_index) {
+ return 0;
+ }
+
+ if (s->adb_data_out_index != 0) {
+ return 0;
+ }
+
+ s->adb_data_in_index = 0;
+ s->adb_data_out_index = 0;
+ s->adb_data_in_size = adb_poll(&s->adb_bus, s->adb_data_in, 0xffff);
+
+ if (s->adb_data_in_size) {
+ *data = s->adb_data_in[s->adb_data_in_index++];
+ qemu_irq_raise(s->adb_data_ready);
+ }
+
+ return s->adb_data_in_size;
+}
+
+static int adb_via_send(MacVIAState *s, int state, uint8_t data)
+{
+ switch (state) {
+ case ADB_STATE_NEW:
+ s->adb_data_out_index = 0;
+ break;
+ case ADB_STATE_EVEN:
+ if ((s->adb_data_out_index & 1) == 0) {
+ return 0;
+ }
+ break;
+ case ADB_STATE_ODD:
+ if (s->adb_data_out_index & 1) {
+ return 0;
+ }
+ break;
+ case ADB_STATE_IDLE:
+ return 0;
+ }
+
+ assert(s->adb_data_out_index < sizeof(s->adb_data_out) - 1);
+
+ s->adb_data_out[s->adb_data_out_index++] = data;
+ qemu_irq_raise(s->adb_data_ready);
+ return 1;
+}
+
+static int adb_via_receive(MacVIAState *s, int state, uint8_t *data)
+{
+ switch (state) {
+ case ADB_STATE_NEW:
+ return 0;
+
+ case ADB_STATE_EVEN:
+ if (s->adb_data_in_size <= 0) {
+ qemu_irq_raise(s->adb_data_ready);
+ return 0;
+ }
+
+ if (s->adb_data_in_index >= s->adb_data_in_size) {
+ *data = 0;
+ qemu_irq_raise(s->adb_data_ready);
+ return 1;
+ }
+
+ if ((s->adb_data_in_index & 1) == 0) {
+ return 0;
+ }
+
+ break;
+
+ case ADB_STATE_ODD:
+ if (s->adb_data_in_size <= 0) {
+ qemu_irq_raise(s->adb_data_ready);
+ return 0;
+ }
+
+ if (s->adb_data_in_index >= s->adb_data_in_size) {
+ *data = 0;
+ qemu_irq_raise(s->adb_data_ready);
+ return 1;
+ }
+
+ if (s->adb_data_in_index & 1) {
+ return 0;
+ }
+
+ break;
+
+ case ADB_STATE_IDLE:
+ if (s->adb_data_out_index == 0) {
+ return 0;
+ }
+
+ s->adb_data_in_size = adb_request(&s->adb_bus, s->adb_data_in,
+ s->adb_data_out,
+ s->adb_data_out_index);
+ s->adb_data_out_index = 0;
+ s->adb_data_in_index = 0;
+ if (s->adb_data_in_size < 0) {
+ *data = 0xff;
+ qemu_irq_raise(s->adb_data_ready);
+ return -1;
+ }
+
+ if (s->adb_data_in_size == 0) {
+ return 0;
+ }
+
+ break;
+ }
+
+ assert(s->adb_data_in_index < sizeof(s->adb_data_in) - 1);
+
+ *data = s->adb_data_in[s->adb_data_in_index++];
+ qemu_irq_raise(s->adb_data_ready);
+ if (*data == 0xff || *data == 0) {
+ return 0;
+ }
+ return 1;
+}
+
+static void via1_adb_update(MacVIAState *m)
+{
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1);
+ MOS6522State *s = MOS6522(v1s);
+ int state;
+ int ret;
+
+ state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift;
+
+ if (s->acr & VIA1ACR_vShiftOut) {
+ /* output mode */
+ ret = adb_via_send(m, state, s->sr);
+ if (ret > 0) {
+ s->b &= ~VIA1B_vADBInt;
+ } else {
+ s->b |= VIA1B_vADBInt;
+ }
+ } else {
+ /* input mode */
+ ret = adb_via_receive(m, state, &s->sr);
+ if (ret > 0 && s->sr != 0xff) {
+ s->b &= ~VIA1B_vADBInt;
+ } else {
+ s->b |= VIA1B_vADBInt;
+ }
+ }
+}
+
+static void via_adb_poll(void *opaque)
+{
+ MacVIAState *m = opaque;
+ MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(&m->mos6522_via1);
+ MOS6522State *s = MOS6522(v1s);
+ int state;
+
+ if (s->b & VIA1B_vADBInt) {
+ state = (s->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift;
+ if (adb_via_poll(m, state, &s->sr)) {
+ s->b &= ~VIA1B_vADBInt;
+ }
+ }
+
+ timer_mod(m->adb_poll_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ));
+}
+
static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque);
@@ -484,6 +665,10 @@ static void mac_via_reset(DeviceState *dev)
{
MacVIAState *m = MAC_VIA(dev);
+ timer_mod(m->adb_poll_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+ (NANOSECONDS_PER_SECOND / VIA_ADB_POLL_FREQ));
+
timer_mod(m->VBL_timer, (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 16630)
/ 16630 * 16630);
@@ -522,6 +707,10 @@ static void mac_via_realize(DeviceState *dev, Error **errp)
qemu_get_timedate(&tm, 0);
m->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
+
+ m->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, via_adb_poll, m);
+ m->adb_data_ready = qdev_get_gpio_in_named(dev, "via1-irq",
+ VIA1_IRQ_ADB_READY_BIT);
}
static void mac_via_init(Object *obj)
@@ -570,6 +759,7 @@ static void mos6522_q800_via1_portB_write(MOS6522State *s)
MacVIAState *m = container_of(v1s, MacVIAState, mos6522_via1);
via1_rtc_update(m);
+ via1_adb_update(m);
v1s->last_b = s->b;
}
diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h
index 69bdecabb0..2181140293 100644
--- a/include/hw/misc/mac_via.h
+++ b/include/hw/misc/mac_via.h
@@ -97,6 +97,13 @@ typedef struct MacVIAState {
/* ADB */
ADBBusState adb_bus;
+ QEMUTimer *adb_poll_timer;
+ qemu_irq adb_data_ready;
+ int adb_data_in_size;
+ int adb_data_in_index;
+ int adb_data_out_index;
+ uint8_t adb_data_in[128];
+ uint8_t adb_data_out[16];
/* external timers */
QEMUTimer *one_second_timer;
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 02/11] hw/m68k: implement ADB bus support for via
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 02/11] hw/m68k: implement ADB bus support for via Mark Cave-Ayland
@ 2018-10-30 6:46 ` Hervé Poussineau
0 siblings, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:46 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/misc/mac_via.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/misc/mac_via.h | 7 ++
> 2 files changed, 197 insertions(+)
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 01/11] hw/m68k: add via support Mark Cave-Ayland
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 02/11] hw/m68k: implement ADB bus support for via Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-29 23:36 ` Philippe Mathieu-Daudé
2018-10-30 6:46 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 04/11] hw/m68k: add macfb video card Mark Cave-Ayland
` (8 subsequent siblings)
11 siblings, 2 replies; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
On Sparc and PowerMac, the bit 0 of the address
selects the register type (control or data) and
bit 1 selects the channel (B or A).
On m68k Macintosh, the bit 0 selects the channel and
bit 1 the register type.
This patch introduces a new parameter (bit_swap) to
the device interface to indicate bits usage must
be swapped between registers and channels.
For the moment all the machines use the bit 0,
but this change will be needed to emulate Quadra 800.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/char/escc.c | 30 ++++++++++++++++++++++++------
include/hw/char/escc.h | 1 +
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 628f5f81f7..cec75b06f9 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -42,14 +42,21 @@
* mouse and keyboard ports don't implement all functions and they are
* only asynchronous. There is no DMA.
*
- * Z85C30 is also used on PowerMacs. There are some small differences
- * between Sparc version (sunzilog) and PowerMac (pmac):
+ * Z85C30 is also used on PowerMacs and m68k Macs.
+ *
+ * There are some small differences between Sparc version (sunzilog)
+ * and PowerMac (pmac):
* Offset between control and data registers
* There is some kind of lockup bug, but we can ignore it
* CTS is inverted
* DMA on pmac using DBDMA chip
* pmac can do IRDA and faster rates, sunzilog can only do 38400
* pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
+ *
+ * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog),
+ * but registers are grouped by type and not by channel:
+ * channel is selected by bit 0 of the address (instead of bit 1)
+ * and register is selected by bit 1 of the address (instead of bit 0).
*/
/*
@@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val);
static int serial_can_receive(void *opaque);
static void serial_receive_byte(ESCCChannelState *s, int ch);
+static int reg_shift(ESCCState *s)
+{
+ return s->bit_swap ? s->it_shift + 1 : s->it_shift;
+}
+
+static int chn_shift(ESCCState *s)
+{
+ return s->bit_swap ? s->it_shift : s->it_shift + 1;
+}
+
static void clear_queue(void *opaque)
{
ESCCChannelState *s = opaque;
@@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr,
int newreg, channel;
val &= 0xff;
- saddr = (addr >> serial->it_shift) & 1;
- channel = (addr >> (serial->it_shift + 1)) & 1;
+ saddr = (addr >> reg_shift(serial)) & 1;
+ channel = (addr >> chn_shift(serial)) & 1;
s = &serial->chn[channel];
switch (saddr) {
case SERIAL_CTRL:
@@ -537,8 +554,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
uint32_t ret;
int channel;
- saddr = (addr >> serial->it_shift) & 1;
- channel = (addr >> (serial->it_shift + 1)) & 1;
+ saddr = (addr >> reg_shift(serial)) & 1;
+ channel = (addr >> chn_shift(serial)) & 1;
s = &serial->chn[channel];
switch (saddr) {
case SERIAL_CTRL:
@@ -822,6 +839,7 @@ static void escc_realize(DeviceState *dev, Error **errp)
static Property escc_properties[] = {
DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0),
DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0),
+ DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false),
DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h
index 42aca83611..8762f61c14 100644
--- a/include/hw/char/escc.h
+++ b/include/hw/char/escc.h
@@ -50,6 +50,7 @@ typedef struct ESCCState {
struct ESCCChannelState chn[2];
uint32_t it_shift;
+ bool bit_swap;
MemoryRegion mmio;
uint32_t disabled;
uint32_t frequency;
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit Mark Cave-Ayland
@ 2018-10-29 23:36 ` Philippe Mathieu-Daudé
2018-10-30 9:38 ` Mark Cave-Ayland
2018-10-30 6:46 ` Hervé Poussineau
1 sibling, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-29 23:36 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: qemu-devel@nongnu.org Developers, Kevin Wolf, Fam Zheng,
open list:Block layer core, Jason Wang, Dr. David Alan Gilbert,
Max Reitz, Hervé Poussineau, Gerd Hoffmann, Paolo Bonzini,
Andreas Färber, Aurelien Jarno, Laurent Vivier
Hi Marc, Laurent.
On Mon, Oct 29, 2018 at 2:43 PM Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> From: Laurent Vivier <laurent@vivier.eu>
>
> On Sparc and PowerMac, the bit 0 of the address
> selects the register type (control or data) and
> bit 1 selects the channel (B or A).
>
> On m68k Macintosh, the bit 0 selects the channel and
> bit 1 the register type.
>
> This patch introduces a new parameter (bit_swap) to
> the device interface to indicate bits usage must
> be swapped between registers and channels.
>
> For the moment all the machines use the bit 0,
> but this change will be needed to emulate Quadra 800.
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/char/escc.c | 30 ++++++++++++++++++++++++------
> include/hw/char/escc.h | 1 +
> 2 files changed, 25 insertions(+), 6 deletions(-)
>
> diff --git a/hw/char/escc.c b/hw/char/escc.c
> index 628f5f81f7..cec75b06f9 100644
> --- a/hw/char/escc.c
> +++ b/hw/char/escc.c
> @@ -42,14 +42,21 @@
> * mouse and keyboard ports don't implement all functions and they are
> * only asynchronous. There is no DMA.
> *
> - * Z85C30 is also used on PowerMacs. There are some small differences
> - * between Sparc version (sunzilog) and PowerMac (pmac):
> + * Z85C30 is also used on PowerMacs and m68k Macs.
> + *
> + * There are some small differences between Sparc version (sunzilog)
> + * and PowerMac (pmac):
> * Offset between control and data registers
> * There is some kind of lockup bug, but we can ignore it
> * CTS is inverted
> * DMA on pmac using DBDMA chip
> * pmac can do IRDA and faster rates, sunzilog can only do 38400
> * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
> + *
> + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog),
> + * but registers are grouped by type and not by channel:
> + * channel is selected by bit 0 of the address (instead of bit 1)
> + * and register is selected by bit 1 of the address (instead of bit 0).
If I understand the datashit correctly, the case bit_swap=true is the
default implementation of the Z85C30,
and the current QEMU implementation (from this patch view:
bit_swap=false) is not: it is PowerMac specific.
I think the PowerMac uses an evolved Z85C30 with more precise IRQ lines.
Anyway, not a blocker, but I wanted to share my view that this model
is eventually going in an incorrect direction.
I'll try to suggest a patch to clean this during the next merge window.
Regards,
Phil.
> */
>
> /*
> @@ -169,6 +176,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val);
> static int serial_can_receive(void *opaque);
> static void serial_receive_byte(ESCCChannelState *s, int ch);
>
> +static int reg_shift(ESCCState *s)
> +{
> + return s->bit_swap ? s->it_shift + 1 : s->it_shift;
> +}
> +
> +static int chn_shift(ESCCState *s)
> +{
> + return s->bit_swap ? s->it_shift : s->it_shift + 1;
> +}
> +
> static void clear_queue(void *opaque)
> {
> ESCCChannelState *s = opaque;
> @@ -433,8 +450,8 @@ static void escc_mem_write(void *opaque, hwaddr addr,
> int newreg, channel;
>
> val &= 0xff;
> - saddr = (addr >> serial->it_shift) & 1;
> - channel = (addr >> (serial->it_shift + 1)) & 1;
> + saddr = (addr >> reg_shift(serial)) & 1;
> + channel = (addr >> chn_shift(serial)) & 1;
> s = &serial->chn[channel];
> switch (saddr) {
> case SERIAL_CTRL:
> @@ -537,8 +554,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
> uint32_t ret;
> int channel;
>
> - saddr = (addr >> serial->it_shift) & 1;
> - channel = (addr >> (serial->it_shift + 1)) & 1;
> + saddr = (addr >> reg_shift(serial)) & 1;
> + channel = (addr >> chn_shift(serial)) & 1;
> s = &serial->chn[channel];
> switch (saddr) {
> case SERIAL_CTRL:
> @@ -822,6 +839,7 @@ static void escc_realize(DeviceState *dev, Error **errp)
> static Property escc_properties[] = {
> DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0),
> DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0),
> + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false),
> DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0),
> DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0),
> DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0),
> diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h
> index 42aca83611..8762f61c14 100644
> --- a/include/hw/char/escc.h
> +++ b/include/hw/char/escc.h
> @@ -50,6 +50,7 @@ typedef struct ESCCState {
>
> struct ESCCChannelState chn[2];
> uint32_t it_shift;
> + bool bit_swap;
> MemoryRegion mmio;
> uint32_t disabled;
> uint32_t frequency;
> --
> 2.11.0
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit
2018-10-29 23:36 ` Philippe Mathieu-Daudé
@ 2018-10-30 9:38 ` Mark Cave-Ayland
0 siblings, 0 replies; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 9:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Kevin Wolf, Fam Zheng, open list:Block layer core, Jason Wang,
qemu-devel@nongnu.org Developers, Dr. David Alan Gilbert,
Hervé Poussineau, Gerd Hoffmann, Paolo Bonzini, Max Reitz,
Andreas Färber, Aurelien Jarno, Laurent Vivier
On 29/10/2018 23:36, Philippe Mathieu-Daudé wrote:
> Hi Marc, Laurent.
>
> On Mon, Oct 29, 2018 at 2:43 PM Mark Cave-Ayland
> <mark.cave-ayland@ilande.co.uk> wrote:
>>
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> On Sparc and PowerMac, the bit 0 of the address
>> selects the register type (control or data) and
>> bit 1 selects the channel (B or A).
>>
>> On m68k Macintosh, the bit 0 selects the channel and
>> bit 1 the register type.
>>
>> This patch introduces a new parameter (bit_swap) to
>> the device interface to indicate bits usage must
>> be swapped between registers and channels.
>>
>> For the moment all the machines use the bit 0,
>> but this change will be needed to emulate Quadra 800.
>>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/char/escc.c | 30 ++++++++++++++++++++++++------
>> include/hw/char/escc.h | 1 +
>> 2 files changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/hw/char/escc.c b/hw/char/escc.c
>> index 628f5f81f7..cec75b06f9 100644
>> --- a/hw/char/escc.c
>> +++ b/hw/char/escc.c
>> @@ -42,14 +42,21 @@
>> * mouse and keyboard ports don't implement all functions and they are
>> * only asynchronous. There is no DMA.
>> *
>> - * Z85C30 is also used on PowerMacs. There are some small differences
>> - * between Sparc version (sunzilog) and PowerMac (pmac):
>> + * Z85C30 is also used on PowerMacs and m68k Macs.
>> + *
>> + * There are some small differences between Sparc version (sunzilog)
>> + * and PowerMac (pmac):
>> * Offset between control and data registers
>> * There is some kind of lockup bug, but we can ignore it
>> * CTS is inverted
>> * DMA on pmac using DBDMA chip
>> * pmac can do IRDA and faster rates, sunzilog can only do 38400
>> * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
>> + *
>> + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog),
>> + * but registers are grouped by type and not by channel:
>> + * channel is selected by bit 0 of the address (instead of bit 1)
>> + * and register is selected by bit 1 of the address (instead of bit 0).
>
> If I understand the datashit correctly, the case bit_swap=true is the
> default implementation of the Z85C30,
> and the current QEMU implementation (from this patch view:
> bit_swap=false) is not: it is PowerMac specific.
>
> I think the PowerMac uses an evolved Z85C30 with more precise IRQ lines.
>
> Anyway, not a blocker, but I wanted to share my view that this model
> is eventually going in an incorrect direction.
> I'll try to suggest a patch to clean this during the next merge window.
Oh I see, so you think that what is currently the swapped version is actually how it
is handled in standard hardware? In that case I tend to agree with you that it would
make sense to switch the sense of the property around so that the standard behaviour
is the default.
Also this makes me feel that "bit_swap" isn't a particularly good property name -
perhaps something like "pmac_bit_swap" would be clearer?
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit Mark Cave-Ayland
2018-10-29 23:36 ` Philippe Mathieu-Daudé
@ 2018-10-30 6:46 ` Hervé Poussineau
1 sibling, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:46 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> On Sparc and PowerMac, the bit 0 of the address
> selects the register type (control or data) and
> bit 1 selects the channel (B or A).
>
> On m68k Macintosh, the bit 0 selects the channel and
> bit 1 the register type.
>
> This patch introduces a new parameter (bit_swap) to
> the device interface to indicate bits usage must
> be swapped between registers and channels.
>
> For the moment all the machines use the bit 0,
> but this change will be needed to emulate Quadra 800.
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/char/escc.c | 30 ++++++++++++++++++++++++------
> include/hw/char/escc.h | 1 +
> 2 files changed, 25 insertions(+), 6 deletions(-)
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 04/11] hw/m68k: add macfb video card
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (2 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 03/11] escc: introduce a selector for the register bit Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:46 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation Mark Cave-Ayland
` (7 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
arch_init.c | 4 +
hw/display/Makefile.objs | 1 +
hw/display/macfb.c | 419 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/display/macfb.h | 43 +++++
qemu-options.hx | 2 +-
vl.c | 3 +-
6 files changed, 470 insertions(+), 2 deletions(-)
create mode 100644 hw/display/macfb.c
create mode 100644 include/hw/display/macfb.h
diff --git a/arch_init.c b/arch_init.c
index f4f3f610c8..5a71b48dc5 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -39,6 +39,10 @@
int graphic_width = 1024;
int graphic_height = 768;
int graphic_depth = 8;
+#elif defined(TARGET_M68K)
+int graphic_width = 800;
+int graphic_height = 600;
+int graphic_depth = 8;
#else
int graphic_width = 800;
int graphic_height = 600;
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 97acd5b6cb..1685492ea0 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -27,6 +27,7 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_fimd.o
common-obj-$(CONFIG_FRAMEBUFFER) += framebuffer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-vgafb.o
common-obj-$(CONFIG_ZAURUS) += tc6393xb.o
+common-obj-$(CONFIG_MACFB) += macfb.o
common-obj-$(CONFIG_MILKYMIST_TMU2) += milkymist-tmu2.o
milkymist-tmu2.o-cflags := $(X11_CFLAGS)
diff --git a/hw/display/macfb.c b/hw/display/macfb.c
new file mode 100644
index 0000000000..61ba2e9e15
--- /dev/null
+++ b/hw/display/macfb.c
@@ -0,0 +1,419 @@
+/*
+ * QEMU Motorola 680x0 Macintosh Video Card Emulation
+ * Copyright (c) 2012-2018 Laurent Vivier
+ *
+ * some parts from QEMU G364 framebuffer Emulator.
+ * Copyright (c) 2007-2011 Herve Poussineau
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "ui/console.h"
+#include "ui/pixel_ops.h"
+#include "hw/display/macfb.h"
+#include "qapi/error.h"
+
+#define VIDEO_BASE 0x00001000
+#define DAFB_BASE 0x00800000
+
+#define MACFB_PAGE_SIZE 4096
+#define MACFB_VRAM_SIZE (4 * MiB)
+
+#define DAFB_RESET 0x200
+#define DAFB_LUT 0x213
+
+
+typedef void macfb_draw_line_func(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width);
+
+static inline uint8_t macfb_read_byte(MacfbState *s, uint32_t addr)
+{
+ return s->vram[addr & s->vram_bit_mask];
+}
+
+/* 1-bit color */
+static void macfb_draw_line1(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ int bit = x & 7;
+ int idx = (macfb_read_byte(s, addr) >> (7 - bit)) & 1;
+ r = g = b = ((1 - idx) << 7);
+ addr += (bit == 7);
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+/* 2-bit color */
+static void macfb_draw_line2(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ int bit = (x & 3);
+ int idx = (macfb_read_byte(s, addr) >> ((3 - bit) << 1)) & 3;
+ r = s->color_palette[idx * 3];
+ g = s->color_palette[idx * 3 + 1];
+ b = s->color_palette[idx * 3 + 2];
+ addr += (bit == 3);
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+/* 4-bit color */
+static void macfb_draw_line4(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ int bit = x & 1;
+ int idx = (macfb_read_byte(s, addr) >> ((1 - bit) << 2)) & 15;
+ r = s->color_palette[idx * 3];
+ g = s->color_palette[idx * 3 + 1];
+ b = s->color_palette[idx * 3 + 2];
+ addr += (bit == 1);
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+/* 8-bit color */
+static void macfb_draw_line8(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ r = s->color_palette[macfb_read_byte(s, addr) * 3];
+ g = s->color_palette[macfb_read_byte(s, addr) * 3 + 1];
+ b = s->color_palette[macfb_read_byte(s, addr) * 3 + 2];
+ addr++;
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+/* 16-bit color */
+static void macfb_draw_line16(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ uint16_t pixel;
+ pixel = (macfb_read_byte(s, addr) << 8) | macfb_read_byte(s, addr + 1);
+ r = ((pixel >> 10) & 0x1f) << 3;
+ g = ((pixel >> 5) & 0x1f) << 3;
+ b = (pixel & 0x1f) << 3;
+ addr += 2;
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+/* 24-bit color */
+static void macfb_draw_line24(MacfbState *s, uint8_t *d, uint32_t addr,
+ int width)
+{
+ uint8_t r, g, b;
+ int x;
+
+ for (x = 0; x < width; x++) {
+ r = macfb_read_byte(s, addr);
+ g = macfb_read_byte(s, addr + 1);
+ b = macfb_read_byte(s, addr + 2);
+ addr += 3;
+
+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);
+ d += 4;
+ }
+}
+
+
+enum {
+ MACFB_DRAW_LINE1,
+ MACFB_DRAW_LINE2,
+ MACFB_DRAW_LINE4,
+ MACFB_DRAW_LINE8,
+ MACFB_DRAW_LINE16,
+ MACFB_DRAW_LINE24,
+ MACFB_DRAW_LINE_NB,
+};
+
+static macfb_draw_line_func * const
+ macfb_draw_line_table[MACFB_DRAW_LINE_NB] = {
+ macfb_draw_line1,
+ macfb_draw_line2,
+ macfb_draw_line4,
+ macfb_draw_line8,
+ macfb_draw_line16,
+ macfb_draw_line24,
+};
+
+static int macfb_check_dirty(MacfbState *s, DirtyBitmapSnapshot *snap,
+ ram_addr_t addr, int len)
+{
+ return memory_region_snapshot_get_dirty(&s->mem_vram, snap, addr, len);
+}
+
+static void macfb_draw_graphic(MacfbState *s)
+{
+ DisplaySurface *surface = qemu_console_surface(s->con);
+ DirtyBitmapSnapshot *snap = NULL;
+ ram_addr_t page;
+ uint32_t v = 0;
+ int y, ymin;
+ int macfb_stride = (s->depth * s->width + 7) / 8;
+ macfb_draw_line_func *macfb_draw_line;
+
+ switch (s->depth) {
+ case 1:
+ v = MACFB_DRAW_LINE1;
+ break;
+ case 2:
+ v = MACFB_DRAW_LINE2;
+ break;
+ case 4:
+ v = MACFB_DRAW_LINE4;
+ break;
+ case 8:
+ v = MACFB_DRAW_LINE8;
+ break;
+ case 16:
+ v = MACFB_DRAW_LINE16;
+ break;
+ case 24:
+ v = MACFB_DRAW_LINE24;
+ break;
+ }
+
+ macfb_draw_line = macfb_draw_line_table[v];
+ assert(macfb_draw_line != NULL);
+
+ snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0x0,
+ memory_region_size(&s->mem_vram),
+ DIRTY_MEMORY_VGA);
+
+ ymin = -1;
+ page = 0;
+ for (y = 0; y < s->height; y++, page += macfb_stride) {
+ if (macfb_check_dirty(s, snap, page, macfb_stride)) {
+ uint8_t *data_display;
+
+ data_display = surface_data(surface) + y * surface_stride(surface);
+ macfb_draw_line(s, data_display, page, s->width);
+
+ if (ymin < 0) {
+ ymin = y;
+ }
+ } else {
+ if (ymin >= 0) {
+ dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin);
+ ymin = -1;
+ }
+ }
+ }
+
+ if (ymin >= 0) {
+ dpy_gfx_update(s->con, 0, ymin, s->width, y - ymin);
+ }
+
+ g_free(snap);
+}
+
+static void macfb_invalidate_display(void *opaque)
+{
+ MacfbState *s = opaque;
+
+ memory_region_set_dirty(&s->mem_vram, 0, MACFB_VRAM_SIZE);
+}
+
+static void macfb_update_display(void *opaque)
+{
+ MacfbState *s = opaque;
+ DisplaySurface *surface = qemu_console_surface(s->con);
+
+ qemu_flush_coalesced_mmio_buffer();
+
+ if (s->width == 0 || s->height == 0) {
+ return;
+ }
+
+ if (s->width != surface_width(surface) ||
+ s->height != surface_height(surface)) {
+ qemu_console_resize(s->con, s->width, s->height);
+ }
+
+ macfb_draw_graphic(s);
+}
+
+static void macfb_reset(MacfbState *s)
+{
+ int i;
+
+ s->palette_current = 0;
+ for (i = 0; i < 256; i++) {
+ s->color_palette[i * 3] = 255 - i;
+ s->color_palette[i * 3 + 1] = 255 - i;
+ s->color_palette[i * 3 + 2] = 255 - i;
+ }
+ memset(s->vram, 0, MACFB_VRAM_SIZE);
+ macfb_invalidate_display(s);
+}
+
+static uint64_t macfb_ctrl_read(void *opaque,
+ hwaddr addr,
+ unsigned int size)
+{
+ return 0;
+}
+
+static void macfb_ctrl_write(void *opaque,
+ hwaddr addr,
+ uint64_t val,
+ unsigned int size)
+{
+ MacfbState *s = opaque;
+ switch (addr) {
+ case DAFB_RESET:
+ s->palette_current = 0;
+ break;
+ case DAFB_LUT:
+ s->color_palette[s->palette_current++] = val;
+ if (s->palette_current % 3) {
+ macfb_invalidate_display(s);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps macfb_ctrl_ops = {
+ .read = macfb_ctrl_read,
+ .write = macfb_ctrl_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 4,
+};
+
+static int macfb_post_load(void *opaque, int version_id)
+{
+ macfb_invalidate_display(opaque);
+ return 0;
+}
+
+static const VMStateDescription vmstate_macfb = {
+ .name = "macfb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = macfb_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(color_palette, MacfbState, 256 * 3),
+ VMSTATE_UINT32(palette_current, MacfbState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const GraphicHwOps macfb_ops = {
+ .invalidate = macfb_invalidate_display,
+ .gfx_update = macfb_update_display,
+};
+
+static void macfb_common_realize(DeviceState *dev, MacfbState *s, Error **errp)
+{
+ DisplaySurface *surface;
+
+ if (s->depth != 1 && s->depth != 2 && s->depth != 4 && s->depth != 8 &&
+ s->depth != 16 && s->depth != 24) {
+ error_setg(errp, "unknown guest depth %d", s->depth);
+ return;
+ }
+
+ s->con = graphic_console_init(dev, 0, &macfb_ops, s);
+ surface = qemu_console_surface(s->con);
+
+ if (surface_bits_per_pixel(surface) != 32) {
+ error_setg(errp, "unknown host depth %d",
+ surface_bits_per_pixel(surface));
+ return;
+ }
+
+ memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "macfb-ctrl",
+ 0x1000);
+
+ memory_region_init_ram_nomigrate(&s->mem_vram, OBJECT(s), "macfb-vram",
+ MACFB_VRAM_SIZE, errp);
+ s->vram = memory_region_get_ram_ptr(&s->mem_vram);
+ s->vram_bit_mask = MACFB_VRAM_SIZE - 1;
+ vmstate_register_ram(&s->mem_vram, dev);
+ memory_region_set_coalescing(&s->mem_vram);
+}
+
+static void macfb_sysbus_realize(DeviceState *dev, Error **errp)
+{
+ MacfbSysBusState *s = MACFB(dev);
+ MacfbState *ms = &s->macfb;
+
+ macfb_common_realize(dev, ms, errp);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_ctrl);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram);
+}
+
+static void macfb_sysbus_reset(DeviceState *d)
+{
+ MacfbSysBusState *s = MACFB(d);
+ macfb_reset(&s->macfb);
+}
+
+static Property macfb_sysbus_properties[] = {
+ DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640),
+ DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480),
+ DEFINE_PROP_UINT8("depth", MacfbSysBusState, macfb.depth, 8),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void macfb_sysbus_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = macfb_sysbus_realize;
+ dc->desc = "SysBus Macintosh framebuffer";
+ dc->reset = macfb_sysbus_reset;
+ dc->vmsd = &vmstate_macfb;
+ dc->props = macfb_sysbus_properties;
+}
+
+static TypeInfo macfb_sysbus_info = {
+ .name = TYPE_MACFB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MacfbSysBusState),
+ .class_init = macfb_sysbus_class_init,
+};
+
+static void macfb_register_types(void)
+{
+ type_register_static(&macfb_sysbus_info);
+}
+
+type_init(macfb_register_types)
diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h
new file mode 100644
index 0000000000..3fe2592735
--- /dev/null
+++ b/include/hw/display/macfb.h
@@ -0,0 +1,43 @@
+/*
+ * QEMU Motorola 680x0 Macintosh Video Card Emulation
+ * Copyright (c) 2012-2018 Laurent Vivier
+ *
+ * some parts from QEMU G364 framebuffer Emulator.
+ * Copyright (c) 2007-2011 Herve Poussineau
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef MACFB_H
+#define MACFB_H
+
+#include "qemu/osdep.h"
+#include "exec/memory.h"
+#include "ui/console.h"
+
+typedef struct MacfbState {
+ MemoryRegion mem_vram;
+ MemoryRegion mem_ctrl;
+ QemuConsole *con;
+
+ uint8_t *vram;
+ uint32_t vram_bit_mask;
+ uint32_t palette_current;
+ uint8_t color_palette[256 * 3];
+ uint32_t width, height; /* in pixels */
+ uint8_t depth;
+} MacfbState;
+
+#define TYPE_MACFB "sysbus-macfb"
+#define MACFB(obj) \
+ OBJECT_CHECK(MacfbSysBusState, (obj), TYPE_MACFB)
+
+typedef struct {
+ SysBusDevice busdev;
+
+ MacfbState macfb;
+} MacfbSysBusState;
+
+#endif
diff --git a/qemu-options.hx b/qemu-options.hx
index 08f8516a9a..509ae6ba4d 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1523,7 +1523,7 @@ ETEXI
DEF("g", 1, QEMU_OPTION_g ,
"-g WxH[xDEPTH] Set the initial graphical resolution and depth\n",
- QEMU_ARCH_PPC | QEMU_ARCH_SPARC)
+ QEMU_ARCH_PPC | QEMU_ARCH_SPARC | QEMU_ARCH_M68K)
STEXI
@item -g @var{width}x@var{height}[x@var{depth}]
@findex -g
diff --git a/vl.c b/vl.c
index 1fcacc5caa..a84f126417 100644
--- a/vl.c
+++ b/vl.c
@@ -3353,7 +3353,8 @@ int main(int argc, char **argv, char **envp)
if (*p == 'x') {
p++;
depth = strtol(p, (char **)&p, 10);
- if (depth != 8 && depth != 15 && depth != 16 &&
+ if (depth != 1 && depth != 2 && depth != 4 &&
+ depth != 8 && depth != 15 && depth != 16 &&
depth != 24 && depth != 32)
goto graphic_error;
} else if (*p == '\0') {
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 04/11] hw/m68k: add macfb video card
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 04/11] hw/m68k: add macfb video card Mark Cave-Ayland
@ 2018-10-30 6:46 ` Hervé Poussineau
0 siblings, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:46 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> arch_init.c | 4 +
> hw/display/Makefile.objs | 1 +
> hw/display/macfb.c | 419 +++++++++++++++++++++++++++++++++++++++++++++
> include/hw/display/macfb.h | 43 +++++
> qemu-options.hx | 2 +-
> vl.c | 3 +-
> 6 files changed, 470 insertions(+), 2 deletions(-)
> create mode 100644 hw/display/macfb.c
> create mode 100644 include/hw/display/macfb.h
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (3 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 04/11] hw/m68k: add macfb video card Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:46 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh Mark Cave-Ayland
` (6 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
This is broken as the linux driver seems broken too...
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/audio/Makefile.objs | 1 +
hw/audio/asc.c | 446 +++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/audio/asc.h | 48 ++++++
3 files changed, 495 insertions(+)
create mode 100644 hw/audio/asc.c
create mode 100644 include/hw/audio/asc.h
diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs
index 63db383709..44d1ada7b0 100644
--- a/hw/audio/Makefile.objs
+++ b/hw/audio/Makefile.objs
@@ -16,3 +16,4 @@ common-obj-$(CONFIG_MARVELL_88W8618) += marvell_88w8618.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-ac97.o
common-obj-y += soundhw.o
+common-obj-$(CONFIG_ASC) += asc.o
diff --git a/hw/audio/asc.c b/hw/audio/asc.c
new file mode 100644
index 0000000000..4fd23eb8e1
--- /dev/null
+++ b/hw/audio/asc.c
@@ -0,0 +1,446 @@
+/*
+ * QEMU Apple Sound Chip emulation
+ *
+ * Apple Sound Chip (ASC) 344S0063
+ * Enhanced Apple Sound Chip (EASC) 343S1063
+ *
+ * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "audio/audio.h"
+#include "hw/audio/asc.h"
+
+/*
+ * Linux doesn't provide information about ASC, see arch/m68k/mac/macboing.c
+ * and arch/m68k/include/asm/mac_asc.h
+ *
+ * best information is coming from MAME:
+ * http://mamedev.org/source/src/emu/sound/asc.h.html
+ * http://mamedev.org/source/src/emu/sound/asc.c.html
+ * Emulation by R. Belmont
+ *
+ * 0x800: VERSION
+ * 0x801: MODE
+ * 1=FIFO mode,
+ * 2=wavetable mode
+ * 0x802: CONTROL
+ * bit 0=analog or PWM output,
+ * 1=stereo/mono,
+ * 7=processing time exceeded
+ * 0x803: FIFO MODE
+ * bit 7=clear FIFO,
+ * bit 1="non-ROM companding",
+ * bit 0="ROM companding")
+ * 0x804: FIFO IRQ STATUS
+ * bit 0=ch A 1/2 full,
+ * 1=ch A full,
+ * 2=ch B 1/2 full,
+ * 3=ch B full)
+ * 0x805: WAVETABLE CONTROL
+ * bits 0-3 wavetables 0-3 start
+ * 0x806: VOLUME
+ * bits 2-4 = 3 bit internal ASC volume,
+ * bits 5-7 = volume control sent to Sony sound chip
+ * 0x807: CLOCK RATE
+ * 0 = Mac 22257 Hz,
+ * 1 = undefined,
+ * 2 = 22050 Hz,
+ * 3 = 44100 Hz
+ * 0x80a: PLAY REC A
+ * 0x80f: TEST
+ * bits 6-7 = digital test,
+ * bits 4-5 = analog test
+ * 0x810: WAVETABLE 0 PHASE
+ * big-endian 9.15 fixed-point, only 24 bits valid
+ * 0x814: WAVETABLE 0 INCREMENT
+ * big-endian 9.15 fixed-point, only 24 bits valid
+ * 0x818: WAVETABLE 1 PHASE
+ * 0x81C: WAVETABLE 1 INCREMENT
+ * 0x820: WAVETABLE 2 PHASE
+ * 0x824: WAVETABLE 2 INCREMENT
+ * 0x828: WAVETABLE 3 PHASE
+ * 0x82C: WAVETABLE 3 INCREMENT
+ */
+
+#define ASC_LENGTH 0x2000
+#define ASC_BUF_SIZE 0x0800
+
+#define ASC_REG_BASE 0x0800
+enum {
+ ASC_VERSION = 0x00,
+ ASC_MODE = 0x01,
+ ASC_CONTROL = 0x02,
+ ASC_FIFOMODE = 0x03,
+ ASC_FIFOIRQ = 0x04,
+ ASC_WAVECTRL = 0x05,
+ ASC_VOLUME = 0x06,
+ ASC_CLOCK = 0x07,
+ ASC_PLAYRECA = 0x0a,
+ ASC_TEST = 0x0f,
+ ASC_WAVETABLE = 0x10
+};
+
+static inline uint32_t get_phase(ASCState *s, int channel)
+{
+ return be32_to_cpu(*(uint32_t *)(s->regs + ASC_WAVETABLE + channel * 8));
+}
+
+static inline void set_phase(ASCState *s, int channel, uint32_t phase)
+{
+ *(uint32_t *)(s->regs + ASC_WAVETABLE + channel * 8) = cpu_to_be32(phase);
+}
+
+static inline uint32_t get_incr(ASCState *s, int channel)
+{
+ return be32_to_cpu(*(uint32_t *)(s->regs + ASC_WAVETABLE + 4 +
+ channel * 8));
+}
+
+static inline uint32_t incr_phase(ASCState *s, int channel)
+{
+ uint32_t incr = get_incr(s, channel);
+ uint32_t phase = get_phase(s, channel);
+
+ set_phase(s, channel, phase + incr);
+
+ return get_phase(s, channel);
+}
+
+static void generate_fifo(ASCState *s, int free_b)
+{
+ int8_t buf[2048];
+ int i;
+ int to_copy;
+
+ do {
+ to_copy = audio_MIN(sizeof(buf), free_b);
+ for (i = 0; i < (to_copy >> 1); to_copy++) {
+ int8_t left, right;
+
+ left = s->fifo[s->a_rptr] ^ 0x80;
+ right = s->fifo[s->b_rptr + 0x400] ^ 0x80;
+
+ if (s->a_cnt) {
+ s->a_rptr++;
+ s->a_rptr &= 0x3ff;
+ s->a_cnt--;
+ }
+
+ if (s->b_cnt) {
+ s->b_rptr++;
+ s->b_rptr &= 0x3ff;
+ s->b_cnt--;
+ }
+
+ if (s->type == ASC_TYPE_SONORA) {
+ if (s->a_cnt < 0x200) {
+ s->regs[ASC_FIFOIRQ] |= 4; /* FIFO A less than half full */
+ qemu_irq_raise(s->irq);
+ }
+ if (s->b_cnt < 0x200) {
+ s->regs[ASC_FIFOIRQ] |= 8; /* FIFO B less than half full */
+ qemu_irq_raise(s->irq);
+ }
+ } else {
+ if (s->a_cnt == 0x1ff) {
+ s->regs[ASC_FIFOIRQ] |= 1; /* FIFO A half empty */
+ qemu_irq_raise(s->irq);
+ } else if (s->a_cnt == 0x001) {
+ s->regs[ASC_FIFOIRQ] |= 2; /* FIFO A half empty */
+ qemu_irq_raise(s->irq);
+ }
+ if (s->b_cnt == 0x1ff) {
+ s->regs[ASC_FIFOIRQ] |= 4; /* FIFO A half empty */
+ qemu_irq_raise(s->irq);
+ } else if (s->b_cnt == 0x001) {
+ s->regs[ASC_FIFOIRQ] |= 8; /* FIFO A half empty */
+ qemu_irq_raise(s->irq);
+ }
+ }
+ buf[i * 2] = left;
+ buf[i * 2 + 1] = right;
+ }
+ AUD_write(s->channel, buf, to_copy);
+ free_b -= to_copy;
+ } while (free_b);
+}
+
+static void generate_wavetable(ASCState *s, int free_b)
+{
+ int8_t buf[2048];
+ int i;
+ int channel;
+ int to_copy;
+ int control = s->regs[ASC_WAVECTRL];
+
+ do {
+ to_copy = audio_MIN(sizeof(buf), free_b);
+ for (i = 0; i < (to_copy >> 1); i++) {
+ int32_t left, right;
+ int8_t sample;
+
+ left = 0;
+ right = 0;
+
+ if (control) { /* FIXME: how to use it ? */
+ for (channel = 0; channel < 4; channel++) {
+ uint32_t phase = incr_phase(s, channel);
+
+ phase = (phase >> 15) & 0x1ff;
+ sample = s->fifo[0x200 * channel + phase] ^ 0x80;
+
+ left += sample;
+ right += sample;
+ }
+ buf[i * 2] = left >> 2;
+ buf[i * 2 + 1] = right >> 2;
+ } else {
+ /* FIXME: only works with linux macboing.c */
+ uint32_t phase = incr_phase(s, 0);
+ phase = (phase >> 15) & 0x7ff;
+ sample = s->fifo[phase];
+ buf[i * 2] = sample;
+ buf[i * 2 + 1] = sample;
+ }
+ }
+ AUD_write(s->channel, buf, to_copy);
+ free_b -= to_copy;
+ } while (free_b);
+}
+
+static void asc_out_cb(void *opaque, int free_b)
+{
+ ASCState *s = opaque;
+
+ switch (s->regs[ASC_MODE] & 3) {
+ case 0: /* Off */
+ break;
+ case 1: /* FIFO mode */
+ generate_fifo(s, free_b);
+ break;
+ case 2: /* Wave table mode */
+ generate_wavetable(s, free_b);
+ break;
+ }
+}
+
+static uint64_t asc_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ ASCState *s = opaque;
+ uint64_t prev;
+
+ if (addr < 0x800) {
+ return s->fifo[addr];
+ }
+
+ addr -= 0x800;
+
+ if (addr >= 0x030) {
+ return 0;
+ }
+
+ switch (addr) {
+ case ASC_VERSION:
+ switch (s->type) {
+ case ASC_TYPE_ASC:
+ return 0;
+ case ASC_TYPE_V8:
+ case ASC_TYPE_EAGLE:
+ case ASC_TYPE_SPICE:
+ case ASC_TYPE_VASP:
+ return 0xe8;
+ case ASC_TYPE_SONORA:
+ return 0xbc;
+ default:
+ break;
+ }
+ break;
+ case ASC_MODE:
+ switch (s->type) {
+ case ASC_TYPE_V8:
+ case ASC_TYPE_EAGLE:
+ case ASC_TYPE_SPICE:
+ case ASC_TYPE_VASP:
+ return 1;
+ default:
+ break;
+ }
+ break;
+ case ASC_CONTROL:
+ switch (s->type) {
+ case ASC_TYPE_V8:
+ case ASC_TYPE_EAGLE:
+ case ASC_TYPE_SPICE:
+ case ASC_TYPE_VASP:
+ return 1;
+ default:
+ break;
+ }
+ break;
+ case ASC_FIFOIRQ:
+ if (s->type == ASC_TYPE_V8) {
+ prev = 3;
+ } else {
+ prev = s->regs[ASC_FIFOIRQ];
+ }
+ s->regs[ASC_FIFOIRQ] = 0;
+ qemu_irq_lower(s->irq);
+ return prev;
+ default:
+ break;
+ }
+
+ return s->regs[addr];
+}
+
+static void asc_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ ASCState *s = opaque;
+
+ if (addr < 0x800) {
+ if (s->regs[ASC_MODE] == 1) {
+ if (addr < 0x400) {
+ /* FIFO A */
+ s->fifo[s->a_wptr++] = value;
+ s->a_cnt++;
+ if (s->a_cnt == 0x3ff) {
+ s->regs[ASC_FIFOIRQ] |= 2; /* FIFO A Full */
+ }
+ s->a_wptr &= 0x3ff;
+ } else {
+ /* FIFO B */
+ s->fifo[s->b_wptr++ + 0x400] = value;
+ s->b_cnt++;
+ if (s->b_cnt == 0x3ff) {
+ s->regs[ASC_FIFOIRQ] |= 8; /* FIFO B Full */
+ }
+ s->b_wptr &= 0x3ff;
+ }
+ } else {
+ s->fifo[addr] = value;
+ }
+ return;
+ }
+
+ addr -= 0x800;
+ if (addr >= 0x30) {
+ return;
+ }
+ switch (addr) {
+ case ASC_MODE:
+ value &= 3;
+ if (value != s->regs[ASC_MODE]) {
+ s->a_rptr = 0;
+ s->a_wptr = 0;
+ s->a_cnt = 0;
+ s->b_rptr = 0;
+ s->b_wptr = 0;
+ s->b_cnt = 0;
+ if (value != 0) {
+ AUD_set_active_out(s->channel, 1);
+ } else {
+ AUD_set_active_out(s->channel, 0);
+ }
+ }
+ break;
+ case ASC_FIFOMODE:
+ if (value & 0x80) {
+ s->a_rptr = 0;
+ s->a_wptr = 0;
+ s->a_cnt = 0;
+ s->b_rptr = 0;
+ s->b_wptr = 0;
+ s->b_cnt = 0;
+ }
+ break;
+ case ASC_WAVECTRL:
+ break;
+ }
+ s->regs[addr] = value;
+}
+
+static const MemoryRegionOps asc_mmio_ops = {
+ .read = asc_read,
+ .write = asc_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void asc_reset(DeviceState *d)
+{
+ ASCState *s = ASC(d);
+
+ AUD_set_active_out(s->channel, 0);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ s->a_wptr = 0;
+ s->a_rptr = 0;
+ s->a_cnt = 0;
+ s->b_wptr = 0;
+ s->b_rptr = 0;
+ s->b_cnt = 0;
+}
+
+static void asc_init(Object *obj)
+{
+ ASCState *s = ASC(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ struct audsettings as;
+
+ AUD_register_card("Apple Sound Chip", &s->card);
+
+ as.freq = 22257;
+ as.nchannels = 2;
+ as.fmt = AUD_FMT_S8;
+ as.endianness = 0;
+
+ s->channel = AUD_open_out(&s->card, s->channel, "asc.out",
+ s, asc_out_cb, &as);
+
+ s->fifo = g_malloc0(ASC_BUF_SIZE);
+
+ memory_region_init_io(&s->mem_regs, obj, &asc_mmio_ops, s, "asc",
+ ASC_LENGTH);
+
+ sysbus_init_irq(sbd, &s->irq);
+ sysbus_init_mmio(sbd, &s->mem_regs);
+}
+
+static Property asc_properties[] = {
+ DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void asc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->reset = asc_reset;
+ dc->props = asc_properties;
+}
+
+static TypeInfo asc_info = {
+ .name = TYPE_ASC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ASCState),
+ .instance_init = asc_init,
+ .class_init = asc_class_init,
+};
+
+static void asc_register_types(void)
+{
+ type_register_static(&asc_info);
+}
+
+type_init(asc_register_types)
diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h
new file mode 100644
index 0000000000..3540e32f69
--- /dev/null
+++ b/include/hw/audio/asc.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_AUDIO_ASC_H
+#define HW_AUDIO_ASC_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "audio/audio.h"
+
+enum {
+ ASC_TYPE_ASC = 0, /* original discrete Apple Sound Chip */
+ ASC_TYPE_EASC = 1, /* discrete Enhanced Apple Sound Chip */
+ ASC_TYPE_V8 = 2, /* ASC included in the V8 ASIC (LC/LCII) */
+ ASC_TYPE_EAGLE = 3, /* ASC included in the Eagle ASIC (Classic II) */
+ ASC_TYPE_SPICE = 4, /* ASC included in the Spice ASIC (Color Classic) */
+ ASC_TYPE_SONORA = 5, /* ASC included in the Sonora ASIC (LCIII) */
+ ASC_TYPE_VASP = 6, /* ASC included in the VASP ASIC (IIvx/IIvi) */
+ ASC_TYPE_ARDBEG = 7 /* ASC included in the Ardbeg ASIC (LC520) */
+};
+
+typedef struct ASCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mem_regs;
+ QEMUSoundCard card;
+ SWVoiceOut *channel;
+
+ qemu_irq irq;
+
+ uint8_t type;
+ int a_wptr, a_rptr, a_cnt;
+ int b_wptr, b_rptr, b_cnt;
+
+ uint8_t *fifo;
+
+ uint8_t regs[48];
+} ASCState;
+
+#define TYPE_ASC "apple-sound-chip"
+#define ASC(obj) OBJECT_CHECK(ASCState, (obj), TYPE_ASC)
+
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation Mark Cave-Ayland
@ 2018-10-30 6:46 ` Hervé Poussineau
2018-10-30 10:46 ` Mark Cave-Ayland
0 siblings, 1 reply; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:46 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> This is broken as the linux driver seems broken too...
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/audio/Makefile.objs | 1 +
> hw/audio/asc.c | 446 +++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/audio/asc.h | 48 ++++++
> 3 files changed, 495 insertions(+)
> create mode 100644 hw/audio/asc.c
> create mode 100644 include/hw/audio/asc.h
According to above comment, this device is broken.
Is it necessary for Q800 emulation? What happens if you remove it?
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation
2018-10-30 6:46 ` Hervé Poussineau
@ 2018-10-30 10:46 ` Mark Cave-Ayland
2018-10-30 12:05 ` Laurent Vivier
0 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 10:46 UTC (permalink / raw)
To: Hervé Poussineau, qemu-devel, kwolf, famz, qemu-block,
jasowang, dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien,
laurent
On 30/10/2018 06:46, Hervé Poussineau wrote:
> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> This is broken as the linux driver seems broken too...
>>
>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/audio/Makefile.objs | 1 +
>> hw/audio/asc.c | 446 +++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/audio/asc.h | 48 ++++++
>> 3 files changed, 495 insertions(+)
>> create mode 100644 hw/audio/asc.c
>> create mode 100644 include/hw/audio/asc.h
>
> According to above comment, this device is broken.
> Is it necessary for Q800 emulation? What happens if you remove it?
A quick test here shows that I can still boot without it, so it doesn't seem to be
essential. Laurent, should we remove this from the next revision of the patchset? The
general consensus seems to be that if a device isn't required (for now) then it
shouldn't be included.
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation
2018-10-30 10:46 ` Mark Cave-Ayland
@ 2018-10-30 12:05 ` Laurent Vivier
0 siblings, 0 replies; 39+ messages in thread
From: Laurent Vivier @ 2018-10-30 12:05 UTC (permalink / raw)
To: Mark Cave-Ayland, Hervé Poussineau, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, kraxel, pbonzini,
afaerber, aurelien
Le 30/10/2018 à 11:46, Mark Cave-Ayland a écrit :
> On 30/10/2018 06:46, Hervé Poussineau wrote:
>
>> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>>> From: Laurent Vivier <laurent@vivier.eu>
>>>
>>> This is broken as the linux driver seems broken too...
>>>
>>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>>> ---
>>> hw/audio/Makefile.objs | 1 +
>>> hw/audio/asc.c | 446 +++++++++++++++++++++++++++++++++++++++++++++++++
>>> include/hw/audio/asc.h | 48 ++++++
>>> 3 files changed, 495 insertions(+)
>>> create mode 100644 hw/audio/asc.c
>>> create mode 100644 include/hw/audio/asc.h
>>
>> According to above comment, this device is broken.
>> Is it necessary for Q800 emulation? What happens if you remove it?
>
> A quick test here shows that I can still boot without it, so it doesn't seem to be
> essential. Laurent, should we remove this from the next revision of the patchset? The
> general consensus seems to be that if a device isn't required (for now) then it
> shouldn't be included.
It can be removed.
I've just checked the kernel and in the case of the Quadra 800 the ASC
is not supported at all.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (4 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 05/11] hw/m68k: Apple Sound Chip (ASC) emulation Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:47 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support Mark Cave-Ayland
` (5 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/scsi/esp.c | 292 +++++++++++++++++++++++++++++++++++++++++++++-----
include/hw/scsi/esp.h | 7 ++
2 files changed, 270 insertions(+), 29 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 630d923623..57589cd69d 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -35,6 +35,8 @@
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
* and
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
+ *
+ * On Macintosh Quadra it is a NCR53C96.
*/
static void esp_raise_irq(ESPState *s)
@@ -55,6 +57,16 @@ static void esp_lower_irq(ESPState *s)
}
}
+static void esp_raise_drq(ESPState *s)
+{
+ qemu_irq_raise(s->irq_data);
+}
+
+static void esp_lower_drq(ESPState *s)
+{
+ qemu_irq_lower(s->irq_data);
+}
+
void esp_dma_enable(ESPState *s, int irq, int level)
{
if (level) {
@@ -81,29 +93,11 @@ void esp_request_cancelled(SCSIRequest *req)
}
}
-static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
+static int get_cmd_cb(ESPState *s)
{
- uint32_t dmalen;
int target;
target = s->wregs[ESP_WBUSID] & BUSID_DID;
- if (s->dma) {
- dmalen = s->rregs[ESP_TCLO];
- dmalen |= s->rregs[ESP_TCMID] << 8;
- dmalen |= s->rregs[ESP_TCHI] << 16;
- if (dmalen > buflen) {
- return 0;
- }
- s->dma_memory_read(s->dma_opaque, buf, dmalen);
- } else {
- dmalen = s->ti_size;
- if (dmalen > TI_BUFSZ) {
- return 0;
- }
- memcpy(buf, s->ti_buf, dmalen);
- buf[0] = buf[2] >> 5;
- }
- trace_esp_get_cmd(dmalen, target);
s->ti_size = 0;
s->ti_rptr = 0;
@@ -122,8 +116,48 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = SEQ_0;
esp_raise_irq(s);
+ return -1;
+ }
+ return 0;
+}
+
+static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
+{
+ int target;
+ uint32_t dmalen;
+
+ target = s->wregs[ESP_WBUSID] & BUSID_DID;
+ if (s->dma) {
+ dmalen = s->rregs[ESP_TCLO];
+ dmalen |= s->rregs[ESP_TCMID] << 8;
+ dmalen |= s->rregs[ESP_TCHI] << 16;
+ if (dmalen > buflen) {
+ return 0;
+ }
+ if (s->dma_memory_read) {
+ s->dma_memory_read(s->dma_opaque, buf, dmalen);
+ } else {
+ memcpy(s->pdma_buf, buf, dmalen);
+ s->pdma_len = dmalen;
+ s->pdma_start = s->pdma_buf;
+ s->pdma_cur = s->pdma_buf;
+ esp_raise_drq(s);
+ return 0;
+ }
+ } else {
+ dmalen = s->ti_size;
+ if (dmalen > TI_BUFSZ) {
+ return 0;
+ }
+ memcpy(buf, s->ti_buf, dmalen);
+ buf[0] = buf[2] >> 5;
+ }
+ trace_esp_get_cmd(dmalen, target);
+
+ if (get_cmd_cb(s) < 0) {
return 0;
}
+
return dmalen;
}
@@ -162,6 +196,15 @@ static void do_cmd(ESPState *s, uint8_t *buf)
do_busid_cmd(s, &buf[1], busid);
}
+static void satn_pdma_cb(ESPState *s)
+{
+ if (get_cmd_cb(s) < 0) {
+ return;
+ }
+ if (s->pdma_cur != s->pdma_start)
+ do_cmd(s, s->pdma_start);
+}
+
static void handle_satn(ESPState *s)
{
uint8_t buf[32];
@@ -171,11 +214,21 @@ static void handle_satn(ESPState *s)
s->dma_cb = handle_satn;
return;
}
+ s->pdma_cb = satn_pdma_cb;
len = get_cmd(s, buf, sizeof(buf));
if (len)
do_cmd(s, buf);
}
+static void s_without_satn_pdma_cb(ESPState *s)
+{
+ if (get_cmd_cb(s) < 0) {
+ return;
+ }
+ if (s->pdma_cur != s->pdma_start)
+ do_busid_cmd(s, s->pdma_start, 0);
+}
+
static void handle_s_without_atn(ESPState *s)
{
uint8_t buf[32];
@@ -185,18 +238,36 @@ static void handle_s_without_atn(ESPState *s)
s->dma_cb = handle_s_without_atn;
return;
}
+ s->pdma_cb = s_without_satn_pdma_cb;
len = get_cmd(s, buf, sizeof(buf));
if (len) {
do_busid_cmd(s, buf, 0);
}
}
+static void satn_stop_pdma_cb(ESPState *s)
+{
+ if (get_cmd_cb(s) < 0) {
+ return;
+ }
+ s->cmdlen = s->pdma_cur - s->pdma_start;
+ if (s->cmdlen) {
+ trace_esp_handle_satn_stop(s->cmdlen);
+ s->do_cmd = 1;
+ s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
+ s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
+ esp_raise_irq(s);
+ }
+}
+
static void handle_satn_stop(ESPState *s)
{
if (s->dma && !s->dma_enabled) {
s->dma_cb = handle_satn_stop;
return;
}
+ s->pdma_cb = satn_stop_pdma_cb;;
s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
if (s->cmdlen) {
trace_esp_handle_satn_stop(s->cmdlen);
@@ -208,16 +279,33 @@ static void handle_satn_stop(ESPState *s)
}
}
+static void write_response_pdma_cb(ESPState *s)
+{
+ s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
+ s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
+ esp_raise_irq(s);
+}
+
static void write_response(ESPState *s)
{
trace_esp_write_response(s->status);
s->ti_buf[0] = s->status;
s->ti_buf[1] = 0;
if (s->dma) {
- s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
- s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
- s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
- s->rregs[ESP_RSEQ] = SEQ_CD;
+ if (s->dma_memory_write) {
+ s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
+ s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
+ s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
+ s->rregs[ESP_RSEQ] = SEQ_CD;
+ } else {
+ s->pdma_len = 2;
+ s->pdma_start = s->ti_buf;
+ s->pdma_cur = s->ti_buf;
+ s->pdma_cb = write_response_pdma_cb;
+ esp_raise_drq(s);
+ return;
+ }
} else {
s->ti_size = 2;
s->ti_rptr = 0;
@@ -239,6 +327,39 @@ static void esp_dma_done(ESPState *s)
esp_raise_irq(s);
}
+static void do_dma_pdma_cb(ESPState *s)
+{
+ int to_device = (s->ti_size < 0);
+ int len = s->pdma_cur - s->pdma_start;
+ if (s->do_cmd) {
+ s->ti_size = 0;
+ s->cmdlen = 0;
+ s->do_cmd = 0;
+ do_cmd(s, s->cmdbuf);
+ return;
+ }
+ s->dma_left -= len;
+ s->async_buf += len;
+ s->async_len -= len;
+ if (to_device) {
+ s->ti_size += len;
+ } else {
+ s->ti_size -= len;
+ }
+ if (s->async_len == 0) {
+ scsi_req_continue(s->current_req);
+ /* If there is still data to be read from the device then
+ complete the DMA operation immediately. Otherwise defer
+ until the scsi layer has completed. */
+ if (to_device || s->dma_left != 0 || s->ti_size == 0) {
+ return;
+ }
+ }
+
+ /* Partially filled a scsi buffer. Complete immediately. */
+ esp_dma_done(s);
+}
+
static void esp_do_dma(ESPState *s)
{
uint32_t len;
@@ -249,10 +370,26 @@ static void esp_do_dma(ESPState *s)
trace_esp_do_dma(s->cmdlen, len);
assert (s->cmdlen <= sizeof(s->cmdbuf) &&
len <= sizeof(s->cmdbuf) - s->cmdlen);
- s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
+ if (s->dma_memory_read) {
+ s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
+ } else {
+ s->pdma_len = len;
+ s->pdma_start = &s->cmdbuf[s->cmdlen];
+ s->pdma_cur = &s->cmdbuf[s->cmdlen];
+ s->pdma_cb = do_dma_pdma_cb;
+ esp_raise_drq(s);
+ return;
+ }
+ s->ti_size = 0;
+ s->cmdlen = 0;
+ s->do_cmd = 0;
+ do_cmd(s, s->cmdbuf);
return;
}
if (s->async_len == 0) {
+ if (s->dma_left == 0) {
+ esp_dma_done(s);
+ }
/* Defer until data is available. */
return;
}
@@ -261,9 +398,27 @@ static void esp_do_dma(ESPState *s)
}
to_device = (s->ti_size < 0);
if (to_device) {
- s->dma_memory_read(s->dma_opaque, s->async_buf, len);
+ if (s->dma_memory_read) {
+ s->dma_memory_read(s->dma_opaque, s->async_buf, len);
+ } else {
+ s->pdma_len = len;
+ s->pdma_start = s->async_buf;
+ s->pdma_cur = s->async_buf;
+ s->pdma_cb = do_dma_pdma_cb;
+ esp_raise_drq(s);
+ return;
+ }
} else {
- s->dma_memory_write(s->dma_opaque, s->async_buf, len);
+ if (s->dma_memory_write) {
+ s->dma_memory_write(s->dma_opaque, s->async_buf, len);
+ } else {
+ s->pdma_len = len;
+ s->pdma_start = s->async_buf;
+ s->pdma_cur = s->async_buf;
+ s->pdma_cb = do_dma_pdma_cb;
+ esp_raise_drq(s);
+ return;
+ }
}
s->dma_left -= len;
s->async_buf += len;
@@ -356,8 +511,7 @@ static void handle_ti(ESPState *s)
s->dma_left = minlen;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
esp_do_dma(s);
- }
- if (s->do_cmd) {
+ } else if (s->do_cmd) {
trace_esp_handle_ti_cmd(s->cmdlen);
s->ti_size = 0;
s->cmdlen = 0;
@@ -384,6 +538,7 @@ void esp_hard_reset(ESPState *s)
static void esp_soft_reset(ESPState *s)
{
qemu_irq_lower(s->irq);
+ qemu_irq_lower(s->irq_data);
esp_hard_reset(s);
}
@@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
s->ti_size--;
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
}
+ esp_raise_irq(s);
if (s->ti_rptr == s->ti_wptr) {
s->ti_rptr = 0;
s->ti_wptr = 0;
@@ -619,6 +775,80 @@ static const MemoryRegionOps sysbus_esp_mem_ops = {
.valid.accepts = esp_mem_accepts,
};
+static void sysbus_esp_pdma_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int size)
+{
+ SysBusESPState *sysbus = opaque;
+ ESPState *s = &sysbus->esp;
+ uint32_t dmalen;
+
+ dmalen = s->rregs[ESP_TCLO];
+ dmalen |= s->rregs[ESP_TCMID] << 8;
+ dmalen |= s->rregs[ESP_TCHI] << 16;
+ if (dmalen == 0 || s->pdma_len == 0) {
+ return;
+ }
+ switch (size) {
+ case 1:
+ *s->pdma_cur++ = val;
+ s->pdma_len--;
+ dmalen--;
+ break;
+ case 2:
+ *s->pdma_cur++ = val >> 8;
+ *s->pdma_cur++ = val;
+ s->pdma_len -= 2;
+ dmalen -= 2;
+ break;
+ }
+ s->rregs[ESP_TCLO] = dmalen & 0xff;
+ s->rregs[ESP_TCMID] = dmalen >> 8;
+ s->rregs[ESP_TCHI] = dmalen >> 16;
+ if (s->pdma_len == 0 && s->pdma_cb) {
+ esp_lower_drq(s);
+ s->pdma_cb(s);
+ s->pdma_cb = NULL;
+ }
+}
+
+static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ SysBusESPState *sysbus = opaque;
+ ESPState *s = &sysbus->esp;
+ uint64_t val = 0;
+
+ if (s->pdma_len == 0) {
+ return 0;
+ }
+ switch (size) {
+ case 1:
+ val = *s->pdma_cur++;
+ s->pdma_len--;
+ break;
+ case 2:
+ val = *s->pdma_cur++;
+ val = (val << 8) | *s->pdma_cur++;
+ s->pdma_len -= 2;
+ break;
+ }
+
+ if (s->pdma_len == 0 && s->pdma_cb) {
+ esp_lower_drq(s);
+ s->pdma_cb(s);
+ s->pdma_cb = NULL;
+ }
+ return val;
+}
+
+static const MemoryRegionOps sysbus_esp_pdma_ops = {
+ .read = sysbus_esp_pdma_read,
+ .write = sysbus_esp_pdma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 2,
+};
+
static const struct SCSIBusInfo esp_scsi_info = {
.tcq = false,
.max_target = ESP_MAX_DEVS,
@@ -651,12 +881,16 @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp)
ESPState *s = &sysbus->esp;
sysbus_init_irq(sbd, &s->irq);
+ sysbus_init_irq(sbd, &s->irq_data);
assert(sysbus->it_shift != -1);
s->chip_id = TCHI_FAS100A;
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
- sysbus, "esp", ESP_REGS << sysbus->it_shift);
+ sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
sysbus_init_mmio(sbd, &sysbus->iomem);
+ memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
+ sysbus, "esp-pdma", 2);
+ sysbus_init_mmio(sbd, &sysbus->pdma);
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h
index 682a0d2de0..5e94917ef8 100644
--- a/include/hw/scsi/esp.h
+++ b/include/hw/scsi/esp.h
@@ -18,6 +18,7 @@ struct ESPState {
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
qemu_irq irq;
+ qemu_irq irq_data;
uint8_t chip_id;
bool tchi_written;
int32_t ti_size;
@@ -46,6 +47,11 @@ struct ESPState {
ESPDMAMemoryReadWriteFunc dma_memory_write;
void *dma_opaque;
void (*dma_cb)(ESPState *s);
+ uint8_t pdma_buf[32];
+ uint32_t pdma_len;
+ uint8_t *pdma_start;
+ uint8_t *pdma_cur;
+ void (*pdma_cb)(ESPState *s);
};
#define TYPE_ESP "esp"
@@ -57,6 +63,7 @@ typedef struct {
/*< public >*/
MemoryRegion iomem;
+ MemoryRegion pdma;
uint32_t it_shift;
ESPState esp;
} SysBusESPState;
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh Mark Cave-Ayland
@ 2018-10-30 6:47 ` Hervé Poussineau
2018-10-30 10:09 ` Mark Cave-Ayland
2018-10-30 18:02 ` Laurent Vivier
0 siblings, 2 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:47 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/scsi/esp.c | 292 +++++++++++++++++++++++++++++++++++++++++++++-----
> include/hw/scsi/esp.h | 7 ++
> 2 files changed, 270 insertions(+), 29 deletions(-)
>
[...]
>
> @@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
> s->ti_size--;
> s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
> }
> + esp_raise_irq(s);
> if (s->ti_rptr == s->ti_wptr) {
> s->ti_rptr = 0;
> s->ti_wptr = 0;
You're now raising irq (not drq) when reading registers. In my opinion, this deserves its own patch with an explanation.
Hervé
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh
2018-10-30 6:47 ` Hervé Poussineau
@ 2018-10-30 10:09 ` Mark Cave-Ayland
2018-10-30 20:08 ` Laurent Vivier
2018-10-30 18:02 ` Laurent Vivier
1 sibling, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 10:09 UTC (permalink / raw)
To: Hervé Poussineau, qemu-devel, kwolf, famz, qemu-block,
jasowang, dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien,
laurent
On 30/10/2018 06:47, Hervé Poussineau wrote:
> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/scsi/esp.c | 292 +++++++++++++++++++++++++++++++++++++++++++++-----
>> include/hw/scsi/esp.h | 7 ++
>> 2 files changed, 270 insertions(+), 29 deletions(-)
>>
>
> [...]
>
>> @@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
>> s->ti_size--;
>> s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
>> }
>> + esp_raise_irq(s);
>> if (s->ti_rptr == s->ti_wptr) {
>> s->ti_rptr = 0;
>> s->ti_wptr = 0;
>
> You're now raising irq (not drq) when reading registers. In my opinion, this deserves
> its own patch with an explanation.
Oooh good spot. Laurent, can you explain a bit more as to how the pseudo-DMA is wired
up for ESP?
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh
2018-10-30 10:09 ` Mark Cave-Ayland
@ 2018-10-30 20:08 ` Laurent Vivier
0 siblings, 0 replies; 39+ messages in thread
From: Laurent Vivier @ 2018-10-30 20:08 UTC (permalink / raw)
To: Mark Cave-Ayland, Hervé Poussineau, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, kraxel, pbonzini,
aurelien
On 30/10/2018 11:09, Mark Cave-Ayland wrote:
> On 30/10/2018 06:47, Hervé Poussineau wrote:
>
>> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>>> From: Laurent Vivier <laurent@vivier.eu>
>>>
>>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>>> ---
>>> hw/scsi/esp.c | 292 +++++++++++++++++++++++++++++++++++++++++++++-----
>>> include/hw/scsi/esp.h | 7 ++
>>> 2 files changed, 270 insertions(+), 29 deletions(-)
>>>
>>
>> [...]
>>
>>> @@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
>>> s->ti_size--;
>>> s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
>>> }
>>> + esp_raise_irq(s);
>>> if (s->ti_rptr == s->ti_wptr) {
>>> s->ti_rptr = 0;
>>> s->ti_wptr = 0;
>>
>> You're now raising irq (not drq) when reading registers. In my opinion, this deserves
>> its own patch with an explanation.
This line must be removed.
> Oooh good spot. Laurent, can you explain a bit more as to how the pseudo-DMA is wired
> up for ESP?
>
There is no DMA in Quadra 800, so the CPU reads/writes the data from the
PDMA register (offset 0x100, ESP_PDMA in hw/m68k/q800.c) and copies them
to/from the memory.
There is a nice assembly loop in the kernel to do that, see
linux/drivers/scsi/mac_esp.c:MAC_ESP_PDMA_LOOP().
The start of the transfer is triggered by the DREQ interrupt (see linux
mac_esp_send_pdma_cmd()), the CPU polls on the IRQ flag to start the
transfer after a SCSI command has been sent (in Quadra 800 it goes
through the VIA2, the via2-irq line and the vIFR register)
The Macintosh hardware includes hardware handshaking to prevent the CPU
from reading invalid data or writing data faster than the peripheral
device can accept it.
This is the "blind mode", and from the doc:
"Approximate maximum SCSI transfer rates within a blocks are 1.4 MB per
second for blind transfers in the Macintosh II"
Some references can be found in:
Apple Macintosh Family Hardware Reference, ISBN 0-201-19255-1
Guide to the Macintosh Family Hardware, ISBN-0-201-52405-8
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh
2018-10-30 6:47 ` Hervé Poussineau
2018-10-30 10:09 ` Mark Cave-Ayland
@ 2018-10-30 18:02 ` Laurent Vivier
1 sibling, 0 replies; 39+ messages in thread
From: Laurent Vivier @ 2018-10-30 18:02 UTC (permalink / raw)
To: Hervé Poussineau, Mark Cave-Ayland, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, kraxel, pbonzini,
aurelien
On 30/10/2018 07:47, Hervé Poussineau wrote:
> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/scsi/esp.c | 292
>> +++++++++++++++++++++++++++++++++++++++++++++-----
>> include/hw/scsi/esp.h | 7 ++
>> 2 files changed, 270 insertions(+), 29 deletions(-)
>>
>
> [...]
>
>> @@ -409,6 +564,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
>> s->ti_size--;
>> s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
>> }
>> + esp_raise_irq(s);
>> if (s->ti_rptr == s->ti_wptr) {
>> s->ti_rptr = 0;
>> s->ti_wptr = 0;
>
> You're now raising irq (not drq) when reading registers. In my opinion,
> this deserves its own patch with an explanation.
Good catch. This line is not needed at all.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (5 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 06/11] esp: add pseudo-DMA as used by Macintosh Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:47 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 08/11] hw/m68k: add Nubus support for macfb video card Mark Cave-Ayland
` (4 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/Makefile.objs | 1 +
hw/nubus/Makefile.objs | 4 +
hw/nubus/mac-nubus-bridge.c | 45 ++++++++
hw/nubus/nubus-bridge.c | 34 ++++++
hw/nubus/nubus-bus.c | 111 +++++++++++++++++++
hw/nubus/nubus-device.c | 214 ++++++++++++++++++++++++++++++++++++
include/hw/nubus/mac-nubus-bridge.h | 24 ++++
include/hw/nubus/nubus.h | 69 ++++++++++++
8 files changed, 502 insertions(+)
create mode 100644 hw/nubus/Makefile.objs
create mode 100644 hw/nubus/mac-nubus-bridge.c
create mode 100644 hw/nubus/nubus-bridge.c
create mode 100644 hw/nubus/nubus-bus.c
create mode 100644 hw/nubus/nubus-device.c
create mode 100644 include/hw/nubus/mac-nubus-bridge.h
create mode 100644 include/hw/nubus/nubus.h
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 39d882af6f..92dc338759 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -36,6 +36,7 @@ devices-dirs-$(CONFIG_SOFTMMU) += watchdog/
devices-dirs-$(CONFIG_SOFTMMU) += xen/
devices-dirs-$(CONFIG_MEM_DEVICE) += mem/
devices-dirs-$(CONFIG_SOFTMMU) += smbios/
+devices-dirs-$(CONFIG_NUBUS) += nubus/
devices-dirs-y += core/
common-obj-y += $(devices-dirs-y)
obj-y += $(devices-dirs-y)
diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs
new file mode 100644
index 0000000000..ebb050a4ad
--- /dev/null
+++ b/hw/nubus/Makefile.objs
@@ -0,0 +1,4 @@
+common-obj-y += nubus-device.o
+common-obj-y += nubus-bus.o
+common-obj-y += nubus-bridge.o
+common-obj-$(CONFIG_MAC) += mac-nubus-bridge.o
diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c
new file mode 100644
index 0000000000..7c329300b8
--- /dev/null
+++ b/hw/nubus/mac-nubus-bridge.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/nubus/mac-nubus-bridge.h"
+
+
+static void mac_nubus_bridge_init(Object *obj)
+{
+ MacNubusState *s = MAC_NUBUS_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ s->bus = NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, DEVICE(s), NULL));
+
+ sysbus_init_mmio(sbd, &s->bus->super_slot_io);
+ sysbus_init_mmio(sbd, &s->bus->slot_io);
+}
+
+static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Nubus bridge";
+}
+
+static const TypeInfo mac_nubus_bridge_info = {
+ .name = TYPE_MAC_NUBUS_BRIDGE,
+ .parent = TYPE_NUBUS_BRIDGE,
+ .instance_init = mac_nubus_bridge_init,
+ .instance_size = sizeof(MacNubusState),
+ .class_init = mac_nubus_bridge_class_init,
+};
+
+static void mac_nubus_bridge_register_types(void)
+{
+ type_register_static(&mac_nubus_bridge_info);
+}
+
+type_init(mac_nubus_bridge_register_types)
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
new file mode 100644
index 0000000000..cd8c6a91eb
--- /dev/null
+++ b/hw/nubus/nubus-bridge.c
@@ -0,0 +1,34 @@
+/*
+ * QEMU Macintosh Nubus
+ *
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/nubus/nubus.h"
+
+static void nubus_bridge_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->fw_name = "nubus";
+}
+
+static const TypeInfo nubus_bridge_info = {
+ .name = TYPE_NUBUS_BRIDGE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SysBusDevice),
+ .class_init = nubus_bridge_class_init,
+};
+
+static void nubus_register_types(void)
+{
+ type_register_static(&nubus_bridge_info);
+}
+
+type_init(nubus_register_types)
diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c
new file mode 100644
index 0000000000..448fa95600
--- /dev/null
+++ b/hw/nubus/nubus-bus.c
@@ -0,0 +1,111 @@
+/*
+ * QEMU Macintosh Nubus
+ *
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nubus/nubus.h"
+#include "hw/sysbus.h"
+#include "qapi/error.h"
+
+
+static NubusBus *nubus_find(void)
+{
+ /* Returns NULL unless there is exactly one nubus device */
+ return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL));
+}
+
+static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ return;
+}
+
+
+static uint64_t nubus_slot_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ return 0;
+}
+
+static const MemoryRegionOps nubus_slot_ops = {
+ .read = nubus_slot_read,
+ .write = nubus_slot_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ return;
+}
+
+static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ return 0;
+}
+
+static const MemoryRegionOps nubus_super_slot_ops = {
+ .read = nubus_super_slot_read,
+ .write = nubus_super_slot_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void nubus_realize(BusState *bus, Error **errp)
+{
+ if (!nubus_find()) {
+ error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_BUS);
+ return;
+ }
+}
+
+static void nubus_init(Object *obj)
+{
+ NubusBus *nubus = NUBUS_BUS(obj);
+
+ memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_ops,
+ nubus, "nubus-super-slots",
+ NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE);
+
+ memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops,
+ nubus, "nubus-slots",
+ NUBUS_SLOT_NB * NUBUS_SLOT_SIZE);
+
+ nubus->current_slot = NUBUS_FIRST_SLOT;
+}
+
+static void nubus_class_init(ObjectClass *oc, void *data)
+{
+ BusClass *bc = BUS_CLASS(oc);
+
+ bc->realize = nubus_realize;
+}
+
+static const TypeInfo nubus_bus_info = {
+ .name = TYPE_NUBUS_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(NubusBus),
+ .instance_init = nubus_init,
+ .class_init = nubus_class_init,
+};
+
+static void nubus_register_types(void)
+{
+ type_register_static(&nubus_bus_info);
+}
+
+type_init(nubus_register_types)
diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c
new file mode 100644
index 0000000000..670a8c4d53
--- /dev/null
+++ b/hw/nubus/nubus-device.c
@@ -0,0 +1,214 @@
+/*
+ * QEMU Macintosh Nubus
+ *
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/nubus/nubus.h"
+#include "qapi/error.h"
+
+
+/* The Format Block Structure */
+
+#define FBLOCK_DIRECTORY_OFFSET 0
+#define FBLOCK_LENGTH 4
+#define FBLOCK_CRC 8
+#define FBLOCK_REVISION_LEVEL 12
+#define FBLOCK_FORMAT 13
+#define FBLOCK_TEST_PATTERN 14
+#define FBLOCK_RESERVED 18
+#define FBLOCK_BYTE_LANES 19
+
+#define FBLOCK_SIZE 20
+#define FBLOCK_PATTERN_VAL 0x5a932bc7
+
+static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ NubusDevice *dev = opaque;
+ uint64_t val;
+
+#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff)
+ switch (addr) {
+ case FBLOCK_BYTE_LANES:
+ val = dev->byte_lanes;
+ val |= (val ^ 0xf) << 4;
+ break;
+ case FBLOCK_RESERVED:
+ val = 0x00;
+ break;
+ case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3:
+ val = BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN);
+ break;
+ case FBLOCK_FORMAT:
+ val = dev->rom_format;
+ break;
+ case FBLOCK_REVISION_LEVEL:
+ val = dev->rom_rev;
+ break;
+ case FBLOCK_CRC...FBLOCK_CRC + 3:
+ val = BYTE(dev->rom_crc, addr - FBLOCK_CRC);
+ break;
+ case FBLOCK_LENGTH...FBLOCK_LENGTH + 3:
+ val = BYTE(dev->rom_length, addr - FBLOCK_LENGTH);
+ break;
+ case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3:
+ val = BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ return val;
+}
+
+static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ /* READ-ONLY */
+}
+
+static const MemoryRegionOps nubus_format_block_ops = {
+ .read = nubus_fblock_read,
+ .write = nubus_fblock_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ }
+};
+
+static void nubus_register_format_block(NubusDevice *dev)
+{
+ char *fblock_name;
+
+ fblock_name = g_strdup_printf("nubus-slot-%d-format-block",
+ dev->slot_nb);
+
+ hwaddr fblock_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE;
+ memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops,
+ dev, fblock_name, FBLOCK_SIZE);
+ memory_region_add_subregion(&dev->slot_mem, fblock_offset,
+ &dev->fblock_io);
+
+ g_free(fblock_name);
+}
+
+static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+}
+
+static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ NubusDevice *dev = opaque;
+
+ return dev->rom[addr];
+}
+
+static const MemoryRegionOps mac_nubus_rom_ops = {
+ .read = mac_nubus_rom_read,
+ .write = mac_nubus_rom_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+
+void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
+ int revision, int format, uint8_t byte_lanes)
+{
+ hwaddr rom_offset;
+ char *rom_name;
+
+ /* FIXME : really compute CRC */
+ dev->rom_length = 0;
+ dev->rom_crc = 0;
+
+ dev->rom_rev = revision;
+ dev->rom_format = format;
+
+ dev->byte_lanes = byte_lanes;
+ dev->directory_offset = -size;
+
+ /* ROM */
+
+ dev->rom = rom;
+ rom_name = g_strdup_printf("nubus-slot-%d-rom", dev->slot_nb);
+ memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops,
+ dev, rom_name, size);
+ memory_region_set_readonly(&dev->rom_io, true);
+
+ rom_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE +
+ dev->directory_offset;
+ memory_region_add_subregion(&dev->slot_mem, rom_offset, &dev->rom_io);
+
+ g_free(rom_name);
+}
+
+static void nubus_device_realize(DeviceState *dev, Error **errp)
+{
+ NubusBus *nubus = NUBUS_BUS(qdev_get_parent_bus(DEVICE(dev)));
+ NubusDevice *nd = NUBUS_DEVICE(dev);
+ char *name;
+ hwaddr slot_offset;
+
+ if (nubus->current_slot < NUBUS_FIRST_SLOT ||
+ nubus->current_slot > NUBUS_LAST_SLOT) {
+ error_setg(errp, "Cannot register nubus card, not enough slots");
+ return;
+ }
+
+ nd->slot_nb = nubus->current_slot++;
+ name = g_strdup_printf("nubus-slot-%d", nd->slot_nb);
+
+ if (nd->slot_nb < NUBUS_FIRST_SLOT) {
+ /* Super */
+ slot_offset = (nd->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE;
+
+ memory_region_init(&nd->slot_mem, OBJECT(dev), name,
+ NUBUS_SUPER_SLOT_SIZE);
+ memory_region_add_subregion(&nubus->super_slot_io, slot_offset,
+ &nd->slot_mem);
+ } else {
+ /* Normal */
+ slot_offset = nd->slot_nb * NUBUS_SLOT_SIZE;
+
+ memory_region_init(&nd->slot_mem, OBJECT(dev), name, NUBUS_SLOT_SIZE);
+ memory_region_add_subregion(&nubus->slot_io, slot_offset,
+ &nd->slot_mem);
+ }
+
+ g_free(name);
+ nubus_register_format_block(nd);
+}
+
+static void nubus_device_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = nubus_device_realize;
+ dc->bus_type = TYPE_NUBUS_BUS;
+}
+
+static const TypeInfo nubus_device_type_info = {
+ .name = TYPE_NUBUS_DEVICE,
+ .parent = TYPE_DEVICE,
+ .abstract = true,
+ .instance_size = sizeof(NubusDevice),
+ .class_init = nubus_device_class_init,
+};
+
+static void nubus_register_types(void)
+{
+ type_register_static(&nubus_device_type_info);
+}
+
+type_init(nubus_register_types)
diff --git a/include/hw/nubus/mac-nubus-bridge.h b/include/hw/nubus/mac-nubus-bridge.h
new file mode 100644
index 0000000000..ce9c789d99
--- /dev/null
+++ b/include/hw/nubus/mac-nubus-bridge.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_NUBUS_MAC_H
+#define HW_NUBUS_MAC_H
+
+#include "hw/nubus/nubus.h"
+
+#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge"
+#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \
+ TYPE_MAC_NUBUS_BRIDGE)
+
+typedef struct MacNubusState {
+ SysBusDevice sysbus_dev;
+
+ NubusBus *bus;
+} MacNubusState;
+
+#endif
diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h
new file mode 100644
index 0000000000..096bafb322
--- /dev/null
+++ b/include/hw/nubus/nubus.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_NUBUS_NUBUS_H
+#define HW_NUBUS_NUBUS_H
+
+#include "hw/qdev.h"
+#include "exec/address-spaces.h"
+
+#define NUBUS_SUPER_SLOT_SIZE 0x10000000U
+#define NUBUS_SUPER_SLOT_NB 0x9
+
+#define NUBUS_SLOT_SIZE 0x01000000
+#define NUBUS_SLOT_NB 0xF
+
+#define NUBUS_FIRST_SLOT 0x9
+#define NUBUS_LAST_SLOT 0xF
+
+#define TYPE_NUBUS_DEVICE "nubus-device"
+#define NUBUS_DEVICE(obj) \
+ OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE)
+
+#define TYPE_NUBUS_BUS "nubus-bus"
+#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
+
+#define TYPE_NUBUS_BRIDGE "nubus-bridge"
+#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
+
+typedef struct NubusBus {
+ BusState qbus;
+
+ MemoryRegion super_slot_io;
+ MemoryRegion slot_io;
+
+ int current_slot;
+} NubusBus;
+
+typedef struct NubusDevice {
+ DeviceState qdev;
+
+ int slot_nb;
+ MemoryRegion slot_mem;
+
+ /* Format Block */
+
+ MemoryRegion fblock_io;
+
+ uint32_t rom_length;
+ uint32_t rom_crc;
+ uint8_t rom_rev;
+ uint8_t rom_format;
+ uint8_t byte_lanes;
+ int32_t directory_offset;
+
+ /* ROM */
+
+ MemoryRegion rom_io;
+ const uint8_t *rom;
+} NubusDevice;
+
+void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
+ int revision, int format, uint8_t byte_lanes);
+
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support Mark Cave-Ayland
@ 2018-10-30 6:47 ` Hervé Poussineau
2018-10-30 10:23 ` Mark Cave-Ayland
0 siblings, 1 reply; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:47 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/Makefile.objs | 1 +
> hw/nubus/Makefile.objs | 4 +
> hw/nubus/mac-nubus-bridge.c | 45 ++++++++
> hw/nubus/nubus-bridge.c | 34 ++++++
> hw/nubus/nubus-bus.c | 111 +++++++++++++++++++
> hw/nubus/nubus-device.c | 214 ++++++++++++++++++++++++++++++++++++
> include/hw/nubus/mac-nubus-bridge.h | 24 ++++
> include/hw/nubus/nubus.h | 69 ++++++++++++
> 8 files changed, 502 insertions(+)
> create mode 100644 hw/nubus/Makefile.objs
> create mode 100644 hw/nubus/mac-nubus-bridge.c
> create mode 100644 hw/nubus/nubus-bridge.c
> create mode 100644 hw/nubus/nubus-bus.c
> create mode 100644 hw/nubus/nubus-device.c
> create mode 100644 include/hw/nubus/mac-nubus-bridge.h
> create mode 100644 include/hw/nubus/nubus.h
>
> diff --git a/hw/Makefile.objs b/hw/Makefile.objs
> index 39d882af6f..92dc338759 100644
> --- a/hw/Makefile.objs
> +++ b/hw/Makefile.objs
> @@ -36,6 +36,7 @@ devices-dirs-$(CONFIG_SOFTMMU) += watchdog/
> devices-dirs-$(CONFIG_SOFTMMU) += xen/
> devices-dirs-$(CONFIG_MEM_DEVICE) += mem/
> devices-dirs-$(CONFIG_SOFTMMU) += smbios/
> +devices-dirs-$(CONFIG_NUBUS) += nubus/
> devices-dirs-y += core/
> common-obj-y += $(devices-dirs-y)
> obj-y += $(devices-dirs-y)
> diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs
> new file mode 100644
> index 0000000000..ebb050a4ad
> --- /dev/null
> +++ b/hw/nubus/Makefile.objs
> @@ -0,0 +1,4 @@
> +common-obj-y += nubus-device.o
> +common-obj-y += nubus-bus.o
> +common-obj-y += nubus-bridge.o
> +common-obj-$(CONFIG_MAC) += mac-nubus-bridge.o
> diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c
> new file mode 100644
> index 0000000000..7c329300b8
> --- /dev/null
> +++ b/hw/nubus/mac-nubus-bridge.c
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/nubus/mac-nubus-bridge.h"
> +
> +
> +static void mac_nubus_bridge_init(Object *obj)
> +{
> + MacNubusState *s = MAC_NUBUS_BRIDGE(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +
> + s->bus = NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, DEVICE(s), NULL));
> +
> + sysbus_init_mmio(sbd, &s->bus->super_slot_io);
> + sysbus_init_mmio(sbd, &s->bus->slot_io);
> +}
> +
> +static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "Nubus bridge";
> +}
> +
> +static const TypeInfo mac_nubus_bridge_info = {
> + .name = TYPE_MAC_NUBUS_BRIDGE,
> + .parent = TYPE_NUBUS_BRIDGE,
> + .instance_init = mac_nubus_bridge_init,
> + .instance_size = sizeof(MacNubusState),
> + .class_init = mac_nubus_bridge_class_init,
> +};
> +
> +static void mac_nubus_bridge_register_types(void)
> +{
> + type_register_static(&mac_nubus_bridge_info);
> +}
> +
> +type_init(mac_nubus_bridge_register_types)
> diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
> new file mode 100644
> index 0000000000..cd8c6a91eb
> --- /dev/null
> +++ b/hw/nubus/nubus-bridge.c
> @@ -0,0 +1,34 @@
> +/*
> + * QEMU Macintosh Nubus
> + *
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/nubus/nubus.h"
> +
> +static void nubus_bridge_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->fw_name = "nubus";
> +}
> +
> +static const TypeInfo nubus_bridge_info = {
> + .name = TYPE_NUBUS_BRIDGE,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(SysBusDevice),
> + .class_init = nubus_bridge_class_init,
> +};
> +
> +static void nubus_register_types(void)
> +{
> + type_register_static(&nubus_bridge_info);
> +}
> +
> +type_init(nubus_register_types)
> diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c
> new file mode 100644
> index 0000000000..448fa95600
> --- /dev/null
> +++ b/hw/nubus/nubus-bus.c
> @@ -0,0 +1,111 @@
> +/*
> + * QEMU Macintosh Nubus
> + *
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/nubus/nubus.h"
> +#include "hw/sysbus.h"
> +#include "qapi/error.h"
> +
> +
> +static NubusBus *nubus_find(void)
> +{
> + /* Returns NULL unless there is exactly one nubus device */
> + return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL));
> +}
> +
> +static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int size)
> +{
> + return;
> +}
Useless return. In some other functions (like nubus_fblock_write), you don't have a return statement, but a comment saying "READ-ONLY".
> +
> +
> +static uint64_t nubus_slot_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + return 0;
> +}
Empty read function. Can your nubus slot be replaced by an "empty_slot" or an "unimplemented device"?
> +
> +static const MemoryRegionOps nubus_slot_ops = {
> + .read = nubus_slot_read,
> + .write = nubus_slot_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> +static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int size)
> +{
> + return;
> +}
Useless return. In some other functions (like nubus_fblock_write), you don't have a return statement, but a comment saying "READ-ONLY".
> +
> +static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + return 0;
> +}
Same thing here. Can your nubus super slot be replaced by an "empty_slot" or an "unimplemented device"?
> +
> +static const MemoryRegionOps nubus_super_slot_ops = {
> + .read = nubus_super_slot_read,
> + .write = nubus_super_slot_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> +static void nubus_realize(BusState *bus, Error **errp)
> +{
> + if (!nubus_find()) {
> + error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_BUS);
> + return;
> + }
> +}
> +
> +static void nubus_init(Object *obj)
> +{
> + NubusBus *nubus = NUBUS_BUS(obj);
> +
> + memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_ops,
> + nubus, "nubus-super-slots",
> + NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE);
> +
> + memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops,
> + nubus, "nubus-slots",
> + NUBUS_SLOT_NB * NUBUS_SLOT_SIZE);
> +
> + nubus->current_slot = NUBUS_FIRST_SLOT;
> +}
> +
> +static void nubus_class_init(ObjectClass *oc, void *data)
> +{
> + BusClass *bc = BUS_CLASS(oc);
> +
> + bc->realize = nubus_realize;
> +}
> +
> +static const TypeInfo nubus_bus_info = {
> + .name = TYPE_NUBUS_BUS,
> + .parent = TYPE_BUS,
> + .instance_size = sizeof(NubusBus),
> + .instance_init = nubus_init,
> + .class_init = nubus_class_init,
> +};
> +
> +static void nubus_register_types(void)
> +{
> + type_register_static(&nubus_bus_info);
> +}
> +
> +type_init(nubus_register_types)
> diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c
> new file mode 100644
> index 0000000000..670a8c4d53
> --- /dev/null
> +++ b/hw/nubus/nubus-device.c
> @@ -0,0 +1,214 @@
> +/*
> + * QEMU Macintosh Nubus
> + *
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/nubus/nubus.h"
> +#include "qapi/error.h"
> +
> +
> +/* The Format Block Structure */
> +
> +#define FBLOCK_DIRECTORY_OFFSET 0
> +#define FBLOCK_LENGTH 4
> +#define FBLOCK_CRC 8
> +#define FBLOCK_REVISION_LEVEL 12
> +#define FBLOCK_FORMAT 13
> +#define FBLOCK_TEST_PATTERN 14
> +#define FBLOCK_RESERVED 18
> +#define FBLOCK_BYTE_LANES 19
> +
> +#define FBLOCK_SIZE 20
> +#define FBLOCK_PATTERN_VAL 0x5a932bc7
> +
> +static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + NubusDevice *dev = opaque;
> + uint64_t val;
> +
> +#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff)
> + switch (addr) {
> + case FBLOCK_BYTE_LANES:
> + val = dev->byte_lanes;
> + val |= (val ^ 0xf) << 4;
> + break;
> + case FBLOCK_RESERVED:
> + val = 0x00;
> + break;
> + case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3:
> + val = BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN);
> + break;
> + case FBLOCK_FORMAT:
> + val = dev->rom_format;
> + break;
> + case FBLOCK_REVISION_LEVEL:
> + val = dev->rom_rev;
> + break;
> + case FBLOCK_CRC...FBLOCK_CRC + 3:
> + val = BYTE(dev->rom_crc, addr - FBLOCK_CRC);
> + break;
> + case FBLOCK_LENGTH...FBLOCK_LENGTH + 3:
> + val = BYTE(dev->rom_length, addr - FBLOCK_LENGTH);
> + break;
> + case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3:
> + val = BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET);
> + break;
> + default:
> + val = 0;
> + break;
> + }
> + return val;
> +}
> +
> +static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int size)
> +{
> + /* READ-ONLY */
> +}
> +
> +static const MemoryRegionOps nubus_format_block_ops = {
> + .read = nubus_fblock_read,
> + .write = nubus_fblock_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + }
> +};
> +
> +static void nubus_register_format_block(NubusDevice *dev)
> +{
> + char *fblock_name;
> +
> + fblock_name = g_strdup_printf("nubus-slot-%d-format-block",
> + dev->slot_nb);
> +
> + hwaddr fblock_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE;
> + memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops,
> + dev, fblock_name, FBLOCK_SIZE);
> + memory_region_add_subregion(&dev->slot_mem, fblock_offset,
> + &dev->fblock_io);
> +
> + g_free(fblock_name);
> +}
> +
> +static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int size)
> +{
> +}
Add a "READ-ONLY" comment?
> +
> +static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + NubusDevice *dev = opaque;
> +
> + return dev->rom[addr];
> +}
> +
> +static const MemoryRegionOps mac_nubus_rom_ops = {
> + .read = mac_nubus_rom_read,
> + .write = mac_nubus_rom_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> +
> +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
> + int revision, int format, uint8_t byte_lanes)
> +{
> + hwaddr rom_offset;
> + char *rom_name;
> +
> + /* FIXME : really compute CRC */
> + dev->rom_length = 0;
> + dev->rom_crc = 0;
> +
> + dev->rom_rev = revision;
> + dev->rom_format = format;
> +
> + dev->byte_lanes = byte_lanes;
> + dev->directory_offset = -size;
> +
> + /* ROM */
> +
> + dev->rom = rom;
> + rom_name = g_strdup_printf("nubus-slot-%d-rom", dev->slot_nb);
> + memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops,
> + dev, rom_name, size);
> + memory_region_set_readonly(&dev->rom_io, true);
> +
> + rom_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE +
> + dev->directory_offset;
> + memory_region_add_subregion(&dev->slot_mem, rom_offset, &dev->rom_io);
> +
> + g_free(rom_name);
> +}
> +
> +static void nubus_device_realize(DeviceState *dev, Error **errp)
> +{
> + NubusBus *nubus = NUBUS_BUS(qdev_get_parent_bus(DEVICE(dev)));
> + NubusDevice *nd = NUBUS_DEVICE(dev);
> + char *name;
> + hwaddr slot_offset;
> +
> + if (nubus->current_slot < NUBUS_FIRST_SLOT ||
> + nubus->current_slot > NUBUS_LAST_SLOT) {
> + error_setg(errp, "Cannot register nubus card, not enough slots");
> + return;
> + }
> +
> + nd->slot_nb = nubus->current_slot++;
> + name = g_strdup_printf("nubus-slot-%d", nd->slot_nb);
> +
> + if (nd->slot_nb < NUBUS_FIRST_SLOT) {
> + /* Super */
> + slot_offset = (nd->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE;
> +
> + memory_region_init(&nd->slot_mem, OBJECT(dev), name,
> + NUBUS_SUPER_SLOT_SIZE);
> + memory_region_add_subregion(&nubus->super_slot_io, slot_offset,
> + &nd->slot_mem);
> + } else {
> + /* Normal */
> + slot_offset = nd->slot_nb * NUBUS_SLOT_SIZE;
> +
> + memory_region_init(&nd->slot_mem, OBJECT(dev), name, NUBUS_SLOT_SIZE);
> + memory_region_add_subregion(&nubus->slot_io, slot_offset,
> + &nd->slot_mem);
> + }
> +
> + g_free(name);
> + nubus_register_format_block(nd);
> +}
> +
> +static void nubus_device_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = nubus_device_realize;
> + dc->bus_type = TYPE_NUBUS_BUS;
> +}
> +
> +static const TypeInfo nubus_device_type_info = {
> + .name = TYPE_NUBUS_DEVICE,
> + .parent = TYPE_DEVICE,
> + .abstract = true,
> + .instance_size = sizeof(NubusDevice),
> + .class_init = nubus_device_class_init,
> +};
> +
> +static void nubus_register_types(void)
> +{
> + type_register_static(&nubus_device_type_info);
> +}
> +
> +type_init(nubus_register_types)
> diff --git a/include/hw/nubus/mac-nubus-bridge.h b/include/hw/nubus/mac-nubus-bridge.h
> new file mode 100644
> index 0000000000..ce9c789d99
> --- /dev/null
> +++ b/include/hw/nubus/mac-nubus-bridge.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_NUBUS_MAC_H
> +#define HW_NUBUS_MAC_H
> +
> +#include "hw/nubus/nubus.h"
> +
> +#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge"
> +#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \
> + TYPE_MAC_NUBUS_BRIDGE)
> +
> +typedef struct MacNubusState {
> + SysBusDevice sysbus_dev;
> +
> + NubusBus *bus;
> +} MacNubusState;
> +
> +#endif
> diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h
> new file mode 100644
> index 0000000000..096bafb322
> --- /dev/null
> +++ b/include/hw/nubus/nubus.h
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef HW_NUBUS_NUBUS_H
> +#define HW_NUBUS_NUBUS_H
> +
> +#include "hw/qdev.h"
> +#include "exec/address-spaces.h"
> +
> +#define NUBUS_SUPER_SLOT_SIZE 0x10000000U
> +#define NUBUS_SUPER_SLOT_NB 0x9
> +
> +#define NUBUS_SLOT_SIZE 0x01000000
> +#define NUBUS_SLOT_NB 0xF
> +
> +#define NUBUS_FIRST_SLOT 0x9
> +#define NUBUS_LAST_SLOT 0xF
> +
> +#define TYPE_NUBUS_DEVICE "nubus-device"
> +#define NUBUS_DEVICE(obj) \
> + OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE)
> +
> +#define TYPE_NUBUS_BUS "nubus-bus"
> +#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
> +
> +#define TYPE_NUBUS_BRIDGE "nubus-bridge"
> +#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
> +
> +typedef struct NubusBus {
> + BusState qbus;
> +
> + MemoryRegion super_slot_io;
> + MemoryRegion slot_io;
> +
> + int current_slot;
> +} NubusBus;
> +
> +typedef struct NubusDevice {
> + DeviceState qdev;
> +
> + int slot_nb;
> + MemoryRegion slot_mem;
> +
> + /* Format Block */
> +
> + MemoryRegion fblock_io;
> +
> + uint32_t rom_length;
> + uint32_t rom_crc;
> + uint8_t rom_rev;
> + uint8_t rom_format;
> + uint8_t byte_lanes;
> + int32_t directory_offset;
> +
> + /* ROM */
> +
> + MemoryRegion rom_io;
> + const uint8_t *rom;
> +} NubusDevice;
> +
> +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
> + int revision, int format, uint8_t byte_lanes);
> +
> +#endif
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support
2018-10-30 6:47 ` Hervé Poussineau
@ 2018-10-30 10:23 ` Mark Cave-Ayland
0 siblings, 0 replies; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 10:23 UTC (permalink / raw)
To: Hervé Poussineau, qemu-devel, kwolf, famz, qemu-block,
jasowang, dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien,
laurent
On 30/10/2018 06:47, Hervé Poussineau wrote:
> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/Makefile.objs | 1 +
>> hw/nubus/Makefile.objs | 4 +
>> hw/nubus/mac-nubus-bridge.c | 45 ++++++++
>> hw/nubus/nubus-bridge.c | 34 ++++++
>> hw/nubus/nubus-bus.c | 111 +++++++++++++++++++
>> hw/nubus/nubus-device.c | 214 ++++++++++++++++++++++++++++++++++++
>> include/hw/nubus/mac-nubus-bridge.h | 24 ++++
>> include/hw/nubus/nubus.h | 69 ++++++++++++
>> 8 files changed, 502 insertions(+)
>> create mode 100644 hw/nubus/Makefile.objs
>> create mode 100644 hw/nubus/mac-nubus-bridge.c
>> create mode 100644 hw/nubus/nubus-bridge.c
>> create mode 100644 hw/nubus/nubus-bus.c
>> create mode 100644 hw/nubus/nubus-device.c
>> create mode 100644 include/hw/nubus/mac-nubus-bridge.h
>> create mode 100644 include/hw/nubus/nubus.h
>>
>> diff --git a/hw/Makefile.objs b/hw/Makefile.objs
>> index 39d882af6f..92dc338759 100644
>> --- a/hw/Makefile.objs
>> +++ b/hw/Makefile.objs
>> @@ -36,6 +36,7 @@ devices-dirs-$(CONFIG_SOFTMMU) += watchdog/
>> devices-dirs-$(CONFIG_SOFTMMU) += xen/
>> devices-dirs-$(CONFIG_MEM_DEVICE) += mem/
>> devices-dirs-$(CONFIG_SOFTMMU) += smbios/
>> +devices-dirs-$(CONFIG_NUBUS) += nubus/
>> devices-dirs-y += core/
>> common-obj-y += $(devices-dirs-y)
>> obj-y += $(devices-dirs-y)
>> diff --git a/hw/nubus/Makefile.objs b/hw/nubus/Makefile.objs
>> new file mode 100644
>> index 0000000000..ebb050a4ad
>> --- /dev/null
>> +++ b/hw/nubus/Makefile.objs
>> @@ -0,0 +1,4 @@
>> +common-obj-y += nubus-device.o
>> +common-obj-y += nubus-bus.o
>> +common-obj-y += nubus-bridge.o
>> +common-obj-$(CONFIG_MAC) += mac-nubus-bridge.o
>> diff --git a/hw/nubus/mac-nubus-bridge.c b/hw/nubus/mac-nubus-bridge.c
>> new file mode 100644
>> index 0000000000..7c329300b8
>> --- /dev/null
>> +++ b/hw/nubus/mac-nubus-bridge.c
>> @@ -0,0 +1,45 @@
>> +/*
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/nubus/mac-nubus-bridge.h"
>> +
>> +
>> +static void mac_nubus_bridge_init(Object *obj)
>> +{
>> + MacNubusState *s = MAC_NUBUS_BRIDGE(obj);
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>> +
>> + s->bus = NUBUS_BUS(qbus_create(TYPE_NUBUS_BUS, DEVICE(s), NULL));
>> +
>> + sysbus_init_mmio(sbd, &s->bus->super_slot_io);
>> + sysbus_init_mmio(sbd, &s->bus->slot_io);
>> +}
>> +
>> +static void mac_nubus_bridge_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->desc = "Nubus bridge";
>> +}
>> +
>> +static const TypeInfo mac_nubus_bridge_info = {
>> + .name = TYPE_MAC_NUBUS_BRIDGE,
>> + .parent = TYPE_NUBUS_BRIDGE,
>> + .instance_init = mac_nubus_bridge_init,
>> + .instance_size = sizeof(MacNubusState),
>> + .class_init = mac_nubus_bridge_class_init,
>> +};
>> +
>> +static void mac_nubus_bridge_register_types(void)
>> +{
>> + type_register_static(&mac_nubus_bridge_info);
>> +}
>> +
>> +type_init(mac_nubus_bridge_register_types)
>> diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
>> new file mode 100644
>> index 0000000000..cd8c6a91eb
>> --- /dev/null
>> +++ b/hw/nubus/nubus-bridge.c
>> @@ -0,0 +1,34 @@
>> +/*
>> + * QEMU Macintosh Nubus
>> + *
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/nubus/nubus.h"
>> +
>> +static void nubus_bridge_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->fw_name = "nubus";
>> +}
>> +
>> +static const TypeInfo nubus_bridge_info = {
>> + .name = TYPE_NUBUS_BRIDGE,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(SysBusDevice),
>> + .class_init = nubus_bridge_class_init,
>> +};
>> +
>> +static void nubus_register_types(void)
>> +{
>> + type_register_static(&nubus_bridge_info);
>> +}
>> +
>> +type_init(nubus_register_types)
>> diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c
>> new file mode 100644
>> index 0000000000..448fa95600
>> --- /dev/null
>> +++ b/hw/nubus/nubus-bus.c
>> @@ -0,0 +1,111 @@
>> +/*
>> + * QEMU Macintosh Nubus
>> + *
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/nubus/nubus.h"
>> +#include "hw/sysbus.h"
>> +#include "qapi/error.h"
>> +
>> +
>> +static NubusBus *nubus_find(void)
>> +{
>> + /* Returns NULL unless there is exactly one nubus device */
>> + return NUBUS_BUS(object_resolve_path_type("", TYPE_NUBUS_BUS, NULL));
>> +}
>> +
>> +static void nubus_slot_write(void *opaque, hwaddr addr, uint64_t val,
>> + unsigned int size)
>> +{
>> + return;
>> +}
>
> Useless return. In some other functions (like nubus_fblock_write), you don't have a
> return statement, but a comment saying "READ-ONLY".
Hmmm that's true (and probably something that I introduced when switching over to
qdev). I'll remove the return from the next revision, and update the comments to be
more consistent.
>> +
>> +
>> +static uint64_t nubus_slot_read(void *opaque, hwaddr addr,
>> + unsigned int size)
>> +{
>> + return 0;
>> +}
>
> Empty read function. Can your nubus slot be replaced by an "empty_slot" or an
> "unimplemented device"?
AFAICT the nubus devices are addressed directly from the bus, so effectively what
this is doing is defining the default bus behaviour when a device isn't present. Note
that a separate memory region container for each slot range is created as part of the
NubusDevice realize function so each "plugged" slot is represented clearly in the
"info mtree" output.
>> +
>> +static const MemoryRegionOps nubus_slot_ops = {
>> + .read = nubus_slot_read,
>> + .write = nubus_slot_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + },
>> +};
>> +
>> +static void nubus_super_slot_write(void *opaque, hwaddr addr, uint64_t val,
>> + unsigned int size)
>> +{
>> + return;
>> +}
>
> Useless return. In some other functions (like nubus_fblock_write), you don't have a
> return statement, but a comment saying "READ-ONLY".
I'll update this too.
>> +
>> +static uint64_t nubus_super_slot_read(void *opaque, hwaddr addr,
>> + unsigned int size)
>> +{
>> + return 0;
>> +}
>
> Same thing here. Can your nubus super slot be replaced by an "empty_slot" or an
> "unimplemented device"?
... and also here.
>> +
>> +static const MemoryRegionOps nubus_super_slot_ops = {
>> + .read = nubus_super_slot_read,
>> + .write = nubus_super_slot_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + },
>> +};
>> +
>> +static void nubus_realize(BusState *bus, Error **errp)
>> +{
>> + if (!nubus_find()) {
>> + error_setg(errp, "at most one %s device is permitted", TYPE_NUBUS_BUS);
>> + return;
>> + }
>> +}
>> +
>> +static void nubus_init(Object *obj)
>> +{
>> + NubusBus *nubus = NUBUS_BUS(obj);
>> +
>> + memory_region_init_io(&nubus->super_slot_io, obj, &nubus_super_slot_ops,
>> + nubus, "nubus-super-slots",
>> + NUBUS_SUPER_SLOT_NB * NUBUS_SUPER_SLOT_SIZE);
>> +
>> + memory_region_init_io(&nubus->slot_io, obj, &nubus_slot_ops,
>> + nubus, "nubus-slots",
>> + NUBUS_SLOT_NB * NUBUS_SLOT_SIZE);
>> +
>> + nubus->current_slot = NUBUS_FIRST_SLOT;
>> +}
>> +
>> +static void nubus_class_init(ObjectClass *oc, void *data)
>> +{
>> + BusClass *bc = BUS_CLASS(oc);
>> +
>> + bc->realize = nubus_realize;
>> +}
>> +
>> +static const TypeInfo nubus_bus_info = {
>> + .name = TYPE_NUBUS_BUS,
>> + .parent = TYPE_BUS,
>> + .instance_size = sizeof(NubusBus),
>> + .instance_init = nubus_init,
>> + .class_init = nubus_class_init,
>> +};
>> +
>> +static void nubus_register_types(void)
>> +{
>> + type_register_static(&nubus_bus_info);
>> +}
>> +
>> +type_init(nubus_register_types)
>> diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c
>> new file mode 100644
>> index 0000000000..670a8c4d53
>> --- /dev/null
>> +++ b/hw/nubus/nubus-device.c
>> @@ -0,0 +1,214 @@
>> +/*
>> + * QEMU Macintosh Nubus
>> + *
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/nubus/nubus.h"
>> +#include "qapi/error.h"
>> +
>> +
>> +/* The Format Block Structure */
>> +
>> +#define FBLOCK_DIRECTORY_OFFSET 0
>> +#define FBLOCK_LENGTH 4
>> +#define FBLOCK_CRC 8
>> +#define FBLOCK_REVISION_LEVEL 12
>> +#define FBLOCK_FORMAT 13
>> +#define FBLOCK_TEST_PATTERN 14
>> +#define FBLOCK_RESERVED 18
>> +#define FBLOCK_BYTE_LANES 19
>> +
>> +#define FBLOCK_SIZE 20
>> +#define FBLOCK_PATTERN_VAL 0x5a932bc7
>> +
>> +static uint64_t nubus_fblock_read(void *opaque, hwaddr addr, unsigned int size)
>> +{
>> + NubusDevice *dev = opaque;
>> + uint64_t val;
>> +
>> +#define BYTE(v, b) (((v) >> (24 - 8 * (b))) & 0xff)
>> + switch (addr) {
>> + case FBLOCK_BYTE_LANES:
>> + val = dev->byte_lanes;
>> + val |= (val ^ 0xf) << 4;
>> + break;
>> + case FBLOCK_RESERVED:
>> + val = 0x00;
>> + break;
>> + case FBLOCK_TEST_PATTERN...FBLOCK_TEST_PATTERN + 3:
>> + val = BYTE(FBLOCK_PATTERN_VAL, addr - FBLOCK_TEST_PATTERN);
>> + break;
>> + case FBLOCK_FORMAT:
>> + val = dev->rom_format;
>> + break;
>> + case FBLOCK_REVISION_LEVEL:
>> + val = dev->rom_rev;
>> + break;
>> + case FBLOCK_CRC...FBLOCK_CRC + 3:
>> + val = BYTE(dev->rom_crc, addr - FBLOCK_CRC);
>> + break;
>> + case FBLOCK_LENGTH...FBLOCK_LENGTH + 3:
>> + val = BYTE(dev->rom_length, addr - FBLOCK_LENGTH);
>> + break;
>> + case FBLOCK_DIRECTORY_OFFSET...FBLOCK_DIRECTORY_OFFSET + 3:
>> + val = BYTE(dev->directory_offset, addr - FBLOCK_DIRECTORY_OFFSET);
>> + break;
>> + default:
>> + val = 0;
>> + break;
>> + }
>> + return val;
>> +}
>> +
>> +static void nubus_fblock_write(void *opaque, hwaddr addr, uint64_t val,
>> + unsigned int size)
>> +{
>> + /* READ-ONLY */
>> +}
>> +
>> +static const MemoryRegionOps nubus_format_block_ops = {
>> + .read = nubus_fblock_read,
>> + .write = nubus_fblock_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + }
>> +};
>> +
>> +static void nubus_register_format_block(NubusDevice *dev)
>> +{
>> + char *fblock_name;
>> +
>> + fblock_name = g_strdup_printf("nubus-slot-%d-format-block",
>> + dev->slot_nb);
>> +
>> + hwaddr fblock_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE;
>> + memory_region_init_io(&dev->fblock_io, NULL, &nubus_format_block_ops,
>> + dev, fblock_name, FBLOCK_SIZE);
>> + memory_region_add_subregion(&dev->slot_mem, fblock_offset,
>> + &dev->fblock_io);
>> +
>> + g_free(fblock_name);
>> +}
>> +
>> +static void mac_nubus_rom_write(void *opaque, hwaddr addr, uint64_t val,
>> + unsigned int size)
>> +{
>> +}
>
> Add a "READ-ONLY" comment?
>
>> +
>> +static uint64_t mac_nubus_rom_read(void *opaque, hwaddr addr,
>> + unsigned int size)
>> +{
>> + NubusDevice *dev = opaque;
>> +
>> + return dev->rom[addr];
>> +}
>> +
>> +static const MemoryRegionOps mac_nubus_rom_ops = {
>> + .read = mac_nubus_rom_read,
>> + .write = mac_nubus_rom_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + },
>> +};
>> +
>> +
>> +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
>> + int revision, int format, uint8_t byte_lanes)
>> +{
>> + hwaddr rom_offset;
>> + char *rom_name;
>> +
>> + /* FIXME : really compute CRC */
>> + dev->rom_length = 0;
>> + dev->rom_crc = 0;
>> +
>> + dev->rom_rev = revision;
>> + dev->rom_format = format;
>> +
>> + dev->byte_lanes = byte_lanes;
>> + dev->directory_offset = -size;
>> +
>> + /* ROM */
>> +
>> + dev->rom = rom;
>> + rom_name = g_strdup_printf("nubus-slot-%d-rom", dev->slot_nb);
>> + memory_region_init_io(&dev->rom_io, NULL, &mac_nubus_rom_ops,
>> + dev, rom_name, size);
>> + memory_region_set_readonly(&dev->rom_io, true);
>> +
>> + rom_offset = memory_region_size(&dev->slot_mem) - FBLOCK_SIZE +
>> + dev->directory_offset;
>> + memory_region_add_subregion(&dev->slot_mem, rom_offset, &dev->rom_io);
>> +
>> + g_free(rom_name);
>> +}
>> +
>> +static void nubus_device_realize(DeviceState *dev, Error **errp)
>> +{
>> + NubusBus *nubus = NUBUS_BUS(qdev_get_parent_bus(DEVICE(dev)));
>> + NubusDevice *nd = NUBUS_DEVICE(dev);
>> + char *name;
>> + hwaddr slot_offset;
>> +
>> + if (nubus->current_slot < NUBUS_FIRST_SLOT ||
>> + nubus->current_slot > NUBUS_LAST_SLOT) {
>> + error_setg(errp, "Cannot register nubus card, not enough slots");
>> + return;
>> + }
>> +
>> + nd->slot_nb = nubus->current_slot++;
>> + name = g_strdup_printf("nubus-slot-%d", nd->slot_nb);
>> +
>> + if (nd->slot_nb < NUBUS_FIRST_SLOT) {
>> + /* Super */
>> + slot_offset = (nd->slot_nb - 6) * NUBUS_SUPER_SLOT_SIZE;
>> +
>> + memory_region_init(&nd->slot_mem, OBJECT(dev), name,
>> + NUBUS_SUPER_SLOT_SIZE);
>> + memory_region_add_subregion(&nubus->super_slot_io, slot_offset,
>> + &nd->slot_mem);
>> + } else {
>> + /* Normal */
>> + slot_offset = nd->slot_nb * NUBUS_SLOT_SIZE;
>> +
>> + memory_region_init(&nd->slot_mem, OBJECT(dev), name, NUBUS_SLOT_SIZE);
>> + memory_region_add_subregion(&nubus->slot_io, slot_offset,
>> + &nd->slot_mem);
>> + }
>> +
>> + g_free(name);
>> + nubus_register_format_block(nd);
>> +}
>> +
>> +static void nubus_device_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->realize = nubus_device_realize;
>> + dc->bus_type = TYPE_NUBUS_BUS;
>> +}
>> +
>> +static const TypeInfo nubus_device_type_info = {
>> + .name = TYPE_NUBUS_DEVICE,
>> + .parent = TYPE_DEVICE,
>> + .abstract = true,
>> + .instance_size = sizeof(NubusDevice),
>> + .class_init = nubus_device_class_init,
>> +};
>> +
>> +static void nubus_register_types(void)
>> +{
>> + type_register_static(&nubus_device_type_info);
>> +}
>> +
>> +type_init(nubus_register_types)
>> diff --git a/include/hw/nubus/mac-nubus-bridge.h b/include/hw/nubus/mac-nubus-bridge.h
>> new file mode 100644
>> index 0000000000..ce9c789d99
>> --- /dev/null
>> +++ b/include/hw/nubus/mac-nubus-bridge.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#ifndef HW_NUBUS_MAC_H
>> +#define HW_NUBUS_MAC_H
>> +
>> +#include "hw/nubus/nubus.h"
>> +
>> +#define TYPE_MAC_NUBUS_BRIDGE "mac-nubus-bridge"
>> +#define MAC_NUBUS_BRIDGE(obj) OBJECT_CHECK(MacNubusState, (obj), \
>> + TYPE_MAC_NUBUS_BRIDGE)
>> +
>> +typedef struct MacNubusState {
>> + SysBusDevice sysbus_dev;
>> +
>> + NubusBus *bus;
>> +} MacNubusState;
>> +
>> +#endif
>> diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h
>> new file mode 100644
>> index 0000000000..096bafb322
>> --- /dev/null
>> +++ b/include/hw/nubus/nubus.h
>> @@ -0,0 +1,69 @@
>> +/*
>> + * Copyright (c) 2013-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#ifndef HW_NUBUS_NUBUS_H
>> +#define HW_NUBUS_NUBUS_H
>> +
>> +#include "hw/qdev.h"
>> +#include "exec/address-spaces.h"
>> +
>> +#define NUBUS_SUPER_SLOT_SIZE 0x10000000U
>> +#define NUBUS_SUPER_SLOT_NB 0x9
>> +
>> +#define NUBUS_SLOT_SIZE 0x01000000
>> +#define NUBUS_SLOT_NB 0xF
>> +
>> +#define NUBUS_FIRST_SLOT 0x9
>> +#define NUBUS_LAST_SLOT 0xF
>> +
>> +#define TYPE_NUBUS_DEVICE "nubus-device"
>> +#define NUBUS_DEVICE(obj) \
>> + OBJECT_CHECK(NubusDevice, (obj), TYPE_NUBUS_DEVICE)
>> +
>> +#define TYPE_NUBUS_BUS "nubus-bus"
>> +#define NUBUS_BUS(obj) OBJECT_CHECK(NubusBus, (obj), TYPE_NUBUS_BUS)
>> +
>> +#define TYPE_NUBUS_BRIDGE "nubus-bridge"
>> +#define NUBUS_BRIDGE(obj) OBJECT_CHECK(NubusBridge, (obj), TYPE_NUBUS_BRIDGE)
>> +
>> +typedef struct NubusBus {
>> + BusState qbus;
>> +
>> + MemoryRegion super_slot_io;
>> + MemoryRegion slot_io;
>> +
>> + int current_slot;
>> +} NubusBus;
>> +
>> +typedef struct NubusDevice {
>> + DeviceState qdev;
>> +
>> + int slot_nb;
>> + MemoryRegion slot_mem;
>> +
>> + /* Format Block */
>> +
>> + MemoryRegion fblock_io;
>> +
>> + uint32_t rom_length;
>> + uint32_t rom_crc;
>> + uint8_t rom_rev;
>> + uint8_t rom_format;
>> + uint8_t byte_lanes;
>> + int32_t directory_offset;
>> +
>> + /* ROM */
>> +
>> + MemoryRegion rom_io;
>> + const uint8_t *rom;
>> +} NubusDevice;
>> +
>> +void nubus_register_rom(NubusDevice *dev, const uint8_t *rom, uint32_t size,
>> + int revision, int format, uint8_t byte_lanes);
>> +
>> +#endif
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 08/11] hw/m68k: add Nubus support for macfb video card
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (6 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 07/11] hw/m68k: add Nubus support Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:47 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller Mark Cave-Ayland
` (3 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/display/macfb.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/display/macfb.h | 21 +++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/hw/display/macfb.c b/hw/display/macfb.c
index 61ba2e9e15..458e268d86 100644
--- a/hw/display/macfb.c
+++ b/hw/display/macfb.c
@@ -15,6 +15,7 @@
#include "hw/sysbus.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
+#include "hw/nubus/nubus.h"
#include "hw/display/macfb.h"
#include "qapi/error.h"
@@ -380,12 +381,38 @@ static void macfb_sysbus_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(SYS_BUS_DEVICE(s), &ms->mem_vram);
}
+const uint8_t macfb_rom[] = {
+ 255, 0, 0, 0,
+};
+
+static void macfb_nubus_realize(DeviceState *dev, Error **errp)
+{
+ NubusDevice *nd = NUBUS_DEVICE(dev);
+ MacfbNubusState *s = NUBUS_MACFB(dev);
+ MacfbNubusDeviceClass *ndc = MACFB_NUBUS_GET_CLASS(dev);
+ MacfbState *ms = &s->macfb;
+
+ ndc->parent_realize(dev, errp);
+
+ macfb_common_realize(dev, ms, errp);
+ memory_region_add_subregion(&nd->slot_mem, DAFB_BASE, &ms->mem_ctrl);
+ memory_region_add_subregion(&nd->slot_mem, VIDEO_BASE, &ms->mem_vram);
+
+ nubus_register_rom(nd, macfb_rom, sizeof(macfb_rom), 1, 9, 0xf);
+}
+
static void macfb_sysbus_reset(DeviceState *d)
{
MacfbSysBusState *s = MACFB(d);
macfb_reset(&s->macfb);
}
+static void macfb_nubus_reset(DeviceState *d)
+{
+ MacfbNubusState *s = NUBUS_MACFB(d);
+ macfb_reset(&s->macfb);
+}
+
static Property macfb_sysbus_properties[] = {
DEFINE_PROP_UINT32("width", MacfbSysBusState, macfb.width, 640),
DEFINE_PROP_UINT32("height", MacfbSysBusState, macfb.height, 480),
@@ -393,6 +420,13 @@ static Property macfb_sysbus_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static Property macfb_nubus_properties[] = {
+ DEFINE_PROP_UINT32("width", MacfbNubusState, macfb.width, 640),
+ DEFINE_PROP_UINT32("height", MacfbNubusState, macfb.height, 480),
+ DEFINE_PROP_UINT8("depth", MacfbNubusState, macfb.depth, 8),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void macfb_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -404,6 +438,19 @@ static void macfb_sysbus_class_init(ObjectClass *klass, void *data)
dc->props = macfb_sysbus_properties;
}
+static void macfb_nubus_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ MacfbNubusDeviceClass *ndc = MACFB_NUBUS_DEVICE_CLASS(klass);
+
+ device_class_set_parent_realize(dc, macfb_nubus_realize,
+ &ndc->parent_realize);
+ dc->desc = "Nubus Macintosh framebuffer";
+ dc->reset = macfb_nubus_reset;
+ dc->vmsd = &vmstate_macfb;
+ dc->props = macfb_nubus_properties;
+}
+
static TypeInfo macfb_sysbus_info = {
.name = TYPE_MACFB,
.parent = TYPE_SYS_BUS_DEVICE,
@@ -411,9 +458,18 @@ static TypeInfo macfb_sysbus_info = {
.class_init = macfb_sysbus_class_init,
};
+static TypeInfo macfb_nubus_info = {
+ .name = TYPE_NUBUS_MACFB,
+ .parent = TYPE_NUBUS_DEVICE,
+ .instance_size = sizeof(MacfbNubusState),
+ .class_init = macfb_nubus_class_init,
+ .class_size = sizeof(MacfbNubusDeviceClass),
+};
+
static void macfb_register_types(void)
{
type_register_static(&macfb_sysbus_info);
+ type_register_static(&macfb_nubus_info);
}
type_init(macfb_register_types)
diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h
index 3fe2592735..26367ae2c4 100644
--- a/include/hw/display/macfb.h
+++ b/include/hw/display/macfb.h
@@ -40,4 +40,25 @@ typedef struct {
MacfbState macfb;
} MacfbSysBusState;
+#define MACFB_NUBUS_DEVICE_CLASS(class) \
+ OBJECT_CLASS_CHECK(MacfbNubusDeviceClass, (class), TYPE_NUBUS_MACFB)
+#define MACFB_NUBUS_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(MacfbNubusDeviceClass, (obj), TYPE_NUBUS_MACFB)
+
+typedef struct MacfbNubusDeviceClass {
+ DeviceClass parent_class;
+
+ DeviceRealize parent_realize;
+} MacfbNubusDeviceClass;
+
+#define TYPE_NUBUS_MACFB "nubus-macfb"
+#define NUBUS_MACFB(obj) \
+ OBJECT_CHECK(MacfbNubusState, (obj), TYPE_NUBUS_MACFB)
+
+typedef struct {
+ NubusDevice busdev;
+
+ MacfbState macfb;
+} MacfbNubusState;
+
#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 08/11] hw/m68k: add Nubus support for macfb video card
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 08/11] hw/m68k: add Nubus support for macfb video card Mark Cave-Ayland
@ 2018-10-30 6:47 ` Hervé Poussineau
0 siblings, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:47 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/display/macfb.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/display/macfb.h | 21 +++++++++++++++++
> 2 files changed, 77 insertions(+)
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (7 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 08/11] hw/m68k: add Nubus support for macfb video card Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:48 ` Hervé Poussineau
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 10/11] dp8393x: manage big endian bus Mark Cave-Ayland
` (2 subsequent siblings)
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
hw/block/Makefile.objs | 1 +
hw/block/swim.c | 415 ++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/block/swim.h | 76 +++++++++
3 files changed, 492 insertions(+)
create mode 100644 hw/block/swim.c
create mode 100644 include/hw/block/swim.h
diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs
index 53ce5751ae..068de3f0c9 100644
--- a/hw/block/Makefile.objs
+++ b/hw/block/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_XEN) += xen_disk.o
common-obj-$(CONFIG_ECC) += ecc.o
common-obj-$(CONFIG_ONENAND) += onenand.o
common-obj-$(CONFIG_NVME_PCI) += nvme.o
+common-obj-$(CONFIG_SWIM) += swim.o
obj-$(CONFIG_SH4) += tc58128.o
diff --git a/hw/block/swim.c b/hw/block/swim.c
new file mode 100644
index 0000000000..850972cc48
--- /dev/null
+++ b/hw/block/swim.c
@@ -0,0 +1,415 @@
+/*
+ * QEMU Macintosh floppy disk controller emulator (SWIM)
+ *
+ * Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "sysemu/block-backend.h"
+#include "hw/sysbus.h"
+#include "hw/block/block.h"
+#include "hw/block/swim.h"
+
+/* IWM registers */
+
+#define IWM_PH0L 0
+#define IWM_PH0H 1
+#define IWM_PH1L 2
+#define IWM_PH1H 3
+#define IWM_PH2L 4
+#define IWM_PH2H 5
+#define IWM_PH3L 6
+#define IWM_PH3H 7
+#define IWM_MTROFF 8
+#define IWM_MTRON 9
+#define IWM_INTDRIVE 10
+#define IWM_EXTDRIVE 11
+#define IWM_Q6L 12
+#define IWM_Q6H 13
+#define IWM_Q7L 14
+#define IWM_Q7H 15
+
+/* SWIM registers */
+
+#define SWIM_WRITE_DATA 0
+#define SWIM_WRITE_MARK 1
+#define SWIM_WRITE_CRC 2
+#define SWIM_WRITE_PARAMETER 3
+#define SWIM_WRITE_PHASE 4
+#define SWIM_WRITE_SETUP 5
+#define SWIM_WRITE_MODE0 6
+#define SWIM_WRITE_MODE1 7
+
+#define SWIM_READ_DATA 8
+#define SWIM_READ_MARK 9
+#define SWIM_READ_ERROR 10
+#define SWIM_READ_PARAMETER 11
+#define SWIM_READ_PHASE 12
+#define SWIM_READ_SETUP 13
+#define SWIM_READ_STATUS 14
+#define SWIM_READ_HANDSHAKE 15
+
+#define REG_SHIFT 9
+
+#define SWIM_MODE_IWM 0
+#define SWIM_MODE_SWIM 1
+
+/* bits in phase register */
+
+#define SWIM_SEEK_NEGATIVE 0x074
+#define SWIM_STEP 0x071
+#define SWIM_MOTOR_ON 0x072
+#define SWIM_MOTOR_OFF 0x076
+#define SWIM_INDEX 0x073
+#define SWIM_EJECT 0x077
+#define SWIM_SETMFM 0x171
+#define SWIM_SETGCR 0x175
+#define SWIM_RELAX 0x033
+#define SWIM_LSTRB 0x008
+#define SWIM_CA_MASK 0x077
+
+/* Select values for swim_select and swim_readbit */
+
+#define SWIM_READ_DATA_0 0x074
+#define SWIM_TWOMEG_DRIVE 0x075
+#define SWIM_SINGLE_SIDED 0x076
+#define SWIM_DRIVE_PRESENT 0x077
+#define SWIM_DISK_IN 0x170
+#define SWIM_WRITE_PROT 0x171
+#define SWIM_TRACK_ZERO 0x172
+#define SWIM_TACHO 0x173
+#define SWIM_READ_DATA_1 0x174
+#define SWIM_MFM_MODE 0x175
+#define SWIM_SEEK_COMPLETE 0x176
+#define SWIM_ONEMEG_MEDIA 0x177
+
+/* Bits in handshake register */
+
+#define SWIM_MARK_BYTE 0x01
+#define SWIM_CRC_ZERO 0x02
+#define SWIM_RDDATA 0x04
+#define SWIM_SENSE 0x08
+#define SWIM_MOTEN 0x10
+#define SWIM_ERROR 0x20
+#define SWIM_DAT2BYTE 0x40
+#define SWIM_DAT1BYTE 0x80
+
+/* bits in setup register */
+
+#define SWIM_S_INV_WDATA 0x01
+#define SWIM_S_3_5_SELECT 0x02
+#define SWIM_S_GCR 0x04
+#define SWIM_S_FCLK_DIV2 0x08
+#define SWIM_S_ERROR_CORR 0x10
+#define SWIM_S_IBM_DRIVE 0x20
+#define SWIM_S_GCR_WRITE 0x40
+#define SWIM_S_TIMEOUT 0x80
+
+/* bits in mode register */
+
+#define SWIM_CLFIFO 0x01
+#define SWIM_ENBL1 0x02
+#define SWIM_ENBL2 0x04
+#define SWIM_ACTION 0x08
+#define SWIM_WRITE_MODE 0x10
+#define SWIM_HEDSEL 0x20
+#define SWIM_MOTON 0x80
+
+static void swim_change_cb(void *opaque, bool load, Error **errp)
+{
+ FDrive *drive = opaque;
+
+ if (!load) {
+ blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
+ } else {
+ if (!blkconf_apply_backend_options(drive->conf,
+ blk_is_read_only(drive->blk), false,
+ errp)) {
+ return;
+ }
+ }
+}
+
+static const BlockDevOps swim_block_ops = {
+ .change_media_cb = swim_change_cb,
+};
+
+static Property swim_drive_properties[] = {
+ DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1),
+ DEFINE_BLOCK_PROPERTIES(SWIMDrive, conf),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void swim_drive_realize(DeviceState *qdev, Error **errp)
+{
+ SWIMDrive *dev = SWIM_DRIVE(qdev);
+ SWIMBus *bus = SWIM_BUS(qdev->parent_bus);
+ FDrive *drive;
+ int ret;
+
+ if (dev->unit == -1) {
+ for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
+ drive = &bus->ctrl->drives[dev->unit];
+ if (!drive->blk) {
+ break;
+ }
+ }
+ }
+
+ if (dev->unit >= MAX_FD) {
+ error_setg(errp, "Can't create floppy unit %d, bus supports "
+ "only %d units", dev->unit, MAX_FD);
+ return;
+ }
+
+ drive = &bus->ctrl->drives[dev->unit];
+ if (drive->blk) {
+ error_setg(errp, "Floppy unit %d is in use", dev->unit);
+ return;
+ }
+
+ if (!dev->conf.blk) {
+ /* Anonymous BlockBackend for an empty drive */
+ dev->conf.blk = blk_new(0, BLK_PERM_ALL);
+ ret = blk_attach_dev(dev->conf.blk, qdev);
+ assert(ret == 0);
+ }
+
+ blkconf_blocksizes(&dev->conf);
+ if (dev->conf.logical_block_size != 512 ||
+ dev->conf.physical_block_size != 512)
+ {
+ error_setg(errp, "Physical and logical block size must "
+ "be 512 for floppy");
+ return;
+ }
+
+ /* rerror/werror aren't supported by fdc and therefore not even registered
+ * with qdev. So set the defaults manually before they are used in
+ * blkconf_apply_backend_options(). */
+ dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
+ dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
+
+ if (!blkconf_apply_backend_options(&dev->conf,
+ blk_is_read_only(dev->conf.blk),
+ false, errp)) {
+ return;
+ }
+
+ /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
+ * for empty drives. */
+ if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
+ blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
+ error_setg(errp, "fdc doesn't support drive option werror");
+ return;
+ }
+ if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
+ error_setg(errp, "fdc doesn't support drive option rerror");
+ return;
+ }
+
+ drive->conf = &dev->conf;
+ drive->blk = dev->conf.blk;
+ drive->swimctrl = bus->ctrl;
+
+ blk_set_dev_ops(drive->blk, &swim_block_ops, drive);
+}
+
+static void swim_drive_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+ k->realize = swim_drive_realize;
+ set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
+ k->bus_type = TYPE_SWIM_BUS;
+ k->props = swim_drive_properties;
+ k->desc = "virtual SWIM drive";
+}
+
+static const TypeInfo swim_drive_info = {
+ .name = TYPE_SWIM_DRIVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(SWIMDrive),
+ .class_init = swim_drive_class_init,
+};
+
+static const TypeInfo swim_bus_info = {
+ .name = TYPE_SWIM_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(SWIMBus),
+};
+
+static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
+ unsigned size)
+{
+ SWIMCtrl *swimctrl = opaque;
+
+ reg >>= REG_SHIFT;
+
+ swimctrl->regs[reg >> 1] = reg & 1;
+
+ if (swimctrl->regs[IWM_Q6] &&
+ swimctrl->regs[IWM_Q7]) {
+ if (swimctrl->regs[IWM_MTR]) {
+ /* data register */
+ swimctrl->iwm_data = value;
+ } else {
+ /* mode register */
+ swimctrl->iwm_mode = value;
+ /* detect sequence to switch from IWM mode to SWIM mode */
+ switch (swimctrl->iwm_switch) {
+ case 0:
+ if (value == 0x57) {
+ swimctrl->iwm_switch++;
+ }
+ break;
+ case 1:
+ if (value == 0x17) {
+ swimctrl->iwm_switch++;
+ }
+ break;
+ case 2:
+ if (value == 0x57) {
+ swimctrl->iwm_switch++;
+ }
+ break;
+ case 3:
+ if (value == 0x57) {
+ swimctrl->mode = SWIM_MODE_SWIM;
+ swimctrl->iwm_switch = 0;
+ }
+ break;
+ }
+ }
+ }
+}
+
+static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
+{
+ SWIMCtrl *swimctrl = opaque;
+
+ reg >>= REG_SHIFT;
+
+ swimctrl->regs[reg >> 1] = reg & 1;
+
+ return 0;
+}
+
+static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
+ unsigned size)
+{
+ SWIMCtrl *swimctrl = opaque;
+
+ if (swimctrl->mode == SWIM_MODE_IWM) {
+ iwmctrl_write(opaque, reg, value, size);
+ return;
+ }
+
+ reg >>= REG_SHIFT;
+
+ switch (reg) {
+ case SWIM_WRITE_PHASE:
+ swimctrl->swim_phase = value;
+ break;
+ case SWIM_WRITE_MODE0:
+ swimctrl->swim_mode &= ~value;
+ break;
+ case SWIM_WRITE_MODE1:
+ swimctrl->swim_mode |= value;
+ break;
+ case SWIM_WRITE_DATA:
+ case SWIM_WRITE_MARK:
+ case SWIM_WRITE_CRC:
+ case SWIM_WRITE_PARAMETER:
+ case SWIM_WRITE_SETUP:
+ break;
+ }
+}
+
+static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
+{
+ SWIMCtrl *swimctrl = opaque;
+ uint32_t value = 0;
+
+ if (swimctrl->mode == SWIM_MODE_IWM) {
+ return iwmctrl_read(opaque, reg, size);
+ }
+
+ reg >>= REG_SHIFT;
+
+ switch (reg) {
+ case SWIM_READ_PHASE:
+ value = swimctrl->swim_phase;
+ break;
+ case SWIM_READ_HANDSHAKE:
+ if (swimctrl->swim_phase == SWIM_DRIVE_PRESENT) {
+ /* always answer "no drive present" */
+ value = SWIM_SENSE;
+ }
+ break;
+ case SWIM_READ_DATA:
+ case SWIM_READ_MARK:
+ case SWIM_READ_ERROR:
+ case SWIM_READ_PARAMETER:
+ case SWIM_READ_SETUP:
+ case SWIM_READ_STATUS:
+ break;
+ }
+
+ return value;
+}
+
+static const MemoryRegionOps swimctrl_mem_ops = {
+ .write = swimctrl_write,
+ .read = swimctrl_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void sysbus_swim_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ SWIM *sbs = SWIM(obj);
+ SWIMCtrl *swimctrl = &sbs->ctrl;
+
+ memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimctrl,
+ "swim", 0x2000);
+ sysbus_init_mmio(sbd, &swimctrl->iomem);
+}
+
+static void sysbus_swim_realize(DeviceState *dev, Error **errp)
+{
+ SWIM *sys = SWIM(dev);
+ SWIMCtrl *swimctrl = &sys->ctrl;
+
+ qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
+ NULL);
+ swimctrl->bus.ctrl = swimctrl;
+}
+
+static void sysbus_swim_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = sysbus_swim_realize;
+}
+
+static const TypeInfo sysbus_swim_info = {
+ .name = TYPE_SWIM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SWIM),
+ .instance_init = sysbus_swim_init,
+ .class_init = sysbus_swim_class_init,
+};
+
+static void swim_register_types(void)
+{
+ type_register_static(&sysbus_swim_info);
+ type_register_static(&swim_bus_info);
+ type_register_static(&swim_drive_info);
+}
+
+type_init(swim_register_types)
diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h
new file mode 100644
index 0000000000..d6fbdc11ac
--- /dev/null
+++ b/include/hw/block/swim.h
@@ -0,0 +1,76 @@
+/*
+ * QEMU Macintosh floppy disk controller emulator (SWIM)
+ *
+ * Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef SWIM_H
+#define SWIM_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+
+#define MAX_FD 2
+
+typedef struct SWIMDrive SWIMDrive;
+typedef struct SWIMBus SWIMBus;
+typedef struct SWIMCtrl SWIMCtrl;
+
+#define TYPE_SWIM_DRIVE "swim-drive"
+#define SWIM_DRIVE(obj) OBJECT_CHECK(SWIMDrive, (obj), TYPE_SWIM_DRIVE)
+
+struct SWIMDrive {
+ DeviceState qdev;
+ int32_t unit;
+ BlockConf conf;
+};
+
+#define TYPE_SWIM_BUS "swim-bus"
+#define SWIM_BUS(obj) OBJECT_CHECK(SWIMBus, (obj), TYPE_SWIM_BUS)
+
+struct SWIMBus {
+ BusState bus;
+ struct SWIMCtrl *ctrl;
+};
+
+typedef struct FDrive {
+ SWIMCtrl *swimctrl;
+ BlockBackend *blk;
+ BlockConf *conf;
+} FDrive;
+
+struct SWIMCtrl {
+ MemoryRegion iomem;
+ FDrive drives[MAX_FD];
+ int mode;
+ /* IWM mode */
+ int iwm_switch;
+ int regs[8];
+#define IWM_PH0 0
+#define IWM_PH1 1
+#define IWM_PH2 2
+#define IWM_PH3 3
+#define IWM_MTR 4
+#define IWM_DRIVE 5
+#define IWM_Q6 6
+#define IWM_Q7 7
+ uint8_t iwm_data;
+ uint8_t iwm_mode;
+ /* SWIM mode */
+ uint8_t swim_phase;
+ uint8_t swim_mode;
+ SWIMBus bus;
+};
+
+#define TYPE_SWIM "swim"
+#define SWIM(obj) OBJECT_CHECK(SWIM, (obj), TYPE_SWIM)
+
+typedef struct SWIM {
+ SysBusDevice parent_obj;
+ SWIMCtrl ctrl;
+} SWIM;
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller Mark Cave-Ayland
@ 2018-10-30 6:48 ` Hervé Poussineau
2018-10-30 10:25 ` Mark Cave-Ayland
0 siblings, 1 reply; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:48 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> hw/block/Makefile.objs | 1 +
> hw/block/swim.c | 415 ++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/block/swim.h | 76 +++++++++
> 3 files changed, 492 insertions(+)
> create mode 100644 hw/block/swim.c
> create mode 100644 include/hw/block/swim.h
[...]
> diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h
> new file mode 100644
> index 0000000000..d6fbdc11ac
> --- /dev/null
> +++ b/include/hw/block/swim.h
> @@ -0,0 +1,76 @@
> +/*
> + * QEMU Macintosh floppy disk controller emulator (SWIM)
> + *
> + * Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See
> + * the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef SWIM_H
> +#define SWIM_H
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +
> +#define MAX_FD 2
Maybe rename MAX_FD to SWIM_MAX_FD, to prevent conflicts with MAX_FD in other files?
Excepted that:
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller
2018-10-30 6:48 ` Hervé Poussineau
@ 2018-10-30 10:25 ` Mark Cave-Ayland
0 siblings, 0 replies; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 10:25 UTC (permalink / raw)
To: Hervé Poussineau, qemu-devel, kwolf, famz, qemu-block,
jasowang, dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien,
laurent
On 30/10/2018 06:48, Hervé Poussineau wrote:
> Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
>> From: Laurent Vivier <laurent@vivier.eu>
>>
>> Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
>> ---
>> hw/block/Makefile.objs | 1 +
>> hw/block/swim.c | 415 ++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/block/swim.h | 76 +++++++++
>> 3 files changed, 492 insertions(+)
>> create mode 100644 hw/block/swim.c
>> create mode 100644 include/hw/block/swim.h
>
> [...]
>
>> diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h
>> new file mode 100644
>> index 0000000000..d6fbdc11ac
>> --- /dev/null
>> +++ b/include/hw/block/swim.h
>> @@ -0,0 +1,76 @@
>> +/*
>> + * QEMU Macintosh floppy disk controller emulator (SWIM)
>> + *
>> + * Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2. See
>> + * the COPYING file in the top-level directory.
>> + *
>> + */
>> +
>> +#ifndef SWIM_H
>> +#define SWIM_H
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +
>> +#define MAX_FD 2
>
> Maybe rename MAX_FD to SWIM_MAX_FD, to prevent conflicts with MAX_FD in other files?
> Excepted that:
> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Yes, that's a good idea (I can see this might clash with in-built OS headers). I'll
make the change and add your R-B to the next version.
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 10/11] dp8393x: manage big endian bus
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (8 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 09/11] hw/m68k: add a dummy SWIM floppy controller Mark Cave-Ayland
@ 2018-10-29 13:39 ` Mark Cave-Ayland
2018-10-30 6:48 ` Hervé Poussineau
2018-10-29 13:40 ` [Qemu-devel] [PATCH v5 11/11] hw/m68k: define Macintosh Quadra 800 Mark Cave-Ayland
2018-10-30 8:15 ` [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Richard Henderson
11 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:39 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
This is needed by Quadra 800, this card can run on little-endian
or big-endian bus.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/net/dp8393x.c | 88 ++++++++++++++++++++++++++++++++++++--------------------
1 file changed, 57 insertions(+), 31 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index b53fcaa8bc..1cf348aea1 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -150,6 +150,7 @@ typedef struct dp8393xState {
/* Hardware */
uint8_t it_shift;
+ bool big_endian;
qemu_irq irq;
#ifdef DEBUG_SONIC
int irq_level;
@@ -220,6 +221,29 @@ static uint32_t dp8393x_wt(dp8393xState *s)
return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
}
+static uint16_t dp8393x_get(dp8393xState *s, int width, uint16_t *base,
+ int offset)
+{
+ uint16_t val;
+
+ if (s->big_endian) {
+ val = be16_to_cpu(base[offset * width + width - 1]);
+ } else {
+ val = le16_to_cpu(base[offset * width]);
+ }
+ return val;
+}
+
+static void dp8393x_put(dp8393xState *s, int width, uint16_t *base, int offset,
+ uint16_t val)
+{
+ if (s->big_endian) {
+ base[offset * width + width - 1] = cpu_to_be16(val);
+ } else {
+ base[offset * width] = cpu_to_le16(val);
+ }
+}
+
static void dp8393x_update_irq(dp8393xState *s)
{
int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
@@ -251,12 +275,12 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Fill current entry */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
- s->cam[index][0] = data[1 * width] & 0xff;
- s->cam[index][1] = data[1 * width] >> 8;
- s->cam[index][2] = data[2 * width] & 0xff;
- s->cam[index][3] = data[2 * width] >> 8;
- s->cam[index][4] = data[3 * width] & 0xff;
- s->cam[index][5] = data[3 * width] >> 8;
+ s->cam[index][0] = dp8393x_get(s, width, data, 1) & 0xff;
+ s->cam[index][1] = dp8393x_get(s, width, data, 1) >> 8;
+ s->cam[index][2] = dp8393x_get(s, width, data, 2) & 0xff;
+ s->cam[index][3] = dp8393x_get(s, width, data, 2) >> 8;
+ s->cam[index][4] = dp8393x_get(s, width, data, 3) & 0xff;
+ s->cam[index][5] = dp8393x_get(s, width, data, 3) >> 8;
DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
s->cam[index][0], s->cam[index][1], s->cam[index][2],
s->cam[index][3], s->cam[index][4], s->cam[index][5]);
@@ -269,7 +293,7 @@ static void dp8393x_do_load_cam(dp8393xState *s)
/* Read CAM enable */
address_space_rw(&s->as, dp8393x_cdp(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
- s->regs[SONIC_CE] = data[0 * width];
+ s->regs[SONIC_CE] = dp8393x_get(s, width, data, 0);
DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
/* Done */
@@ -290,10 +314,10 @@ static void dp8393x_do_read_rra(dp8393xState *s)
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
/* Update SONIC registers */
- s->regs[SONIC_CRBA0] = data[0 * width];
- s->regs[SONIC_CRBA1] = data[1 * width];
- s->regs[SONIC_RBWC0] = data[2 * width];
- s->regs[SONIC_RBWC1] = data[3 * width];
+ s->regs[SONIC_CRBA0] = dp8393x_get(s, width, data, 0);
+ s->regs[SONIC_CRBA1] = dp8393x_get(s, width, data, 1);
+ s->regs[SONIC_RBWC0] = dp8393x_get(s, width, data, 2);
+ s->regs[SONIC_RBWC1] = dp8393x_get(s, width, data, 3);
DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
@@ -408,12 +432,12 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
tx_len = 0;
/* Update registers */
- s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
- s->regs[SONIC_TPS] = data[1 * width];
- s->regs[SONIC_TFC] = data[2 * width];
- s->regs[SONIC_TSA0] = data[3 * width];
- s->regs[SONIC_TSA1] = data[4 * width];
- s->regs[SONIC_TFS] = data[5 * width];
+ s->regs[SONIC_TCR] = dp8393x_get(s, width, data, 0) & 0xf000;
+ s->regs[SONIC_TPS] = dp8393x_get(s, width, data, 1);
+ s->regs[SONIC_TFC] = dp8393x_get(s, width, data, 2);
+ s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 3);
+ s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 4);
+ s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 5);
/* Handle programmable interrupt */
if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
@@ -439,9 +463,9 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
- s->regs[SONIC_TSA0] = data[0 * width];
- s->regs[SONIC_TSA1] = data[1 * width];
- s->regs[SONIC_TFS] = data[2 * width];
+ s->regs[SONIC_TSA0] = dp8393x_get(s, width, data, 0);
+ s->regs[SONIC_TSA1] = dp8393x_get(s, width, data, 1);
+ s->regs[SONIC_TFS] = dp8393x_get(s, width, data, 2);
}
}
@@ -468,7 +492,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
/* Write status */
- data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
+ dp8393x_put(s, width, data, 0,
+ s->regs[SONIC_TCR] & 0x0fff); /* status */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
dp8393x_ttda(s),
@@ -482,8 +507,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s)
sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
- s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
- if (data[0 * width] & 0x1) {
+ s->regs[SONIC_CTDA] = dp8393x_get(s, width, data, 0) & ~0x1;
+ if (dp8393x_get(s, width, data, 0) & 0x1) {
/* EOL detected */
break;
}
@@ -746,7 +771,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
(uint8_t *)data, size, 0);
- if (data[0 * width] & 0x1) {
+ if (dp8393x_get(s, width, data, 0) & 0x1) {
/* Still EOL ; stop reception */
return -1;
} else {
@@ -790,11 +815,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
/* Write status to memory */
DPRINTF("Write status at %08x\n", dp8393x_crda(s));
- data[0 * width] = s->regs[SONIC_RCR]; /* status */
- data[1 * width] = rx_len; /* byte count */
- data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
- data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
- data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
+ dp8393x_put(s, width, data, 0, s->regs[SONIC_RCR]); /* status */
+ dp8393x_put(s, width, data, 1, rx_len); /* byte count */
+ dp8393x_put(s, width, data, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
+ dp8393x_put(s, width, data, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
+ dp8393x_put(s, width, data, 4, s->regs[SONIC_RSC]); /* seq_no */
size = sizeof(uint16_t) * 5 * width;
address_space_rw(&s->as, dp8393x_crda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
@@ -803,12 +828,12 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
size = sizeof(uint16_t) * width;
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
- s->regs[SONIC_LLFA] = data[0 * width];
+ s->regs[SONIC_LLFA] = dp8393x_get(s, width, data, 0);
if (s->regs[SONIC_LLFA] & 0x1) {
/* EOL detected */
s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
} else {
- data[0 * width] = 0; /* in_use */
+ dp8393x_put(s, width, data, 0, 0); /* in_use */
address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
@@ -921,6 +946,7 @@ static Property dp8393x_properties[] = {
DEFINE_NIC_PROPERTIES(dp8393xState, conf),
DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
+ DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 10/11] dp8393x: manage big endian bus
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 10/11] dp8393x: manage big endian bus Mark Cave-Ayland
@ 2018-10-30 6:48 ` Hervé Poussineau
0 siblings, 0 replies; 39+ messages in thread
From: Hervé Poussineau @ 2018-10-30 6:48 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, kraxel, pbonzini, afaerber, aurelien, laurent
Le 29/10/2018 à 14:39, Mark Cave-Ayland a écrit :
> From: Laurent Vivier <laurent@vivier.eu>
>
> This is needed by Quadra 800, this card can run on little-endian
> or big-endian bus.
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> Tested-by: Hervé Poussineau <hpoussin@reactos.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH v5 11/11] hw/m68k: define Macintosh Quadra 800
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (9 preceding siblings ...)
2018-10-29 13:39 ` [Qemu-devel] [PATCH v5 10/11] dp8393x: manage big endian bus Mark Cave-Ayland
@ 2018-10-29 13:40 ` Mark Cave-Ayland
2018-10-30 8:15 ` [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Richard Henderson
11 siblings, 0 replies; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-29 13:40 UTC (permalink / raw)
To: qemu-devel, kwolf, famz, qemu-block, jasowang, dgilbert, mreitz,
hpoussin, kraxel, pbonzini, afaerber, aurelien, laurent
From: Laurent Vivier <laurent@vivier.eu>
If you want to test the machine, it doesn't yet boot a MacROM, but you can
boot a linux kernel from the command line.
You can install your own disk using debian-installer with:
./qemu-system-m68k \
-M q800 \
-serial none -serial mon:stdio \
-m 1000M -drive file=m68k.qcow2,format=qcow2 \
-net nic,model=dp83932,addr=09:00:07:12:34:57 \
-append "console=ttyS0 vga=off" \
-kernel vmlinux-4.15.0-2-m68k \
-initrd initrd.gz \
-drive file=debian-9.0-m68k-NETINST-1.iso \
-drive file=m68k.qcow2,format=qcow2 \
-nographic
If you use a graphic adapter instead of "-nographic", you can use "-g" to set the
size of the display (I use "-g 1600x800x24").
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
MAINTAINERS | 19 +++
default-configs/m68k-softmmu.mak | 14 ++
hw/intc/Makefile.objs | 1 +
hw/intc/q800_irq.c | 73 ++++++++
hw/m68k/Makefile.objs | 5 +-
hw/m68k/bootinfo.h | 100 +++++++++++
hw/m68k/q800.c | 356 +++++++++++++++++++++++++++++++++++++++
include/hw/intc/q800_irq.h | 39 +++++
8 files changed, 605 insertions(+), 2 deletions(-)
create mode 100644 hw/intc/q800_irq.c
create mode 100644 hw/m68k/bootinfo.h
create mode 100644 hw/m68k/q800.c
create mode 100644 include/hw/intc/q800_irq.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d794bd7a66..70175f3815 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -720,6 +720,25 @@ F: hw/char/mcf_uart.c
F: hw/net/mcf_fec.c
F: include/hw/m68k/mcf*.h
+q800
+M: Laurent Vivier <laurent@vivier.eu>
+S: Maintained
+F: hw/audio/asc.c
+F: hw/block/swim.c
+F: hw/m68k/bootinfo.h
+F: hw/display/macfb-template.h
+F: hw/display/macfb.c
+F: hw/intc/q800_irq.c
+F: hw/m68k/q800.c
+F: hw/misc/mac_via.c
+F: hw/nubus/*
+F: include/hw/audio/asc.h
+F: include/hw/block/swim.h
+F: include/hw/display/macfb.h
+F: include/hw/intc/q800_irq.h
+F: include/hw/misc/mac_via.h
+F: include/hw/nubus/*
+
MicroBlaze Machines
-------------------
petalogix_s3adsp1800
diff --git a/default-configs/m68k-softmmu.mak b/default-configs/m68k-softmmu.mak
index 60f7cdfbf2..993644aa42 100644
--- a/default-configs/m68k-softmmu.mak
+++ b/default-configs/m68k-softmmu.mak
@@ -2,3 +2,17 @@
CONFIG_COLDFIRE=y
CONFIG_PTIMER=y
+CONFIG_ESCC=y
+CONFIG_FRAMEBUFFER=y
+CONFIG_ADB=y
+CONFIG_MOS6522=y
+CONFIG_MAC_VIA=y
+CONFIG_Q800_IRQ=y
+CONFIG_MAC=y
+CONFIG_SCSI=y
+CONFIG_ESP=y
+CONFIG_ASC=y
+CONFIG_MACFB=y
+CONFIG_NUBUS=y
+CONFIG_DP8393X=y
+CONFIG_SWIM=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 0e9963f5ee..030967a0b3 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -46,3 +46,4 @@ obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
obj-$(CONFIG_MIPS_CPS) += mips_gic.o
obj-$(CONFIG_NIOS2) += nios2_iic.o
obj-$(CONFIG_OMPIC) += ompic.o
+obj-$(CONFIG_Q800_IRQ) += q800_irq.o
diff --git a/hw/intc/q800_irq.c b/hw/intc/q800_irq.c
new file mode 100644
index 0000000000..ec9d542d2e
--- /dev/null
+++ b/hw/intc/q800_irq.c
@@ -0,0 +1,73 @@
+/*
+ * QEMU Motorla 680x0 Macintosh hardware System Emulator
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/intc/q800_irq.h"
+
+
+static void q800_set_irq(void *opaque, int irq, int level)
+{
+ Q800IRQControllerState *s = opaque;
+ int i;
+
+
+ if (level) {
+ s->ipr |= 1 << irq;
+ } else {
+ s->ipr &= ~(1 << irq);
+ }
+
+ for (i = 7; i >= 0; i--) {
+ if ((s->ipr >> i) & 1) {
+ m68k_set_irq_level(s->cpu, i + 1, i + 25);
+ return;
+ }
+ }
+ m68k_set_irq_level(s->cpu, 0, 0);
+}
+
+static void q800_irq_init(Object *obj)
+{
+ Q800IRQControllerState *s = Q800_IRQC(obj);
+
+ qdev_init_gpio_in(DEVICE(obj), q800_set_irq, 8);
+
+ object_property_add_link(obj, "cpu", TYPE_M68K_CPU,
+ (Object **) &s->cpu,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+}
+
+static const TypeInfo q800_irq_type_info = {
+ .name = TYPE_Q800_IRQC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Q800IRQControllerState),
+ .instance_init = q800_irq_init,
+};
+
+static void q800_irq_register_types(void)
+{
+ type_register_static(&q800_irq_type_info);
+}
+
+type_init(q800_irq_register_types);
diff --git a/hw/m68k/Makefile.objs b/hw/m68k/Makefile.objs
index d1f089c08a..db01b0b203 100644
--- a/hw/m68k/Makefile.objs
+++ b/hw/m68k/Makefile.objs
@@ -1,2 +1,3 @@
-obj-y += an5206.o mcf5208.o
-obj-y += mcf5206.o mcf_intc.o
+obj-$(CONFIG_COLDFIRE) += an5206.o mcf5208.o
+obj-$(CONFIG_COLDFIRE) += mcf5206.o mcf_intc.o
+obj-$(CONFIG_MAC) += q800.o
diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h
new file mode 100644
index 0000000000..6584775f6d
--- /dev/null
+++ b/hw/m68k/bootinfo.h
@@ -0,0 +1,100 @@
+struct bi_record {
+ uint16_t tag; /* tag ID */
+ uint16_t size; /* size of record */
+ uint32_t data[0]; /* data */
+};
+
+/* machine independent tags */
+
+#define BI_LAST 0x0000 /* last record */
+#define BI_MACHTYPE 0x0001 /* machine type (u_long) */
+#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */
+#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */
+#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */
+#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */
+ /* (struct mem_info) */
+#define BI_RAMDISK 0x0006 /* ramdisk address and size */
+ /* (struct mem_info) */
+#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */
+ /* (string) */
+
+/* Macintosh-specific tags (all u_long) */
+
+#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */
+#define BI_MAC_VADDR 0x8001 /* Mac video base address */
+#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */
+#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */
+#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */
+#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */
+#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */
+#define BI_MAC_BTIME 0x8007 /* Mac boot time */
+#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
+#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
+#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
+#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
+
+/* Macintosh hardware profile data */
+
+#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
+#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */
+#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */
+#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */
+#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */
+#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */
+#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */
+#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */
+#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */
+#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */
+#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */
+#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */
+#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */
+#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */
+#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */
+#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */
+#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */
+#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */
+
+#define BOOTINFO0(as, base, id) \
+ do { \
+ stw_phys(as, base, id); \
+ base += 2; \
+ stw_phys(as, base, sizeof(struct bi_record)); \
+ base += 2; \
+ } while (0)
+
+#define BOOTINFO1(as, base, id, value) \
+ do { \
+ stw_phys(as, base, id); \
+ base += 2; \
+ stw_phys(as, base, sizeof(struct bi_record) + 4); \
+ base += 2; \
+ stl_phys(as, base, value); \
+ base += 4; \
+ } while (0)
+
+#define BOOTINFO2(as, base, id, value1, value2) \
+ do { \
+ stw_phys(as, base, id); \
+ base += 2; \
+ stw_phys(as, base, sizeof(struct bi_record) + 8); \
+ base += 2; \
+ stl_phys(as, base, value1); \
+ base += 4; \
+ stl_phys(as, base, value2); \
+ base += 4; \
+ } while (0)
+
+#define BOOTINFOSTR(as, base, id, string) \
+ do { \
+ int i; \
+ stw_phys(as, base, id); \
+ base += 2; \
+ stw_phys(as, base, \
+ (sizeof(struct bi_record) + strlen(string) + 2) & ~1); \
+ base += 2; \
+ for (i = 0; string[i]; i++) { \
+ stb_phys(as, base++, string[i]); \
+ } \
+ stb_phys(as, base++, 0); \
+ base = (parameters_base + 1) & ~1; \
+ } while (0)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
new file mode 100644
index 0000000000..249cb30882
--- /dev/null
+++ b/hw/m68k/q800.c
@@ -0,0 +1,356 @@
+/*
+ * QEMU Motorla 680x0 Macintosh hardware System Emulator
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/sysemu.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/boards.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/display/framebuffer.h"
+#include "ui/console.h"
+#include "exec/address-spaces.h"
+#include "hw/char/escc.h"
+#include "hw/sysbus.h"
+#include "hw/scsi/esp.h"
+#include "bootinfo.h"
+#include "hw/misc/mac_via.h"
+#include "hw/input/adb.h"
+#include "hw/audio/asc.h"
+#include "hw/nubus/mac-nubus-bridge.h"
+#include "hw/display/macfb.h"
+#include "hw/intc/q800_irq.h"
+#include "hw/block/swim.h"
+#include "net/net.h"
+#include "qapi/error.h"
+#include "sysemu/qtest.h"
+
+#define MACROM_ADDR 0x40000000
+#define MACROM_SIZE 0x00100000
+
+#define MACROM_FILENAME "MacROM.bin"
+
+#define Q800_MACHINE_ID 35
+#define Q800_CPU_ID (1 << 2)
+#define Q800_FPU_ID (1 << 2)
+#define Q800_MMU_ID (1 << 2)
+
+#define MACH_MAC 3
+#define Q800_MAC_CPU_ID 2
+
+#define VIA_BASE 0x50f00000
+#define SONIC_PROM_BASE 0x50f08000
+#define SONIC_BASE 0x50f0a000
+#define SCC_BASE 0x50f0c020
+#define ESP_BASE 0x50f10000
+#define ESP_PDMA 0x50f10100
+#define ASC_BASE 0x50F14000
+#define SWIM_BASE 0x50F1E000
+#define NUBUS_SUPER_SLOT_BASE 0x60000000
+#define NUBUS_SLOT_BASE 0xf0000000
+
+/* the video base, whereas it a Nubus address,
+ * is needed by the kernel to have early display and
+ * thus provided by the bootloader
+ */
+#define VIDEO_BASE 0xf9001000
+
+#define MAC_CLOCK 3686418
+
+static void main_cpu_reset(void *opaque)
+{
+ M68kCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(cs);
+ cpu->env.aregs[7] = ldl_phys(cs->as, 0);
+ cpu->env.pc = ldl_phys(cs->as, 4);
+}
+
+static void q800_init(MachineState *machine)
+{
+ M68kCPU *cpu = NULL;
+ int linux_boot;
+ int32_t kernel_size;
+ uint64_t elf_entry;
+ char *filename;
+ int bios_size;
+ ram_addr_t initrd_base;
+ int32_t initrd_size;
+ MemoryRegion *rom;
+ MemoryRegion *ram;
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ const char *initrd_filename = machine->initrd_filename;
+ const char *kernel_cmdline = machine->kernel_cmdline;
+ hwaddr parameters_base;
+ CPUState *cs;
+ DeviceState *dev;
+ DeviceState *via_dev, *pic_dev;
+ SysBusESPState *sysbus_esp;
+ ESPState *esp;
+ SysBusDevice *sysbus;
+ BusState *adb_bus;
+ NubusBus *nubus;
+
+ linux_boot = (kernel_filename != NULL);
+
+ /* init CPUs */
+ cpu = M68K_CPU(cpu_create(machine->cpu_type));
+ qemu_register_reset(main_cpu_reset, cpu);
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abort);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ /* IRQ controller */
+
+ pic_dev = qdev_create(NULL, TYPE_Q800_IRQC);
+ object_property_set_link(OBJECT(pic_dev), OBJECT(cpu), "cpu",
+ &error_abort);
+ qdev_init_nofail(pic_dev);
+
+ /* VIA */
+
+ via_dev = qdev_create(NULL, TYPE_MAC_VIA);
+ qdev_init_nofail(via_dev);
+ sysbus = SYS_BUS_DEVICE(via_dev);
+ sysbus_mmio_map(sysbus, 0, VIA_BASE);
+ qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 0,
+ qdev_get_gpio_in(pic_dev, 0));
+ qdev_connect_gpio_out_named(DEVICE(sysbus), "irq", 1,
+ qdev_get_gpio_in(pic_dev, 1));
+
+ adb_bus = qdev_get_child_bus(via_dev, "adb.0");
+ dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
+ qdev_init_nofail(dev);
+ dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
+ qdev_init_nofail(dev);
+
+ /* MACSONIC */
+
+ if (nb_nics > 1) {
+ error_report("q800 can only have one ethernet interface");
+ exit(1);
+ }
+
+ qemu_check_nic_model(&nd_table[0], "dp83932");
+
+ /* MacSonic driver needs an Apple MAC address
+ * Valid prefix are:
+ * 00:05:02 Apple
+ * 00:80:19 Dayna Communications, Inc.
+ * 00:A0:40 Apple
+ * 08:00:07 Apple
+ * (Q800 use the last one)
+ */
+ nd_table[0].macaddr.a[0] = 0x08;
+ nd_table[0].macaddr.a[1] = 0x00;
+ nd_table[0].macaddr.a[2] = 0x07;
+
+ dev = qdev_create(NULL, "dp8393x");
+ qdev_set_nic_properties(dev, &nd_table[0]);
+ qdev_prop_set_uint8(dev, "it_shift", 2);
+ qdev_prop_set_bit(dev, "big_endian", true);
+ qdev_prop_set_ptr(dev, "dma_mr", get_system_memory());
+ qdev_init_nofail(dev);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(sysbus, 0, SONIC_BASE);
+ sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE);
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(pic_dev, 2));
+
+ /* SCC */
+
+ dev = qdev_create(NULL, TYPE_ESCC);
+ qdev_prop_set_uint32(dev, "disabled", 0);
+ qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
+ qdev_prop_set_uint32(dev, "it_shift", 1);
+ qdev_prop_set_bit(dev, "bit_swap", true);
+ qdev_prop_set_chr(dev, "chrA", serial_hd(0));
+ qdev_prop_set_chr(dev, "chrB", serial_hd(1));
+ qdev_prop_set_uint32(dev, "chnBtype", 0);
+ qdev_prop_set_uint32(dev, "chnAtype", 0);
+ qdev_init_nofail(dev);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(pic_dev, 3));
+ sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(pic_dev, 3));
+ sysbus_mmio_map(sysbus, 0, SCC_BASE);
+
+ /* SCSI */
+
+ dev = qdev_create(NULL, TYPE_ESP);
+ sysbus_esp = ESP_STATE(dev);
+ esp = &sysbus_esp->esp;
+ esp->dma_memory_read = NULL;
+ esp->dma_memory_write = NULL;
+ esp->dma_opaque = NULL;
+ sysbus_esp->it_shift = 4;
+ esp->dma_enabled = 1;
+ qdev_init_nofail(dev);
+
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in_named(via_dev,
+ "via2-irq",
+ VIA2_IRQ_SCSI_BIT));
+ sysbus_connect_irq(sysbus, 1,
+ qdev_get_gpio_in_named(via_dev, "via2-irq",
+ VIA2_IRQ_SCSI_DATA_BIT));
+ sysbus_mmio_map(sysbus, 0, ESP_BASE);
+ sysbus_mmio_map(sysbus, 1, ESP_PDMA);
+
+ scsi_bus_legacy_handle_cmdline(&esp->bus);
+
+ /* Apple Sound Chip */
+
+ dev = qdev_create(NULL, TYPE_ASC);
+ qdev_prop_set_uint8(dev, "asctype", ASC_TYPE_ASC);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ASC_BASE);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+ qdev_get_gpio_in_named(via_dev, "via2-irq",
+ VIA2_IRQ_ASC_BIT));
+
+ /* SWIM floppy controller */
+
+ dev = qdev_create(NULL, TYPE_SWIM);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
+
+ /* NuBus */
+
+ dev = qdev_create(NULL, TYPE_MAC_NUBUS_BRIDGE);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, NUBUS_SUPER_SLOT_BASE);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE);
+
+ nubus = MAC_NUBUS_BRIDGE(dev)->bus;
+
+ /* framebuffer in nubus slot #9 */
+
+ dev = qdev_create(BUS(nubus), TYPE_NUBUS_MACFB);
+ qdev_prop_set_uint32(dev, "width", graphic_width);
+ qdev_prop_set_uint32(dev, "height", graphic_height);
+ qdev_prop_set_uint8(dev, "depth", graphic_depth);
+ qdev_init_nofail(dev);
+
+ cs = CPU(cpu);
+ if (linux_boot) {
+ uint64_t high;
+ kernel_size = load_elf(kernel_filename, NULL, NULL,
+ &elf_entry, NULL, &high, 1,
+ EM_68K, 0, 0);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s'", kernel_filename);
+ exit(1);
+ }
+ stl_phys(cs->as, 4, elf_entry); /* reset initial PC */
+ parameters_base = (high + 1) & ~1;
+
+ BOOTINFO1(cs->as, parameters_base, BI_MACHTYPE, MACH_MAC);
+ BOOTINFO1(cs->as, parameters_base, BI_FPUTYPE, Q800_FPU_ID);
+ BOOTINFO1(cs->as, parameters_base, BI_MMUTYPE, Q800_MMU_ID);
+ BOOTINFO1(cs->as, parameters_base, BI_CPUTYPE, Q800_CPU_ID);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_CPUID, Q800_MAC_CPU_ID);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_MODEL, Q800_MACHINE_ID);
+ BOOTINFO1(cs->as, parameters_base,
+ BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */
+ BOOTINFO2(cs->as, parameters_base, BI_MEMCHUNK, 0, ram_size);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_VADDR, VIDEO_BASE);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_VDEPTH, graphic_depth);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_VDIM,
+ (graphic_height << 16) | graphic_width);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_VROW,
+ (graphic_width * graphic_depth + 7) / 8);
+ BOOTINFO1(cs->as, parameters_base, BI_MAC_SCCBASE, SCC_BASE);
+
+ if (kernel_cmdline) {
+ BOOTINFOSTR(cs->as, parameters_base, BI_COMMAND_LINE,
+ kernel_cmdline);
+ }
+
+ /* load initrd */
+ if (initrd_filename) {
+ initrd_size = get_image_size(initrd_filename);
+ if (initrd_size < 0) {
+ error_report("could not load initial ram disk '%s'",
+ initrd_filename);
+ exit(1);
+ }
+
+ initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
+ load_image_targphys(initrd_filename, initrd_base,
+ ram_size - initrd_base);
+ BOOTINFO2(cs->as, parameters_base, BI_RAMDISK, initrd_base,
+ initrd_size);
+ } else {
+ initrd_base = 0;
+ initrd_size = 0;
+ }
+ BOOTINFO0(cs->as, parameters_base, BI_LAST);
+ } else {
+ uint8_t *ptr;
+ /* allocate and load BIOS */
+ rom = g_malloc(sizeof(*rom));
+ memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
+ &error_abort);
+ if (bios_name == NULL) {
+ bios_name = MACROM_FILENAME;
+ }
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ memory_region_set_readonly(rom, true);
+ memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
+
+ /* Load MacROM binary */
+ if (filename) {
+ bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE);
+ g_free(filename);
+ } else {
+ bios_size = -1;
+ }
+
+ /* Remove qtest_enabled() check once firmware files are in the tree */
+ if (!qtest_enabled()) {
+ if (bios_size < 0 || bios_size > MACROM_SIZE) {
+ error_report("could not load MacROM '%s'", bios_name);
+ exit(1);
+ }
+
+ ptr = rom_ptr(MACROM_ADDR, MACROM_SIZE);
+ stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */
+ stl_phys(cs->as, 4,
+ MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */
+ }
+ }
+}
+
+static void q800_machine_init(MachineClass *mc)
+{
+ mc->desc = "Macintosh Quadra 800";
+ mc->init = q800_init;
+ mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
+ mc->max_cpus = 1;
+ mc->is_default = 0;
+ mc->block_default_type = IF_SCSI;
+}
+
+DEFINE_MACHINE("q800", q800_machine_init)
diff --git a/include/hw/intc/q800_irq.h b/include/hw/intc/q800_irq.h
new file mode 100644
index 0000000000..91c2de1cc5
--- /dev/null
+++ b/include/hw/intc/q800_irq.h
@@ -0,0 +1,39 @@
+/*
+ * QEMU Motorla 680x0 Macintosh hardware System Emulator
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef Q800_IRQ_H
+#define Q800_IRQ_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_Q800_IRQC "q800-irq-controller"
+#define Q800_IRQC(obj) OBJECT_CHECK(Q800IRQControllerState, (obj), \
+ TYPE_Q800_IRQC)
+
+typedef struct Q800IRQControllerState {
+ SysBusDevice parent_obj;
+
+ M68kCPU *cpu;
+ uint8_t ipr;
+} Q800IRQControllerState;
+
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-29 13:39 [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Mark Cave-Ayland
` (10 preceding siblings ...)
2018-10-29 13:40 ` [Qemu-devel] [PATCH v5 11/11] hw/m68k: define Macintosh Quadra 800 Mark Cave-Ayland
@ 2018-10-30 8:15 ` Richard Henderson
2018-10-30 11:48 ` Mark Cave-Ayland
11 siblings, 1 reply; 39+ messages in thread
From: Richard Henderson @ 2018-10-30 8:15 UTC (permalink / raw)
To: Mark Cave-Ayland, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, hpoussin, kraxel, pbonzini, afaerber, aurelien,
laurent
On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
> You can install your own disk using debian-installer, with:
>
> ...
> -M q800 \
> -serial none -serial mon:stdio \
> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
> -append "console=ttyS0 vga=off" \
> -kernel vmlinux-4.15.0-2-m68k \
> -initrd initrd.gz \
> -drive file=debian-9.0-m68k-NETINST-1.iso \
> -drive file=m68k.qcow2,format=qcow2 \
> -nographic
I tried this and got
Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
which lead straight to buserr and panic. This happens way early in boot --
only 1926 TranslationBlocks generated.
Is there some device missing from the command-line that the kernel is expecting?
r~
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-30 8:15 ` [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine Richard Henderson
@ 2018-10-30 11:48 ` Mark Cave-Ayland
2018-10-30 12:49 ` Laurent Vivier
0 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 11:48 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, kwolf, famz, qemu-block, jasowang,
dgilbert, mreitz, hpoussin, kraxel, pbonzini, afaerber, aurelien,
laurent
On 30/10/2018 08:15, Richard Henderson wrote:
> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>> You can install your own disk using debian-installer, with:
>>
>> ...
>> -M q800 \
>> -serial none -serial mon:stdio \
>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>> -append "console=ttyS0 vga=off" \
>> -kernel vmlinux-4.15.0-2-m68k \
>> -initrd initrd.gz \
>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>> -drive file=m68k.qcow2,format=qcow2 \
>> -nographic
>
> I tried this and got
>
> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>
> which lead straight to buserr and panic. This happens way early in boot --
> only 1926 TranslationBlocks generated.
>
> Is there some device missing from the command-line that the kernel is expecting?
Heh that's annoying. The original branch I forked that Laurent was working on had
some extra patches at the start of the series: some were required for q800 whilst
others were for new development. I thought that all of the patches required for q800
had been applied over the past few months, but sadly that isn't the case :(
I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
which contains the patchset plus two extra patches that are still needed to boot to
the debian installer here:
9281a5371f "tmp"
629754d847 "target/m68k: manage FPU exceptions"
Laurent, are these patches ready for upstream or do they need work in which case we
should leave q800 until the 3.2 cycle?
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-30 11:48 ` Mark Cave-Ayland
@ 2018-10-30 12:49 ` Laurent Vivier
2018-10-30 13:12 ` Mark Cave-Ayland
0 siblings, 1 reply; 39+ messages in thread
From: Laurent Vivier @ 2018-10-30 12:49 UTC (permalink / raw)
To: Mark Cave-Ayland, Richard Henderson, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, hpoussin, kraxel,
pbonzini, afaerber, aurelien
Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
> On 30/10/2018 08:15, Richard Henderson wrote:
>
>> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>>> You can install your own disk using debian-installer, with:
>>>
>>> ...
>>> -M q800 \
>>> -serial none -serial mon:stdio \
>>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>>> -append "console=ttyS0 vga=off" \
>>> -kernel vmlinux-4.15.0-2-m68k \
>>> -initrd initrd.gz \
>>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>>> -drive file=m68k.qcow2,format=qcow2 \
>>> -nographic
>>
>> I tried this and got
>>
>> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
>> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
>> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
>> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>>
>> which lead straight to buserr and panic. This happens way early in boot --
>> only 1926 TranslationBlocks generated.
>>
>> Is there some device missing from the command-line that the kernel is expecting?
>
> Heh that's annoying. The original branch I forked that Laurent was working on had
> some extra patches at the start of the series: some were required for q800 whilst
> others were for new development. I thought that all of the patches required for q800
> had been applied over the past few months, but sadly that isn't the case :(
>
> I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
> which contains the patchset plus two extra patches that are still needed to boot to
> the debian installer here:
>
> 9281a5371f "tmp"
> 629754d847 "target/m68k: manage FPU exceptions"
>
> Laurent, are these patches ready for upstream or do they need work in which case we
> should leave q800 until the 3.2 cycle?
The only needed part is from 9281a5371f.
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1552,7 +1552,7 @@ DISAS_INSN(undef)
but actually illegal for CPU32 or pre-68020. */
qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
insn, s->base.pc_next);
- gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
}
DISAS_INSN(mulw)
@@ -2799,7 +2799,7 @@ DISAS_INSN(mull)
if (ext & 0x400) {
if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
- gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
@@ -4509,7 +4509,7 @@ DISAS_INSN(strldsr)
addr = s->pc - 2;
ext = read_im16(env, s);
if (ext != 0x46FC) {
- gen_exception(s, addr, EXCP_UNSUPPORTED);
+ gen_exception(s, addr, EXCP_ILLEGAL);
return;
}
ext = read_im16(env, s);
Because kernel only manages illegal instruction exception not unsupported.
Without the patch, we have:
IN:
0x0000d454: 071400
INT 1: Unassigned(0xf4) pc=0000d454 sp=00331e60 sr=2700
with the patch:
IN:
0x0000d454: 071400
INT 1: Illegal Instruction(0x10) pc=0000d454 sp=00331e60 sr=2700
We have in linux/arch/m68k/kernel/vectors.c:
/*
* this must be called very early as the kernel might
* use some instruction that are emulated on the 060
* and so we're prepared for early probe attempts (e.g. nf_init).
*/
void __init base_trap_init(void)
{
...
vectors[VEC_BUSERR] = buserr;
vectors[VEC_ILLEGAL] = trap;
vectors[VEC_SYS] = system_call;
}
So I think the unsupported vector jumps to an invalid address.
This seems triggered by the aranym native feature:
d454: 7300 mvsb %d0,%d1
from linux/arch/m68k/emu/natfeat.c
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-30 12:49 ` Laurent Vivier
@ 2018-10-30 13:12 ` Mark Cave-Ayland
2018-10-30 13:39 ` Laurent Vivier
0 siblings, 1 reply; 39+ messages in thread
From: Mark Cave-Ayland @ 2018-10-30 13:12 UTC (permalink / raw)
To: Laurent Vivier, Richard Henderson, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, hpoussin, kraxel,
pbonzini, aurelien
On 30/10/2018 12:49, Laurent Vivier wrote:
> Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
>> On 30/10/2018 08:15, Richard Henderson wrote:
>>
>>> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>>>> You can install your own disk using debian-installer, with:
>>>>
>>>> ...
>>>> -M q800 \
>>>> -serial none -serial mon:stdio \
>>>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>>>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>>>> -append "console=ttyS0 vga=off" \
>>>> -kernel vmlinux-4.15.0-2-m68k \
>>>> -initrd initrd.gz \
>>>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>>>> -drive file=m68k.qcow2,format=qcow2 \
>>>> -nographic
>>>
>>> I tried this and got
>>>
>>> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
>>> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
>>> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
>>> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>>>
>>> which lead straight to buserr and panic. This happens way early in boot --
>>> only 1926 TranslationBlocks generated.
>>>
>>> Is there some device missing from the command-line that the kernel is expecting?
>>
>> Heh that's annoying. The original branch I forked that Laurent was working on had
>> some extra patches at the start of the series: some were required for q800 whilst
>> others were for new development. I thought that all of the patches required for q800
>> had been applied over the past few months, but sadly that isn't the case :(
>>
>> I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
>> which contains the patchset plus two extra patches that are still needed to boot to
>> the debian installer here:
>>
>> 9281a5371f "tmp"
>> 629754d847 "target/m68k: manage FPU exceptions"
>>
>> Laurent, are these patches ready for upstream or do they need work in which case we
>> should leave q800 until the 3.2 cycle?
>
> The only needed part is from 9281a5371f.
Yeah I think you're right, sorry about that. I'm sure I tried without 629754d847 and
I got a premature exit from QEMU but only in graphic mode, but I've just tried again
and can't seem to recreate it now.
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -1552,7 +1552,7 @@ DISAS_INSN(undef)
> but actually illegal for CPU32 or pre-68020. */
> qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
> insn, s->base.pc_next);
> - gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
> + gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
> }
>
> DISAS_INSN(mulw)
> @@ -2799,7 +2799,7 @@ DISAS_INSN(mull)
>
> if (ext & 0x400) {
> if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
> - gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
> + gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
> return;
> }
>
> @@ -4509,7 +4509,7 @@ DISAS_INSN(strldsr)
> addr = s->pc - 2;
> ext = read_im16(env, s);
> if (ext != 0x46FC) {
> - gen_exception(s, addr, EXCP_UNSUPPORTED);
> + gen_exception(s, addr, EXCP_ILLEGAL);
> return;
> }
> ext = read_im16(env, s);
>
> Because kernel only manages illegal instruction exception not unsupported.
>
> Without the patch, we have:
>
> IN:
> 0x0000d454: 071400
>
> INT 1: Unassigned(0xf4) pc=0000d454 sp=00331e60 sr=2700
>
> with the patch:
>
> IN:
> 0x0000d454: 071400
>
> INT 1: Illegal Instruction(0x10) pc=0000d454 sp=00331e60 sr=2700
>
> We have in linux/arch/m68k/kernel/vectors.c:
>
> /*
> * this must be called very early as the kernel might
> * use some instruction that are emulated on the 060
> * and so we're prepared for early probe attempts (e.g. nf_init).
> */
> void __init base_trap_init(void)
> {
> ...
>
> vectors[VEC_BUSERR] = buserr;
> vectors[VEC_ILLEGAL] = trap;
> vectors[VEC_SYS] = system_call;
> }
>
> So I think the unsupported vector jumps to an invalid address.
>
> This seems triggered by the aranym native feature:
>
> d454: 7300 mvsb %d0,%d1
>
> from linux/arch/m68k/emu/natfeat.c
Interesting. So is this an actual bug in QEMU in terms of implementing the processor
specification, or is it relying on undefined behaviour on real hardware?
ATB,
Mark.
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-30 13:12 ` Mark Cave-Ayland
@ 2018-10-30 13:39 ` Laurent Vivier
2018-11-02 0:32 ` Thomas Huth
0 siblings, 1 reply; 39+ messages in thread
From: Laurent Vivier @ 2018-10-30 13:39 UTC (permalink / raw)
To: Mark Cave-Ayland, Richard Henderson, qemu-devel, kwolf, famz,
qemu-block, jasowang, dgilbert, mreitz, hpoussin, kraxel,
pbonzini, aurelien, Thomas Huth
Le 30/10/2018 à 14:12, Mark Cave-Ayland a écrit :
> On 30/10/2018 12:49, Laurent Vivier wrote:
>
>> Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
>>> On 30/10/2018 08:15, Richard Henderson wrote:
>>>
>>>> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>>>>> You can install your own disk using debian-installer, with:
>>>>>
>>>>> ...
>>>>> -M q800 \
>>>>> -serial none -serial mon:stdio \
>>>>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>>>>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>>>>> -append "console=ttyS0 vga=off" \
>>>>> -kernel vmlinux-4.15.0-2-m68k \
>>>>> -initrd initrd.gz \
>>>>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>>>>> -drive file=m68k.qcow2,format=qcow2 \
>>>>> -nographic
>>>>
>>>> I tried this and got
>>>>
>>>> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
>>>> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
>>>> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
>>>> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>>>>
>>>> which lead straight to buserr and panic. This happens way early in boot --
>>>> only 1926 TranslationBlocks generated.
>>>>
>>>> Is there some device missing from the command-line that the kernel is expecting?
>>>
>>> Heh that's annoying. The original branch I forked that Laurent was working on had
>>> some extra patches at the start of the series: some were required for q800 whilst
>>> others were for new development. I thought that all of the patches required for q800
>>> had been applied over the past few months, but sadly that isn't the case :(
>>>
>>> I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
>>> which contains the patchset plus two extra patches that are still needed to boot to
>>> the debian installer here:
>>>
>>> 9281a5371f "tmp"
>>> 629754d847 "target/m68k: manage FPU exceptions"
>>>
>>> Laurent, are these patches ready for upstream or do they need work in which case we
>>> should leave q800 until the 3.2 cycle?
>>
>> The only needed part is from 9281a5371f.
>
> Yeah I think you're right, sorry about that. I'm sure I tried without 629754d847 and
> I got a premature exit from QEMU but only in graphic mode, but I've just tried again
> and can't seem to recreate it now.
>
>> --- a/target/m68k/translate.c
>> +++ b/target/m68k/translate.c
>> @@ -1552,7 +1552,7 @@ DISAS_INSN(undef)
>> but actually illegal for CPU32 or pre-68020. */
>> qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
>> insn, s->base.pc_next);
>> - gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
>> + gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
>> }
>>
>> DISAS_INSN(mulw)
>> @@ -2799,7 +2799,7 @@ DISAS_INSN(mull)
>>
>> if (ext & 0x400) {
>> if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
>> - gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
>> + gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
>> return;
>> }
>>
>> @@ -4509,7 +4509,7 @@ DISAS_INSN(strldsr)
>> addr = s->pc - 2;
>> ext = read_im16(env, s);
>> if (ext != 0x46FC) {
>> - gen_exception(s, addr, EXCP_UNSUPPORTED);
>> + gen_exception(s, addr, EXCP_ILLEGAL);
>> return;
>> }
>> ext = read_im16(env, s);
>>
>> Because kernel only manages illegal instruction exception not unsupported.
>>
>> Without the patch, we have:
>>
>> IN:
>> 0x0000d454: 071400
>>
>> INT 1: Unassigned(0xf4) pc=0000d454 sp=00331e60 sr=2700
>>
>> with the patch:
>>
>> IN:
>> 0x0000d454: 071400
>>
>> INT 1: Illegal Instruction(0x10) pc=0000d454 sp=00331e60 sr=2700
>>
>> We have in linux/arch/m68k/kernel/vectors.c:
>>
>> /*
>> * this must be called very early as the kernel might
>> * use some instruction that are emulated on the 060
>> * and so we're prepared for early probe attempts (e.g. nf_init).
>> */
>> void __init base_trap_init(void)
>> {
>> ...
>>
>> vectors[VEC_BUSERR] = buserr;
>> vectors[VEC_ILLEGAL] = trap;
>> vectors[VEC_SYS] = system_call;
>> }
>>
>> So I think the unsupported vector jumps to an invalid address.
>>
>> This seems triggered by the aranym native feature:
>>
>> d454: 7300 mvsb %d0,%d1
>>
>> from linux/arch/m68k/emu/natfeat.c
>
> Interesting. So is this an actual bug in QEMU in terms of implementing the processor
> specification, or is it relying on undefined behaviour on real hardware?
It's a bug in QEMU.
EXCP_UNSUPPORTED is defined to a QEMU specific value (61) that is in the
Unassigned/Reserved range of the vector table.
It is used by QEMU user-mode to trigger illegal instruction, whereas
illegal is also used to do simcalls (some thing like a syscall with an
illegal instruction trap). I think this should be deprecated as no one
is maintaining that and knows how to use that.
Perhaps Thomas as an idea as it comes with the coldfire implementation?
(e6e5906b6e ColdFire target)
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-10-30 13:39 ` Laurent Vivier
@ 2018-11-02 0:32 ` Thomas Huth
2018-11-02 11:25 ` Laurent Vivier
0 siblings, 1 reply; 39+ messages in thread
From: Thomas Huth @ 2018-11-02 0:32 UTC (permalink / raw)
To: Laurent Vivier, Mark Cave-Ayland, Richard Henderson, qemu-devel,
hpoussin, aurelien
On 2018-10-30 13:39, Laurent Vivier wrote:
> Le 30/10/2018 à 14:12, Mark Cave-Ayland a écrit :
>> On 30/10/2018 12:49, Laurent Vivier wrote:
>>
>>> Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
>>>> On 30/10/2018 08:15, Richard Henderson wrote:
>>>>
>>>>> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>>>>>> You can install your own disk using debian-installer, with:
>>>>>>
>>>>>> ...
>>>>>> -M q800 \
>>>>>> -serial none -serial mon:stdio \
>>>>>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>>>>>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>>>>>> -append "console=ttyS0 vga=off" \
>>>>>> -kernel vmlinux-4.15.0-2-m68k \
>>>>>> -initrd initrd.gz \
>>>>>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>>>>>> -drive file=m68k.qcow2,format=qcow2 \
>>>>>> -nographic
>>>>>
>>>>> I tried this and got
>>>>>
>>>>> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
>>>>> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
>>>>> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
>>>>> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>>>>>
>>>>> which lead straight to buserr and panic. This happens way early in boot --
>>>>> only 1926 TranslationBlocks generated.
>>>>>
>>>>> Is there some device missing from the command-line that the kernel is expecting?
>>>>
>>>> Heh that's annoying. The original branch I forked that Laurent was working on had
>>>> some extra patches at the start of the series: some were required for q800 whilst
>>>> others were for new development. I thought that all of the patches required for q800
>>>> had been applied over the past few months, but sadly that isn't the case :(
>>>>
>>>> I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
>>>> which contains the patchset plus two extra patches that are still needed to boot to
>>>> the debian installer here:
>>>>
>>>> 9281a5371f "tmp"
>>>> 629754d847 "target/m68k: manage FPU exceptions"
>>>>
>>>> Laurent, are these patches ready for upstream or do they need work in which case we
>>>> should leave q800 until the 3.2 cycle?
>>>
>>> The only needed part is from 9281a5371f.
>>
>> Yeah I think you're right, sorry about that. I'm sure I tried without 629754d847 and
>> I got a premature exit from QEMU but only in graphic mode, but I've just tried again
>> and can't seem to recreate it now.
[...]
>>> Because kernel only manages illegal instruction exception not unsupported.
>>>
>>> Without the patch, we have:
>>>
>>> IN:
>>> 0x0000d454: 071400
>>>
>>> INT 1: Unassigned(0xf4) pc=0000d454 sp=00331e60 sr=2700
>>>
>>> with the patch:
>>>
>>> IN:
>>> 0x0000d454: 071400
>>>
>>> INT 1: Illegal Instruction(0x10) pc=0000d454 sp=00331e60 sr=2700
>>>
>>> We have in linux/arch/m68k/kernel/vectors.c:
>>>
>>> /*
>>> * this must be called very early as the kernel might
>>> * use some instruction that are emulated on the 060
>>> * and so we're prepared for early probe attempts (e.g. nf_init).
>>> */
>>> void __init base_trap_init(void)
>>> {
>>> ...
>>>
>>> vectors[VEC_BUSERR] = buserr;
>>> vectors[VEC_ILLEGAL] = trap;
>>> vectors[VEC_SYS] = system_call;
>>> }
>>>
>>> So I think the unsupported vector jumps to an invalid address.
>>>
>>> This seems triggered by the aranym native feature:
>>>
>>> d454: 7300 mvsb %d0,%d1
>>>
>>> from linux/arch/m68k/emu/natfeat.c
>>
>> Interesting. So is this an actual bug in QEMU in terms of implementing the processor
>> specification, or is it relying on undefined behaviour on real hardware?
>
> It's a bug in QEMU.
>
> EXCP_UNSUPPORTED is defined to a QEMU specific value (61) that is in the
> Unassigned/Reserved range of the vector table.
>
> It is used by QEMU user-mode to trigger illegal instruction, whereas
> illegal is also used to do simcalls (some thing like a syscall with an
> illegal instruction trap). I think this should be deprecated as no one
> is maintaining that and knows how to use that.
>
> Perhaps Thomas as an idea as it comes with the coldfire implementation?
> (e6e5906b6e ColdFire target)
No clue, I've never used those simcalls before.
Maybe we could "fix" it simply by changing the #define in cpu.h like this:
#if defined(CONFIG_USER_ONLY)
#define EXCP_UNSUPPORTED 61
#else
#define EXCP_UNSUPPORTED EXCP_ILLEGAL
#endif
?
If that does not work, I'm also fine if we simply deprecate the simcalls
(if possible).
Thomas
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-11-02 0:32 ` Thomas Huth
@ 2018-11-02 11:25 ` Laurent Vivier
2018-11-19 2:30 ` Rob Landley
0 siblings, 1 reply; 39+ messages in thread
From: Laurent Vivier @ 2018-11-02 11:25 UTC (permalink / raw)
To: Thomas Huth, Mark Cave-Ayland, Richard Henderson, qemu-devel,
hpoussin, aurelien
On 02/11/2018 01:32, Thomas Huth wrote:
> On 2018-10-30 13:39, Laurent Vivier wrote:
>> Le 30/10/2018 à 14:12, Mark Cave-Ayland a écrit :
>>> On 30/10/2018 12:49, Laurent Vivier wrote:
>>>
>>>> Le 30/10/2018 à 12:48, Mark Cave-Ayland a écrit :
>>>>> On 30/10/2018 08:15, Richard Henderson wrote:
>>>>>
>>>>>> On 10/29/18 1:39 PM, Mark Cave-Ayland wrote:
>>>>>>> You can install your own disk using debian-installer, with:
>>>>>>>
>>>>>>> ...
>>>>>>> -M q800 \
>>>>>>> -serial none -serial mon:stdio \
>>>>>>> -m 1000M -drive file=m68k.qcow2,format=qcow2 \
>>>>>>> -net nic,model=dp83932,addr=09:00:07:12:34:57 \
>>>>>>> -append "console=ttyS0 vga=off" \
>>>>>>> -kernel vmlinux-4.15.0-2-m68k \
>>>>>>> -initrd initrd.gz \
>>>>>>> -drive file=debian-9.0-m68k-NETINST-1.iso \
>>>>>>> -drive file=m68k.qcow2,format=qcow2 \
>>>>>>> -nographic
>>>>>>
>>>>>> I tried this and got
>>>>>>
>>>>>> Trace 0: 0x7f2e886c7140 [00000000/0000d404/0xe000]
>>>>>> INT 1: Unassigned(0xf4) pc=0000d404 sp=00393e60 sr=2700
>>>>>> INT 2: Access Fault(0x8) pc=00000000 sp=00393e58 sr=2700
>>>>>> ssw: 00000506 ea: 00000000 sfc: 5 dfc: 5
>>>>>>
>>>>>> which lead straight to buserr and panic. This happens way early in boot --
>>>>>> only 1926 TranslationBlocks generated.
>>>>>>
>>>>>> Is there some device missing from the command-line that the kernel is expecting?
>>>>>
>>>>> Heh that's annoying. The original branch I forked that Laurent was working on had
>>>>> some extra patches at the start of the series: some were required for q800 whilst
>>>>> others were for new development. I thought that all of the patches required for q800
>>>>> had been applied over the past few months, but sadly that isn't the case :(
>>>>>
>>>>> I've pushed an updated branch to https://github.com/mcayland/qemu/tree/q800-test
>>>>> which contains the patchset plus two extra patches that are still needed to boot to
>>>>> the debian installer here:
>>>>>
>>>>> 9281a5371f "tmp"
>>>>> 629754d847 "target/m68k: manage FPU exceptions"
>>>>>
>>>>> Laurent, are these patches ready for upstream or do they need work in which case we
>>>>> should leave q800 until the 3.2 cycle?
>>>>
>>>> The only needed part is from 9281a5371f.
>>>
>>> Yeah I think you're right, sorry about that. I'm sure I tried without 629754d847 and
>>> I got a premature exit from QEMU but only in graphic mode, but I've just tried again
>>> and can't seem to recreate it now.
> [...]
>>>> Because kernel only manages illegal instruction exception not unsupported.
>>>>
>>>> Without the patch, we have:
>>>>
>>>> IN:
>>>> 0x0000d454: 071400
>>>>
>>>> INT 1: Unassigned(0xf4) pc=0000d454 sp=00331e60 sr=2700
>>>>
>>>> with the patch:
>>>>
>>>> IN:
>>>> 0x0000d454: 071400
>>>>
>>>> INT 1: Illegal Instruction(0x10) pc=0000d454 sp=00331e60 sr=2700
>>>>
>>>> We have in linux/arch/m68k/kernel/vectors.c:
>>>>
>>>> /*
>>>> * this must be called very early as the kernel might
>>>> * use some instruction that are emulated on the 060
>>>> * and so we're prepared for early probe attempts (e.g. nf_init).
>>>> */
>>>> void __init base_trap_init(void)
>>>> {
>>>> ...
>>>>
>>>> vectors[VEC_BUSERR] = buserr;
>>>> vectors[VEC_ILLEGAL] = trap;
>>>> vectors[VEC_SYS] = system_call;
>>>> }
>>>>
>>>> So I think the unsupported vector jumps to an invalid address.
>>>>
>>>> This seems triggered by the aranym native feature:
>>>>
>>>> d454: 7300 mvsb %d0,%d1
>>>>
>>>> from linux/arch/m68k/emu/natfeat.c
>>>
>>> Interesting. So is this an actual bug in QEMU in terms of implementing the processor
>>> specification, or is it relying on undefined behaviour on real hardware?
>>
>> It's a bug in QEMU.
>>
>> EXCP_UNSUPPORTED is defined to a QEMU specific value (61) that is in the
>> Unassigned/Reserved range of the vector table.
>>
>> It is used by QEMU user-mode to trigger illegal instruction, whereas
>> illegal is also used to do simcalls (some thing like a syscall with an
>> illegal instruction trap). I think this should be deprecated as no one
>> is maintaining that and knows how to use that.
>>
>> Perhaps Thomas as an idea as it comes with the coldfire implementation?
>> (e6e5906b6e ColdFire target)
>
> No clue, I've never used those simcalls before.
>
> Maybe we could "fix" it simply by changing the #define in cpu.h like this:
>
> #if defined(CONFIG_USER_ONLY)
> #define EXCP_UNSUPPORTED 61
> #else
> #define EXCP_UNSUPPORTED EXCP_ILLEGAL
> #endif
>
I've found EXCP_UNSUPPORTED is a valid value to softmmu too, only
supported by some coldfire version.
In fact, we don't need the EXCP_UNSUPPORTED, the EXCP_ILLEGAL is used to
call the simcall interface. Before the introduction of m680x0 emulation
, EXCP_ILLEGAL was only used with the "illegal" instruction, other
unsupported instructions triggered the EXCP_UNSUPPORTED. So only the
"illegal" instruction was able to enter in the simcall interface.
As I have changed that, I think it should not work correctly anymore,
and I have no idea how to test that... and I'm pretty sure no one is
using that anymore (and if needed could switch to the standard "trap #0"
linux-user interface)
>
> If that does not work, I'm also fine if we simply deprecate the simcalls
> (if possible).
I have a patch to deprecate the interface. I will send it once the
release will be done.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/11] hw/m68k: add Apple Machintosh Quadra 800 machine
2018-11-02 11:25 ` Laurent Vivier
@ 2018-11-19 2:30 ` Rob Landley
0 siblings, 0 replies; 39+ messages in thread
From: Rob Landley @ 2018-11-19 2:30 UTC (permalink / raw)
To: Laurent Vivier, Thomas Huth, Mark Cave-Ayland, Richard Henderson,
qemu-devel, hpoussin, aurelien
On 11/2/18 6:25 AM, Laurent Vivier wrote:
>> If that does not work, I'm also fine if we simply deprecate the simcalls
>> (if possible).
>
> I have a patch to deprecate the interface. I will send it once the
> release will be done.
Did I ever point out that I got m68k running under your q800 emulation in my
https://github.com/landley/mkroot project?
Now that m68k is in musl-libc, you can build
https://github.com/richfelker/musl-cross-make or grab a prebuilt binary a
toolchain from http://b.zv.io/mcm/bin/m68k-linux-musl-cross.tar.gz and then:
CROSS_COMPILE=/path/to/m68k-linux-musl-cross/bin/m68k-linux-musl- \
./mkroot.sh kernel
And then:
cd output/m68k
./qemu-m68k.sh -hda log.txt
The -hda is just so you have a hard drive image you can play with. Cat /dev/?da
should show you the log.txt contents. The network interface works too, although
I haven't got wget in toybox yet but:
echo GET / | netcat landley.net /
Works. :)
When does this go upstream?
P.S. to build a current kernel:
cd download
git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
cd ..
And then mkroot.sh again. I tested with 4.20-rc1 and m68k worked fine.
> Thanks,
> Laurent
Rob
^ permalink raw reply [flat|nested] 39+ messages in thread