* [PULL 0/7] x86 queue, 2018-10-30
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Marcelo Tosatti,
Paolo Bonzini, Richard Henderson
Sorry for submitting this at the last minute.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to c4fc3c4d9b456a145e8f3fd75496e1dacb578473:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 0/7] x86 queue, 2018-10-30
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti
Sorry for submitting this at the last minute.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to c4fc3c4d9b456a145e8f3fd75496e1dacb578473:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 1/7] i386: correct cpu_x86_cpuid(0xd)
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin,
Sebastian Andrzej Siewior, Marcelo Tosatti, Paolo Bonzini,
Richard Henderson
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Intel SDM says for CPUID function 0DH, sub-function 0:
| • ECX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components supported by this
| processor.
| • EBX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components corresponding to bits
| currently set in XCR0.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Message-Id: <20180928104319.3296-1-bigeasy@linutronix.de>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1469a1be01..fe7c963e5e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4178,7 +4178,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
*eax = env->features[FEAT_XSAVE_COMP_LO];
*edx = env->features[FEAT_XSAVE_COMP_HI];
- *ebx = *ecx;
+ *ebx = xsave_area_size(env->xcr0);
} else if (count == 1) {
*eax = env->features[FEAT_XSAVE];
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 1/7] i386: correct cpu_x86_cpuid(0xd)
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti,
Sebastian Andrzej Siewior
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Intel SDM says for CPUID function 0DH, sub-function 0:
| • ECX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components supported by this
| processor.
| • EBX enumerates the size (in bytes) required by the XSAVE instruction for an
| XSAVE area containing all the user state components corresponding to bits
| currently set in XCR0.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Message-Id: <20180928104319.3296-1-bigeasy@linutronix.de>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1469a1be01..fe7c963e5e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4178,7 +4178,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
*eax = env->features[FEAT_XSAVE_COMP_LO];
*edx = env->features[FEAT_XSAVE_COMP_HI];
- *ebx = *ecx;
+ *ebx = xsave_area_size(env->xcr0);
} else if (count == 1) {
*eax = env->features[FEAT_XSAVE];
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 2/7] target/i386: Remove #ifdeffed-out icebp debugging hack
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Marcelo Tosatti,
Paolo Bonzini, Richard Henderson
From: Peter Maydell <peter.maydell@linaro.org>
Remove a debugging hack which could be used to cause the
undocumented 'icebp' instruction to enable QEMU internal
debug logging. This code has always been #ifdeffed out
since it was introduced in commit aba9d61e34b9 in 2005;
judging by the rest of that commit (which is entirely
unrelated) it may have even been committed by accident.
(Note that WANT_ICEBP is not defined by default anyway.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20181009183314.13416-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 83c1ebe491..f8bc7680af 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -7028,13 +7028,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
-#if 1
gen_debug(s, pc_start - s->cs_base);
-#else
- /* start debug */
- tb_flush(CPU(x86_env_get_cpu(env)));
- qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
-#endif
break;
#endif
case 0xfa: /* cli */
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 2/7] target/i386: Remove #ifdeffed-out icebp debugging hack
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti
From: Peter Maydell <peter.maydell@linaro.org>
Remove a debugging hack which could be used to cause the
undocumented 'icebp' instruction to enable QEMU internal
debug logging. This code has always been #ifdeffed out
since it was introduced in commit aba9d61e34b9 in 2005;
judging by the rest of that commit (which is entirely
unrelated) it may have even been committed by accident.
(Note that WANT_ICEBP is not defined by default anyway.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20181009183314.13416-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 83c1ebe491..f8bc7680af 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -7028,13 +7028,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
#ifdef WANT_ICEBP
case 0xf1: /* icebp (undocumented, exits to external debugger) */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
-#if 1
gen_debug(s, pc_start - s->cs_base);
-#else
- /* start debug */
- tb_flush(CPU(x86_env_get_cpu(env)));
- qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
-#endif
break;
#endif
case 0xfa: /* cli */
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 3/7] kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo, Paolo Bonzini, Richard Henderson
From: Robert Hoo <robert.hu@linux.intel.com>
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-2-git-send-email-robert.hu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c | 80 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e067..97d8d9d0d5 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -463,6 +463,8 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension);
uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
uint32_t index, int reg);
+uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
+
void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 115d8b4c14..161fc38397 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -107,6 +107,7 @@ static int has_pit_state2;
static bool has_msr_mcg_ext_ctl;
static struct kvm_cpuid2 *cpuid_cache;
+static struct kvm_msr_list *kvm_feature_msrs;
int kvm_has_pit_state2(void)
{
@@ -420,6 +421,42 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
return ret;
}
+uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
+{
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[1];
+ } msr_data;
+ uint32_t ret;
+
+ if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
+ return 0;
+ }
+
+ /* Check if requested MSR is supported feature MSR */
+ int i;
+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
+ if (kvm_feature_msrs->indices[i] == index) {
+ break;
+ }
+ if (i == kvm_feature_msrs->nmsrs) {
+ return 0; /* if the feature MSR is not supported, simply return 0 */
+ }
+
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = index;
+
+ ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
+ if (ret != 1) {
+ error_report("KVM get MSR (index=0x%x) feature failed, %s",
+ index, strerror(-ret));
+ exit(1);
+ }
+
+ return msr_data.entries[0].data;
+}
+
+
typedef struct HWPoisonPage {
ram_addr_t ram_addr;
QLIST_ENTRY(HWPoisonPage) list;
@@ -1286,6 +1323,47 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu)
}
}
+static int kvm_get_supported_feature_msrs(KVMState *s)
+{
+ int ret = 0;
+
+ if (kvm_feature_msrs != NULL) {
+ return 0;
+ }
+
+ if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
+ return 0;
+ }
+
+ struct kvm_msr_list msr_list;
+
+ msr_list.nmsrs = 0;
+ ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
+ if (ret < 0 && ret != -E2BIG) {
+ error_report("Fetch KVM feature MSR list failed: %s",
+ strerror(-ret));
+ return ret;
+ }
+
+ assert(msr_list.nmsrs > 0);
+ kvm_feature_msrs = (struct kvm_msr_list *) \
+ g_malloc0(sizeof(msr_list) +
+ msr_list.nmsrs * sizeof(msr_list.indices[0]));
+
+ kvm_feature_msrs->nmsrs = msr_list.nmsrs;
+ ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
+
+ if (ret < 0) {
+ error_report("Fetch KVM feature MSR list failed: %s",
+ strerror(-ret));
+ g_free(kvm_feature_msrs);
+ kvm_feature_msrs = NULL;
+ return ret;
+ }
+
+ return 0;
+}
+
static int kvm_get_supported_msrs(KVMState *s)
{
static int kvm_supported_msrs;
@@ -1439,6 +1517,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
return ret;
}
+ kvm_get_supported_feature_msrs(s);
+
uname(&utsname);
lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 3/7] kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo
From: Robert Hoo <robert.hu@linux.intel.com>
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-2-git-send-email-robert.hu@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c | 80 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e067..97d8d9d0d5 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -463,6 +463,8 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension);
uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function,
uint32_t index, int reg);
+uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index);
+
void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 115d8b4c14..161fc38397 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -107,6 +107,7 @@ static int has_pit_state2;
static bool has_msr_mcg_ext_ctl;
static struct kvm_cpuid2 *cpuid_cache;
+static struct kvm_msr_list *kvm_feature_msrs;
int kvm_has_pit_state2(void)
{
@@ -420,6 +421,42 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
return ret;
}
+uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
+{
+ struct {
+ struct kvm_msrs info;
+ struct kvm_msr_entry entries[1];
+ } msr_data;
+ uint32_t ret;
+
+ if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
+ return 0;
+ }
+
+ /* Check if requested MSR is supported feature MSR */
+ int i;
+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
+ if (kvm_feature_msrs->indices[i] == index) {
+ break;
+ }
+ if (i == kvm_feature_msrs->nmsrs) {
+ return 0; /* if the feature MSR is not supported, simply return 0 */
+ }
+
+ msr_data.info.nmsrs = 1;
+ msr_data.entries[0].index = index;
+
+ ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
+ if (ret != 1) {
+ error_report("KVM get MSR (index=0x%x) feature failed, %s",
+ index, strerror(-ret));
+ exit(1);
+ }
+
+ return msr_data.entries[0].data;
+}
+
+
typedef struct HWPoisonPage {
ram_addr_t ram_addr;
QLIST_ENTRY(HWPoisonPage) list;
@@ -1286,6 +1323,47 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu)
}
}
+static int kvm_get_supported_feature_msrs(KVMState *s)
+{
+ int ret = 0;
+
+ if (kvm_feature_msrs != NULL) {
+ return 0;
+ }
+
+ if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
+ return 0;
+ }
+
+ struct kvm_msr_list msr_list;
+
+ msr_list.nmsrs = 0;
+ ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
+ if (ret < 0 && ret != -E2BIG) {
+ error_report("Fetch KVM feature MSR list failed: %s",
+ strerror(-ret));
+ return ret;
+ }
+
+ assert(msr_list.nmsrs > 0);
+ kvm_feature_msrs = (struct kvm_msr_list *) \
+ g_malloc0(sizeof(msr_list) +
+ msr_list.nmsrs * sizeof(msr_list.indices[0]));
+
+ kvm_feature_msrs->nmsrs = msr_list.nmsrs;
+ ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
+
+ if (ret < 0) {
+ error_report("Fetch KVM feature MSR list failed: %s",
+ strerror(-ret));
+ g_free(kvm_feature_msrs);
+ kvm_feature_msrs = NULL;
+ return ret;
+ }
+
+ return 0;
+}
+
static int kvm_get_supported_msrs(KVMState *s)
{
static int kvm_supported_msrs;
@@ -1439,6 +1517,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
return ret;
}
+ kvm_get_supported_feature_msrs(s);
+
uname(&utsname);
lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 4/7] x86: Data structure changes to support MSR based features
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo, Paolo Bonzini, Richard Henderson
From: Robert Hoo <robert.hu@linux.intel.com>
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
[ehabkost: fixed hvf_enabled() case]
---
target/i386/cpu.c | 197 +++++++++++++++++++++++++++++++++-------------
1 file changed, 142 insertions(+), 55 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fe7c963e5e..989a71ac9a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -770,17 +770,36 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
/* missing:
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
+typedef enum FeatureWordType {
+ CPUID_FEATURE_WORD,
+ MSR_FEATURE_WORD,
+} FeatureWordType;
+
typedef struct FeatureWordInfo {
+ FeatureWordType type;
/* feature flags names are taken from "Intel Processor Identification and
* the CPUID Instruction" and AMD's "CPUID Specification".
* In cases of disagreement between feature naming conventions,
* aliases may be added.
*/
const char *feat_names[32];
- uint32_t cpuid_eax; /* Input EAX for CPUID */
- bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
- uint32_t cpuid_ecx; /* Input ECX value for CPUID */
- int cpuid_reg; /* output register (R_* constant) */
+ union {
+ /* If type==CPUID_FEATURE_WORD */
+ struct {
+ uint32_t eax; /* Input EAX for CPUID */
+ bool needs_ecx; /* CPUID instruction uses ECX as input */
+ uint32_t ecx; /* Input ECX value for CPUID */
+ int reg; /* output register (R_* constant) */
+ } cpuid;
+ /* If type==MSR_FEATURE_WORD */
+ struct {
+ uint32_t index;
+ struct { /*CPUID that enumerate this MSR*/
+ FeatureWord cpuid_class;
+ uint32_t cpuid_flag;
+ } cpuid_dep;
+ } msr;
+ };
uint32_t tcg_features; /* Feature flags supported by TCG */
uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
uint32_t migratable_flags; /* Feature flags known to be migratable */
@@ -790,6 +809,7 @@ typedef struct FeatureWordInfo {
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"fpu", "vme", "de", "pse",
"tsc", "msr", "pae", "mce",
@@ -800,10 +820,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"fxsr", "sse", "sse2", "ss",
"ht" /* Intel htt */, "tm", "ia64", "pbe",
},
- .cpuid_eax = 1, .cpuid_reg = R_EDX,
+ .cpuid = {.eax = 1, .reg = R_EDX, },
.tcg_features = TCG_FEATURES,
},
[FEAT_1_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
"ds-cpl", "vmx", "smx", "est",
@@ -814,7 +835,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"tsc-deadline", "aes", "xsave", NULL /* osxsave */,
"avx", "f16c", "rdrand", "hypervisor",
},
- .cpuid_eax = 1, .cpuid_reg = R_ECX,
+ .cpuid = { .eax = 1, .reg = R_ECX, },
.tcg_features = TCG_EXT_FEATURES,
},
/* Feature names that are already defined on feature_name[] but
@@ -823,6 +844,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
*/
[FEAT_8000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
@@ -833,10 +855,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
NULL, "lm", "3dnowext", "3dnow",
},
- .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
.tcg_features = TCG_EXT2_FEATURES,
},
[FEAT_8000_0001_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"lahf-lm", "cmp-legacy", "svm", "extapic",
"cr8legacy", "abm", "sse4a", "misalignsse",
@@ -847,7 +870,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"perfctr-nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
+ .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
.tcg_features = TCG_EXT3_FEATURES,
/*
* TOPOEXT is always allowed but can't be enabled blindly by
@@ -857,6 +880,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
[FEAT_C000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "xstore", "xstore-en",
NULL, NULL, "xcrypt", "xcrypt-en",
@@ -867,10 +891,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
.tcg_features = TCG_EXT4_FEATURES,
},
[FEAT_KVM] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
@@ -881,10 +906,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"kvmclock-stable-bit", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
.tcg_features = TCG_KVM_FEATURES,
},
[FEAT_KVM_HINTS] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"kvm-hint-dedicated", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -895,7 +921,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
.tcg_features = TCG_KVM_FEATURES,
/*
* KVM hints aren't auto-enabled by -cpu host, they need to be
@@ -904,6 +930,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.no_autoenable_flags = ~0U,
},
[FEAT_HYPERV_EAX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
@@ -918,9 +945,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
},
[FEAT_HYPERV_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
@@ -934,9 +962,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
},
[FEAT_HYPERV_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
@@ -949,9 +978,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
},
[FEAT_SVM] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"npt", "lbrv", "svm-lock", "nrip-save",
"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
@@ -962,10 +992,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
.tcg_features = TCG_SVM_FEATURES,
},
[FEAT_7_0_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"fsgsbase", "tsc-adjust", NULL, "bmi1",
"hle", "avx2", NULL, "smep",
@@ -976,12 +1007,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"clwb", "intel-pt", "avx512pf", "avx512er",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EBX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EBX,
+ },
.tcg_features = TCG_7_0_EBX_FEATURES,
},
[FEAT_7_0_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
NULL /* ospke */, NULL, "avx512vbmi2", NULL,
@@ -992,12 +1026,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "cldemote", NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_ECX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_ECX,
+ },
.tcg_features = TCG_7_0_ECX_FEATURES,
},
[FEAT_7_0_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL,
@@ -1008,13 +1045,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, "spec-ctrl", NULL,
NULL, "arch-capabilities", NULL, "ssbd",
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EDX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_7_0_EDX_FEATURES,
.unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
},
[FEAT_8000_0007_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -1025,12 +1065,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000007,
- .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
.tcg_features = TCG_APM_FEATURES,
.unmigratable_flags = CPUID_APM_INVTSC,
},
[FEAT_8000_0008_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -1041,12 +1081,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000008,
- .cpuid_reg = R_EBX,
+ .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
.tcg_features = 0,
.unmigratable_flags = 0,
},
[FEAT_XSAVE] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
NULL, NULL, NULL, NULL,
@@ -1057,12 +1097,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0xd,
- .cpuid_needs_ecx = true, .cpuid_ecx = 1,
- .cpuid_reg = R_EAX,
+ .cpuid = {
+ .eax = 0xd,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
.tcg_features = TCG_XSAVE_FEATURES,
},
[FEAT_6_EAX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "arat", NULL,
NULL, NULL, NULL, NULL,
@@ -1073,13 +1116,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 6, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = 6, .reg = R_EAX, },
.tcg_features = TCG_6_EAX_FEATURES,
},
[FEAT_XSAVE_COMP_LO] = {
- .cpuid_eax = 0xD,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EAX,
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EAX,
+ },
.tcg_features = ~0U,
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
@@ -1087,9 +1133,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
XSTATE_PKRU_MASK,
},
[FEAT_XSAVE_COMP_HI] = {
- .cpuid_eax = 0xD,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EDX,
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
.tcg_features = ~0U,
},
};
@@ -2975,21 +3024,41 @@ static const TypeInfo host_x86_cpu_type_info = {
#endif
+static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
+{
+ assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
+
+ switch (f->type) {
+ case CPUID_FEATURE_WORD:
+ {
+ const char *reg = get_register_name_32(f->cpuid.reg);
+ assert(reg);
+ return g_strdup_printf("CPUID.%02XH:%s",
+ f->cpuid.eax, reg);
+ }
+ case MSR_FEATURE_WORD:
+ return g_strdup_printf("MSR(%02XH)",
+ f->msr.index);
+ }
+
+ return NULL;
+}
+
static void report_unavailable_features(FeatureWord w, uint32_t mask)
{
FeatureWordInfo *f = &feature_word_info[w];
int i;
+ char *feat_word_str;
for (i = 0; i < 32; ++i) {
if ((1UL << i) & mask) {
- const char *reg = get_register_name_32(f->cpuid_reg);
- assert(reg);
- warn_report("%s doesn't support requested feature: "
- "CPUID.%02XH:%s%s%s [bit %d]",
+ feat_word_str = feature_word_description(f, i);
+ warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
accel_uses_host_cpuid() ? "host" : "TCG",
- f->cpuid_eax, reg,
+ feat_word_str,
f->feat_names[i] ? "." : "",
f->feat_names[i] ? f->feat_names[i] : "", i);
+ g_free(feat_word_str);
}
}
}
@@ -3233,11 +3302,18 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *wi = &feature_word_info[w];
+ /*
+ * We didn't have MSR features when "feature-words" was
+ * introduced. Therefore skipped other type entries.
+ */
+ if (wi->type != CPUID_FEATURE_WORD) {
+ continue;
+ }
X86CPUFeatureWordInfo *qwi = &word_infos[w];
- qwi->cpuid_input_eax = wi->cpuid_eax;
- qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
- qwi->cpuid_input_ecx = wi->cpuid_ecx;
- qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
+ qwi->cpuid_input_eax = wi->cpuid.eax;
+ qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
+ qwi->cpuid_input_ecx = wi->cpuid.ecx;
+ qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
qwi->features = array[w];
/* List will be in reverse order, but order shouldn't matter */
@@ -3610,16 +3686,26 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only)
{
FeatureWordInfo *wi = &feature_word_info[w];
- uint32_t r;
+ uint32_t r = 0;
if (kvm_enabled()) {
- r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
- wi->cpuid_ecx,
- wi->cpuid_reg);
+ switch (wi->type) {
+ case CPUID_FEATURE_WORD:
+ r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
+ wi->cpuid.ecx,
+ wi->cpuid.reg);
+ break;
+ case MSR_FEATURE_WORD:
+ r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
+ break;
+ }
} else if (hvf_enabled()) {
- r = hvf_get_supported_cpuid(wi->cpuid_eax,
- wi->cpuid_ecx,
- wi->cpuid_reg);
+ if (wi->type != CPUID_FEATURE_WORD) {
+ return 0;
+ }
+ r = hvf_get_supported_cpuid(wi->cpuid.eax,
+ wi->cpuid.ecx,
+ wi->cpuid.reg);
} else if (tcg_enabled()) {
r = wi->tcg_features;
} else {
@@ -4680,9 +4766,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
{
CPUX86State *env = &cpu->env;
FeatureWordInfo *fi = &feature_word_info[w];
- uint32_t eax = fi->cpuid_eax;
+ uint32_t eax = fi->cpuid.eax;
uint32_t region = eax & 0xF0000000;
+ assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
if (!env->features[w]) {
return;
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 4/7] x86: Data structure changes to support MSR based features
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo
From: Robert Hoo <robert.hu@linux.intel.com>
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
[ehabkost: fixed hvf_enabled() case]
---
target/i386/cpu.c | 197 +++++++++++++++++++++++++++++++++-------------
1 file changed, 142 insertions(+), 55 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fe7c963e5e..989a71ac9a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -770,17 +770,36 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
/* missing:
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
+typedef enum FeatureWordType {
+ CPUID_FEATURE_WORD,
+ MSR_FEATURE_WORD,
+} FeatureWordType;
+
typedef struct FeatureWordInfo {
+ FeatureWordType type;
/* feature flags names are taken from "Intel Processor Identification and
* the CPUID Instruction" and AMD's "CPUID Specification".
* In cases of disagreement between feature naming conventions,
* aliases may be added.
*/
const char *feat_names[32];
- uint32_t cpuid_eax; /* Input EAX for CPUID */
- bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
- uint32_t cpuid_ecx; /* Input ECX value for CPUID */
- int cpuid_reg; /* output register (R_* constant) */
+ union {
+ /* If type==CPUID_FEATURE_WORD */
+ struct {
+ uint32_t eax; /* Input EAX for CPUID */
+ bool needs_ecx; /* CPUID instruction uses ECX as input */
+ uint32_t ecx; /* Input ECX value for CPUID */
+ int reg; /* output register (R_* constant) */
+ } cpuid;
+ /* If type==MSR_FEATURE_WORD */
+ struct {
+ uint32_t index;
+ struct { /*CPUID that enumerate this MSR*/
+ FeatureWord cpuid_class;
+ uint32_t cpuid_flag;
+ } cpuid_dep;
+ } msr;
+ };
uint32_t tcg_features; /* Feature flags supported by TCG */
uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
uint32_t migratable_flags; /* Feature flags known to be migratable */
@@ -790,6 +809,7 @@ typedef struct FeatureWordInfo {
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"fpu", "vme", "de", "pse",
"tsc", "msr", "pae", "mce",
@@ -800,10 +820,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"fxsr", "sse", "sse2", "ss",
"ht" /* Intel htt */, "tm", "ia64", "pbe",
},
- .cpuid_eax = 1, .cpuid_reg = R_EDX,
+ .cpuid = {.eax = 1, .reg = R_EDX, },
.tcg_features = TCG_FEATURES,
},
[FEAT_1_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
"ds-cpl", "vmx", "smx", "est",
@@ -814,7 +835,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"tsc-deadline", "aes", "xsave", NULL /* osxsave */,
"avx", "f16c", "rdrand", "hypervisor",
},
- .cpuid_eax = 1, .cpuid_reg = R_ECX,
+ .cpuid = { .eax = 1, .reg = R_ECX, },
.tcg_features = TCG_EXT_FEATURES,
},
/* Feature names that are already defined on feature_name[] but
@@ -823,6 +844,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
*/
[FEAT_8000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
@@ -833,10 +855,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
NULL, "lm", "3dnowext", "3dnow",
},
- .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
.tcg_features = TCG_EXT2_FEATURES,
},
[FEAT_8000_0001_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"lahf-lm", "cmp-legacy", "svm", "extapic",
"cr8legacy", "abm", "sse4a", "misalignsse",
@@ -847,7 +870,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"perfctr-nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
+ .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
.tcg_features = TCG_EXT3_FEATURES,
/*
* TOPOEXT is always allowed but can't be enabled blindly by
@@ -857,6 +880,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
},
[FEAT_C000_0001_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "xstore", "xstore-en",
NULL, NULL, "xcrypt", "xcrypt-en",
@@ -867,10 +891,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
.tcg_features = TCG_EXT4_FEATURES,
},
[FEAT_KVM] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
@@ -881,10 +906,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"kvmclock-stable-bit", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
.tcg_features = TCG_KVM_FEATURES,
},
[FEAT_KVM_HINTS] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"kvm-hint-dedicated", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -895,7 +921,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
.tcg_features = TCG_KVM_FEATURES,
/*
* KVM hints aren't auto-enabled by -cpu host, they need to be
@@ -904,6 +930,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.no_autoenable_flags = ~0U,
},
[FEAT_HYPERV_EAX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
@@ -918,9 +945,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
},
[FEAT_HYPERV_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
@@ -934,9 +962,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
},
[FEAT_HYPERV_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
@@ -949,9 +978,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
},
[FEAT_SVM] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"npt", "lbrv", "svm-lock", "nrip-save",
"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
@@ -962,10 +992,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
.tcg_features = TCG_SVM_FEATURES,
},
[FEAT_7_0_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"fsgsbase", "tsc-adjust", NULL, "bmi1",
"hle", "avx2", NULL, "smep",
@@ -976,12 +1007,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"clwb", "intel-pt", "avx512pf", "avx512er",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EBX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EBX,
+ },
.tcg_features = TCG_7_0_EBX_FEATURES,
},
[FEAT_7_0_ECX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, "avx512vbmi", "umip", "pku",
NULL /* ospke */, NULL, "avx512vbmi2", NULL,
@@ -992,12 +1026,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "cldemote", NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_ECX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_ECX,
+ },
.tcg_features = TCG_7_0_ECX_FEATURES,
},
[FEAT_7_0_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL,
@@ -1008,13 +1045,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, "spec-ctrl", NULL,
NULL, "arch-capabilities", NULL, "ssbd",
},
- .cpuid_eax = 7,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EDX,
+ .cpuid = {
+ .eax = 7,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
.tcg_features = TCG_7_0_EDX_FEATURES,
.unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
},
[FEAT_8000_0007_EDX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -1025,12 +1065,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000007,
- .cpuid_reg = R_EDX,
+ .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
.tcg_features = TCG_APM_FEATURES,
.unmigratable_flags = CPUID_APM_INVTSC,
},
[FEAT_8000_0008_EBX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -1041,12 +1081,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0x80000008,
- .cpuid_reg = R_EBX,
+ .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
.tcg_features = 0,
.unmigratable_flags = 0,
},
[FEAT_XSAVE] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
NULL, NULL, NULL, NULL,
@@ -1057,12 +1097,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 0xd,
- .cpuid_needs_ecx = true, .cpuid_ecx = 1,
- .cpuid_reg = R_EAX,
+ .cpuid = {
+ .eax = 0xd,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
.tcg_features = TCG_XSAVE_FEATURES,
},
[FEAT_6_EAX] = {
+ .type = CPUID_FEATURE_WORD,
.feat_names = {
NULL, NULL, "arat", NULL,
NULL, NULL, NULL, NULL,
@@ -1073,13 +1116,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
- .cpuid_eax = 6, .cpuid_reg = R_EAX,
+ .cpuid = { .eax = 6, .reg = R_EAX, },
.tcg_features = TCG_6_EAX_FEATURES,
},
[FEAT_XSAVE_COMP_LO] = {
- .cpuid_eax = 0xD,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EAX,
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EAX,
+ },
.tcg_features = ~0U,
.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
@@ -1087,9 +1133,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
XSTATE_PKRU_MASK,
},
[FEAT_XSAVE_COMP_HI] = {
- .cpuid_eax = 0xD,
- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
- .cpuid_reg = R_EDX,
+ .type = CPUID_FEATURE_WORD,
+ .cpuid = {
+ .eax = 0xD,
+ .needs_ecx = true, .ecx = 0,
+ .reg = R_EDX,
+ },
.tcg_features = ~0U,
},
};
@@ -2975,21 +3024,41 @@ static const TypeInfo host_x86_cpu_type_info = {
#endif
+static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
+{
+ assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
+
+ switch (f->type) {
+ case CPUID_FEATURE_WORD:
+ {
+ const char *reg = get_register_name_32(f->cpuid.reg);
+ assert(reg);
+ return g_strdup_printf("CPUID.%02XH:%s",
+ f->cpuid.eax, reg);
+ }
+ case MSR_FEATURE_WORD:
+ return g_strdup_printf("MSR(%02XH)",
+ f->msr.index);
+ }
+
+ return NULL;
+}
+
static void report_unavailable_features(FeatureWord w, uint32_t mask)
{
FeatureWordInfo *f = &feature_word_info[w];
int i;
+ char *feat_word_str;
for (i = 0; i < 32; ++i) {
if ((1UL << i) & mask) {
- const char *reg = get_register_name_32(f->cpuid_reg);
- assert(reg);
- warn_report("%s doesn't support requested feature: "
- "CPUID.%02XH:%s%s%s [bit %d]",
+ feat_word_str = feature_word_description(f, i);
+ warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
accel_uses_host_cpuid() ? "host" : "TCG",
- f->cpuid_eax, reg,
+ feat_word_str,
f->feat_names[i] ? "." : "",
f->feat_names[i] ? f->feat_names[i] : "", i);
+ g_free(feat_word_str);
}
}
}
@@ -3233,11 +3302,18 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *wi = &feature_word_info[w];
+ /*
+ * We didn't have MSR features when "feature-words" was
+ * introduced. Therefore skipped other type entries.
+ */
+ if (wi->type != CPUID_FEATURE_WORD) {
+ continue;
+ }
X86CPUFeatureWordInfo *qwi = &word_infos[w];
- qwi->cpuid_input_eax = wi->cpuid_eax;
- qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
- qwi->cpuid_input_ecx = wi->cpuid_ecx;
- qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
+ qwi->cpuid_input_eax = wi->cpuid.eax;
+ qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
+ qwi->cpuid_input_ecx = wi->cpuid.ecx;
+ qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
qwi->features = array[w];
/* List will be in reverse order, but order shouldn't matter */
@@ -3610,16 +3686,26 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only)
{
FeatureWordInfo *wi = &feature_word_info[w];
- uint32_t r;
+ uint32_t r = 0;
if (kvm_enabled()) {
- r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
- wi->cpuid_ecx,
- wi->cpuid_reg);
+ switch (wi->type) {
+ case CPUID_FEATURE_WORD:
+ r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
+ wi->cpuid.ecx,
+ wi->cpuid.reg);
+ break;
+ case MSR_FEATURE_WORD:
+ r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
+ break;
+ }
} else if (hvf_enabled()) {
- r = hvf_get_supported_cpuid(wi->cpuid_eax,
- wi->cpuid_ecx,
- wi->cpuid_reg);
+ if (wi->type != CPUID_FEATURE_WORD) {
+ return 0;
+ }
+ r = hvf_get_supported_cpuid(wi->cpuid.eax,
+ wi->cpuid.ecx,
+ wi->cpuid.reg);
} else if (tcg_enabled()) {
r = wi->tcg_features;
} else {
@@ -4680,9 +4766,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
{
CPUX86State *env = &cpu->env;
FeatureWordInfo *fi = &feature_word_info[w];
- uint32_t eax = fi->cpuid_eax;
+ uint32_t eax = fi->cpuid.eax;
uint32_t region = eax & 0xF0000000;
+ assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
if (!env->features[w]) {
return;
}
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 5/7] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo, Paolo Bonzini, Richard Henderson
From: Robert Hoo <robert.hu@linux.intel.com>
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
[ehabkost: removed automatic enabling of RSBA]
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 8 ++++++++
target/i386/cpu.c | 24 +++++++++++++++++++++++-
target/i386/kvm.c | 11 +++++++++++
3 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 663f3a5e67..ad0e0b4534 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -502,6 +502,7 @@ typedef enum FeatureWord {
FEAT_6_EAX, /* CPUID[6].EAX */
FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
+ FEAT_ARCH_CAPABILITIES,
FEATURE_WORDS,
} FeatureWord;
@@ -730,6 +731,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
+/* MSR Feature Bits */
+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
+#define MSR_ARCH_CAP_RSBA (1U << 2)
+#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
+
#ifndef HYPERV_SPINLOCK_NEVER_RETRY
#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 989a71ac9a..e92117a476 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1141,6 +1141,27 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = ~0U,
},
+ /*Below are MSR exposed features*/
+ [FEAT_ARCH_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
+ "ssb-no", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_ARCH_CAPABILITIES,
+ .cpuid_dep = {
+ FEAT_7_0_EDX,
+ CPUID_7_0_EDX_ARCH_CAPABILITIES
+ }
+ },
+ },
};
typedef struct X86RegisterInfo32 {
@@ -3696,7 +3717,8 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
wi->cpuid.reg);
break;
case MSR_FEATURE_WORD:
- r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
+ r = kvm_arch_get_supported_msr_feature(kvm_state,
+ wi->msr.index);
break;
}
} else if (hvf_enabled()) {
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 161fc38397..796a049a0d 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1975,6 +1975,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
#endif
+ /* If host supports feature MSR, write down. */
+ if (kvm_feature_msrs) {
+ int i;
+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
+ if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
+ env->features[FEAT_ARCH_CAPABILITIES]);
+ break;
+ }
+ }
+
/*
* The following MSRs have side effects on the guest or are too heavy
* for normal writeback. Limit them to reset or full state updates.
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 5/7] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti,
Robert Hoo
From: Robert Hoo <robert.hu@linux.intel.com>
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
[ehabkost: removed automatic enabling of RSBA]
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 8 ++++++++
target/i386/cpu.c | 24 +++++++++++++++++++++++-
target/i386/kvm.c | 11 +++++++++++
3 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 663f3a5e67..ad0e0b4534 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -502,6 +502,7 @@ typedef enum FeatureWord {
FEAT_6_EAX, /* CPUID[6].EAX */
FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
+ FEAT_ARCH_CAPABILITIES,
FEATURE_WORDS,
} FeatureWord;
@@ -730,6 +731,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
+/* MSR Feature Bits */
+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
+#define MSR_ARCH_CAP_RSBA (1U << 2)
+#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
+
#ifndef HYPERV_SPINLOCK_NEVER_RETRY
#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
#endif
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 989a71ac9a..e92117a476 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1141,6 +1141,27 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = ~0U,
},
+ /*Below are MSR exposed features*/
+ [FEAT_ARCH_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
+ "ssb-no", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_ARCH_CAPABILITIES,
+ .cpuid_dep = {
+ FEAT_7_0_EDX,
+ CPUID_7_0_EDX_ARCH_CAPABILITIES
+ }
+ },
+ },
};
typedef struct X86RegisterInfo32 {
@@ -3696,7 +3717,8 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
wi->cpuid.reg);
break;
case MSR_FEATURE_WORD:
- r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
+ r = kvm_arch_get_supported_msr_feature(kvm_state,
+ wi->msr.index);
break;
}
} else if (hvf_enabled()) {
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 161fc38397..796a049a0d 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1975,6 +1975,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
#endif
+ /* If host supports feature MSR, write down. */
+ if (kvm_feature_msrs) {
+ int i;
+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
+ if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
+ env->features[FEAT_ARCH_CAPABILITIES]);
+ break;
+ }
+ }
+
/*
* The following MSRs have side effects on the guest or are too heavy
* for normal writeback. Limit them to reset or full state updates.
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 6/7] i386: Add new model of Cascadelake-Server
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Tao Xu,
Marcelo Tosatti, Paolo Bonzini, Richard Henderson
From: Tao Xu <tao3.xu@intel.com>
New CPU models mostly inherit features from ancestor Skylake-Server,
while addin new features: AVX512_VNNI, Intel PT.
SSBD support for speculative execution
side channel mitigations.
Note:
On Cascadelake, some capabilities (RDCL_NO, IBRS_ALL, RSBA,
SKIP_L1DFL_VMENTRY and SSB_NO) are enumerated by MSR.
These features rely on MSR based feature support patch.
Will be added later after that patch's in.
http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00074.html
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20180919031122.28487-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e92117a476..9f2e93bdae 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2456,6 +2456,60 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
},
+ {
+ .name = "Cascadelake-Server",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 85,
+ .stepping = 5,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_INTEL_PT,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
+ CPUID_7_0_ECX_AVX512VNNI,
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+ /* Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x80000008,
+ .model_id = "Intel Xeon Processor (Cascadelake)",
+ },
{
.name = "Icelake-Client",
.level = 0xd,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 6/7] i386: Add new model of Cascadelake-Server
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti, Tao Xu
From: Tao Xu <tao3.xu@intel.com>
New CPU models mostly inherit features from ancestor Skylake-Server,
while addin new features: AVX512_VNNI, Intel PT.
SSBD support for speculative execution
side channel mitigations.
Note:
On Cascadelake, some capabilities (RDCL_NO, IBRS_ALL, RSBA,
SKIP_L1DFL_VMENTRY and SSB_NO) are enumerated by MSR.
These features rely on MSR based feature support patch.
Will be added later after that patch's in.
http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00074.html
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20180919031122.28487-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e92117a476..9f2e93bdae 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2456,6 +2456,60 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake, IBRS)",
},
+ {
+ .name = "Cascadelake-Server",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 85,
+ .stepping = 5,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_INTEL_PT,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
+ CPUID_7_0_ECX_AVX512VNNI,
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+ /* Missing: XSAVES (not supported by some Linux versions,
+ * including v4.1 to v4.12).
+ * KVM doesn't yet expose any XSAVES state save component,
+ * and the only one defined in Skylake (processor tracing)
+ * probably will block migration anyway.
+ */
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .xlevel = 0x80000008,
+ .model_id = "Intel Xeon Processor (Cascadelake)",
+ },
{
.name = "Icelake-Client",
.level = 0xd,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 7/7] i386: Add PKU on Skylake-Server CPU model
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 0:45 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Eduardo Habkost, kvm, Michael S. Tsirkin, Tao Xu,
Marcelo Tosatti, Paolo Bonzini, Richard Henderson
From: Tao Xu <tao3.xu@intel.com>
As the release document ref below link (page 13):
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
PKU is supported in Skylake Server (Only Server) and later, and
on Intel(R) Xeon(R) Processor Scalable Family. So PKU is supposed
to be in Skylake-Server CPU model. And PKU's CPUID has been
exposed to QEMU. But PKU can't be find in Skylake-Server CPU
model in the code. So this patch will fix this issue in
Skylake-Server CPU model.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <5014b57f834dcfa8fd3781504d98dcf063d54fde.1540801392.git.tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/i386/pc.h | 10 +++++++++-
target/i386/cpu.c | 4 ++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index dfe6746692..136fe497b6 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -300,7 +300,15 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = TYPE_X86_CPU,\
.property = "x-hv-synic-kvm-only",\
.value = "on",\
- }
+ },{\
+ .driver = "Skylake-Server" "-" TYPE_X86_CPU,\
+ .property = "pku",\
+ .value = "off",\
+ },{\
+ .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\
+ .property = "pku",\
+ .value = "off",\
+ },
#define PC_COMPAT_2_12 \
HW_COMPAT_2_12 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9f2e93bdae..af7e9f09cc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2392,6 +2392,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
@@ -2442,6 +2444,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [Qemu-devel] [PULL 7/7] i386: Add PKU on Skylake-Server CPU model
@ 2018-10-31 0:45 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 0:45 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Eduardo Habkost, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti, Tao Xu
From: Tao Xu <tao3.xu@intel.com>
As the release document ref below link (page 13):
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
PKU is supported in Skylake Server (Only Server) and later, and
on Intel(R) Xeon(R) Processor Scalable Family. So PKU is supposed
to be in Skylake-Server CPU model. And PKU's CPUID has been
exposed to QEMU. But PKU can't be find in Skylake-Server CPU
model in the code. So this patch will fix this issue in
Skylake-Server CPU model.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <5014b57f834dcfa8fd3781504d98dcf063d54fde.1540801392.git.tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/i386/pc.h | 10 +++++++++-
target/i386/cpu.c | 4 ++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index dfe6746692..136fe497b6 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -300,7 +300,15 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = TYPE_X86_CPU,\
.property = "x-hv-synic-kvm-only",\
.value = "on",\
- }
+ },{\
+ .driver = "Skylake-Server" "-" TYPE_X86_CPU,\
+ .property = "pku",\
+ .value = "off",\
+ },{\
+ .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\
+ .property = "pku",\
+ .value = "off",\
+ },
#define PC_COMPAT_2_12 \
HW_COMPAT_2_12 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9f2e93bdae..af7e9f09cc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2392,6 +2392,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
@@ -2442,6 +2444,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_PKU,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.12).
* KVM doesn't yet expose any XSAVES state save component,
--
2.18.0.rc1.1.g3f1ff2140
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PULL 4/7] x86: Data structure changes to support MSR based features
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 13:24 ` Eric Blake
-1 siblings, 0 replies; 24+ messages in thread
From: Eric Blake @ 2018-10-31 13:24 UTC (permalink / raw)
To: Eduardo Habkost, Peter Maydell, qemu-devel
Cc: kvm, Michael S. Tsirkin, Marcelo Tosatti, Robert Hoo,
Paolo Bonzini, Richard Henderson
On 10/30/18 7:45 PM, Eduardo Habkost wrote:
> From: Robert Hoo <robert.hu@linux.intel.com>
>
> Add FeatureWordType indicator in struct FeatureWordInfo.
> Change feature_word_info[] accordingly.
> Change existing functions that refer to feature_word_info[] accordingly.
>
> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
> [ehabkost: fixed hvf_enabled() case]
Eduardo, this is missing your S-o-b, which is odd for a pull request.
> ---
> target/i386/cpu.c | 197 +++++++++++++++++++++++++++++++++-------------
> 1 file changed, 142 insertions(+), 55 deletions(-)
>
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 4/7] x86: Data structure changes to support MSR based features
@ 2018-10-31 13:24 ` Eric Blake
0 siblings, 0 replies; 24+ messages in thread
From: Eric Blake @ 2018-10-31 13:24 UTC (permalink / raw)
To: Eduardo Habkost, Peter Maydell, qemu-devel
Cc: kvm, Michael S. Tsirkin, Marcelo Tosatti, Robert Hoo,
Paolo Bonzini, Richard Henderson
On 10/30/18 7:45 PM, Eduardo Habkost wrote:
> From: Robert Hoo <robert.hu@linux.intel.com>
>
> Add FeatureWordType indicator in struct FeatureWordInfo.
> Change feature_word_info[] accordingly.
> Change existing functions that refer to feature_word_info[] accordingly.
>
> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
> [ehabkost: fixed hvf_enabled() case]
Eduardo, this is missing your S-o-b, which is odd for a pull request.
> ---
> target/i386/cpu.c | 197 +++++++++++++++++++++++++++++++++-------------
> 1 file changed, 142 insertions(+), 55 deletions(-)
>
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/7] x86 queue, 2018-10-30
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
@ 2018-10-31 14:07 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 14:07 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: kvm, Michael S. Tsirkin, Marcelo Tosatti, Paolo Bonzini,
Richard Henderson
Peter, my S-o-b line was missing on some commits, I have just pushed a new
x86-next-pull-request tag, with exactly the same tree. Sorry for the noise.
Thanks to Eric Blake for reporting the issue.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
On Tue, Oct 30, 2018 at 09:45:43PM -0300, Eduardo Habkost wrote:
> Sorry for submitting this at the last minute.
>
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
>
> for you to fetch changes up to c4fc3c4d9b456a145e8f3fd75496e1dacb578473:
>
> i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
>
> ----------------------------------------------------------------
> x86 queue, 2018-10-30
>
> * MSR-based feature support for
> MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
> * Cascadelake-Server CPU model (Tao Xu)
> * Add PKU on Skylake-Server CPU model (Tao Xu)
> * Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
> * Remove dead code (Peter Maydell)
>
> ----------------------------------------------------------------
>
> Peter Maydell (1):
> target/i386: Remove #ifdeffed-out icebp debugging hack
>
> Robert Hoo (3):
> kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
> system ioctl
> x86: Data structure changes to support MSR based features
> x86: define a new MSR based feature word --
> FEATURE_WORDS_ARCH_CAPABILITIES
>
> Sebastian Andrzej Siewior (1):
> i386: correct cpu_x86_cpuid(0xd)
>
> Tao Xu (2):
> i386: Add new model of Cascadelake-Server
> i386: Add PKU on Skylake-Server CPU model
>
> include/hw/i386/pc.h | 10 +-
> include/sysemu/kvm.h | 2 +
> target/i386/cpu.h | 8 ++
> target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
> target/i386/kvm.c | 91 +++++++++++++
> target/i386/translate.c | 6 -
> 6 files changed, 333 insertions(+), 63 deletions(-)
>
> --
> 2.18.0.rc1.1.g3f1ff2140
>
--
Eduardo
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/7] x86 queue, 2018-10-30
@ 2018-10-31 14:07 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 14:07 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
Cc: Paolo Bonzini, kvm, Marcel Apfelbaum, Richard Henderson,
Michael S. Tsirkin, Marcelo Tosatti, Eric Blake
Peter, my S-o-b line was missing on some commits, I have just pushed a new
x86-next-pull-request tag, with exactly the same tree. Sorry for the noise.
Thanks to Eric Blake for reporting the issue.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
On Tue, Oct 30, 2018 at 09:45:43PM -0300, Eduardo Habkost wrote:
> Sorry for submitting this at the last minute.
>
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
>
> for you to fetch changes up to c4fc3c4d9b456a145e8f3fd75496e1dacb578473:
>
> i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
>
> ----------------------------------------------------------------
> x86 queue, 2018-10-30
>
> * MSR-based feature support for
> MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
> * Cascadelake-Server CPU model (Tao Xu)
> * Add PKU on Skylake-Server CPU model (Tao Xu)
> * Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
> * Remove dead code (Peter Maydell)
>
> ----------------------------------------------------------------
>
> Peter Maydell (1):
> target/i386: Remove #ifdeffed-out icebp debugging hack
>
> Robert Hoo (3):
> kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
> system ioctl
> x86: Data structure changes to support MSR based features
> x86: define a new MSR based feature word --
> FEATURE_WORDS_ARCH_CAPABILITIES
>
> Sebastian Andrzej Siewior (1):
> i386: correct cpu_x86_cpuid(0xd)
>
> Tao Xu (2):
> i386: Add new model of Cascadelake-Server
> i386: Add PKU on Skylake-Server CPU model
>
> include/hw/i386/pc.h | 10 +-
> include/sysemu/kvm.h | 2 +
> target/i386/cpu.h | 8 ++
> target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
> target/i386/kvm.c | 91 +++++++++++++
> target/i386/translate.c | 6 -
> 6 files changed, 333 insertions(+), 63 deletions(-)
>
> --
> 2.18.0.rc1.1.g3f1ff2140
>
--
Eduardo
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 4/7] x86: Data structure changes to support MSR based features
2018-10-31 13:24 ` [Qemu-devel] " Eric Blake
@ 2018-10-31 14:08 ` Eduardo Habkost
-1 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 14:08 UTC (permalink / raw)
To: Eric Blake
Cc: Peter Maydell, kvm, Michael S. Tsirkin, Marcelo Tosatti,
qemu-devel, Robert Hoo, Paolo Bonzini, Richard Henderson
On Wed, Oct 31, 2018 at 08:24:10AM -0500, Eric Blake wrote:
> On 10/30/18 7:45 PM, Eduardo Habkost wrote:
> > From: Robert Hoo <robert.hu@linux.intel.com>
> >
> > Add FeatureWordType indicator in struct FeatureWordInfo.
> > Change feature_word_info[] accordingly.
> > Change existing functions that refer to feature_word_info[] accordingly.
> >
> > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> > Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
> > [ehabkost: fixed hvf_enabled() case]
>
> Eduardo, this is missing your S-o-b, which is odd for a pull request.
Ouch, my mistake. I have just pushed a new tag with the same
tree.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
--
Eduardo
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 4/7] x86: Data structure changes to support MSR based features
@ 2018-10-31 14:08 ` Eduardo Habkost
0 siblings, 0 replies; 24+ messages in thread
From: Eduardo Habkost @ 2018-10-31 14:08 UTC (permalink / raw)
To: Eric Blake
Cc: Peter Maydell, qemu-devel, kvm, Michael S. Tsirkin,
Marcelo Tosatti, Robert Hoo, Paolo Bonzini, Richard Henderson
On Wed, Oct 31, 2018 at 08:24:10AM -0500, Eric Blake wrote:
> On 10/30/18 7:45 PM, Eduardo Habkost wrote:
> > From: Robert Hoo <robert.hu@linux.intel.com>
> >
> > Add FeatureWordType indicator in struct FeatureWordInfo.
> > Change feature_word_info[] accordingly.
> > Change existing functions that refer to feature_word_info[] accordingly.
> >
> > Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> > Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
> > [ehabkost: fixed hvf_enabled() case]
>
> Eduardo, this is missing your S-o-b, which is odd for a pull request.
Ouch, my mistake. I have just pushed a new tag with the same
tree.
The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
----------------------------------------------------------------
x86 queue, 2018-10-30
* MSR-based feature support for
MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)
----------------------------------------------------------------
Peter Maydell (1):
target/i386: Remove #ifdeffed-out icebp debugging hack
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
x86: define a new MSR based feature word --
FEATURE_WORDS_ARCH_CAPABILITIES
Sebastian Andrzej Siewior (1):
i386: correct cpu_x86_cpuid(0xd)
Tao Xu (2):
i386: Add new model of Cascadelake-Server
i386: Add PKU on Skylake-Server CPU model
include/hw/i386/pc.h | 10 +-
include/sysemu/kvm.h | 2 +
target/i386/cpu.h | 8 ++
target/i386/cpu.c | 279 ++++++++++++++++++++++++++++++++--------
target/i386/kvm.c | 91 +++++++++++++
target/i386/translate.c | 6 -
6 files changed, 333 insertions(+), 63 deletions(-)
--
2.18.0.rc1.1.g3f1ff2140
--
Eduardo
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/7] x86 queue, 2018-10-30
2018-10-31 14:07 ` [Qemu-devel] " Eduardo Habkost
@ 2018-11-01 17:25 ` Peter Maydell
-1 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2018-11-01 17:25 UTC (permalink / raw)
To: Eduardo Habkost
Cc: kvm-devel, Michael S. Tsirkin, Marcelo Tosatti, QEMU Developers,
Paolo Bonzini, Richard Henderson
On 31 October 2018 at 14:07, Eduardo Habkost <ehabkost@redhat.com> wrote:
> Peter, my S-o-b line was missing on some commits, I have just pushed a new
> x86-next-pull-request tag, with exactly the same tree. Sorry for the noise.
>
> Thanks to Eric Blake for reporting the issue.
>
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
>
> for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
>
> i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
>
> ----------------------------------------------------------------
> x86 queue, 2018-10-30
>
> * MSR-based feature support for
> MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
> * Cascadelake-Server CPU model (Tao Xu)
> * Add PKU on Skylake-Server CPU model (Tao Xu)
> * Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
> * Remove dead code (Peter Maydell)
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PULL 0/7] x86 queue, 2018-10-30
@ 2018-11-01 17:25 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2018-11-01 17:25 UTC (permalink / raw)
To: Eduardo Habkost
Cc: QEMU Developers, Paolo Bonzini, kvm-devel, Marcel Apfelbaum,
Richard Henderson, Michael S. Tsirkin, Marcelo Tosatti,
Eric Blake
On 31 October 2018 at 14:07, Eduardo Habkost <ehabkost@redhat.com> wrote:
> Peter, my S-o-b line was missing on some commits, I have just pushed a new
> x86-next-pull-request tag, with exactly the same tree. Sorry for the noise.
>
> Thanks to Eric Blake for reporting the issue.
>
> The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging (2018-10-30 15:49:55 +0000)
>
> are available in the Git repository at:
>
> git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
>
> for you to fetch changes up to 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f:
>
> i386: Add PKU on Skylake-Server CPU model (2018-10-30 21:14:43 -0300)
>
> ----------------------------------------------------------------
> x86 queue, 2018-10-30
>
> * MSR-based feature support for
> MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
> * Cascadelake-Server CPU model (Tao Xu)
> * Add PKU on Skylake-Server CPU model (Tao Xu)
> * Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
> * Remove dead code (Peter Maydell)
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2018-11-01 17:26 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-31 0:45 [PULL 0/7] x86 queue, 2018-10-30 Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 1/7] i386: correct cpu_x86_cpuid(0xd) Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 2/7] target/i386: Remove #ifdeffed-out icebp debugging hack Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 3/7] kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 4/7] x86: Data structure changes to support MSR based features Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 13:24 ` Eric Blake
2018-10-31 13:24 ` [Qemu-devel] " Eric Blake
2018-10-31 14:08 ` Eduardo Habkost
2018-10-31 14:08 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 5/7] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 6/7] i386: Add new model of Cascadelake-Server Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 0:45 ` [PULL 7/7] i386: Add PKU on Skylake-Server CPU model Eduardo Habkost
2018-10-31 0:45 ` [Qemu-devel] " Eduardo Habkost
2018-10-31 14:07 ` [PULL 0/7] x86 queue, 2018-10-30 Eduardo Habkost
2018-10-31 14:07 ` [Qemu-devel] " Eduardo Habkost
2018-11-01 17:25 ` Peter Maydell
2018-11-01 17:25 ` [Qemu-devel] " Peter Maydell
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