* [v6 0/2] Enable Plane Input CSC for ICL
@ 2018-10-31 13:35 Uma Shankar
2018-10-31 13:35 ` [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers Uma Shankar
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Uma Shankar @ 2018-10-31 13:35 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
This patch series enables plane input csc feature for
ICL. This is needed for YUV to RGB conversion on bottom
3 planes on ICL, other planes are handled in the legacy
way using fixed function hardware.
This series enables color conversion for Full Range YUV data,
limited range handling will be done as a separate patch.
v2: Separated the patch into 2 parts as per Maarten's comments.
Addressed Ville and Maarten's review comment.
v3: Redesigned the register macro definition as per Matt's comment.
Addressed Maarten's review comment.
v4: Added support for Limited Range Color Handling.
v5: Fixed Matt and Maarten's review comments.
v6: Added human readable matrix values for YUV to RGB Conversion along
with just the bspec register values, as per Matt's suggestion.
This has been verified and tested by Maarten and the change is working
as expected.
Uma Shankar (2):
drm/i915/icl: Define Plane Input CSC Coefficient Registers
drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++
drivers/gpu/drm/i915/intel_color.c | 103 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
drivers/gpu/drm/i915/intel_drv.h | 2 +
4 files changed, 172 insertions(+), 6 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
@ 2018-10-31 13:35 ` Uma Shankar
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
` (4 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Uma Shankar @ 2018-10-31 13:35 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.
v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
v5: Renamed the register Macro as per Matt's suggestion.
v6: No Change
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69eb573..87c275c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6569,6 +6569,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
@@ -6585,6 +6586,55 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+ _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+ _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
2018-10-31 13:35 ` [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers Uma Shankar
@ 2018-10-31 13:35 ` Uma Shankar
2018-10-31 14:02 ` Ville Syrjälä
` (2 more replies)
2018-10-31 13:51 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev5) Patchwork
` (3 subsequent siblings)
5 siblings, 3 replies; 14+ messages in thread
From: Uma Shankar @ 2018-10-31 13:35 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the co-efficient values for YUV to RGB conversion
in BT709 and BT601 formats. It programs the coefficients and enables
the plane input csc unit in hardware.
This has been verified and tested by Maarten and the change is working
as expected.
v2: Addressed Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.
v3: Added individual coefficient matrix (9 values) instead of 6
register values as per Maarten's comment. Also addresed a shift
issue with B channel coefficient.
v4: Added support for Limited Range Color Handling
v5: Fixed Matt and Maarten's review comments.
v6: Added human readable matrix values for YUV to RGB Conversion along
with just the bspec register values, as per Matt's suggestion.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 103 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 122 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..6dc9075 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -57,6 +57,15 @@
#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
#define CSC_RGB_TO_YUV_BV 0x1e080000
+#define ROFF(x) (((x) & 0xffff) << 16)
+#define GOFF(x) (((x) & 0xffff) << 0)
+#define BOFF(x) (((x) & 0xffff) << 16)
+
+/* Preoffset values for YUV to RGB Conversion */
+#define PREOFF_YUV_TO_RGB_HI 0x1800
+#define PREOFF_YUV_TO_RGB_ME 0x1F00
+#define PREOFF_YUV_TO_RGB_LO 0x1800
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
return -EINVAL;
}
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ enum pipe pipe = crtc->pipe;
+ struct intel_plane *intel_plane =
+ to_intel_plane(plane_state->base.plane);
+ enum plane_id plane = intel_plane->id;
+
+ static const u16 input_csc_matrix[][9] = {
+ /*
+ * BT.601 full range YCbCr -> full range RGB
+ * The matrix required is :
+ * [1.000, 0.000, 1.371,
+ * 1.000, -0.336, -0.698,
+ * 1.000, 1.732, 0.0000]
+ */
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7AF8, 0x7800, 0x0,
+ 0x8B28, 0x7800, 0x9AC0,
+ 0x0, 0x7800, 0x7DD8,
+ },
+ /*
+ * BT.709 full range YCbCr -> full range RGB
+ * The matrix required is :
+ * [1.000, 0.000, 1.574,
+ * 1.000, -0.187, -0.468,
+ * 1.000, 1.855, 0.0000]
+ */
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7C98, 0x7800, 0x0,
+ 0x9EF8, 0x7800, 0xABF8,
+ 0x0, 0x7800, 0x7ED8,
+ },
+ };
+
+ /* Matrix for Limited Range to Full Range Conversion */
+ static const u16 input_csc_matrix_lr[][9] = {
+ /*
+ * BT.601 Limted range YCbCr -> full range RGB
+ * The matrix required is :
+ * [1.164384, 0.000, 1.596370,
+ * 1.138393, -0.382500, -0.794598,
+ * 1.138393, 1.971696, 0.0000]
+ */
+ [DRM_COLOR_YCBCR_BT601] = {
+ 0x7CC8, 0x7950, 0x0,
+ 0x8CB8, 0x7918, 0x9C40,
+ 0x0, 0x7918, 0x7FC8,
+ },
+ /*
+ * BT.709 Limited range YCbCr -> full range RGB
+ * The matrix required is :
+ * [1.164, 0.000, 1.833671,
+ * 1.138393, -0.213249, -0.532909,
+ * 1.138393, 2.112402, 0.0000]
+ */
+ [DRM_COLOR_YCBCR_BT709] = {
+ 0x7EA8, 0x7950, 0x0,
+ 0x8888, 0x7918, 0xADA8,
+ 0x0, 0x7918, 0x6870,
+ },
+ };
+ const u16 *csc;
+
+ if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
+ csc = input_csc_matrix[plane_state->base.color_encoding];
+ else
+ csc = input_csc_matrix_lr[plane_state->base.color_encoding];
+
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
+ GOFF(csc[1]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
+ GOFF(csc[4]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
+ GOFF(csc[7]));
+ I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
+
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
+ PREOFF_YUV_TO_RGB_HI);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
+ PREOFF_YUV_TO_RGB_ME);
+ I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
+ PREOFF_YUV_TO_RGB_LO);
+
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
+ I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0);
+}
+
void intel_color_init(struct drm_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fe045ab..d16a064 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 plane_color_ctl = 0;
if (INTEL_GEN(dev_priv) < 11) {
@@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv) {
- if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
- plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
- else
- plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
+ if (!icl_is_hdr_plane(plane)) {
+ if (plane_state->base.color_encoding ==
+ DRM_COLOR_YCBCR_BT709)
+ plane_color_ctl |=
+ PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
+ else
+ plane_color_ctl |=
+ PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
- if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
- plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+ if (plane_state->base.color_range ==
+ DRM_COLOR_YCBCR_FULL_RANGE)
+ plane_color_ctl |=
+ PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
+ } else {
+ icl_program_input_csc_coeff(crtc_state, plane_state);
+ plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
+ }
}
return plane_color_ctl;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index db24308..bd9e946 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
void intel_color_set_csc(struct drm_crtc_state *crtc_state);
void intel_color_load_luts(struct drm_crtc_state *crtc_state);
+void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state);
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev5)
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
2018-10-31 13:35 ` [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers Uma Shankar
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
@ 2018-10-31 13:51 ` Patchwork
2018-10-31 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-10-31 13:51 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0788076afc3f drm/i915/icl: Define Plane Input CSC Coefficient Registers
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:6602:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:6602:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#74: FILE: drivers/gpu/drm/i915/i915_reg.h:6618:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:74: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#74: FILE: drivers/gpu/drm/i915/i915_reg.h:6618:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/i915_reg.h:6634:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/i915_reg.h:6634:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
total: 0 errors, 0 warnings, 6 checks, 62 lines checked
d14aa7612d93 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Enable Plane Input CSC for ICL (rev5)
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
` (2 preceding siblings ...)
2018-10-31 13:51 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev5) Patchwork
@ 2018-10-31 13:53 ` Patchwork
2018-10-31 14:12 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-31 18:36 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-10-31 13:53 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Define Plane Input CSC Coefficient Registers
Okay!
Commit: drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/intel_color.c:105:33: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
@ 2018-10-31 14:02 ` Ville Syrjälä
2018-11-01 6:20 ` Shankar, Uma
2018-10-31 14:06 ` Ville Syrjälä
2018-10-31 17:02 ` Matt Roper
2 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2018-10-31 14:02 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> This has been verified and tested by Maarten and the change is working
> as expected.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> v6: Added human readable matrix values for YUV to RGB Conversion along
> with just the bspec register values, as per Matt's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 103 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 122 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..6dc9075 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e080000
>
> +#define ROFF(x) (((x) & 0xffff) << 16)
> +#define GOFF(x) (((x) & 0xffff) << 0)
> +#define BOFF(x) (((x) & 0xffff) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /*
> + * BT.601 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.371,
> + * 1.000, -0.336, -0.698,
> + * 1.000, 1.732, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /*
> + * BT.709 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.574,
> + * 1.000, -0.187, -0.468,
> + * 1.000, 1.855, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /*
> + * BT.601 Limted range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164384, 0.000, 1.596370,
> + * 1.138393, -0.382500, -0.794598,
> + * 1.138393, 1.971696, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /*
> + * BT.709 Limited range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164, 0.000, 1.833671,
> + * 1.138393, -0.213249, -0.532909,
> + * 1.138393, 2.112402, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x8888, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + csc = input_csc_matrix[plane_state->base.color_encoding];
> + else
> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> +
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
> + GOFF(csc[1]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
> + GOFF(csc[4]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
> + GOFF(csc[7]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
> +
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
> + PREOFF_YUV_TO_RGB_HI);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
> + PREOFF_YUV_TO_RGB_ME);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
> + PREOFF_YUV_TO_RGB_LO);
> +
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0);
> +}
> +
> void intel_color_init(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fe045ab..d16a064 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 plane_color_ctl = 0;
>
> if (INTEL_GEN(dev_priv) < 11) {
> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>
> if (fb->format->is_yuv) {
> - if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> - else
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> + if (!icl_is_hdr_plane(plane)) {
> + if (plane_state->base.color_encoding ==
> + DRM_COLOR_YCBCR_BT709)
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> + else
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>
> - if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> - plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + if (plane_state->base.color_range ==
> + DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |=
> + PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + } else {
> + icl_program_input_csc_coeff(crtc_state, plane_state);
Wrong place. This needs to be .in update_plane().
> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + }
I'd probably write this whole thing as something like:
if (is_hdr_plane() && is_yuv) {
ctl |= INPUT_CSC_ENABLE;
} else if (is_yuv) {
...
}
as that avoids the deep nesting you now have.
> }
>
> return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index db24308..bd9e946 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> void intel_color_set_csc(struct drm_crtc_state *crtc_state);
> void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
>
> /* intel_lspcon.c */
> bool lspcon_init(struct intel_digital_port *intel_dig_port);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
2018-10-31 14:02 ` Ville Syrjälä
@ 2018-10-31 14:06 ` Ville Syrjälä
2018-11-01 6:22 ` Shankar, Uma
2018-10-31 17:02 ` Matt Roper
2 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2018-10-31 14:06 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> This has been verified and tested by Maarten and the change is working
> as expected.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> v6: Added human readable matrix values for YUV to RGB Conversion along
> with just the bspec register values, as per Matt's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 103 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 122 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..6dc9075 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e080000
>
> +#define ROFF(x) (((x) & 0xffff) << 16)
> +#define GOFF(x) (((x) & 0xffff) << 0)
> +#define BOFF(x) (((x) & 0xffff) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /*
> + * BT.601 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.371,
> + * 1.000, -0.336, -0.698,
> + * 1.000, 1.732, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /*
> + * BT.709 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.574,
> + * 1.000, -0.187, -0.468,
> + * 1.000, 1.855, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /*
> + * BT.601 Limted range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164384, 0.000, 1.596370,
> + * 1.138393, -0.382500, -0.794598,
> + * 1.138393, 1.971696, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /*
> + * BT.709 Limited range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164, 0.000, 1.833671,
> + * 1.138393, -0.213249, -0.532909,
> + * 1.138393, 2.112402, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x8888, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + csc = input_csc_matrix[plane_state->base.color_encoding];
> + else
> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> +
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
> + GOFF(csc[1]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
> + GOFF(csc[4]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
> + GOFF(csc[7]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
> +
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
> + PREOFF_YUV_TO_RGB_HI);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
> + PREOFF_YUV_TO_RGB_ME);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
> + PREOFF_YUV_TO_RGB_LO);
> +
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0);
> +}
Oh and please move this function into intel_sprite.c. That way it can be
static.
> +
> void intel_color_init(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fe045ab..d16a064 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 plane_color_ctl = 0;
>
> if (INTEL_GEN(dev_priv) < 11) {
> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>
> if (fb->format->is_yuv) {
> - if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> - else
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> + if (!icl_is_hdr_plane(plane)) {
> + if (plane_state->base.color_encoding ==
> + DRM_COLOR_YCBCR_BT709)
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> + else
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>
> - if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> - plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + if (plane_state->base.color_range ==
> + DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |=
> + PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + } else {
> + icl_program_input_csc_coeff(crtc_state, plane_state);
> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + }
> }
>
> return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index db24308..bd9e946 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> void intel_color_set_csc(struct drm_crtc_state *crtc_state);
> void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
>
> /* intel_lspcon.c */
> bool lspcon_init(struct intel_digital_port *intel_dig_port);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for Enable Plane Input CSC for ICL (rev5)
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
` (3 preceding siblings ...)
2018-10-31 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-10-31 14:12 ` Patchwork
2018-10-31 18:36 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-10-31 14:12 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10666 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51463/revisions/5/mbox/
== Known issues ==
Here are the changes found in Patchwork_10666 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
==== Possible fixes ====
igt@kms_chamelium@common-hpd-after-suspend:
fi-skl-6700k2: INCOMPLETE (fdo#105524, fdo#104108, k.org#199541) -> PASS
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541
== Participating hosts (49 -> 43) ==
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5062 -> Patchwork_10666
CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10666: d14aa7612d93371216d77ae2dc684afd4550047b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d14aa7612d93 drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
0788076afc3f drm/i915/icl: Define Plane Input CSC Coefficient Registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10666/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
2018-10-31 14:02 ` Ville Syrjälä
2018-10-31 14:06 ` Ville Syrjälä
@ 2018-10-31 17:02 ` Matt Roper
2018-11-01 6:37 ` Shankar, Uma
2 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2018-10-31 17:02 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> This has been verified and tested by Maarten and the change is working
> as expected.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> v6: Added human readable matrix values for YUV to RGB Conversion along
> with just the bspec register values, as per Matt's suggestion.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 103 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 122 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..6dc9075 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e080000
>
> +#define ROFF(x) (((x) & 0xffff) << 16)
> +#define GOFF(x) (((x) & 0xffff) << 0)
> +#define BOFF(x) (((x) & 0xffff) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /*
> + * BT.601 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.371,
> + * 1.000, -0.336, -0.698,
> + * 1.000, 1.732, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /*
> + * BT.709 full range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.000, 0.000, 1.574,
> + * 1.000, -0.187, -0.468,
> + * 1.000, 1.855, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /*
> + * BT.601 Limted range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164384, 0.000, 1.596370,
> + * 1.138393, -0.382500, -0.794598,
> + * 1.138393, 1.971696, 0.0000]
> + */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /*
> + * BT.709 Limited range YCbCr -> full range RGB
> + * The matrix required is :
> + * [1.164, 0.000, 1.833671,
> + * 1.138393, -0.213249, -0.532909,
> + * 1.138393, 2.112402, 0.0000]
> + */
Did you scale the BT.709 values slightly differently than the BT.601
values above? The non-0/1 values don't seem to be exactly full*255/224
or full*255/219, but they're still close enough though that the hex
representation comes out the same for all of the values except for the
0xADA8 (which I get as 0xADA0). So double-check that, but otherwise the
patch is,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x8888, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + csc = input_csc_matrix[plane_state->base.color_encoding];
> + else
> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> +
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
> + GOFF(csc[1]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
> + GOFF(csc[4]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
> + GOFF(csc[7]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
> +
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
> + PREOFF_YUV_TO_RGB_HI);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
> + PREOFF_YUV_TO_RGB_ME);
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
> + PREOFF_YUV_TO_RGB_LO);
> +
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0);
> +}
> +
> void intel_color_init(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fe045ab..d16a064 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> u32 plane_color_ctl = 0;
>
> if (INTEL_GEN(dev_priv) < 11) {
> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>
> if (fb->format->is_yuv) {
> - if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> - else
> - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> + if (!icl_is_hdr_plane(plane)) {
> + if (plane_state->base.color_encoding ==
> + DRM_COLOR_YCBCR_BT709)
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> + else
> + plane_color_ctl |=
> + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>
> - if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> - plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + if (plane_state->base.color_range ==
> + DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_color_ctl |=
> + PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> + } else {
> + icl_program_input_csc_coeff(crtc_state, plane_state);
> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> + }
> }
>
> return plane_color_ctl;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index db24308..bd9e946 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> void intel_color_set_csc(struct drm_crtc_state *crtc_state);
> void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state);
>
> /* intel_lspcon.c */
> bool lspcon_init(struct intel_digital_port *intel_dig_port);
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.IGT: failure for Enable Plane Input CSC for ICL (rev5)
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
` (4 preceding siblings ...)
2018-10-31 14:12 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-10-31 18:36 ` Patchwork
5 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-10-31 18:36 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10666_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10666_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10666_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10666_full:
=== IGT changes ===
==== Possible regressions ====
igt@gem_exec_suspend@basic-s4-devices:
shard-snb: NOTRUN -> FAIL +1
== Known issues ==
Here are the changes found in Patchwork_10666_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411)
igt@gem_exec_faulting_reloc@normal:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) +1
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@gem_mmap@big-bo:
shard-snb: PASS -> INCOMPLETE (fdo#105411)
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
shard-skl: PASS -> FAIL (fdo#108470, fdo#107815, fdo#108228)
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL (fdo#106641)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1
igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
shard-apl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +10
igt@kms_cursor_crc@cursor-128x42-sliding:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-256x85-random:
shard-apl: PASS -> FAIL (fdo#103232) +3
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: NOTRUN -> FAIL (fdo#103232, fdo#103191)
igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
shard-glk: NOTRUN -> FAIL (fdo#105454, fdo#106509)
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-rte:
shard-apl: PASS -> DMESG-WARN (fdo#105602, fdo#103558, fdo#108131)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
shard-skl: PASS -> FAIL (fdo#107362, fdo#103191)
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
shard-apl: NOTRUN -> FAIL (fdo#108145)
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
shard-glk: NOTRUN -> FAIL (fdo#108145)
igt@kms_setmode@basic:
shard-snb: NOTRUN -> FAIL (fdo#99912)
igt@pm_rpm@system-suspend-devices:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
==== Possible fixes ====
igt@kms_color@pipe-b-degamma:
shard-apl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS
igt@kms_cursor_crc@cursor-256x85-random:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: FAIL (fdo#103232) -> PASS +4
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-snb: DMESG-WARN (fdo#102365) -> PASS
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-apl: FAIL (fdo#103166) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
igt@pm_rpm@modeset-lpsp-stress-no-wait:
shard-skl: INCOMPLETE (fdo#107807) -> PASS
==== Warnings ====
igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
shard-apl: FAIL (fdo#108145) -> DMESG-WARN (fdo#105602, fdo#103558)
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108131 https://bugs.freedesktop.org/show_bug.cgi?id=108131
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108228 https://bugs.freedesktop.org/show_bug.cgi?id=108228
fdo#108470 https://bugs.freedesktop.org/show_bug.cgi?id=108470
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5062 -> Patchwork_10666
CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10666: d14aa7612d93371216d77ae2dc684afd4550047b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10666/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 14:02 ` Ville Syrjälä
@ 2018-11-01 6:20 ` Shankar, Uma
0 siblings, 0 replies; 14+ messages in thread
From: Shankar, Uma @ 2018-11-01 6:20 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Wednesday, October 31, 2018 7:32 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
>Lankhorst, Maarten <maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to
>RGB Conversion
>
>On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
>> Plane input CSC needs to be enabled to convert frambuffers from YUV to
>> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>> have hardcoded conversion and taken care by the legacy code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> This has been verified and tested by Maarten and the change is working
>> as expected.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift issue
>> with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> v5: Fixed Matt and Maarten's review comments.
>>
>> v6: Added human readable matrix values for YUV to RGB Conversion along
>> with just the bspec register values, as per Matt's suggestion.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 103
>+++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 3 files changed, 122 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..6dc9075 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
>CSC_RGB_TO_YUV_BV
>> 0x1e080000
>>
>> +#define ROFF(x) (((x) & 0xffff) << 16)
>> +#define GOFF(x) (((x) & 0xffff) << 0)
>> +#define BOFF(x) (((x) & 0xffff) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI 0x1800
>> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
>> +#define PREOFF_YUV_TO_RGB_LO 0x1800
>> +
>> /*
>> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>> * format). This macro takes the coefficient we want transformed and
>> the @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
>> return -EINVAL;
>> }
>>
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state) {
>> + struct drm_i915_private *dev_priv =
>> + to_i915(plane_state->base.plane->dev);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + enum pipe pipe = crtc->pipe;
>> + struct intel_plane *intel_plane =
>> + to_intel_plane(plane_state->base.plane);
>> + enum plane_id plane = intel_plane->id;
>> +
>> + static const u16 input_csc_matrix[][9] = {
>> + /*
>> + * BT.601 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.371,
>> + * 1.000, -0.336, -0.698,
>> + * 1.000, 1.732, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7AF8, 0x7800, 0x0,
>> + 0x8B28, 0x7800, 0x9AC0,
>> + 0x0, 0x7800, 0x7DD8,
>> + },
>> + /*
>> + * BT.709 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.574,
>> + * 1.000, -0.187, -0.468,
>> + * 1.000, 1.855, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7C98, 0x7800, 0x0,
>> + 0x9EF8, 0x7800, 0xABF8,
>> + 0x0, 0x7800, 0x7ED8,
>> + },
>> + };
>> +
>> + /* Matrix for Limited Range to Full Range Conversion */
>> + static const u16 input_csc_matrix_lr[][9] = {
>> + /*
>> + * BT.601 Limted range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164384, 0.000, 1.596370,
>> + * 1.138393, -0.382500, -0.794598,
>> + * 1.138393, 1.971696, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7CC8, 0x7950, 0x0,
>> + 0x8CB8, 0x7918, 0x9C40,
>> + 0x0, 0x7918, 0x7FC8,
>> + },
>> + /*
>> + * BT.709 Limited range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164, 0.000, 1.833671,
>> + * 1.138393, -0.213249, -0.532909,
>> + * 1.138393, 2.112402, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7EA8, 0x7950, 0x0,
>> + 0x8888, 0x7918, 0xADA8,
>> + 0x0, 0x7918, 0x6870,
>> + },
>> + };
>> + const u16 *csc;
>> +
>> + if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> + csc = input_csc_matrix[plane_state->base.color_encoding];
>> + else
>> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
>> + GOFF(csc[1]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
>> + GOFF(csc[4]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
>> + GOFF(csc[7]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
>> + PREOFF_YUV_TO_RGB_HI);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
>> + PREOFF_YUV_TO_RGB_ME);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
>> + PREOFF_YUV_TO_RGB_LO);
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0); }
>> +
>> void intel_color_init(struct drm_crtc *crtc) {
>> struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git
>> a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index fe045ab..d16a064 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
>*crtc_state,
>> struct drm_i915_private *dev_priv =
>> to_i915(plane_state->base.plane->dev);
>> const struct drm_framebuffer *fb = plane_state->base.fb;
>> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> u32 plane_color_ctl = 0;
>>
>> if (INTEL_GEN(dev_priv) < 11) {
>> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct
>intel_crtc_state *crtc_state,
>> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>>
>> if (fb->format->is_yuv) {
>> - if (plane_state->base.color_encoding ==
>DRM_COLOR_YCBCR_BT709)
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> - else
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>> + if (!icl_is_hdr_plane(plane)) {
>> + if (plane_state->base.color_encoding ==
>> + DRM_COLOR_YCBCR_BT709)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> + else
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>
>> - if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> - plane_color_ctl |=
>PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + if (plane_state->base.color_range ==
>> + DRM_COLOR_YCBCR_FULL_RANGE)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + } else {
>> + icl_program_input_csc_coeff(crtc_state, plane_state);
>
>Wrong place. This needs to be .in update_plane().
Ok, will update this.
>> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
>> + }
>
>I'd probably write this whole thing as something like:
>
>if (is_hdr_plane() && is_yuv) {
> ctl |= INPUT_CSC_ENABLE;
>} else if (is_yuv) {
> ...
>}
>
>as that avoids the deep nesting you now have.
Yes, this is better. Will update the patch. Thanks..
>
>> }
>>
>> return plane_color_ctl;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index db24308..bd9e946 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_ int intel_color_check(struct
>> drm_crtc *crtc, struct drm_crtc_state *state); void
>> intel_color_set_csc(struct drm_crtc_state *crtc_state); void
>> intel_color_load_luts(struct drm_crtc_state *crtc_state);
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state);
>>
>> /* intel_lspcon.c */
>> bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 14:06 ` Ville Syrjälä
@ 2018-11-01 6:22 ` Shankar, Uma
2018-11-01 9:44 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Shankar, Uma @ 2018-11-01 6:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Wednesday, October 31, 2018 7:36 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
>Lankhorst, Maarten <maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to
>RGB Conversion
>
>On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
>> Plane input CSC needs to be enabled to convert frambuffers from YUV to
>> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>> have hardcoded conversion and taken care by the legacy code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> This has been verified and tested by Maarten and the change is working
>> as expected.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift issue
>> with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> v5: Fixed Matt and Maarten's review comments.
>>
>> v6: Added human readable matrix values for YUV to RGB Conversion along
>> with just the bspec register values, as per Matt's suggestion.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 103
>+++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 3 files changed, 122 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..6dc9075 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
>CSC_RGB_TO_YUV_BV
>> 0x1e080000
>>
>> +#define ROFF(x) (((x) & 0xffff) << 16)
>> +#define GOFF(x) (((x) & 0xffff) << 0)
>> +#define BOFF(x) (((x) & 0xffff) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI 0x1800
>> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
>> +#define PREOFF_YUV_TO_RGB_LO 0x1800
>> +
>> /*
>> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>> * format). This macro takes the coefficient we want transformed and
>> the @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
>> return -EINVAL;
>> }
>>
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state) {
>> + struct drm_i915_private *dev_priv =
>> + to_i915(plane_state->base.plane->dev);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + enum pipe pipe = crtc->pipe;
>> + struct intel_plane *intel_plane =
>> + to_intel_plane(plane_state->base.plane);
>> + enum plane_id plane = intel_plane->id;
>> +
>> + static const u16 input_csc_matrix[][9] = {
>> + /*
>> + * BT.601 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.371,
>> + * 1.000, -0.336, -0.698,
>> + * 1.000, 1.732, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7AF8, 0x7800, 0x0,
>> + 0x8B28, 0x7800, 0x9AC0,
>> + 0x0, 0x7800, 0x7DD8,
>> + },
>> + /*
>> + * BT.709 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.574,
>> + * 1.000, -0.187, -0.468,
>> + * 1.000, 1.855, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7C98, 0x7800, 0x0,
>> + 0x9EF8, 0x7800, 0xABF8,
>> + 0x0, 0x7800, 0x7ED8,
>> + },
>> + };
>> +
>> + /* Matrix for Limited Range to Full Range Conversion */
>> + static const u16 input_csc_matrix_lr[][9] = {
>> + /*
>> + * BT.601 Limted range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164384, 0.000, 1.596370,
>> + * 1.138393, -0.382500, -0.794598,
>> + * 1.138393, 1.971696, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7CC8, 0x7950, 0x0,
>> + 0x8CB8, 0x7918, 0x9C40,
>> + 0x0, 0x7918, 0x7FC8,
>> + },
>> + /*
>> + * BT.709 Limited range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164, 0.000, 1.833671,
>> + * 1.138393, -0.213249, -0.532909,
>> + * 1.138393, 2.112402, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7EA8, 0x7950, 0x0,
>> + 0x8888, 0x7918, 0xADA8,
>> + 0x0, 0x7918, 0x6870,
>> + },
>> + };
>> + const u16 *csc;
>> +
>> + if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> + csc = input_csc_matrix[plane_state->base.color_encoding];
>> + else
>> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
>> + GOFF(csc[1]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
>> + GOFF(csc[4]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
>> + GOFF(csc[7]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
>> + PREOFF_YUV_TO_RGB_HI);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
>> + PREOFF_YUV_TO_RGB_ME);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
>> + PREOFF_YUV_TO_RGB_LO);
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0); }
>
>Oh and please move this function into intel_sprite.c. That way it can be static.
We were trying to consolidate all the color stuff and the helper functions in
intel_color.c. Since its currently called from one place, it can be made static.
Will update the patch. Thanks.
>> +
>> void intel_color_init(struct drm_crtc *crtc) {
>> struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git
>> a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index fe045ab..d16a064 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
>*crtc_state,
>> struct drm_i915_private *dev_priv =
>> to_i915(plane_state->base.plane->dev);
>> const struct drm_framebuffer *fb = plane_state->base.fb;
>> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> u32 plane_color_ctl = 0;
>>
>> if (INTEL_GEN(dev_priv) < 11) {
>> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct
>intel_crtc_state *crtc_state,
>> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>>
>> if (fb->format->is_yuv) {
>> - if (plane_state->base.color_encoding ==
>DRM_COLOR_YCBCR_BT709)
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> - else
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>> + if (!icl_is_hdr_plane(plane)) {
>> + if (plane_state->base.color_encoding ==
>> + DRM_COLOR_YCBCR_BT709)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> + else
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>
>> - if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> - plane_color_ctl |=
>PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + if (plane_state->base.color_range ==
>> + DRM_COLOR_YCBCR_FULL_RANGE)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + } else {
>> + icl_program_input_csc_coeff(crtc_state, plane_state);
>> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
>> + }
>> }
>>
>> return plane_color_ctl;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index db24308..bd9e946 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_ int intel_color_check(struct
>> drm_crtc *crtc, struct drm_crtc_state *state); void
>> intel_color_set_csc(struct drm_crtc_state *crtc_state); void
>> intel_color_load_luts(struct drm_crtc_state *crtc_state);
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state);
>>
>> /* intel_lspcon.c */
>> bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-10-31 17:02 ` Matt Roper
@ 2018-11-01 6:37 ` Shankar, Uma
0 siblings, 0 replies; 14+ messages in thread
From: Shankar, Uma @ 2018-11-01 6:37 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Roper, Matthew D
>Sent: Wednesday, October 31, 2018 10:32 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
><maarten.lankhorst@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Sharma,
>Shashank <shashank.sharma@intel.com>
>Subject: Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB
>Conversion
>
>On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
>> Plane input CSC needs to be enabled to convert frambuffers from YUV to
>> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
>> have hardcoded conversion and taken care by the legacy code.
>>
>> This patch defines the co-efficient values for YUV to RGB conversion
>> in BT709 and BT601 formats. It programs the coefficients and enables
>> the plane input csc unit in hardware.
>>
>> This has been verified and tested by Maarten and the change is working
>> as expected.
>>
>> v2: Addressed Maarten's and Ville's review comments and added the
>> coefficients in a 2D array instead of independent Macros.
>>
>> v3: Added individual coefficient matrix (9 values) instead of 6
>> register values as per Maarten's comment. Also addresed a shift issue
>> with B channel coefficient.
>>
>> v4: Added support for Limited Range Color Handling
>>
>> v5: Fixed Matt and Maarten's review comments.
>>
>> v6: Added human readable matrix values for YUV to RGB Conversion along
>> with just the bspec register values, as per Matt's suggestion.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 103
>+++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 3 files changed, 122 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..6dc9075 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -57,6 +57,15 @@
>> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
>CSC_RGB_TO_YUV_BV
>> 0x1e080000
>>
>> +#define ROFF(x) (((x) & 0xffff) << 16)
>> +#define GOFF(x) (((x) & 0xffff) << 0)
>> +#define BOFF(x) (((x) & 0xffff) << 16)
>> +
>> +/* Preoffset values for YUV to RGB Conversion */
>> +#define PREOFF_YUV_TO_RGB_HI 0x1800
>> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
>> +#define PREOFF_YUV_TO_RGB_LO 0x1800
>> +
>> /*
>> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>> * format). This macro takes the coefficient we want transformed and
>> the @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
>> return -EINVAL;
>> }
>>
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state) {
>> + struct drm_i915_private *dev_priv =
>> + to_i915(plane_state->base.plane->dev);
>> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> + enum pipe pipe = crtc->pipe;
>> + struct intel_plane *intel_plane =
>> + to_intel_plane(plane_state->base.plane);
>> + enum plane_id plane = intel_plane->id;
>> +
>> + static const u16 input_csc_matrix[][9] = {
>> + /*
>> + * BT.601 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.371,
>> + * 1.000, -0.336, -0.698,
>> + * 1.000, 1.732, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7AF8, 0x7800, 0x0,
>> + 0x8B28, 0x7800, 0x9AC0,
>> + 0x0, 0x7800, 0x7DD8,
>> + },
>> + /*
>> + * BT.709 full range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.000, 0.000, 1.574,
>> + * 1.000, -0.187, -0.468,
>> + * 1.000, 1.855, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7C98, 0x7800, 0x0,
>> + 0x9EF8, 0x7800, 0xABF8,
>> + 0x0, 0x7800, 0x7ED8,
>> + },
>> + };
>> +
>> + /* Matrix for Limited Range to Full Range Conversion */
>> + static const u16 input_csc_matrix_lr[][9] = {
>> + /*
>> + * BT.601 Limted range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164384, 0.000, 1.596370,
>> + * 1.138393, -0.382500, -0.794598,
>> + * 1.138393, 1.971696, 0.0000]
>> + */
>> + [DRM_COLOR_YCBCR_BT601] = {
>> + 0x7CC8, 0x7950, 0x0,
>> + 0x8CB8, 0x7918, 0x9C40,
>> + 0x0, 0x7918, 0x7FC8,
>> + },
>> + /*
>> + * BT.709 Limited range YCbCr -> full range RGB
>> + * The matrix required is :
>> + * [1.164, 0.000, 1.833671,
>> + * 1.138393, -0.213249, -0.532909,
>> + * 1.138393, 2.112402, 0.0000]
>> + */
>
>Did you scale the BT.709 values slightly differently than the BT.601 values above?
>The non-0/1 values don't seem to be exactly full*255/224 or full*255/219, but
>they're still close enough though that the hex representation comes out the same
>for all of the values except for the
>0xADA8 (which I get as 0xADA0). So double-check that, but otherwise the patch
>is,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
As mentioned in earlier reply, This is due to the higher precision (-0.18732427293)
which I took for conversion. So the values will match.
Thanks a lot Matt for all your comment and review.
Regards,
Uma Shankar
>> + [DRM_COLOR_YCBCR_BT709] = {
>> + 0x7EA8, 0x7950, 0x0,
>> + 0x8888, 0x7918, 0xADA8,
>> + 0x0, 0x7918, 0x6870,
>> + },
>> + };
>> + const u16 *csc;
>> +
>> + if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> + csc = input_csc_matrix[plane_state->base.color_encoding];
>> + else
>> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
>> + GOFF(csc[1]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
>> + GOFF(csc[4]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
>> + GOFF(csc[7]));
>> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
>> + PREOFF_YUV_TO_RGB_HI);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
>> + PREOFF_YUV_TO_RGB_ME);
>> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
>> + PREOFF_YUV_TO_RGB_LO);
>> +
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
>> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0); }
>> +
>> void intel_color_init(struct drm_crtc *crtc) {
>> struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git
>> a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index fe045ab..d16a064 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
>*crtc_state,
>> struct drm_i915_private *dev_priv =
>> to_i915(plane_state->base.plane->dev);
>> const struct drm_framebuffer *fb = plane_state->base.fb;
>> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>> u32 plane_color_ctl = 0;
>>
>> if (INTEL_GEN(dev_priv) < 11) {
>> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct
>intel_crtc_state *crtc_state,
>> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
>>
>> if (fb->format->is_yuv) {
>> - if (plane_state->base.color_encoding ==
>DRM_COLOR_YCBCR_BT709)
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> - else
>> - plane_color_ctl |=
>PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>> + if (!icl_is_hdr_plane(plane)) {
>> + if (plane_state->base.color_encoding ==
>> + DRM_COLOR_YCBCR_BT709)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>> + else
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
>>
>> - if (plane_state->base.color_range ==
>DRM_COLOR_YCBCR_FULL_RANGE)
>> - plane_color_ctl |=
>PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + if (plane_state->base.color_range ==
>> + DRM_COLOR_YCBCR_FULL_RANGE)
>> + plane_color_ctl |=
>> +
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>> + } else {
>> + icl_program_input_csc_coeff(crtc_state, plane_state);
>> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
>> + }
>> }
>>
>> return plane_color_ctl;
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index db24308..bd9e946 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const
>> struct intel_crtc_state *old_crtc_ int intel_color_check(struct
>> drm_crtc *crtc, struct drm_crtc_state *state); void
>> intel_color_set_csc(struct drm_crtc_state *crtc_state); void
>> intel_color_load_luts(struct drm_crtc_state *crtc_state);
>> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
>> + const struct intel_plane_state *plane_state);
>>
>> /* intel_lspcon.c */
>> bool lspcon_init(struct intel_digital_port *intel_dig_port);
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
2018-11-01 6:22 ` Shankar, Uma
@ 2018-11-01 9:44 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2018-11-01 9:44 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
On Thu, Nov 01, 2018 at 06:22:08AM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> >Sent: Wednesday, October 31, 2018 7:36 PM
> >To: Shankar, Uma <uma.shankar@intel.com>
> >Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>;
> >Lankhorst, Maarten <maarten.lankhorst@intel.com>
> >Subject: Re: [Intel-gfx] [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to
> >RGB Conversion
> >
> >On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> >> Plane input CSC needs to be enabled to convert frambuffers from YUV to
> >> RGB. This is needed for bottom 3 planes on ICL, rest of the planes
> >> have hardcoded conversion and taken care by the legacy code.
> >>
> >> This patch defines the co-efficient values for YUV to RGB conversion
> >> in BT709 and BT601 formats. It programs the coefficients and enables
> >> the plane input csc unit in hardware.
> >>
> >> This has been verified and tested by Maarten and the change is working
> >> as expected.
> >>
> >> v2: Addressed Maarten's and Ville's review comments and added the
> >> coefficients in a 2D array instead of independent Macros.
> >>
> >> v3: Added individual coefficient matrix (9 values) instead of 6
> >> register values as per Maarten's comment. Also addresed a shift issue
> >> with B channel coefficient.
> >>
> >> v4: Added support for Limited Range Color Handling
> >>
> >> v5: Fixed Matt and Maarten's review comments.
> >>
> >> v6: Added human readable matrix values for YUV to RGB Conversion along
> >> with just the bspec register values, as per Matt's suggestion.
> >>
> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_color.c | 103
> >+++++++++++++++++++++++++++++++++++
> >> drivers/gpu/drm/i915/intel_display.c | 23 ++++++--
> >> drivers/gpu/drm/i915/intel_drv.h | 2 +
> >> 3 files changed, 122 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_color.c
> >> b/drivers/gpu/drm/i915/intel_color.c
> >> index 5127da2..6dc9075 100644
> >> --- a/drivers/gpu/drm/i915/intel_color.c
> >> +++ b/drivers/gpu/drm/i915/intel_color.c
> >> @@ -57,6 +57,15 @@
> >> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 #define
> >CSC_RGB_TO_YUV_BV
> >> 0x1e080000
> >>
> >> +#define ROFF(x) (((x) & 0xffff) << 16)
> >> +#define GOFF(x) (((x) & 0xffff) << 0)
> >> +#define BOFF(x) (((x) & 0xffff) << 16)
> >> +
> >> +/* Preoffset values for YUV to RGB Conversion */
> >> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> >> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> >> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> >> +
> >> /*
> >> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> >> * format). This macro takes the coefficient we want transformed and
> >> the @@ -643,6 +652,100 @@ int intel_color_check(struct drm_crtc *crtc,
> >> return -EINVAL;
> >> }
> >>
> >> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> >> + const struct intel_plane_state *plane_state) {
> >> + struct drm_i915_private *dev_priv =
> >> + to_i915(plane_state->base.plane->dev);
> >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >> + enum pipe pipe = crtc->pipe;
> >> + struct intel_plane *intel_plane =
> >> + to_intel_plane(plane_state->base.plane);
> >> + enum plane_id plane = intel_plane->id;
> >> +
> >> + static const u16 input_csc_matrix[][9] = {
> >> + /*
> >> + * BT.601 full range YCbCr -> full range RGB
> >> + * The matrix required is :
> >> + * [1.000, 0.000, 1.371,
> >> + * 1.000, -0.336, -0.698,
> >> + * 1.000, 1.732, 0.0000]
> >> + */
> >> + [DRM_COLOR_YCBCR_BT601] = {
> >> + 0x7AF8, 0x7800, 0x0,
> >> + 0x8B28, 0x7800, 0x9AC0,
> >> + 0x0, 0x7800, 0x7DD8,
> >> + },
> >> + /*
> >> + * BT.709 full range YCbCr -> full range RGB
> >> + * The matrix required is :
> >> + * [1.000, 0.000, 1.574,
> >> + * 1.000, -0.187, -0.468,
> >> + * 1.000, 1.855, 0.0000]
> >> + */
> >> + [DRM_COLOR_YCBCR_BT709] = {
> >> + 0x7C98, 0x7800, 0x0,
> >> + 0x9EF8, 0x7800, 0xABF8,
> >> + 0x0, 0x7800, 0x7ED8,
> >> + },
> >> + };
> >> +
> >> + /* Matrix for Limited Range to Full Range Conversion */
> >> + static const u16 input_csc_matrix_lr[][9] = {
> >> + /*
> >> + * BT.601 Limted range YCbCr -> full range RGB
> >> + * The matrix required is :
> >> + * [1.164384, 0.000, 1.596370,
> >> + * 1.138393, -0.382500, -0.794598,
> >> + * 1.138393, 1.971696, 0.0000]
> >> + */
> >> + [DRM_COLOR_YCBCR_BT601] = {
> >> + 0x7CC8, 0x7950, 0x0,
> >> + 0x8CB8, 0x7918, 0x9C40,
> >> + 0x0, 0x7918, 0x7FC8,
> >> + },
> >> + /*
> >> + * BT.709 Limited range YCbCr -> full range RGB
> >> + * The matrix required is :
> >> + * [1.164, 0.000, 1.833671,
> >> + * 1.138393, -0.213249, -0.532909,
> >> + * 1.138393, 2.112402, 0.0000]
> >> + */
> >> + [DRM_COLOR_YCBCR_BT709] = {
> >> + 0x7EA8, 0x7950, 0x0,
> >> + 0x8888, 0x7918, 0xADA8,
> >> + 0x0, 0x7918, 0x6870,
> >> + },
> >> + };
> >> + const u16 *csc;
> >> +
> >> + if (plane_state->base.color_range ==
> >DRM_COLOR_YCBCR_FULL_RANGE)
> >> + csc = input_csc_matrix[plane_state->base.color_encoding];
> >> + else
> >> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> >> +
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
> >> + GOFF(csc[1]));
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
> >> + GOFF(csc[4]));
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
> >> + GOFF(csc[7]));
> >> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
> >> +
> >> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
> >> + PREOFF_YUV_TO_RGB_HI);
> >> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 1),
> >> + PREOFF_YUV_TO_RGB_ME);
> >> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 2),
> >> + PREOFF_YUV_TO_RGB_LO);
> >> +
> >> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 0), 0x0);
> >> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 1), 0x0);
> >> + I915_WRITE(PLANE_INPUT_CSC_POSTOFF(pipe, plane, 2), 0x0); }
> >
> >Oh and please move this function into intel_sprite.c. That way it can be static.
>
> We were trying to consolidate all the color stuff and the helper functions in
> intel_color.c.
I prefer organizing based on hardware block. If there is other use for
the same matrices and whatnot those can of course be put into
intel_color.c, but the plane programming stuff should be in the plane
code IMO.
> Since its currently called from one place, it can be made static.
> Will update the patch. Thanks.
>
> >> +
> >> void intel_color_init(struct drm_crtc *crtc) {
> >> struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git
> >> a/drivers/gpu/drm/i915/intel_display.c
> >> b/drivers/gpu/drm/i915/intel_display.c
> >> index fe045ab..d16a064 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -3666,6 +3666,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
> >*crtc_state,
> >> struct drm_i915_private *dev_priv =
> >> to_i915(plane_state->base.plane->dev);
> >> const struct drm_framebuffer *fb = plane_state->base.fb;
> >> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> >> u32 plane_color_ctl = 0;
> >>
> >> if (INTEL_GEN(dev_priv) < 11) {
> >> @@ -3676,13 +3677,23 @@ u32 glk_plane_color_ctl(const struct
> >intel_crtc_state *crtc_state,
> >> plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
> >>
> >> if (fb->format->is_yuv) {
> >> - if (plane_state->base.color_encoding ==
> >DRM_COLOR_YCBCR_BT709)
> >> - plane_color_ctl |=
> >PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> >> - else
> >> - plane_color_ctl |=
> >PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> >> + if (!icl_is_hdr_plane(plane)) {
> >> + if (plane_state->base.color_encoding ==
> >> + DRM_COLOR_YCBCR_BT709)
> >> + plane_color_ctl |=
> >> +
> > PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> >> + else
> >> + plane_color_ctl |=
> >> +
> > PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> >>
> >> - if (plane_state->base.color_range ==
> >DRM_COLOR_YCBCR_FULL_RANGE)
> >> - plane_color_ctl |=
> >PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> >> + if (plane_state->base.color_range ==
> >> + DRM_COLOR_YCBCR_FULL_RANGE)
> >> + plane_color_ctl |=
> >> +
> > PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> >> + } else {
> >> + icl_program_input_csc_coeff(crtc_state, plane_state);
> >> + plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
> >> + }
> >> }
> >>
> >> return plane_color_ctl;
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >> b/drivers/gpu/drm/i915/intel_drv.h
> >> index db24308..bd9e946 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -2285,6 +2285,8 @@ int intel_plane_atomic_check_with_state(const
> >> struct intel_crtc_state *old_crtc_ int intel_color_check(struct
> >> drm_crtc *crtc, struct drm_crtc_state *state); void
> >> intel_color_set_csc(struct drm_crtc_state *crtc_state); void
> >> intel_color_load_luts(struct drm_crtc_state *crtc_state);
> >> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> >> + const struct intel_plane_state *plane_state);
> >>
> >> /* intel_lspcon.c */
> >> bool lspcon_init(struct intel_digital_port *intel_dig_port);
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-11-01 9:44 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-31 13:35 [v6 0/2] Enable Plane Input CSC for ICL Uma Shankar
2018-10-31 13:35 ` [v6 1/2] drm/i915/icl: Define Plane Input CSC Coefficient Registers Uma Shankar
2018-10-31 13:35 ` [v6 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion Uma Shankar
2018-10-31 14:02 ` Ville Syrjälä
2018-11-01 6:20 ` Shankar, Uma
2018-10-31 14:06 ` Ville Syrjälä
2018-11-01 6:22 ` Shankar, Uma
2018-11-01 9:44 ` Ville Syrjälä
2018-10-31 17:02 ` Matt Roper
2018-11-01 6:37 ` Shankar, Uma
2018-10-31 13:51 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Plane Input CSC for ICL (rev5) Patchwork
2018-10-31 13:53 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-31 14:12 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-31 18:36 ` ✗ Fi.CI.IGT: failure " Patchwork
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