[PATCH 0/1] PCI/ASPM: Proposal to add a fix for an erratum of the PI7C9X111SLB PCI-to-PCIe bridge

["Stefan Mätje" <stefan.maetje@esd.eu>]

The proposed patch fixes an erratum of the PI7C9X111SLB PCI-to-PCIe bridge in reverse mode.
It is somewhat ugly because it introduces hardware dependend code in the function 
pcie_aspm_configure_common_clock() of drivers/pci/pcie/aspm.c that is totally device agnostic
atm. Also because the code which checks for the PI7C9X111SLB bridge and then applies a workaround
is executed for all devices that are candidates for a PCIe link clock reconfiguration. But I have
no idea how to move the code out of this "hotpath".

It would be cool if the fix could be included in the current release.

To quote the errata sheet:

> In Reverse Mode, retrain Link bit is not cleared automatically; this bit
> needs to be cleared manually by configuration write after it is set.
> 
> Problem: 
> In Reverse mode, after setting Retrain Link (bit 5 of register C0h), this bit will stay on
> and PI7C9x111SL will continuously retrain until this bit is cleared by another
> Configuration Write to register C0h.
> 
> Workaround: 
> Issue another configuration write to clear Retrain Link bit after setting this bit. No delay
> is required between these two configuration write.

Regards,
	Stefan

Stefan Mätje (1):
  PCI/ASPM: Add a fix for an erratum of the PI7C9X111SLB PCI-to-PCIe
    bridge

 drivers/pci/pcie/aspm.c | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.15.0