From: Paul Kocialkowski <contact@paulk.fr>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Thierry Reding <thierry.reding@gmail.com>,
David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
linux-sunxi@googlegroups.com,
Paul Kocialkowski <contact@paulk.fr>
Subject: [PATCH v2 2/7] drm/sun4i: tcon: Support an active-low DE signal with RGB interface
Date: Thu, 1 Nov 2018 21:00:40 +0100 [thread overview]
Message-ID: <20181101200045.6078-3-contact@paulk.fr> (raw)
In-Reply-To: <20181101200045.6078-1-contact@paulk.fr>
Some panels need an active-low data enable (DE) signal for the RGB
interface. This requires flipping a bit in the TCON0 polarity register
when setting up the mode for the RGB interface.
Match the associated bus flag and use it to set the polarity inversion
bit for the DE signal when required.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++++++-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 262ffb6b0f82..0420f5c978b9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -543,6 +543,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
+ if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+ val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
+
/*
* On A20 and similar SoCs, the only way to achieve Positive Edge
* (Rising Edge), is setting dclk clock phase to 2/3(240°).
@@ -565,7 +568,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
clk_set_phase(tcon->dclk, 0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
- SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
+ SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_DE_NEGATIVE,
val);
/* Map output pins to channel 0 */
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 3d492c8be1fc..b5214d71610f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -116,6 +116,7 @@
#define SUN4I_TCON0_IO_POL_REG 0x88
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
+#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Maxime Ripard
<maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
Subject: [PATCH v2 2/7] drm/sun4i: tcon: Support an active-low DE signal with RGB interface
Date: Thu, 1 Nov 2018 21:00:40 +0100 [thread overview]
Message-ID: <20181101200045.6078-3-contact@paulk.fr> (raw)
In-Reply-To: <20181101200045.6078-1-contact-W9ppeneeCTY@public.gmane.org>
Some panels need an active-low data enable (DE) signal for the RGB
interface. This requires flipping a bit in the TCON0 polarity register
when setting up the mode for the RGB interface.
Match the associated bus flag and use it to set the polarity inversion
bit for the DE signal when required.
Signed-off-by: Paul Kocialkowski <contact-W9ppeneeCTY@public.gmane.org>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++++++-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 262ffb6b0f82..0420f5c978b9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -543,6 +543,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
+ if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+ val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
+
/*
* On A20 and similar SoCs, the only way to achieve Positive Edge
* (Rising Edge), is setting dclk clock phase to 2/3(240°).
@@ -565,7 +568,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
clk_set_phase(tcon->dclk, 0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
- SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
+ SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_DE_NEGATIVE,
val);
/* Map output pins to channel 0 */
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 3d492c8be1fc..b5214d71610f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -116,6 +116,7 @@
#define SUN4I_TCON0_IO_POL_REG 0x88
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
+#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
--
2.19.1
--
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WARNING: multiple messages have this Message-ID (diff)
From: contact@paulk.fr (Paul Kocialkowski)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/7] drm/sun4i: tcon: Support an active-low DE signal with RGB interface
Date: Thu, 1 Nov 2018 21:00:40 +0100 [thread overview]
Message-ID: <20181101200045.6078-3-contact@paulk.fr> (raw)
In-Reply-To: <20181101200045.6078-1-contact@paulk.fr>
Some panels need an active-low data enable (DE) signal for the RGB
interface. This requires flipping a bit in the TCON0 polarity register
when setting up the mode for the RGB interface.
Match the associated bus flag and use it to set the polarity inversion
bit for the DE signal when required.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++++++-
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 262ffb6b0f82..0420f5c978b9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -543,6 +543,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
+ if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+ val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
+
/*
* On A20 and similar SoCs, the only way to achieve Positive Edge
* (Rising Edge), is setting dclk clock phase to 2/3(240?).
@@ -565,7 +568,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
clk_set_phase(tcon->dclk, 0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
- SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
+ SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
+ SUN4I_TCON0_IO_POL_DE_NEGATIVE,
val);
/* Map output pins to channel 0 */
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 3d492c8be1fc..b5214d71610f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -116,6 +116,7 @@
#define SUN4I_TCON0_IO_POL_REG 0x88
#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
+#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
--
2.19.1
next prev parent reply other threads:[~2018-11-01 20:01 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-01 20:00 [PATCH v2 0/7] BL035-RGB-002 3.5" LCD sunxi DRM support Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` [PATCH v2 1/7] drm/sun4i: tcon: Pass encoder instead of using panel for RGB setup Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-05 8:59 ` Maxime Ripard
2018-11-05 8:59 ` Maxime Ripard
2018-11-05 8:59 ` Maxime Ripard
2018-11-05 10:21 ` Paul Kocialkowski
2018-11-05 10:21 ` Paul Kocialkowski
2018-11-05 10:21 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski [this message]
2018-11-01 20:00 ` [PATCH v2 2/7] drm/sun4i: tcon: Support an active-low DE signal with RGB interface Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` [PATCH v2 3/7] dt-bindings: Add vendor prefix for LeMaker Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-05 22:08 ` Rob Herring
2018-11-05 22:08 ` Rob Herring
2018-11-05 22:08 ` Rob Herring
2018-11-07 14:26 ` Paul Kocialkowski
2018-11-07 14:26 ` Paul Kocialkowski
2018-11-07 14:26 ` Paul Kocialkowski
2018-11-01 20:00 ` [PATCH v2 4/7] dt-bindings: Add bindings for the LeMaker BL035-RGB-002 LCD panel Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-05 22:09 ` Rob Herring
2018-11-05 22:09 ` Rob Herring
2018-11-05 22:09 ` Rob Herring
2018-11-01 20:00 ` [PATCH v2 5/7] drm/panel: simple: Add support for the LeMaker BL035-RGB-002 3.5" LCD Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` [PATCH NOT FOR MERGE v2 6/7] ARM: dts: sun7i: Add pinmux configuration for LCD0 RGB888 pins Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` [PATCH NOT FOR MERGE v2 7/7] ARM: dts: sun7i-a20-bananapi: Add bindings for the LeMaker 3.5" LCD Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:00 ` Paul Kocialkowski
2018-11-01 20:33 ` [PATCH v2 0/7] BL035-RGB-002 3.5" LCD sunxi DRM support Paul Kocialkowski
2018-11-01 20:33 ` Paul Kocialkowski
2018-11-01 20:33 ` Paul Kocialkowski
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