* [PATCH] drm/i915/icl: Fix DSS_CTL register names @ 2018-11-01 21:42 Anusha Srivatsa 2018-11-01 21:55 ` Manasi Navare ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Anusha Srivatsa @ 2018-11-01 21:42 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula This patch fixes the naming of the registers: s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL And also fix the hex values to lower case, to match rest of the definitions. Manasi noticed this with the patch that was merged. v2: fix "Fixes" tag. Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers") Suggested-by: Manasi Navare <manasi.d.navare@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index aef1a30ff9f6..c0e6e14fe9fa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10050,7 +10050,7 @@ enum skl_power_gate { #define OVERLAP_PIXELS(pixels) ((pixels) << 16) #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0 +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 #define DSS_CTL2 _MMIO(0x67404) #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) @@ -10058,20 +10058,20 @@ enum skl_power_gate { #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) -#define _PIPE_DSS_CTL1_PB 0x78200 -#define _PIPE_DSS_CTL1_PC 0x78400 -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _PIPE_DSS_CTL1_PB, \ - _PIPE_DSS_CTL1_PC) +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL1_PB, \ + _ICL_PIPE_DSS_CTL1_PC) #define BIG_JOINER_ENABLE (1 << 29) #define MASTER_BIG_JOINER_ENABLE (1 << 28) #define VGA_CENTERING_ENABLE (1 << 27) -#define _PIPE_DSS_CTL2_PB 0x78204 -#define _PIPE_DSS_CTL2_PC 0x78404 -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _PIPE_DSS_CTL2_PB, \ - _PIPE_DSS_CTL2_PC) +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _ICL_PIPE_DSS_CTL2_PB, \ + _ICL_PIPE_DSS_CTL2_PC) #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) #define STAP_SELECT (1 << 0) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names 2018-11-01 21:42 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa @ 2018-11-01 21:55 ` Manasi Navare 2018-11-02 5:08 ` Manasi Navare 2018-11-01 22:46 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Fix DSS_CTL register names (rev2) Patchwork 2018-11-02 4:17 ` ✓ Fi.CI.IGT: " Patchwork 2 siblings, 1 reply; 6+ messages in thread From: Manasi Navare @ 2018-11-01 21:55 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote: > This patch fixes the naming of the registers: > > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL > > And also fix the hex values to lower case, to match > rest of the definitions. > > Manasi noticed this with the patch that was merged. > > v2: fix "Fixes" tag. > > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers") > Suggested-by: Manasi Navare <manasi.d.navare@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Looks good. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index aef1a30ff9f6..c0e6e14fe9fa 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10050,7 +10050,7 @@ enum skl_power_gate { > #define OVERLAP_PIXELS(pixels) ((pixels) << 16) > #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) > #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) > -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0 > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 > > #define DSS_CTL2 _MMIO(0x67404) > #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) > @@ -10058,20 +10058,20 @@ enum skl_power_gate { > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) > > -#define _PIPE_DSS_CTL1_PB 0x78200 > -#define _PIPE_DSS_CTL1_PC 0x78400 > -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > - _PIPE_DSS_CTL1_PB, \ > - _PIPE_DSS_CTL1_PC) > +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 > +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 > +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > + _ICL_PIPE_DSS_CTL1_PB, \ > + _ICL_PIPE_DSS_CTL1_PC) > #define BIG_JOINER_ENABLE (1 << 29) > #define MASTER_BIG_JOINER_ENABLE (1 << 28) > #define VGA_CENTERING_ENABLE (1 << 27) > > -#define _PIPE_DSS_CTL2_PB 0x78204 > -#define _PIPE_DSS_CTL2_PC 0x78404 > -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > - _PIPE_DSS_CTL2_PB, \ > - _PIPE_DSS_CTL2_PC) > +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 > +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 > +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > + _ICL_PIPE_DSS_CTL2_PB, \ > + _ICL_PIPE_DSS_CTL2_PC) > > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) > #define STAP_SELECT (1 << 0) > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names 2018-11-01 21:55 ` Manasi Navare @ 2018-11-02 5:08 ` Manasi Navare 2018-11-02 7:14 ` Jani Nikula 0 siblings, 1 reply; 6+ messages in thread From: Manasi Navare @ 2018-11-02 5:08 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx Pushed to the dinq, thanks for the patch. Manasi On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote: > On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote: > > This patch fixes the naming of the registers: > > > > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL > > > > And also fix the hex values to lower case, to match > > rest of the definitions. > > > > Manasi noticed this with the patch that was merged. > > > > v2: fix "Fixes" tag. > > > > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers") > > Suggested-by: Manasi Navare <manasi.d.navare@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Manasi Navare <manasi.d.navare@intel.com> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Looks good. > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Manasi > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- > > 1 file changed, 11 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index aef1a30ff9f6..c0e6e14fe9fa 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -10050,7 +10050,7 @@ enum skl_power_gate { > > #define OVERLAP_PIXELS(pixels) ((pixels) << 16) > > #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) > > #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) > > -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0 > > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 > > > > #define DSS_CTL2 _MMIO(0x67404) > > #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) > > @@ -10058,20 +10058,20 @@ enum skl_power_gate { > > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) > > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) > > > > -#define _PIPE_DSS_CTL1_PB 0x78200 > > -#define _PIPE_DSS_CTL1_PC 0x78400 > > -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > > - _PIPE_DSS_CTL1_PB, \ > > - _PIPE_DSS_CTL1_PC) > > +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 > > +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 > > +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > > + _ICL_PIPE_DSS_CTL1_PB, \ > > + _ICL_PIPE_DSS_CTL1_PC) > > #define BIG_JOINER_ENABLE (1 << 29) > > #define MASTER_BIG_JOINER_ENABLE (1 << 28) > > #define VGA_CENTERING_ENABLE (1 << 27) > > > > -#define _PIPE_DSS_CTL2_PB 0x78204 > > -#define _PIPE_DSS_CTL2_PC 0x78404 > > -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > > - _PIPE_DSS_CTL2_PB, \ > > - _PIPE_DSS_CTL2_PC) > > +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 > > +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 > > +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ > > + _ICL_PIPE_DSS_CTL2_PB, \ > > + _ICL_PIPE_DSS_CTL2_PC) > > > > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) > > #define STAP_SELECT (1 << 0) > > -- > > 2.17.1 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names 2018-11-02 5:08 ` Manasi Navare @ 2018-11-02 7:14 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2018-11-02 7:14 UTC (permalink / raw) To: Manasi Navare, Anusha Srivatsa; +Cc: intel-gfx On Thu, 01 Nov 2018, Manasi Navare <manasi.d.navare@intel.com> wrote: > Pushed to the dinq, thanks for the patch. Thanks, sorry for the trouble. BR, Jani. > > Manasi > > On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote: >> On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote: >> > This patch fixes the naming of the registers: >> > >> > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL >> > >> > And also fix the hex values to lower case, to match >> > rest of the definitions. >> > >> > Manasi noticed this with the patch that was merged. >> > >> > v2: fix "Fixes" tag. >> > >> > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers") >> > Suggested-by: Manasi Navare <manasi.d.navare@intel.com> >> > Cc: Jani Nikula <jani.nikula@intel.com> >> > Cc: Manasi Navare <manasi.d.navare@intel.com> >> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >> >> Looks good. >> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> >> >> Manasi >> >> > --- >> > drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- >> > 1 file changed, 11 insertions(+), 11 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > index aef1a30ff9f6..c0e6e14fe9fa 100644 >> > --- a/drivers/gpu/drm/i915/i915_reg.h >> > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > @@ -10050,7 +10050,7 @@ enum skl_power_gate { >> > #define OVERLAP_PIXELS(pixels) ((pixels) << 16) >> > #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) >> > #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) >> > -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0 >> > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 >> > >> > #define DSS_CTL2 _MMIO(0x67404) >> > #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) >> > @@ -10058,20 +10058,20 @@ enum skl_power_gate { >> > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) >> > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) >> > >> > -#define _PIPE_DSS_CTL1_PB 0x78200 >> > -#define _PIPE_DSS_CTL1_PC 0x78400 >> > -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ >> > - _PIPE_DSS_CTL1_PB, \ >> > - _PIPE_DSS_CTL1_PC) >> > +#define _ICL_PIPE_DSS_CTL1_PB 0x78200 >> > +#define _ICL_PIPE_DSS_CTL1_PC 0x78400 >> > +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ >> > + _ICL_PIPE_DSS_CTL1_PB, \ >> > + _ICL_PIPE_DSS_CTL1_PC) >> > #define BIG_JOINER_ENABLE (1 << 29) >> > #define MASTER_BIG_JOINER_ENABLE (1 << 28) >> > #define VGA_CENTERING_ENABLE (1 << 27) >> > >> > -#define _PIPE_DSS_CTL2_PB 0x78204 >> > -#define _PIPE_DSS_CTL2_PC 0x78404 >> > -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ >> > - _PIPE_DSS_CTL2_PB, \ >> > - _PIPE_DSS_CTL2_PC) >> > +#define _ICL_PIPE_DSS_CTL2_PB 0x78204 >> > +#define _ICL_PIPE_DSS_CTL2_PC 0x78404 >> > +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ >> > + _ICL_PIPE_DSS_CTL2_PB, \ >> > + _ICL_PIPE_DSS_CTL2_PC) >> > >> > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) >> > #define STAP_SELECT (1 << 0) >> > -- >> > 2.17.1 >> > >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: Fix DSS_CTL register names (rev2) 2018-11-01 21:42 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa 2018-11-01 21:55 ` Manasi Navare @ 2018-11-01 22:46 ` Patchwork 2018-11-02 4:17 ` ✓ Fi.CI.IGT: " Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-11-01 22:46 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Fix DSS_CTL register names (rev2) URL : https://patchwork.freedesktop.org/series/51901/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5070 -> Patchwork_10700 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51901/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10700 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@drv_selftest@live_hangcheck: fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108315) igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107556, fdo#107774) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) ==== Possible fixes ==== igt@drv_selftest@live_evict: fi-bsw-kefka: DMESG-WARN (fdo#107709) -> PASS igt@drv_selftest@live_hangcheck: fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS igt@gem_mmap_gtt@basic-small-bo: fi-glk-dsi: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-icl-u: INCOMPLETE (fdo#107713) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709 fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (45 -> 41) == Additional (1): fi-kbl-soraka Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 == Build changes == * Linux: CI_DRM_5070 -> Patchwork_10700 CI_DRM_5070: db4461d736dcee952c0cdededcbcbed7de3ddb69 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10700: 69f1f027a3c9a011d8d0171932c81d8166eb9ef1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 69f1f027a3c9 drm/i915/icl: Fix DSS_CTL register names == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10700/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: Fix DSS_CTL register names (rev2) 2018-11-01 21:42 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa 2018-11-01 21:55 ` Manasi Navare 2018-11-01 22:46 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Fix DSS_CTL register names (rev2) Patchwork @ 2018-11-02 4:17 ` Patchwork 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-11-02 4:17 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Fix DSS_CTL register names (rev2) URL : https://patchwork.freedesktop.org/series/51901/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5070_full -> Patchwork_10700_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10700_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10700_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10700_full: === IGT changes === ==== Warnings ==== igt@kms_flip@flip-vs-expired-vblank: shard-snb: DMESG-WARN (fdo#107469) -> DMESG-FAIL == Known issues == Here are the changes found in Patchwork_10700_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@gem_exec_schedule@pi-ringfull-vebox: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-apl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-128x42-onscreen: shard-glk: PASS -> FAIL (fdo#103232) +2 shard-apl: PASS -> FAIL (fdo#103232) +2 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc: shard-glk: PASS -> DMESG-FAIL (fdo#106538) +1 igt@kms_frontbuffer_tracking@fbcpsr-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: PASS -> FAIL (fdo#107815) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: PASS -> FAIL (fdo#103166) +2 igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) igt@perf_pmu@semaphore-wait-vecs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) ==== Possible fixes ==== igt@gem_ctx_switch@basic-default-heavy: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-skl: TIMEOUT (fdo#108039) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-256x256-onscreen: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-random: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_crc@cursor-64x64-suspend: shard-skl: INCOMPLETE (fdo#104108) -> PASS +1 igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled: shard-skl: FAIL (fdo#103184) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-skl: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS +3 igt@kms_plane@plane-position-covered-pipe-c-planes: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105683 https://bugs.freedesktop.org/show_bug.cgi?id=105683 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#107469 https://bugs.freedesktop.org/show_bug.cgi?id=107469 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5070 -> Patchwork_10700 CI_DRM_5070: db4461d736dcee952c0cdededcbcbed7de3ddb69 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10700: 69f1f027a3c9a011d8d0171932c81d8166eb9ef1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10700/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-11-02 7:14 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-01 21:42 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa 2018-11-01 21:55 ` Manasi Navare 2018-11-02 5:08 ` Manasi Navare 2018-11-02 7:14 ` Jani Nikula 2018-11-01 22:46 ` ✓ Fi.CI.BAT: success for drm/i915/icl: Fix DSS_CTL register names (rev2) Patchwork 2018-11-02 4:17 ` ✓ Fi.CI.IGT: " Patchwork
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