[v3 0/7] Forward Error Correction

[v3 0/7] Forward Error Correction

[Anusha Srivatsa]

With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of bit errors in the compressed
stream.

v2: Avoid doing aux channel read everytime we check
for FEC support. Instead cache the value of the DPCD
registers, similar to the DSC implementaion (Jani)

v3: Add fec as a state to crtc. Move around the code. (Ville)

v4: s/can_fec/fec_enable; s/intel_dp_can_fec/intel_dp_supports_fec;
Add intel_dp_source supports_fec() (Ville)

v5: Reduce unwanted checks. Pass intel_encoder to fec func
instead of intel_dp. Move code around to suitable place.

This is rebased on top of Manasi's End-to-end DSC
Implementation: https://patchwork.freedesktop.org/series/47514/

Anusha Srivatsa (7):
  i915/dp/fec: Cache the FEC_CAPABLE DPCD register
  drm/dp/fec: DRM helper for Forward Error Correction
  i915/dp/fec: Check for FEC Support
  i915/dp/fec: Add can_fec to the crtc state.
  drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
  i915/dp/fec: Configure the Forward Error Correction bits.
  drm/i915/fec: Disable FEC state.

 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c  | 58 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
 include/drm/drm_dp_helper.h      |  7 ++++
 5 files changed, 136 insertions(+), 2 deletions(-)

-- 
2.17.1

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[v5 1/6] i915/dp/fec: Cache the FEC_CAPABLE DPCD register

[Anusha Srivatsa]

Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.

v2: Avoid using memset and array for a single
field. (Manasi,Jani)

v3: Print FEC CAPABILITY value. (Manasi)

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5a638503e36a..253e063e23b0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4201,6 +4201,9 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
 	 */
 	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
 
+	/* Clear fec_capable to avoid using stale values */
+	intel_dp->fec_capable = 0;
+
 	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
 	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4213,6 +4216,15 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
 		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
 			      (int)sizeof(intel_dp->dsc_dpcd),
 			      intel_dp->dsc_dpcd);
+		/* FEC is supported only on DP 1.4 */
+		if (!intel_dp_is_edp(intel_dp)) {
+			if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+					      &intel_dp->fec_capable) < 0)
+				DRM_ERROR("Failed to read FEC DPCD register\n");
+
+		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
+			      intel_dp->fec_capable);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 16bbc3768e02..9a94c6544bf5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1119,6 +1119,7 @@ struct intel_dp {
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+	u8 fec_capable;
 	/* source rates */
 	int num_source_rates;
 	const int *source_rates;
-- 
2.17.1

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[v5 2/6] drm/dp/fec: DRM helper for Forward Error Correction

[Anusha Srivatsa]

DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.

v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)

v3:
- Move the code to drm_dp_helper.c (Manasi)
- change the return type, code style changes (Gaurav)
- Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani)

v4:
- Avoid aux reads everytime, instead read cached
values of dpcd register (jani)
- Move helper to drm_dp_helper.h like other dsc
helpers.(Anusha)

v5: rebased. Change the helper parameter suitably.

Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 include/drm/drm_dp_helper.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 2649529d0d8f..b08f50b852f5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1101,6 +1101,13 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
 }
 
+/* Forward Error Correction Support on DP 1.4 */
+static inline bool
+drm_dp_sink_supports_fec(const u8 fec_capable)
+{
+	return fec_capable & DP_FEC_CAPABLE;
+}
+
 /*
  * DisplayPort AUX channel
  */
-- 
2.17.1

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[v5 3/6] i915/dp/fec: Add fec_enable to the crtc state.

[Anusha Srivatsa]

For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.

Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.

v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)

- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)

v3: Check for FEC support along with setting crtc state.

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 26 +++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 253e063e23b0..6f73923b229f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -680,7 +680,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 			dsc_slice_count =
 				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 								true);
-		} else {
+		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 			dsc_max_output_bpp =
 				intel_dp_dsc_get_output_bpp(max_link_clock,
 							    max_lanes,
@@ -2044,6 +2044,21 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 	return false;
 }
 
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum port port = dig_port->base.port;
+
+	return INTEL_GEN(dev_priv) >= 11 && port != PORT_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *pipe_config)
+{
+	return intel_dp_source_supports_fec(intel_dp) &&
+		drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 					struct intel_crtc_state *pipe_config,
 					struct link_config_limits *limits)
@@ -2055,6 +2070,8 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	u16 dsc_max_output_bpp = 0;
 	u8 dsc_dp_slice_count = 0;
 
+	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp);
+
 	if (INTEL_GEN(dev_priv) < 10 ||
 	    !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))
 		return false;
@@ -2063,6 +2080,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp))
 		return false;
 
+	/* DSC not supported if external DP sink does not support FEC */
+	if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp, pipe_config)) {
+		DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
+		pipe_config->dsc_params.compression_enable = false;
+		return false;
+	}
+
 	/* DSC not supported for DSC sink BPC < 8 */
 	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
 		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9a94c6544bf5..9f701463219b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -940,6 +940,9 @@ struct intel_crtc_state {
 		u8 slice_count;
 	} dsc_params;
 	struct drm_dsc_config dp_dsc_cfg;
+
+	/* Forward Error correction State */
+	bool fec_enable;
 };
 
 struct intel_crtc {
-- 
2.17.1

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[v5 4/6] drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION

[Anusha Srivatsa]

If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.

This has to happen before link training.

v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
   - change commit message. (Gaurav)

v3: rebased. (r-b Manasi)

v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)

v5: Move to intel_ddi.c
- Make the function static (Anusha)

Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1de0a3917d7f..05b6ffeb13be 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2889,6 +2889,20 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	}
 }
 
+static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state,
+					int state)
+{
+	int ret;
+
+	if (!crtc_state->fec_enable)
+		return;
+
+	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
@@ -2932,6 +2946,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
 					      DP_DECOMPRESSION_EN);
+	intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
 	intel_dp_start_link_train(intel_dp);
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
-- 
2.17.1

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[v5 5/6] i915/dp/fec: Configure the Forward Error Correction bits.

[Anusha Srivatsa]

If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.

The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.

v2:
- Change commit message. Configure fec state after
  link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)

v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)

v4: rebased.

v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.

v6: Pass intel_encoder, instead of intel_dp. (Ville)

Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e85f53cb9cdd..8b1753939299 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9134,6 +9134,7 @@ enum skl_power_gate {
 #define _DP_TP_CTL_B			0x64140
 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
 #define  DP_TP_CTL_ENABLE			(1 << 31)
+#define  DP_TP_CTL_FEC_ENABLE			(1 << 30)
 #define  DP_TP_CTL_MODE_SST			(0 << 27)
 #define  DP_TP_CTL_MODE_MST			(1 << 27)
 #define  DP_TP_CTL_FORCE_ACT			(1 << 25)
@@ -9152,6 +9153,7 @@ enum skl_power_gate {
 #define _DP_TP_STATUS_A			0x64044
 #define _DP_TP_STATUS_B			0x64144
 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define  DP_TP_STATUS_FEC_ENABLE_LIVE		(1 << 28)
 #define  DP_TP_STATUS_IDLE_DONE			(1 << 25)
 #define  DP_TP_STATUS_ACT_SENT			(1 << 24)
 #define  DP_TP_STATUS_MODE_STATUS_MST		(1 << 23)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 05b6ffeb13be..807edba4cd6f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2903,6 +2903,28 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
 		DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
 }
 
+static void intel_ddi_enable_fec(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	u32 val;
+
+	/* FEC support exists for DP 1.4 only */
+	if (!crtc_state->fec_enable)
+		return;
+
+	val = I915_READ(DP_TP_CTL(port));
+	val |= DP_TP_CTL_FEC_ENABLE;
+	I915_WRITE(DP_TP_CTL(port), val);
+
+	if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+				    DP_TP_STATUS_FEC_ENABLE_LIVE,
+				    DP_TP_STATUS_FEC_ENABLE_LIVE,
+				    1))
+		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
@@ -2951,6 +2973,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
 
+	intel_ddi_enable_fec(encoder, crtc_state);
+
 	icl_enable_phy_clock_gating(dig_port);
 
 	if (!is_mst)
-- 
2.17.1

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[v5 6/6] drm/i915/fec: Disable FEC state.

[Anusha Srivatsa]

Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.

v2:
- rebased.
- Add additional check for compression state. (Gaurav)

v3: rebased.

v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)

v5: Remove unnecessary checks (Ville)

Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 807edba4cd6f..5e915c771953 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2925,6 +2925,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
 }
 
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+					const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	u32 val;
+
+	if (!crtc_state->fec_enable)
+		return;
+
+	val = I915_READ(DP_TP_CTL(port));
+	val &= ~DP_TP_CTL_FEC_ENABLE;
+	I915_WRITE(DP_TP_CTL(port), val);
+	POSTING_READ(DP_TP_CTL(port));
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
@@ -3063,7 +3079,9 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 static void intel_disable_ddi_buf(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc_state *crtc_state;
 	enum port port = encoder->port;
+
 	bool wait = false;
 	u32 val;
 
@@ -3079,6 +3097,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder)
 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
 	I915_WRITE(DP_TP_CTL(port), val);
 
+	/* Disable FEC in DP Sink */
+	intel_ddi_disable_fec_state(encoder, crtc_state);
+
 	if (wait)
 		intel_wait_ddi_buf_idle(dev_priv, port);
 }
-- 
2.17.1

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✗ Fi.CI.BAT: failure for Forward Error Correction (rev5)

[Patchwork]

== Series Details ==

Series: Forward Error Correction (rev5)
URL   : https://patchwork.freedesktop.org/series/47848/
State : failure

== Summary ==

Applying: i915/dp/fec: Cache the FEC_CAPABLE DPCD register
Applying: drm/dp/fec: DRM helper for Forward Error Correction
Applying: i915/dp/fec: Add fec_enable to the crtc state.
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_dp.c).
error: could not build fake ancestor
Patch failed at 0003 i915/dp/fec: Add fec_enable to the crtc state.
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[v3 0/7] Forward Error Correction

[Anusha Srivatsa]

With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of bit errors in the compressed
stream.

v2: Avoid doing aux channel read eberytime we check
for FEC support. Instead cache the value of the DPCD
registers, similar to the DSC implementaion (Jani)

v3: Add fec as a state to crtc. Move around the code. (Ville)

v4: s/can_fec/fec_enable; s/intel_dp_can_fec/intel_de_supports_fec;
Add intel_dp_source supports_fec() (Ville)

This is rebased on top of Manasi's End-to-end DSC
Implementation: https://patchwork.freedesktop.org/series/47514/

Anusha Srivatsa (7):
  i915/dp/fec: Cache the FEC_CAPABLE DPCD register
  drm/dp/fec: DRM helper for Forward Error Correction
  i915/dp/fec: Check for FEC Support
  i915/dp/fec: Add can_fec to the crtc state.
  drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
  i915/dp/fec: Configure the Forward Error Correction bits.
  drm/i915/fec: Disable FEC state.

 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c  | 58 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
 include/drm/drm_dp_helper.h      |  7 ++++
 5 files changed, 136 insertions(+), 2 deletions(-)

-- 
2.17.1

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Re: [v3 0/7] Forward Error Correction

[Ville Syrjälä]

On Tue, Oct 30, 2018 at 05:45:10PM -0700, Anusha Srivatsa wrote:
> With Display Compression, the bit error in the pixel
> stream can turn into a significant corruption on
> the screen. The DP1.4 adds FEC - Forward Error Correction
> scheme which uses Reed-Solomon parity/correction check
> generated by the source and used by the sink to detect
> and correct small numbers of bit errors in the compressed
> stream.
> 
> v2: Avoid doing aux channel read eberytime we check
> for FEC support. Instead cache the value of the DPCD
> registers, similar to the DSC implementaion (Jani)
> 
> v3: Add fec as a state to crtc. Move around the code. (Ville)
> 
> v4: s/can_fec/fec_enable; s/intel_dp_can_fec/intel_de_supports_fec;
> Add intel_dp_source supports_fec() (Ville)

One clear thing missing is from this series is the
state readout + PIPE_CONF_CHECK

> 
> This is rebased on top of Manasi's End-to-end DSC
> Implementation: https://patchwork.freedesktop.org/series/47514/
> 
> Anusha Srivatsa (7):
>   i915/dp/fec: Cache the FEC_CAPABLE DPCD register
>   drm/dp/fec: DRM helper for Forward Error Correction
>   i915/dp/fec: Check for FEC Support
>   i915/dp/fec: Add can_fec to the crtc state.
>   drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
>   i915/dp/fec: Configure the Forward Error Correction bits.
>   drm/i915/fec: Disable FEC state.
> 
>  drivers/gpu/drm/i915/i915_reg.h  |  2 ++
>  drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c  | 58 ++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
>  include/drm/drm_dp_helper.h      |  7 ++++
>  5 files changed, 136 insertions(+), 2 deletions(-)
> 
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[v3 0/7] Forward Error Correction

[Anusha Srivatsa]

With Display Compression, the bit error in the pixel
stream can turn into a significant corruption on
the screen. The DP1.4 adds FEC - Forward Error Correction
scheme which uses Reed-Solomon parity/correction check
generated by the source and used by the sink to detect
and correct small numbers of bit errors in the compressed
stream.

v2: Avoid doing aux channel read eberytime we check
for FEC support. Instead cache the value of the DPCD
registers, similar to the DSC implementaion (Jani)

v3: Add fec as a state to crtc. Move around the code. (Ville)

This is rebased on top of Manasi's End-to-end DSC
Implementation: https://patchwork.freedesktop.org/series/47514/

Anusha Srivatsa (7):
  i915/dp/fec: Cache the FEC_CAPABLE DPCD register
  drm/dp/fec: DRM helper for Forward Error Correction
  i915/dp/fec: Check for FEC Support
  i915/dp/fec: Add can_fec to the crtc state.
  drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
  i915/dp/fec: Configure the Forward Error Correction bits.
  drm/i915/fec: Disable FEC state.

 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c  | 58 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h | 11 ++++++
 include/drm/drm_dp_helper.h      |  7 ++++
 5 files changed, 136 insertions(+), 2 deletions(-)

-- 
2.17.1

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