* [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux
@ 2018-11-02 10:54 Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 1/3] gpio: dwapb_gpio: fix binding without bank-name property Simon Goldschmidt
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Simon Goldschmidt @ 2018-11-02 10:54 UTC (permalink / raw)
To: u-boot
This series merges socfpga gen5 dts and dtsi files from linux
while keeping U-Boot behaviour. Changes in those files that need
fixing (mostly in -u-boot.dtsi board files) are:
- watchdog is now enabled
- ethernet, spi and i2c aliases removed from socfpga.dtsi
- gpio bank names not available
- mmc disabled
- qspi compatible string different
- 'clock-frequency' removed from uarts
These changes are mostly handled in changed dts files or U-Boot
specific dtsi files except for:
- change compatible to "cdns,qspi-nor" for cadence_qspi.c
- allow binding dwapb_gpio driver without "bank-name" property
(gpios still work, only access via bank name fails)
Changes in v2:
- remove old compatible "cadence,qspi" for cadence qspi driver and change
all affected dts files to the new compatible "cdns,qspi-nor"
- "cadence,qspi" to "cdns,qspi-nor" change in socfpga.dtsi moved to patch 2
Simon Goldschmidt (3):
gpio: dwapb_gpio: fix binding without bank-name property
spi: cadence_qspi: use "cdns,qspi-nor" as compatible
dts: arm: socfpga: merge gen5 devicetrees from linux
arch/arm/dts/keystone-k2g.dtsi | 2 +-
arch/arm/dts/socfpga.dtsi | 404 ++++++++++++------
arch/arm/dts/socfpga_arria10.dtsi | 2 +-
arch/arm/dts/socfpga_arria5.dtsi | 11 +-
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 56 +++
arch/arm/dts/socfpga_arria5_socdk.dts | 97 +++--
arch/arm/dts/socfpga_cyclone5.dtsi | 9 +-
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 17 +-
.../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 46 ++
.../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 69 +--
arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 16 +
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 16 +
arch/arm/dts/socfpga_cyclone5_is1.dts | 8 +
.../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 72 ++++
arch/arm/dts/socfpga_cyclone5_socdk.dts | 88 +++-
.../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 56 +++
arch/arm/dts/socfpga_cyclone5_sockit.dts | 149 +++++--
.../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 60 +++
arch/arm/dts/socfpga_cyclone5_socrates.dts | 85 ++--
arch/arm/dts/socfpga_cyclone5_sr1500.dts | 12 +
.../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 60 +++
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 222 ++++++++--
arch/arm/dts/stv0991.dts | 2 +-
doc/device-tree-bindings/spi/spi-cadence.txt | 2 +-
drivers/gpio/dwapb_gpio.c | 7 +
drivers/spi/cadence_qspi.c | 2 +-
26 files changed, 1235 insertions(+), 335 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 1/3] gpio: dwapb_gpio: fix binding without bank-name property
2018-11-02 10:54 [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
@ 2018-11-02 10:54 ` Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 2/3] spi: cadence_qspi: use "cdns, qspi-nor" as compatible Simon Goldschmidt
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Simon Goldschmidt @ 2018-11-02 10:54 UTC (permalink / raw)
To: u-boot
As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.
This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.
This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.
The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v2: None
drivers/gpio/dwapb_gpio.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 68836a7902..e55fb4ac73 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -180,6 +180,13 @@ static int gpio_dwapb_bind(struct udevice *dev)
plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
NULL);
+ if (!plat->name) {
+ /*
+ * Fall back to node name. This means accessing pins
+ * via bank name won't work.
+ */
+ plat->name = fdt_get_name(blob, node, NULL);
+ }
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 2/3] spi: cadence_qspi: use "cdns, qspi-nor" as compatible
2018-11-02 10:54 [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 1/3] gpio: dwapb_gpio: fix binding without bank-name property Simon Goldschmidt
@ 2018-11-02 10:54 ` Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 3/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
2018-11-02 13:25 ` [U-Boot] [PATCH v2 0/3] " Marek Vasut
3 siblings, 0 replies; 5+ messages in thread
From: Simon Goldschmidt @ 2018-11-02 10:54 UTC (permalink / raw)
To: u-boot
Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v2:
- remove old compatible "cadence,qspi" for cadence qspi driver and change
all affected dts files to the new compatible "cdns,qspi-nor"
arch/arm/dts/keystone-k2g.dtsi | 2 +-
arch/arm/dts/socfpga.dtsi | 2 +-
arch/arm/dts/socfpga_arria10.dtsi | 2 +-
arch/arm/dts/stv0991.dts | 2 +-
doc/device-tree-bindings/spi/spi-cadence.txt | 2 +-
drivers/spi/cadence_qspi.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index 9bcfea6d86..bbbb9874c8 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -85,7 +85,7 @@
};
qspi: qspi at 2940000 {
- compatible = "cadence,qspi";
+ compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02940000 0x1000>,
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 314449478d..9d8c4ebd15 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -646,7 +646,7 @@
};
qspi: spi at ff705000 {
- compatible = "cadence,qspi";
+ compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 46f2fd4b69..2c5249c1eb 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -748,7 +748,7 @@
};
qspi: spi at ff809000 {
- compatible = "cdns,qspi-nor", "cadence,qspi";
+ compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff809000 0x100>,
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index bceac09154..98bd5dfc70 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -26,7 +26,7 @@
};
qspi: spi at 80203000 {
- compatible = "cadence,qspi";
+ compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80203000 0x100>,
diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt
index 74c82080fc..69e02c1c4b 100644
--- a/doc/device-tree-bindings/spi/spi-cadence.txt
+++ b/doc/device-tree-bindings/spi/spi-cadence.txt
@@ -2,7 +2,7 @@ Cadence QSPI controller device tree bindings
--------------------------------------------
Required properties:
-- compatible : should be "cadence,qspi".
+- compatible : should be "cdns,qspi-nor"
- reg : 1.Physical base address and size of SPI registers map.
2. Physical base address & size of NOR Flash.
- clocks : Clock phandles (see clock bindings for details).
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 29db6fa368..11fce9c4fe 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -329,7 +329,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
};
static const struct udevice_id cadence_spi_ids[] = {
- { .compatible = "cadence,qspi" },
+ { .compatible = "cdns,qspi-nor" },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 3/3] dts: arm: socfpga: merge gen5 devicetrees from linux
2018-11-02 10:54 [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 1/3] gpio: dwapb_gpio: fix binding without bank-name property Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 2/3] spi: cadence_qspi: use "cdns, qspi-nor" as compatible Simon Goldschmidt
@ 2018-11-02 10:54 ` Simon Goldschmidt
2018-11-02 13:25 ` [U-Boot] [PATCH v2 0/3] " Marek Vasut
3 siblings, 0 replies; 5+ messages in thread
From: Simon Goldschmidt @ 2018-11-02 10:54 UTC (permalink / raw)
To: u-boot
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)
Adapt board dts files that are not in Linux to keep their old
behaviour.
Change licenses to SPDX.
(Patman warnings/errors are in 1:1 copied files from Linux)
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v2:
- "cadence,qspi" to "cdns,qspi-nor" change in socfpga.dtsi moved to patch 2
arch/arm/dts/socfpga.dtsi | 402 ++++++++++++------
arch/arm/dts/socfpga_arria5.dtsi | 11 +-
arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 56 +++
arch/arm/dts/socfpga_arria5_socdk.dts | 97 +++--
arch/arm/dts/socfpga_cyclone5.dtsi | 9 +-
arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 17 +-
.../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 46 ++
.../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 69 +--
arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 16 +
arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 16 +
arch/arm/dts/socfpga_cyclone5_is1.dts | 8 +
.../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 72 ++++
arch/arm/dts/socfpga_cyclone5_socdk.dts | 88 +++-
.../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 56 +++
arch/arm/dts/socfpga_cyclone5_sockit.dts | 149 +++++--
.../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 60 +++
arch/arm/dts/socfpga_cyclone5_socrates.dts | 85 ++--
arch/arm/dts/socfpga_cyclone5_sr1500.dts | 12 +
.../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 60 +++
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 222 ++++++++--
20 files changed, 1222 insertions(+), 329 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 9d8c4ebd15..2458d6707d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -1,9 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera <www.altera.com>
+ * Copyright (C) 2012 Altera <www.altera.com>
*/
-#include "skeleton.dtsi"
#include <dt-bindings/reset/altr,rst-mgr.h>
/ {
@@ -11,34 +10,26 @@
#size-cells = <1>;
aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
- spi0 = &qspi;
- spi1 = &spi0;
- spi2 = &spi1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "altr,socfpga-smp";
- cpu at 0 {
+ cpu0: cpu at 0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
- cpu at 1 {
+ cpu1: cpu at 1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -46,6 +37,15 @@
};
};
+ pmu: pmu at ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 176 4>, <0 177 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
intc: intc at fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -63,7 +63,7 @@
ranges;
amba {
- compatible = "arm,amba-bus";
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -87,6 +87,14 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
can0: can at ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -131,7 +139,7 @@
compatible = "fixed-clock";
};
- main_pll: main_pll {
+ main_pll: main_pll at 40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -139,7 +147,7 @@
clocks = <&osc1>;
reg = <0x40>;
- mpuclk: mpuclk {
+ mpuclk: mpuclk at 48 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -147,7 +155,7 @@
reg = <0x48>;
};
- mainclk: mainclk {
+ mainclk: mainclk at 4c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -155,29 +163,29 @@
reg = <0x4C>;
};
- dbg_base_clk: dbg_base_clk {
+ dbg_base_clk: dbg_base_clk at 50 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
+ clocks = <&main_pll>, <&osc1>;
div-reg = <0xe8 0 9>;
reg = <0x50>;
};
- main_qspi_clk: main_qspi_clk {
+ main_qspi_clk: main_qspi_clk at 54 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x54>;
};
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk at 58 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x58>;
};
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk at 5c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -185,7 +193,7 @@
};
};
- periph_pll: periph_pll {
+ periph_pll: periph_pll at 80 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -193,42 +201,42 @@
clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
reg = <0x80>;
- emac0_clk: emac0_clk {
+ emac0_clk: emac0_clk at 88 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x88>;
};
- emac1_clk: emac1_clk {
+ emac1_clk: emac1_clk at 8c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x8C>;
};
- per_qspi_clk: per_qsi_clk {
+ per_qspi_clk: per_qsi_clk at 90 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x90>;
};
- per_nand_mmc_clk: per_nand_mmc_clk {
+ per_nand_mmc_clk: per_nand_mmc_clk at 94 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x94>;
};
- per_base_clk: per_base_clk {
+ per_base_clk: per_base_clk at 98 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x98>;
};
- h2f_usr1_clk: h2f_usr1_clk {
+ h2f_usr1_clk: h2f_usr1_clk at 9c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
@@ -236,7 +244,7 @@
};
};
- sdram_pll: sdram_pll {
+ sdram_pll: sdram_pll at c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -244,28 +252,28 @@
clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
reg = <0xC0>;
- ddr_dqs_clk: ddr_dqs_clk {
+ ddr_dqs_clk: ddr_dqs_clk at c8 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xC8>;
};
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk at cc {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xCC>;
};
- ddr_dq_clk: ddr_dq_clk {
+ ddr_dq_clk: ddr_dq_clk at d0 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xD0>;
};
- h2f_usr2_clk: h2f_usr2_clk {
+ h2f_usr2_clk: h2f_usr2_clk at d4 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
@@ -312,7 +320,7 @@
l3_sp_clk: l3_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
+ clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
@@ -343,7 +351,7 @@
dbg_clk: dbg_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
+ clocks = <&dbg_at_clk>;
div-reg = <0x68 2 2>;
clk-gate = <0x60 5>;
};
@@ -446,6 +454,14 @@
clk-phase = <0 135>;
};
+ sdmmc_clk_divided: sdmmc_clk_divided {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&sdmmc_clk>;
+ clk-gate = <0xa0 8>;
+ fixed-divider = <4>;
+ };
+
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
@@ -453,10 +469,17 @@
clk-gate = <0xa0 9>;
};
+ nand_ecc_clk: nand_ecc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&nand_x_clk>;
+ clk-gate = <0xa0 9>;
+ };
+
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clocks = <&nand_x_clk>;
clk-gate = <0xa0 10>;
fixed-divider = <4>;
};
@@ -467,8 +490,58 @@
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
+
+ ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dqs_clk>;
+ clk-gate = <0xd8 0>;
+ };
+
+ ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_2x_dqs_clk>;
+ clk-gate = <0xd8 1>;
+ };
+
+ ddr_dq_clk_gate: ddr_dq_clk_gate {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&ddr_dq_clk>;
+ clk-gate = <0xd8 2>;
+ };
+
+ h2f_user2_clk: h2f_user2_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&h2f_usr2_clk>;
+ clk-gate = <0xd8 3>;
+ };
+
};
- };
+ };
+
+ fpga_bridge0: fpga_bridge at ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge at ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpgamgr0: fpgamgr at ff706000 {
+ compatible = "altr,socfpga-fpga-mgr";
+ reg = <0xff706000 0x1000
+ 0xffb90000 0x4>;
+ interrupts = <0 175 4>;
+ };
gmac0: ethernet at ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
@@ -477,12 +550,14 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
+ clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -493,60 +568,14 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
+ clocks = <&emac_1_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
- status = "disabled";
- };
-
- i2c0: i2c at ffc04000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc04000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C0_RESET>;
- reset-names = "i2c";
- interrupts = <0 158 0x4>;
- status = "disabled";
- };
-
- i2c1: i2c at ffc05000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc05000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C1_RESET>;
- reset-names = "i2c";
- interrupts = <0 159 0x4>;
- status = "disabled";
- };
-
- i2c2: i2c at ffc06000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc06000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C2_RESET>;
- reset-names = "i2c";
- interrupts = <0 160 0x4>;
- status = "disabled";
- };
-
- i2c3: i2c at ffc07000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xffc07000 0x1000>;
- clocks = <&l4_sp_clk>;
- resets = <&rst I2C3_RESET>;
- reset-names = "i2c";
- interrupts = <0 161 0x4>;
+ tx-fifo-depth = <4096>;
+ rx-fifo-depth = <4096>;
status = "disabled";
};
@@ -555,12 +584,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
porta: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -576,12 +604,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
portb: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -597,12 +624,11 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
- clocks = <&per_base_clk>;
+ clocks = <&l4_mp_clk>;
status = "disabled";
portc: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
@@ -613,15 +639,68 @@
};
};
- sdr: sdr at ffc25000 {
- compatible = "syscon";
- reg = <0xffc25000 0x1000>;
+ i2c0: i2c at ffc04000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc04000 0x1000>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 158 0x4>;
+ status = "disabled";
};
- sdramedac {
- compatible = "altr,sdram-edac";
- altr,sdr-syscon = <&sdr>;
- interrupts = <0 39 4>;
+ i2c1: i2c at ffc05000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc05000 0x1000>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 159 0x4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at ffc06000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc06000 0x1000>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 160 0x4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at ffc07000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc07000 0x1000>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 161 0x4>;
+ status = "disabled";
+ };
+
+ eccmgr: eccmgr {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc at ffd08140 {
+ compatible = "altr,socfpga-l2-ecc";
+ reg = <0xffd08140 0x4>;
+ interrupts = <0 36 1>, <0 37 1>;
+ };
+
+ ocram-ecc at ffd08144 {
+ compatible = "altr,socfpga-ocram-ecc";
+ reg = <0xffd08144 0x4>;
+ iram = <&ocram>;
+ interrupts = <0 178 1>, <0 179 1>;
+ };
};
L2: l2-cache at fffef000 {
@@ -632,36 +711,89 @@
cache-level = <2>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <2 1 1>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ arm,shared-override;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <0>;
+ arm,prefetch-offset = <7>;
+ };
+
+ l3regs at 0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
};
- mmc0: dwmmc0 at ff704000 {
+ mmc: dwmmc0 at ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 139 4>;
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
+ status = "disabled";
+ };
+
+ nand0: nand at ff900000 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "altr,socfpga-denali-nand";
+ reg = <0xff900000 0x100000>,
+ <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0x0 0x90 0x4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+ clock-names = "nand", "nand_x", "ecc";
+ status = "disabled";
+ };
+
+ ocram: sram at ffff0000 {
+ compatible = "mmio-sram";
+ reg = <0xffff0000 0x10000>;
};
qspi: spi at ff705000 {
compatible = "cdns,qspi-nor";
- #address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
+ <0xffa00000 0x1000>;
interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- ext-decoder = <0>; /* external decoder */
- num-cs = <4>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
- bus-num = <2>;
+ clocks = <&qspi_clk>;
status = "disabled";
};
+ rst: rstmgr at ffd05000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
+ };
+
+ scu: snoop-control-unit at fffec000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffec000 0x100>;
+ };
+
+ sdr: sdr at ffc25000 {
+ compatible = "altr,sdr-ctl", "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
spi0: spi at fff00000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
@@ -669,10 +801,7 @@
reg = <0xfff00000 0x1000>;
interrupts = <0 154 4>;
num-cs = <4>;
- bus-num = <0>;
- tx-dma-channel = <&pdma 16>;
- rx-dma-channel = <&pdma 17>;
- clocks = <&per_base_clk>;
+ clocks = <&spi_m_clk>;
status = "disabled";
};
@@ -681,20 +810,22 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfff01000 0x1000>;
- interrupts = <0 156 4>;
+ interrupts = <0 155 4>;
num-cs = <4>;
- bus-num = <1>;
- tx-dma-channel = <&pdma 20>;
- rx-dma-channel = <&pdma 21>;
- clocks = <&per_base_clk>;
+ clocks = <&spi_m_clk>;
status = "disabled";
};
+ sysmgr: sysmgr at ffd08000 {
+ compatible = "altr,sys-mgr", "syscon";
+ reg = <0xffd08000 0x4000>;
+ };
+
/* Local timer */
timer at fffec600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
+ interrupts = <1 13 0xf01>;
clocks = <&mpu_periph_clk>;
};
@@ -704,6 +835,8 @@
reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER0_RESET>;
+ reset-names = "timer";
};
timer1: timer1 at ffc09000 {
@@ -712,6 +845,8 @@
reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER1_RESET>;
+ reset-names = "timer";
};
timer2: timer2 at ffd00000 {
@@ -720,6 +855,8 @@
reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER0_RESET>;
+ reset-names = "timer";
};
timer3: timer3 at ffd01000 {
@@ -728,6 +865,8 @@
reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER1_RESET>;
+ reset-names = "timer";
};
uart0: serial0 at ffc02000 {
@@ -737,7 +876,9 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
- clock-frequency = <100000000>;
+ dmas = <&pdma 28>,
+ <&pdma 29>;
+ dma-names = "tx", "rx";
};
uart1: serial1 at ffc03000 {
@@ -747,16 +888,12 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
- clock-frequency = <100000000>;
+ dmas = <&pdma 30>,
+ <&pdma 31>;
+ dma-names = "tx", "rx";
};
- rst: rstmgr at ffd05000 {
- #reset-cells = <1>;
- compatible = "altr,rst-mgr";
- reg = <0xffd05000 0x1000>;
- };
-
- usbphy0: usbphy at 0 {
+ usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
@@ -768,6 +905,8 @@
interrupts = <0 125 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
+ resets = <&rst USB0_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -779,6 +918,8 @@
interrupts = <0 128 4>;
clocks = <&usb_mp_clk>;
clock-names = "otg";
+ resets = <&rst USB1_RESET>;
+ reset-names = "dwc2";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -799,10 +940,5 @@
clocks = <&osc1>;
status = "disabled";
};
-
- sysmgr: sysmgr at ffd08000 {
- compatible = "altr,sys-mgr", "syscon";
- reg = <0xffd08000 0x4000>;
- };
};
};
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
index b117383d75..22dbf07afc 100644
--- a/arch/arm/dts/socfpga_arria5.dtsi
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
/dts-v1/;
@@ -19,13 +19,10 @@
};
mmc0: dwmmc0 at ff704000 {
- num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- drvsel = <3>;
- smplsel = <0>;
};
sysmgr at ffd08000 {
@@ -33,3 +30,7 @@
};
};
};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
new file mode 100644
index 0000000000..c44d1ee2fa
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi at ff705000";
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&flash {
+ compatible = "n25q00", "spi-flash";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 6f4de2f563..90e676e701 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
#include "socfpga_arria5.dtsi"
@@ -10,22 +10,44 @@
compatible = "altr,socfpga-arria5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
- memory {
+ memory at 0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
- /* this allow the ethaddr uboot environment variable contents
- * to be added to the gmac1 device tree blob.
- */
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
ethernet0 = &gmac1;
- udc0 = &usb1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&porta 0 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 11 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&porta 17 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&porta 18 1>;
+ };
};
regulator_3_3v: 3-3-v-regulator {
@@ -34,10 +56,6 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
-
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac1 {
@@ -54,8 +72,28 @@
rxc-skew-ps = <2000>;
};
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom at 51 {
compatible = "atmel,24c32";
@@ -72,35 +110,42 @@
&mmc0 {
vmmc-supply = <®ulator_3_3v>;
vqmmc-supply = <®ulator_3_3v>;
- bus-width = <4>;
- u-boot,dm-pre-reloc;
-};
-
-&usb1 {
status = "okay";
};
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
- flash0: n25q00 at 0 {
- u-boot,dm-pre-reloc;
+ flash: flash at 0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00", "spi-flash";
- reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ compatible = "n25q256a";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
+
+ partition at qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition at qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
};
};
-&uart0 {
- u-boot,dm-pre-reloc;
+&usb1 {
+ status = "okay";
};
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
index 8f356cb580..319a71e41e 100644
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
*/
/dts-v1/;
@@ -19,13 +19,10 @@
};
mmc0: dwmmc0 at ff704000 {
- num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
- drvsel = <3>;
- smplsel = <0>;
};
sysmgr at ffd08000 {
@@ -33,3 +30,7 @@
};
};
};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
index 139a70f265..a387071674 100644
--- a/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts
@@ -47,9 +47,20 @@
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
&mmc0 {
status = "okay";
- bus-width = <4>;
u-boot,dm-pre-reloc;
};
@@ -61,3 +72,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
+
+&watchdog0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
new file mode 100644
index 0000000000..08d81da169
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright Altera Corporation (C) 2015
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
index d504150edd..67076e1b1c 100644
--- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -1,32 +1,43 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright Altera Corporation (C) 2015
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
*/
#include "socfpga_cyclone5.dtsi"
/ {
- model = "Terasic DE0-Nano(Atlas)";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ model = "Terasic DE-0(Atlas)";
+ compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
+ memory at 0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
aliases {
ethernet0 = &gmac1;
- udc0 = &usb1;
};
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
- soc {
- u-boot,dm-pre-reloc;
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 24 0>;
+ linux,default-trigger = "heartbeat";
+ };
};
};
@@ -34,14 +45,20 @@
status = "okay";
phy-mode = "rgmii";
- rxd0-skew-ps = <420>;
- rxd1-skew-ps = <420>;
- rxd2-skew-ps = <420>;
- rxd3-skew-ps = <420>;
- txen-skew-ps = <0>;
- txc-skew-ps = <1860>;
- rxdv-skew-ps = <420>;
- rxc-skew-ps = <1680>;
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+
+ max-frame-size = <3800>;
};
&gpio0 {
@@ -58,8 +75,9 @@
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
- dxl345: adxl345 at 0 {
+ adxl345: adxl345 at 53 {
compatible = "adi,adxl345";
reg = <0x53>;
@@ -69,14 +87,15 @@
};
&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
status = "okay";
- u-boot,dm-pre-reloc;
};
-&usb1 {
+&uart0 {
status = "okay";
};
-&uart0 {
- u-boot,dm-pre-reloc;
+&usb1 {
+ status = "okay";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
index d4dd9e9bca..e9105743ea 100644
--- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -58,6 +58,18 @@
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
&mmc0 {
status = "okay";
u-boot,dm-pre-reloc;
@@ -70,3 +82,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
+
+&watchdog0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
index f62292284d..4f076bce93 100644
--- a/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
+++ b/arch/arm/dts/socfpga_cyclone5_de1_soc.dts
@@ -56,6 +56,18 @@
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
&mmc0 {
status = "okay";
u-boot,dm-pre-reloc;
@@ -68,3 +80,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
+
+&watchdog0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 4e94d86114..b7054bfd5a 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -55,6 +55,10 @@
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
&i2c0 {
status = "okay";
@@ -107,3 +111,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
+
+&watchdog0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
new file mode 100644
index 0000000000..9436e0fa8b
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi at ff705000";
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+ compatible = "n25q00", "spi-flash";
+ u-boot,dm-pre-reloc;
+
+ partition at qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition at qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index c28be67bb9..6f138b2b26 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -1,31 +1,53 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Altera SOCFPGA Cyclone V SoC Development Kit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
- memory {
+ memory at 0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
aliases {
- /* this allow the ethaddr uboot environment variable contents
+ /* this allow the ethaddr uboot environmnet variable contents
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
- udc0 = &usb1;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 15 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 14 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 13 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&portb 12 1>;
+ };
};
regulator_3_3v: 3-3-v-regulator {
@@ -34,10 +56,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+};
- soc {
- u-boot,dm-pre-reloc;
- };
+&can0 {
+ status = "okay";
};
&gmac1 {
@@ -68,6 +90,14 @@
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom at 51 {
compatible = "atmel,24c32";
@@ -82,39 +112,55 @@
};
&mmc0 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
cd-gpios = <&portb 18 0>;
vmmc-supply = <®ulator_3_3v>;
vqmmc-supply = <®ulator_3_3v>;
+ status = "okay";
};
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
flash0: n25q00 at 0 {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00", "spi-flash";
- reg = <0>; /* chip select */
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
+
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
+
+ partition at qspi-boot {
+ /* 8MB for raw data. */
+ label = "Flash 0 Raw Data";
+ reg = <0x0 0x800000>;
+ };
+
+ partition at qspi-rootfs {
+ /* 120MB for jffs2 data. */
+ label = "Flash 0 jffs2 Filesystem";
+ reg = <0x800000 0x7800000>;
+ };
};
};
-&usb1 {
+&spi0 {
status = "okay";
+
+ spidev at 0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
};
-&uart0 {
- u-boot,dm-pre-reloc;
+&usb1 {
+ status = "okay";
};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
new file mode 100644
index 0000000000..648f1bd01d
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi at ff705000";
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&flash {
+ compatible = "n25q00", "spi-flash";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
index c7a6cf2db8..c155ff02eb 100644
--- a/arch/arm/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -1,32 +1,121 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Terasic SoCkit";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
+ memory at 0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac1 device tree blob.
+ */
ethernet0 = &gmac1;
- udc0 = &usb1;
};
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
+ leds {
+ compatible = "gpio-leds";
+
+ hps_led0 {
+ label = "hps:blue:led0";
+ gpios = <&portb 24 0>; /* HPS_GPIO53 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ hps_led1 {
+ label = "hps:blue:led1";
+ gpios = <&portb 25 0>; /* HPS_GPIO54 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ hps_led2 {
+ label = "hps:blue:led2";
+ gpios = <&portb 26 0>; /* HPS_GPIO55 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ hps_led3 {
+ label = "hps:blue:led3";
+ gpios = <&portb 27 0>; /* HPS_GPIO56 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ hps_sw0 {
+ label = "hps_sw0";
+ gpios = <&portc 20 0>; /* HPS_GPI7 */
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0x0>; /* SW_LID */
+ };
+
+ hps_sw1 {
+ label = "hps_sw1";
+ gpios = <&portc 19 0>; /* HPS_GPI6 */
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0x5>; /* SW_DOCK */
+ };
+
+ hps_sw2 {
+ label = "hps_sw2";
+ gpios = <&portc 18 0>; /* HPS_GPI5 */
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0xa>; /* SW_KEYPAD_SLIDE */
+ };
+
+ hps_sw3 {
+ label = "hps_sw3";
+ gpios = <&portc 17 0>; /* HPS_GPI4 */
+ linux,input-type = <5>; /* EV_SW */
+ linux,code = <0xc>; /* SW_ROTATE_LOCK */
+ };
+
+ hps_hkey0 {
+ label = "hps_hkey0";
+ gpios = <&portc 21 1>; /* HPS_GPI8 */
+ linux,code = <187>; /* KEY_F17 */
+ };
+
+ hps_hkey1 {
+ label = "hps_hkey1";
+ gpios = <&portc 22 1>; /* HPS_GPI9 */
+ linux,code = <188>; /* KEY_F18 */
+ };
+
+ hps_hkey2 {
+ label = "hps_hkey2";
+ gpios = <&portc 23 1>; /* HPS_GPI10 */
+ linux,code = <189>; /* KEY_F19 */
+ };
+
+ hps_hkey3 {
+ label = "hps_hkey3";
+ gpios = <&portc 24 1>; /* HPS_GPI11 */
+ linux,code = <190>; /* KEY_F20 */
+ };
};
- soc {
- u-boot,dm-pre-reloc;
+ regulator_3_3v: vcc3p3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
};
@@ -44,46 +133,50 @@
rxc-skew-ps = <2000>;
};
-&gpio0 {
+&gpio0 { /* GPIO 0..29 */
status = "okay";
};
-&gpio1 {
+&gpio1 { /* GPIO 30..57 */
status = "okay";
};
-&gpio2 {
+&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
-&i2c0 {
+&i2c1 {
status = "okay";
- rtc: rtc at 68 {
- compatible = "stm,m41t82";
- reg = <0x68>;
+ accel1: accelerometer at 53 {
+ compatible = "adi,adxl345";
+ reg = <0x53>;
+
+ interrupt-parent = <&portc>;
+ interrupts = <3 2>;
};
};
&mmc0 {
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
status = "okay";
- u-boot,dm-pre-reloc;
};
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
- flash0: n25q00 at 0 {
- u-boot,dm-pre-reloc;
+ flash: flash at 0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00", "spi-flash";
- reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ compatible = "n25q00";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
@@ -94,7 +187,3 @@
&usb1 {
status = "okay";
};
-
-&uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
new file mode 100644
index 0000000000..31bd1dba0f
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi at ff705000";
+ udc0 = &usb1;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&flash {
+ compatible = "n25q256a", "spi-flash";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 8cde9906a0..8d5d3996f6 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*/
#include "socfpga_cyclone5.dtsi"
@@ -9,83 +9,86 @@
model = "EBV SOCrates";
compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
aliases {
- /*
- * This allows the ethaddr uboot environment variable
- * contents to be added to the gmac1 device tree blob.
- */
ethernet0 = &gmac1;
- udc0 = &usb1;
};
- memory {
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
- soc {
- u-boot,dm-pre-reloc;
+ leds: gpio-leds {
};
};
&gmac1 {
- status = "okay";
phy-mode = "rgmii";
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+&gpio1 {
+ status = "okay";
};
&i2c0 {
status = "okay";
rtc: rtc at 68 {
- compatible = "stm,m41t82";
+ compatible = "st,m41t82";
reg = <0x68>;
};
};
-&mmc0 {
+&leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "led:green:heartbeat";
+ gpios = <&porta 28 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1 {
+ label = "led:green:D7";
+ gpios = <&portb 19 1>;
+ };
+
+ led2 {
+ label = "led:green:D8";
+ gpios = <&portb 25 1>;
+ };
+};
+
+&mmc {
status = "okay";
- u-boot,dm-pre-reloc;
};
&qspi {
status = "okay";
- flash0: n25q00 at 0 {
+ flash: flash at 0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00", "spi-flash";
- reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ compatible = "n25q256a";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
+ status = "okay";
};
};
-
-&usb1 {
- disable-over-current;
- status = "okay";
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 86c61fe081..6a6c29be79 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -50,6 +50,18 @@
status = "okay";
};
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
&i2c0 {
status = "okay";
speed-mode = <0>;
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
new file mode 100644
index 0000000000..360b946ba2
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+/{
+ aliases {
+ spi0 = "/soc/spi at ff705000";
+ udc0 = &usb0;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+
+ n25q128 at 0 {
+ compatible = "n25q128", "spi-flash";
+ u-boot,dm-pre-reloc;
+ };
+ n25q00 at 1 {
+ compatible = "n25q00", "spi-flash";
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
index 85ab56379f..355b3dbf43 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -1,100 +1,238 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*/
#include "socfpga_cyclone5.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "samtec VIN|ING FPGA";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+ compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
+ memory at 0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
aliases {
+ /*
+ * This allow the ethaddr uboot environment variable contents
+ * to be added to the gmac1 device tree blob.
+ */
ethernet0 = &gmac1;
- udc0 = &usb0;
+ ethernet1 = &gmac0;
};
- memory {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ hps_temp0 {
+ label = "BTN_0"; /* TEMP_OS */
+ gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */
+ linux,code = <BTN_0>;
+ };
+
+ hps_hkey0 {
+ label = "BTN_1"; /* DIS_PWR */
+ gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */
+ linux,code = <BTN_1>;
+ };
+
+ hps_hkey1 {
+ label = "hps_hkey1"; /* POWER_DOWN */
+ gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
+ linux,code = <KEY_POWER>;
+ };
};
- soc {
- u-boot,dm-pre-reloc;
+ regulator-usb-nrst {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_nrst";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-always-on;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <10000 10000 10000>;
- rxd0-skew-ps = <0>;
- rxd1-skew-ps = <0>;
- rxd2-skew-ps = <0>;
- rxd3-skew-ps = <0>;
- txen-skew-ps = <0>;
- txc-skew-ps = <2600>;
- rxdv-skew-ps = <0>;
- rxc-skew-ps = <2000>;
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <2600>;
+ rxdv-skew-ps = <0>;
+ rxc-skew-ps = <2000>;
+ };
+ };
};
-&gpio0 {
+&gpio0 { /* GPIO 0..29 */
status = "okay";
};
-&gpio1 {
+&gpio1 { /* GPIO 30..57 */
status = "okay";
};
-&gpio2 {
+&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
&i2c0 {
status = "okay";
- rtc: rtc at 68 {
- compatible = "stm,m41t82";
- reg = <0x68>;
+ gpio: pca9557 at 1f {
+ compatible = "nxp,pca9557";
+ reg = <0x1f>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ temp: lm75 at 48 {
+ compatible = "lm75";
+ reg = <0x48>;
+ };
+
+ at24 at 50 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x50>;
+ };
+
+ i2cswitch at 70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c at 6 { /* Backplane EEPROM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ eeprom at 51 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x51>;
+ };
+ };
+
+ i2c at 7 { /* Power board EEPROM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ eeprom at 51 {
+ compatible = "atmel,24c01";
+ pagesize = <8>;
+ reg = <0x51>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ at24 at 50 {
+ compatible = "atmel,24c02";
+ pagesize = <8>;
+ reg = <0x50>;
};
};
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
- flash0: n25q128 at 0 {
- u-boot,dm-pre-reloc;
+ n25q128 at 0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q128", "spi-flash";
- reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ compatible = "n25q128";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <100000000>;
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
};
- flash1: n25q00 at 1 {
- u-boot,dm-pre-reloc;
+ n25q00 at 1 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00", "spi-flash";
- reg = <1>; /* chip select */
- spi-max-frequency = <50000000>;
+ compatible = "n25q00";
+ reg = <1>; /* chip select */
+ spi-max-frequency = <100000000>;
m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
@@ -103,13 +241,11 @@
};
&usb0 {
+ dr_mode = "host";
status = "okay";
};
&usb1 {
+ dr_mode = "peripheral";
status = "okay";
};
-
-&uart0 {
- u-boot,dm-pre-reloc;
-};
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux
2018-11-02 10:54 [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
` (2 preceding siblings ...)
2018-11-02 10:54 ` [U-Boot] [PATCH v2 3/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
@ 2018-11-02 13:25 ` Marek Vasut
3 siblings, 0 replies; 5+ messages in thread
From: Marek Vasut @ 2018-11-02 13:25 UTC (permalink / raw)
To: u-boot
On 11/02/2018 11:54 AM, Simon Goldschmidt wrote:
> This series merges socfpga gen5 dts and dtsi files from linux
> while keeping U-Boot behaviour. Changes in those files that need
> fixing (mostly in -u-boot.dtsi board files) are:
> - watchdog is now enabled
> - ethernet, spi and i2c aliases removed from socfpga.dtsi
> - gpio bank names not available
> - mmc disabled
> - qspi compatible string different
> - 'clock-frequency' removed from uarts
Applied all three to socfpga/next, thanks!
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-11-02 13:25 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-02 10:54 [U-Boot] [PATCH v2 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 1/3] gpio: dwapb_gpio: fix binding without bank-name property Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 2/3] spi: cadence_qspi: use "cdns, qspi-nor" as compatible Simon Goldschmidt
2018-11-02 10:54 ` [U-Boot] [PATCH v2 3/3] dts: arm: socfpga: merge gen5 devicetrees from linux Simon Goldschmidt
2018-11-02 13:25 ` [U-Boot] [PATCH v2 0/3] " Marek Vasut
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