* [PATCH] drm/amdgpu/vega20: add CLK base offset
@ 2018-11-06 16:24 Alex Deucher
[not found] ` <20181106162400.21189-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Alex Deucher @ 2018-11-06 16:24 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
In case we need to access CLK registers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index 2d4473557b0d..d13fc4fcb517 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+ adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
}
return 0;
}
--
2.13.6
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amdgpu/vega20: add CLK base offset
[not found] ` <20181106162400.21189-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-11-06 16:51 ` Wentland, Harry
0 siblings, 0 replies; 2+ messages in thread
From: Wentland, Harry @ 2018-11-06 16:51 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander
On 2018-11-06 11:24 a.m., Alex Deucher wrote:
> In case we need to access CLK registers.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> index 2d4473557b0d..d13fc4fcb517 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
> @@ -49,6 +49,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
> adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
> adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
> + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
> }
> return 0;
> }
>
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2018-11-06 16:24 [PATCH] drm/amdgpu/vega20: add CLK base offset Alex Deucher
[not found] ` <20181106162400.21189-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-11-06 16:51 ` Wentland, Harry
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