[PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Bob Paauwe]

For ppgtt, what we're really interested in is the number of page
walk levels for each platform. Rename the device info fields to
reflect this:

.has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
.has_full_ppgtt	     -> .has_full_3lvl_ppgtt

Also add a new field, full_ppgtt_bits, that defines the actual
address range.  This gives us more flexibility and will work for
cases where we have platforms with different address ranges but
share the same page walk levels.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h                  |  4 +--
 drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c       |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 34 +++++++++++++-----------
 drivers/gpu/drm/i915/i915_params.c               |  3 ++-
 drivers/gpu/drm/i915/i915_pci.c                  | 17 +++++++-----
 drivers/gpu/drm/i915/intel_device_info.h         |  7 +++--
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c    |  2 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 11 files changed, 45 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..b9f7903e60d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
 #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
-#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_FULL_3LVL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
+#define USES_FULL_4LVL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..a0dc3170b358 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (USES_FULL_PPGTT(dev_priv)) {
+	if (USES_FULL_3LVL_PPGTT(dev_priv)) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a926d7d47183..166f1ea1786f 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
 
 	eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
-	if (USES_FULL_PPGTT(eb.i915))
+	if (USES_FULL_3LVL_PPGTT(eb.i915))
 		eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 	reloc_cache_init(&eb.reloc_cache, eb.i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4137af4bd8f5..15f957a6ae38 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -136,19 +136,19 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 			       	int enable_ppgtt)
 {
-	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
+	bool has_full_3lvl_ppgtt;
+	bool has_full_4lvl_ppgtt;
 
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
-	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_3lvl_ppgtt = dev_priv->info.has_full_3lvl_ppgtt;
+	has_full_4lvl_ppgtt = dev_priv->info.has_full_4lvl_ppgtt;
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
-		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+		has_full_3lvl_ppgtt = false;
+		has_full_4lvl_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
 	}
 
 	/*
@@ -161,10 +161,10 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (enable_ppgtt == 1)
 		return 1;
 
-	if (enable_ppgtt == 2 && has_full_ppgtt)
+	if (enable_ppgtt == 2 && has_full_3lvl_ppgtt)
 		return 2;
 
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 		return 3;
 
 	/* Disable ppgtt on SNB if VT-d is on. */
@@ -173,10 +173,10 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (has_full_48bit_ppgtt)
+	if (has_full_4lvl_ppgtt)
 		return 3;
 
-	if (has_full_ppgtt)
+	if (has_full_3lvl_ppgtt)
 		return 2;
 
 	return 1;
@@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	if (USES_FULL_3LVL_PPGTT(i915) && !USES_FULL_4LVL_PPGTT(i915))
+		ppgtt->vm.total = 1ULL << 32;
+	else
+		ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1789,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
@@ -2958,7 +2959,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
+	if (USES_PPGTT(dev_priv) && !USES_FULL_3LVL_PPGTT(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
@@ -3408,7 +3409,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	ggtt->vm.cleanup = gen6_gmch_remove;
 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
 	ggtt->vm.clear_range = nop_clear_range;
-	if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
+	if (!USES_FULL_3LVL_PPGTT(dev_priv) ||
+	    intel_scanout_needs_vtd_wa(dev_priv))
 		ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 295e981e4a39..71ac381807a6 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -84,7 +84,8 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
 
 i915_param_named_unsafe(enable_ppgtt, int, 0400,
 	"Override PPGTT usage. "
-	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
+	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full with 32 bits, "
+	"3=full with extended address space)");
 
 i915_param_named_unsafe(enable_psr, int, 0600,
 	"Enable PSR "
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..6e0d4476e553 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -298,7 +298,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
+	.has_full_3lvl_ppgtt = 1, \
+	.full_ppgtt_bits = 32, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -352,7 +353,8 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.has_full_3lvl_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +401,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.has_full_4lvl_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -444,7 +447,8 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.has_full_3lvl_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -519,8 +523,9 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.has_full_3lvl_ppgtt = 1, \
+	.has_full_4lvl_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..df3263b97c7d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,8 +87,8 @@ enum intel_platform {
 	func(has_reset_engine); \
 	func(has_fbc); \
 	func(has_fpga_dbg); \
-	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
+	func(has_full_3lvl_ppgtt); \
+	func(has_full_4lvl_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -182,6 +182,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..9f74244ef3e1 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
+	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
 		pr_info("48b PPGTT not supported, skipping\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 128ad1cf0647..05df36863694 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!USES_FULL_PPGTT(i915))
+	if (!USES_FULL_3LVL_PPGTT(i915))
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8e2e269db97e..49420e98f374 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!USES_FULL_PPGTT(dev_priv))
+	if (!USES_FULL_3LVL_PPGTT(dev_priv))
 		return 0;
 
 	file = mock_file(dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..33d7225edbbb 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

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Re: [PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Chris Wilson]

Quoting Bob Paauwe (2018-08-31 16:47:04)
> For ppgtt, what we're really interested in is the number of page
> walk levels for each platform. Rename the device info fields to
> reflect this:
> 
> .has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
> .has_full_ppgtt      -> .has_full_3lvl_ppgtt
> 
> Also add a new field, full_ppgtt_bits, that defines the actual
> address range.  This gives us more flexibility and will work for
> cases where we have platforms with different address ranges but
> share the same page walk levels.
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h                  |  4 +--
>  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c       |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c              | 34 +++++++++++++-----------
>  drivers/gpu/drm/i915/i915_params.c               |  3 ++-
>  drivers/gpu/drm/i915/i915_pci.c                  | 17 +++++++-----
>  drivers/gpu/drm/i915/intel_device_info.h         |  7 +++--
>  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c    |  2 +-
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  11 files changed, 45 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e5b9d3c77139..b9f7903e60d1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>  
>  #define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> +#define USES_FULL_3LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> +#define USES_FULL_4LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>         GEM_BUG_ON((sizes) == 0); \
>         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f15a039772db..a0dc3170b358 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
>         if (IS_ERR(ctx))
>                 return ctx;
>  
> -       if (USES_FULL_PPGTT(dev_priv)) {
> +       if (USES_FULL_3LVL_PPGTT(dev_priv)) {

That is not an improvement. It really is a question of whether or not
full-ppgtt is enabled.

>                 struct i915_hw_ppgtt *ppgtt;
>  
>                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index a926d7d47183..166f1ea1786f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
>         eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
>  
>         eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
> -       if (USES_FULL_PPGTT(eb.i915))
> +       if (USES_FULL_3LVL_PPGTT(eb.i915))

Again the same complaint.

I think you need to rethink the semantics carefully.
-Chris
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✓ Fi.CI.BAT: success for drm/i915: Rename full ppgtt configuration to be more generic

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4750 -> Patchwork_10062 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10062 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-kbl-guc:         PASS -> DMESG-FAIL (fdo#107710, fdo#106947)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#105128, fdo#107139)
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      {fi-byt-clapper}:   FAIL (fdo#107362, fdo#103191) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         FAIL (fdo#104008) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107710 https://bugs.freedesktop.org/show_bug.cgi?id=107710
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (52 -> 47) ==

  Missing    (5): fi-hsw-4770r fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4750 -> Patchwork_10062

  CI_DRM_4750: ef9613f5ddd35f2bd2834489b6d96e54c0cae8c6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4618: 9d83154c898b5acc8b462d17104df50cfd71e9a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10062: 605141a980b8ab7f839a294dc0a577f477907987 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

605141a980b8 drm/i915: Rename full ppgtt configuration to be more generic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10062/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Bob Paauwe]

On Fri, 31 Aug 2018 16:51:29 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
> > 
> > .has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
> > .has_full_ppgtt      -> .has_full_3lvl_ppgtt
> > 
> > Also add a new field, full_ppgtt_bits, that defines the actual
> > address range.  This gives us more flexibility and will work for
> > cases where we have platforms with different address ranges but
> > share the same page walk levels.
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Michel Thierry <michel.thierry@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h                  |  4 +--
> >  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_execbuffer.c       |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 34 +++++++++++++-----------
> >  drivers/gpu/drm/i915/i915_params.c               |  3 ++-
> >  drivers/gpu/drm/i915/i915_pci.c                  | 17 +++++++-----
> >  drivers/gpu/drm/i915/intel_device_info.h         |  7 +++--
> >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c    |  2 +-
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  11 files changed, 45 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e5b9d3c77139..b9f7903e60d1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> > +#define USES_FULL_3LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >         GEM_BUG_ON((sizes) == 0); \
> >         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..a0dc3170b358 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
> >         if (IS_ERR(ctx))
> >                 return ctx;
> >  
> > -       if (USES_FULL_PPGTT(dev_priv)) {
> > +       if (USES_FULL_3LVL_PPGTT(dev_priv)) {  
> 
> That is not an improvement. It really is a question of whether or not
> full-ppgtt is enabled.
> 
> >                 struct i915_hw_ppgtt *ppgtt;
> >  
> >                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > index a926d7d47183..166f1ea1786f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > @@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> >         eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
> >  
> >         eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
> > -       if (USES_FULL_PPGTT(eb.i915))
> > +       if (USES_FULL_3LVL_PPGTT(eb.i915))  
> 
> Again the same complaint.
> 
> I think you need to rethink the semantics carefully.
> -Chris

Would USES_FULL_PPGTT() and USES_EXTENDED_PPGTT() make more sense
then?  I think the biggest issue is with the FULL_48BIT_PPGTT name
going forward.

Bob

-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Rodrigo Vivi]

On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> Quoting Bob Paauwe (2018-08-31 16:47:04)
> > For ppgtt, what we're really interested in is the number of page
> > walk levels for each platform. Rename the device info fields to
> > reflect this:
> > 
> > .has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
> > .has_full_ppgtt      -> .has_full_3lvl_ppgtt
> > 
> > Also add a new field, full_ppgtt_bits, that defines the actual
> > address range.  This gives us more flexibility and will work for
> > cases where we have platforms with different address ranges but
> > share the same page walk levels.
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Michel Thierry <michel.thierry@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h                  |  4 +--
> >  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_execbuffer.c       |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 34 +++++++++++++-----------
> >  drivers/gpu/drm/i915/i915_params.c               |  3 ++-
> >  drivers/gpu/drm/i915/i915_pci.c                  | 17 +++++++-----
> >  drivers/gpu/drm/i915/intel_device_info.h         |  7 +++--
> >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
> >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c    |  2 +-
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  11 files changed, 45 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e5b9d3c77139..b9f7903e60d1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> > +#define USES_FULL_3LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >         GEM_BUG_ON((sizes) == 0); \
> >         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..a0dc3170b358 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
> >         if (IS_ERR(ctx))
> >                 return ctx;
> >  
> > -       if (USES_FULL_PPGTT(dev_priv)) {
> > +       if (USES_FULL_3LVL_PPGTT(dev_priv)) {
> 
> That is not an improvement. It really is a question of whether or not
> full-ppgtt is enabled.

I think we do need this change, but only with USES_FULL_PPGTT macro
and the rest should be checked with the full_ppgtt number of bits if
needed.

> 
> >                 struct i915_hw_ppgtt *ppgtt;
> >  
> >                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > index a926d7d47183..166f1ea1786f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > @@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> >         eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
> >  
> >         eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
> > -       if (USES_FULL_PPGTT(eb.i915))
> > +       if (USES_FULL_3LVL_PPGTT(eb.i915))
> 
> Again the same complaint.
> 
> I think you need to rethink the semantics carefully.
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Rename full ppgtt configuration to be more generic

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4750_full -> Patchwork_10062_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10062_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-snb:          PASS -> FAIL (fdo#106886)

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          PASS -> DMESG-WARN (fdo#105763)

    igt@kms_flip_tiling@flip-yf-tiled:
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    
    ==== Possible fixes ====

    igt@gem_exec_await@wide-contexts:
      shard-kbl:          FAIL (fdo#105900) -> PASS

    igt@gem_exec_suspend@basic-s3-devices:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4750 -> Patchwork_10062

  CI_DRM_4750: ef9613f5ddd35f2bd2834489b6d96e54c0cae8c6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4618: 9d83154c898b5acc8b462d17104df50cfd71e9a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10062: 605141a980b8ab7f839a294dc0a577f477907987 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10062/shards.html
_______________________________________________
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Re: [PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Bob Paauwe]

On Fri, 31 Aug 2018 13:21:40 -0700
Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:

> On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> > Quoting Bob Paauwe (2018-08-31 16:47:04)  
> > > For ppgtt, what we're really interested in is the number of page
> > > walk levels for each platform. Rename the device info fields to
> > > reflect this:
> > > 
> > > .has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
> > > .has_full_ppgtt      -> .has_full_3lvl_ppgtt
> > > 
> > > Also add a new field, full_ppgtt_bits, that defines the actual
> > > address range.  This gives us more flexibility and will work for
> > > cases where we have platforms with different address ranges but
> > > share the same page walk levels.
> > > 
> > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > CC: Michel Thierry <michel.thierry@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h                  |  4 +--
> > >  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
> > >  drivers/gpu/drm/i915/i915_gem_execbuffer.c       |  2 +-
> > >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 34 +++++++++++++-----------
> > >  drivers/gpu/drm/i915/i915_params.c               |  3 ++-
> > >  drivers/gpu/drm/i915/i915_pci.c                  | 17 +++++++-----
> > >  drivers/gpu/drm/i915/intel_device_info.h         |  7 +++--
> > >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c    |  2 +-
> > >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> > >  11 files changed, 45 insertions(+), 32 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index e5b9d3c77139..b9f7903e60d1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> > >  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> > >  
> > >  #define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > > -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> > > -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> > > +#define USES_FULL_3LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> > > +#define USES_FULL_4LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
> > >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > >         GEM_BUG_ON((sizes) == 0); \
> > >         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > > index f15a039772db..a0dc3170b358 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > > @@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
> > >         if (IS_ERR(ctx))
> > >                 return ctx;
> > >  
> > > -       if (USES_FULL_PPGTT(dev_priv)) {
> > > +       if (USES_FULL_3LVL_PPGTT(dev_priv)) {  
> > 
> > That is not an improvement. It really is a question of whether or not
> > full-ppgtt is enabled.  
> 
> I think we do need this change, but only with USES_FULL_PPGTT macro
> and the rest should be checked with the full_ppgtt number of bits if
> needed.
> 

USES_FULL_PPGTT() is currently used to mean at least 3 level, but could
be 4 level so I get Chris's point that USES_FULL_3LVL_PPGTT doesn't
really work, at least not as a simple substitution.

There are only a couple of places where we care that it's actually 4
level so changing those to actually check the number of bits seems to
make sense to me.  Either

#define USES_FULL_4LVL_PPGTT(i915) (i915.number_of_bits > 32)

or just use the condition without the macro where needed.

> >   
> > >                 struct i915_hw_ppgtt *ppgtt;
> > >  
> > >                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > index a926d7d47183..166f1ea1786f 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > @@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> > >         eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
> > >  
> > >         eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
> > > -       if (USES_FULL_PPGTT(eb.i915))
> > > +       if (USES_FULL_3LVL_PPGTT(eb.i915))  
> > 
> > Again the same complaint.
> > 
> > I think you need to rethink the semantics carefully.
> > -Chris
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx  



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.

v2: keep USES_FULL_PPGTT() unchanged (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 19 ++++++++++---------
 drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
 drivers/gpu/drm/i915/intel_device_info.h         |  3 +++
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 6 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..a367686fd735 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..530a4c1452b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 			       	int enable_ppgtt)
 {
 	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
+	bool has_full_4lvl_ppgtt;
 
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
 	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
 		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+		has_full_4lvl_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
 	}
 
 	/*
@@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 		return 3;
 
 	/* Disable ppgtt on SNB if VT-d is on. */
@@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (has_full_48bit_ppgtt)
+	if (has_full_4lvl_ppgtt)
 		return 3;
 
 	if (has_full_ppgtt)
@@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))
+		ppgtt->vm.total = 1ULL << 32;
+	else
+		ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1789,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..a99c1f6de64e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
+	.full_ppgtt_bits = 32, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32, \
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32, \
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..083590e98195 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -182,6 +182,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..9f74244ef3e1 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
+	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
 		pr_info("48b PPGTT not supported, skipping\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..33d7225edbbb 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-06 21:04:09)
> @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>         ppgtt->vm.i915 = i915;
>         ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> -               1ULL << 48 :
> -               1ULL << 32;
> +       if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))
(brackets (because(?))

> +               ppgtt->vm.total = 1ULL << 32;
> +       else
> +               ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;

How about

ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
if (i915_modparams.enable_ppgtt < 3)
	ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);

Although let me complain loudly about introducing more modparams.

Please no. If you want to configure it, do so at runtime via context
parameters or creation.
-Chris
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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev2)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6e4a835ff874 drm/i915: Make 48bit full ppgtt configuration generic (v2)
-:85: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'i915_modparams.enable_ppgtt < 3'
#85: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1650:
+	if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))

-:117: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#117: FILE: drivers/gpu/drm/i915/i915_pci.c:357:
+	.full_ppgtt_bits = 32, \

-:134: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#134: FILE: drivers/gpu/drm/i915/i915_pci.c:450:
+	.full_ppgtt_bits = 32, \

total: 0 errors, 2 warnings, 1 checks, 128 lines checked

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Bob Paauwe]

On Thu, 6 Sep 2018 21:08:33 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Quoting Bob Paauwe (2018-09-06 21:04:09)
> > @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> >         ppgtt->vm.i915 = i915;
> >         ppgtt->vm.dma = &i915->drm.pdev->dev;
> >  
> > -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > -               1ULL << 48 :
> > -               1ULL << 32;
> > +       if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))  
> (brackets (because(?))
habit mostly. 

> 
> > +               ppgtt->vm.total = 1ULL << 32;
> > +       else
> > +               ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;  
> 
> How about
> 
> ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> if (i915_modparams.enable_ppgtt < 3)
> 	ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);

That looks a bit cleaner, thanks!

> 
> Although let me complain loudly about introducing more modparams.

I didn't introduce a modparam, enable.ppgtt is an existing modparam
and it's currently able to "downgrade" an extended address range device
to use only 32 bits by setting it to 2.  I'm just trying to keep that
existing behavior. 

In the current code, setting enable_ppgtt=2 sets USES_FULL_PPGTT to
true and USES_FULL_48BIT_PPGTT to false.

If that existing behavior is not desired, I can rework this to remove
enable_ppgtt and have this use just the appropriate device info
settings.  It does get a bit more complicated as there are other parts
of the code that rely on the enable_ppgtt value today.

> 
> Please no. If you want to configure it, do so at runtime via context
> parameters or creation.
> -Chris


-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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✓ Fi.CI.BAT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev2)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10114 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10114 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191) +1

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
      fi-kbl-8809g:       DMESG-WARN (fdo#107762) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-kbl-7560u:       FAIL (fdo#107336) -> PASS

    
    ==== Warnings ====

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       DMESG-FAIL (fdo#107762) -> FAIL (fdo#107341)

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107762 https://bugs.freedesktop.org/show_bug.cgi?id=107762


== Participating hosts (52 -> 49) ==

  Additional (2): fi-byt-j1900 fi-gdg-551 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4782 -> Patchwork_10114

  CI_DRM_4782: 60edf94611d2374821fbe2a824cebcb425ce7b0d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4632: 94b4e204473a7d9f49e536c8877a4a5636e0d1b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10114: 6e4a835ff8745da0bdbf72548f8dc2e31cb43969 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6e4a835ff874 drm/i915: Make 48bit full ppgtt configuration generic (v2)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10114/issues.html
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Rodrigo Vivi]

On Thu, Sep 06, 2018 at 01:04:09PM -0700, Bob Paauwe wrote:
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> 
> v2: keep USES_FULL_PPGTT() unchanged (Chris)
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c              | 19 ++++++++++---------
>  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
>  drivers/gpu/drm/i915/intel_device_info.h         |  3 +++
>  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  6 files changed, 22 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a4da5b723fd..a367686fd735 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>  	GEM_BUG_ON((sizes) == 0); \
>  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index eb0e446d6482..530a4c1452b3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  			       	int enable_ppgtt)
>  {
>  	bool has_full_ppgtt;
> -	bool has_full_48bit_ppgtt;
> +	bool has_full_4lvl_ppgtt;
>  
>  	if (!dev_priv->info.has_aliasing_ppgtt)
>  		return 0;
>  
>  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
>  
>  	if (intel_vgpu_active(dev_priv)) {
>  		/* GVT-g has no support for 32bit ppgtt */
>  		has_full_ppgtt = false;
> -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> +		has_full_4lvl_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);

I wonder if we should already rename this function to match 4lvl instead
of full and/or 48bit on it.

>  	}
>  
>  	/*
> @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  	if (enable_ppgtt == 2 && has_full_ppgtt)
>  		return 2;
>  
> -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	/* Disable ppgtt on SNB if VT-d is on. */
> @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> -	if (has_full_48bit_ppgtt)
> +	if (has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	if (has_full_ppgtt)
> @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>  	ppgtt->vm.i915 = i915;
>  	ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> -		1ULL << 48 :
> -		1ULL << 32;
> +	if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))
> +		ppgtt->vm.total = 1ULL << 32;
> +	else
> +		ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;
>  
>  	/*
>  	 * From bdw, there is support for read-only pages in the PPGTT.
> @@ -1788,7 +1789,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
>  	enum intel_engine_id id;
>  
>  	for_each_engine(engine, dev_priv, id) {
> -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
>  				 GEN8_GFX_PPGTT_48B : 0;
>  		I915_WRITE(RING_MODE_GEN7(engine),
>  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..a99c1f6de64e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>  	.has_rc6p = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> +	.full_ppgtt_bits = 32, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	GEN_DEFAULT_PAGE_SIZES, \
>  	IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_hotplug = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32, \
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
>  		      I915_GTT_PAGE_SIZE_2M, \
>  	.has_logical_ring_contexts = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_64bit_reloc = 1, \
>  	.has_reset_engine = 1
>  
> @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_gmch_display = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32, \
>  	.has_reset_engine = 1,
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
> @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.has_guc = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_reset_engine = 1, \
>  	.has_snoop = true, \
>  	.has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6eecd64734d5..083590e98195 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -182,6 +182,9 @@ struct intel_device_info {
>  		u16 degamma_lut_size;
>  		u16 gamma_lut_size;
>  	} color;
> +
> +	/* PPGTT bit size */
> +	int full_ppgtt_bits;
>  };
>  
>  struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index e272127783fe..9f74244ef3e1 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
>  	 * huge-gtt-pages.
>  	 */
>  
> -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
>  		pr_info("48b PPGTT not supported, skipping\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 43ed8b28aeaa..33d7225edbbb 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
>  		I915_GTT_PAGE_SIZE_64K |
>  		I915_GTT_PAGE_SIZE_2M;
>  
> +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> +
>  	mock_uncore_init(i915);
>  	i915_gem_init__mm(i915);
>  
> -- 
> 2.14.4
> 
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Rodrigo Vivi]

On Thu, Sep 06, 2018 at 09:08:33PM +0100, Chris Wilson wrote:
> Quoting Bob Paauwe (2018-09-06 21:04:09)
> > @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> >         ppgtt->vm.i915 = i915;
> >         ppgtt->vm.dma = &i915->drm.pdev->dev;
> >  
> > -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > -               1ULL << 48 :
> > -               1ULL << 32;
> > +       if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))
> (brackets (because(?))
> 
> > +               ppgtt->vm.total = 1ULL << 32;
> > +       else
> > +               ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;
> 
> How about
> 
> ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> if (i915_modparams.enable_ppgtt < 3)
> 	ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);
> 
> Although let me complain loudly about introducing more modparams.
> 
> Please no. If you want to configure it, do so at runtime via context
> parameters or creation.

I agree with you, as well as Bob's approach apparently. His patch
is one step further to reduce the use of this parameter.

All the other work to kill it for good could come in follow-up patches imo.

> -Chris
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✓ Fi.CI.IGT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev2)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4782_full -> Patchwork_10114_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10114_full that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@drv_suspend@shrink:
      shard-snb:          INCOMPLETE (fdo#106886, fdo#105411) -> PASS
      shard-glk:          FAIL (fdo#106886) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4782 -> Patchwork_10114

  CI_DRM_4782: 60edf94611d2374821fbe2a824cebcb425ce7b0d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4632: 94b4e204473a7d9f49e536c8877a4a5636e0d1b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10114: 6e4a835ff8745da0bdbf72548f8dc2e31cb43969 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10114/shards.html
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v2)

[Bob Paauwe]

On Thu, 6 Sep 2018 14:10:35 -0700
Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:

> On Thu, Sep 06, 2018 at 01:04:09PM -0700, Bob Paauwe wrote:
> > 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> > 
> > Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> > describe that a 4 level walk table extended range PPGTT is being
> > used. Add a new device info field that specifies the number of
> > bits to prepare for cases where the range is not 32 or 48 bits.
> > 
> > v2: keep USES_FULL_PPGTT() unchanged (Chris)
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Michel Thierry <michel.thierry@intel.com>
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 19 ++++++++++---------
> >  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
> >  drivers/gpu/drm/i915/intel_device_info.h         |  3 +++
> >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  2 +-
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  6 files changed, 22 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5a4da5b723fd..a367686fd735 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
> >  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >  	GEM_BUG_ON((sizes) == 0); \
> >  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index eb0e446d6482..530a4c1452b3 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  			       	int enable_ppgtt)
> >  {
> >  	bool has_full_ppgtt;
> > -	bool has_full_48bit_ppgtt;
> > +	bool has_full_4lvl_ppgtt;
> >  
> >  	if (!dev_priv->info.has_aliasing_ppgtt)
> >  		return 0;
> >  
> >  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
> >  
> >  	if (intel_vgpu_active(dev_priv)) {
> >  		/* GVT-g has no support for 32bit ppgtt */
> >  		has_full_ppgtt = false;
> > -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > +		has_full_4lvl_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);  
> 
> I wonder if we should already rename this function to match 4lvl instead
> of full and/or 48bit on it.

If I start down that path, do I rename i915_vm_is_48bit() too and go
through comments that use 48b/48bit?   

Or is it better to split this up into multiple patches?

> 
> >  	}
> >  
> >  	/*
> > @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  	if (enable_ppgtt == 2 && has_full_ppgtt)
> >  		return 2;
> >  
> > -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	/* Disable ppgtt on SNB if VT-d is on. */
> > @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  		return 0;
> >  	}
> >  
> > -	if (has_full_48bit_ppgtt)
> > +	if (has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	if (has_full_ppgtt)
> > @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> >  	ppgtt->vm.i915 = i915;
> >  	ppgtt->vm.dma = &i915->drm.pdev->dev;
> >  
> > -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > -		1ULL << 48 :
> > -		1ULL << 32;
> > +	if ((i915_modparams.enable_ppgtt < 3) && USES_FULL_4LVL_PPGTT(i915))
> > +		ppgtt->vm.total = 1ULL << 32;
> > +	else
> > +		ppgtt->vm.total = 1ULL << i915->info.full_ppgtt_bits;
> >  
> >  	/*
> >  	 * From bdw, there is support for read-only pages in the PPGTT.
> > @@ -1788,7 +1789,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> >  	enum intel_engine_id id;
> >  
> >  	for_each_engine(engine, dev_priv, id) {
> > -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
> >  				 GEN8_GFX_PPGTT_48B : 0;
> >  		I915_WRITE(RING_MODE_GEN7(engine),
> >  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..a99c1f6de64e 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> >  	.has_rc6p = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > +	.full_ppgtt_bits = 32, \
> >  	GEN_DEFAULT_PIPEOFFSETS, \
> >  	GEN_DEFAULT_PAGE_SIZES, \
> >  	IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> >  	.has_hotplug = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32, \
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> >  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> > @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> >  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
> >  		      I915_GTT_PAGE_SIZE_2M, \
> >  	.has_logical_ring_contexts = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_64bit_reloc = 1, \
> >  	.has_reset_engine = 1
> >  
> > @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
> >  	.has_gmch_display = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32, \
> >  	.has_reset_engine = 1,
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> > @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> >  	.has_guc = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_reset_engine = 1, \
> >  	.has_snoop = true, \
> >  	.has_coherent_ggtt = false, \
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 6eecd64734d5..083590e98195 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -182,6 +182,9 @@ struct intel_device_info {
> >  		u16 degamma_lut_size;
> >  		u16 gamma_lut_size;
> >  	} color;
> > +
> > +	/* PPGTT bit size */
> > +	int full_ppgtt_bits;
> >  };
> >  
> >  struct intel_driver_caps {
> > diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > index e272127783fe..9f74244ef3e1 100644
> > --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > @@ -1434,7 +1434,7 @@ static int igt_ppgtt_pin_update(void *arg)
> >  	 * huge-gtt-pages.
> >  	 */
> >  
> > -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
> >  		pr_info("48b PPGTT not supported, skipping\n");
> >  		return 0;
> >  	}
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> >  		I915_GTT_PAGE_SIZE_64K |
> >  		I915_GTT_PAGE_SIZE_2M;
> >  
> > +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> > +
> >  	mock_uncore_init(i915);
> >  	i915_gem_init__mm(i915);
> >  
> > -- 
> > 2.14.4
> >   



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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[PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.

v2: keep USES_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>

Additional work to rename 48bit to 4 level

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
 drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
 drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 13 files changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..52bebd67173a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..a367686fd735 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..1add339ca6be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -249,7 +249,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..c66bbf409791 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 			       	int enable_ppgtt)
 {
 	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
+	bool has_full_4lvl_ppgtt;
 
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
 	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
 		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
 	}
 
 	/*
@@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 		return 3;
 
 	/* Disable ppgtt on SNB if VT-d is on. */
@@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (has_full_48bit_ppgtt)
+	if (has_full_4lvl_ppgtt)
 		return 3;
 
 	if (has_full_ppgtt)
@@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
+	if (i915_modparams.enable_ppgtt < 3)
+		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..e0619952ff52 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
+	.full_ppgtt_bits = 32, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..6d2f9f06ab57 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..180f2dca1223 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..b830a7b5064f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..50acb0463e9a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,7 +88,6 @@ enum intel_platform {
 	func(has_fbc); \
 	func(has_fpga_dbg); \
 	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -182,6 +181,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index def467c2451b..52a86a8c06b7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -2019,7 +2019,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not needed in 48-bit.*/
 	if (rq->gem_context->ppgtt &&
 	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2688,8 +2688,8 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
-		/* 64b PPGTT (48bit canonical)
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
+		/* > 32b PPGTT
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
 		 */
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..b065630bf672 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..33d7225edbbb 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Rodrigo Vivi]

On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> 
> v2: keep USES_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
>     Remove unecessary line coninuations (Bob)
>     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> 
> Additional work to rename 48bit to 4 level

Thanks for the additional work.
Bikeshed on this comment here: Shouldn't this be mentioned on the
"v3" portion directly instead of the middle of tags' block?

> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
>  drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
>  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
>  drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
>  drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
>  drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
>  drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  13 files changed, 39 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index a4e8e3cf74fd..52bebd67173a 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
>  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>  
> -	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> +	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
>  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a4da5b723fd..a367686fd735 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)

another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>  	GEM_BUG_ON((sizes) == 0); \
>  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f15a039772db..1add339ca6be 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
>  	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>  
>  	address_mode = INTEL_LEGACY_32B_CONTEXT;
> -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
>  		address_mode = INTEL_LEGACY_64B_CONTEXT;
>  	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index eb0e446d6482..c66bbf409791 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  			       	int enable_ppgtt)
>  {
>  	bool has_full_ppgtt;
> -	bool has_full_48bit_ppgtt;
> +	bool has_full_4lvl_ppgtt;
>  
>  	if (!dev_priv->info.has_aliasing_ppgtt)
>  		return 0;
>  
>  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
>  
>  	if (intel_vgpu_active(dev_priv)) {
>  		/* GVT-g has no support for 32bit ppgtt */
>  		has_full_ppgtt = false;
> -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> +		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
>  	}
>  
>  	/*
> @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  	if (enable_ppgtt == 2 && has_full_ppgtt)
>  		return 2;
>  
> -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	/* Disable ppgtt on SNB if VT-d is on. */
> @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  		return 0;
>  	}
>  
> -	if (has_full_48bit_ppgtt)
> +	if (has_full_4lvl_ppgtt)
>  		return 3;
>  
>  	if (has_full_ppgtt)
> @@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
>  	 * page-table operating in 64K mode must point to a properly aligned 64K
>  	 * region, including any PTEs which happen to point to scratch.
>  	 *
> -	 * This is only relevant for the 48b PPGTT where we support
> +	 * This is only relevant for the 4-level PPGTT where we support
>  	 * huge-gtt-pages, see also i915_vma_insert().
>  	 *
>  	 * TODO: we should really consider write-protecting the scratch-page and
>  	 * sharing between ppgtt
>  	 */
>  	size = I915_GTT_PAGE_SIZE_4K;
> -	if (i915_vm_is_48bit(vm) &&
> +	if (i915_vm_is_4lvl(vm) &&
>  	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
>  		size = I915_GTT_PAGE_SIZE_64K;
>  		gfp |= __GFP_NOWARN;
> @@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
>  
>  static inline bool use_4lvl(const struct i915_address_space *vm)
>  {
> -	return i915_vm_is_48bit(vm);
> +	return i915_vm_is_4lvl(vm);
>  }
>  
>  static struct i915_page_directory_pointer *
> @@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>  	ppgtt->vm.i915 = i915;
>  	ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> -		1ULL << 48 :
> -		1ULL << 32;
> +	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> +	if (i915_modparams.enable_ppgtt < 3)
> +		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);

but actually this is the only real thing that holds me from putting the rv-b
right now...
I think this change deserves a separated patch, but maybe it is because
I simply didn't understand why start using this min SZ_4G and I miss
some explanation...

The rest of the patch lgtm ;)

Thanks a lot,
Rodrigo.

>  
>  	/*
>  	 * From bdw, there is support for read-only pages in the PPGTT.
> @@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
>  	enum intel_engine_id id;
>  
>  	for_each_engine(engine, dev_priv, id) {
> -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
>  				 GEN8_GFX_PPGTT_48B : 0;
>  		I915_WRITE(RING_MODE_GEN7(engine),
>  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 7e2af5f4f39b..b2a709a27cb9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -363,7 +363,7 @@ struct i915_address_space {
>  #define i915_is_ggtt(vm) ((vm)->is_ggtt)
>  
>  static inline bool
> -i915_vm_is_48bit(const struct i915_address_space *vm)
> +i915_vm_is_4lvl(const struct i915_address_space *vm)
>  {
>  	return (vm->total - 1) >> 32;
>  }
> @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
>  static inline unsigned int
>  i915_pdpes_per_pdp(const struct i915_address_space *vm)
>  {
> -	if (i915_vm_is_48bit(vm))
> +	if (i915_vm_is_4lvl(vm))
>  		return GEN8_PML4ES_PER_PML4;
>  
>  	return GEN8_3LVL_PDPES;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>  	.has_rc6p = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> +	.full_ppgtt_bits = 32, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	GEN_DEFAULT_PAGE_SIZES, \
>  	IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_hotplug = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32,
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
>  		      I915_GTT_PAGE_SIZE_2M, \
>  	.has_logical_ring_contexts = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_64bit_reloc = 1, \
>  	.has_reset_engine = 1
>  
> @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_gmch_display = 1,
>  	.has_aliasing_ppgtt = 1,
>  	.has_full_ppgtt = 1,
> +	.full_ppgtt_bits = 32,
>  	.has_reset_engine = 1,
>  	.has_snoop = true,
>  	.has_coherent_ggtt = false,
> @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.has_guc = 1, \
>  	.has_aliasing_ppgtt = 1, \
>  	.has_full_ppgtt = 1, \
> -	.has_full_48bit_ppgtt = 1, \
> +	.full_ppgtt_bits = 48, \
>  	.has_reset_engine = 1, \
>  	.has_snoop = true, \
>  	.has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..6d2f9f06ab57 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
>  /*
>   * VGT capabilities type
>   */
> -#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
> +#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
>  #define VGT_CAPS_HWSP_EMULATION		BIT(3)
>  #define VGT_CAPS_HUGE_GTT		BIT(4)
>  
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..180f2dca1223 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
>  }
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
>  {
> -	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> +	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
>  }
>  
>  struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..b830a7b5064f 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>  
>  void i915_check_vgpu(struct drm_i915_private *dev_priv);
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
>  
>  static inline bool
>  intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6eecd64734d5..50acb0463e9a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -88,7 +88,6 @@ enum intel_platform {
>  	func(has_fbc); \
>  	func(has_fpga_dbg); \
>  	func(has_full_ppgtt); \
> -	func(has_full_48bit_ppgtt); \
>  	func(has_gmch_display); \
>  	func(has_guc); \
>  	func(has_guc_ct); \
> @@ -182,6 +181,9 @@ struct intel_device_info {
>  		u16 degamma_lut_size;
>  		u16 gamma_lut_size;
>  	} color;
> +
> +	/* PPGTT bit size */
> +	int full_ppgtt_bits;
>  };
>  
>  struct intel_driver_caps {
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index def467c2451b..52a86a8c06b7 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
>  	 * PML4 is allocated during ppgtt init, so this is not needed
>  	 * in 48-bit mode.
>  	 */
> -	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
> +	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
>  		execlists_update_context_pdps(ppgtt, reg_state);
>  
>  	return ce->lrc_desc;
> @@ -2019,7 +2019,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>  	 * not needed in 48-bit.*/
>  	if (rq->gem_context->ppgtt &&
>  	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> -	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> +	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
>  	    !intel_vgpu_active(rq->i915)) {
>  		ret = intel_logical_ring_emit_pdps(rq);
>  		if (ret)
> @@ -2688,8 +2688,8 @@ static void execlists_init_reg_state(u32 *regs,
>  	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
>  	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>  
> -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
> -		/* 64b PPGTT (48bit canonical)
> +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
> +		/* > 32b PPGTT
>  		 * PDP0_DESCRIPTOR contains the base address to PML4 and
>  		 * other PDP Descriptors are ignored.
>  		 */
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index e272127783fe..b065630bf672 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
>  	 * huge-gtt-pages.
>  	 */
>  
> -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> -		pr_info("48b PPGTT not supported, skipping\n");
> +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
> +		pr_info("Extended range PPGTT not supported, skipping\n");
>  		return 0;
>  	}
>  
> @@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
>  		goto out_unlock;
>  	}
>  
> -	if (!i915_vm_is_48bit(&ppgtt->vm)) {
> -		pr_err("failed to create 48b PPGTT\n");
> +	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
> +		pr_err("failed to create extended PPGTT\n");
>  		err = -EINVAL;
>  		goto out_close;
>  	}
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 43ed8b28aeaa..33d7225edbbb 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
>  		I915_GTT_PAGE_SIZE_64K |
>  		I915_GTT_PAGE_SIZE_2M;
>  
> +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> +
>  	mock_uncore_init(i915);
>  	i915_gem_init__mm(i915);
>  
> -- 
> 2.14.4
> 
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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4c677e951cdc drm/i915: Make 48bit full ppgtt configuration generic (v3)
-:16: WARNING:TYPO_SPELLING: 'unecessary' may be misspelled - perhaps 'unnecessary'?
#16: 
    Remove unecessary line coninuations (Bob)

-:26: WARNING:BAD_SIGN_OFF: Duplicate signature
#26: 
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>

total: 0 errors, 2 warnings, 0 checks, 255 lines checked

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✗ Fi.CI.SPARSE: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Make 48bit full ppgtt configuration generic (v3)
+drivers/gpu/drm/i915/i915_gem_gtt.c:1652:35: warning: expression using sizeof(void)

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✗ Fi.CI.BAT: failure for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4793 -> Patchwork_10138 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10138 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10138, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10138:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-icl-u:           PASS -> INCOMPLETE

    
    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-hsw-4770r:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10138 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#107425)

    igt@drv_selftest@live_guc:
      fi-skl-guc:         NOTRUN -> DMESG-WARN (fdo#107258)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@kms_psr@primary_page_flip:
      fi-whl-u:           FAIL (fdo#107336) -> PASS

    
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (51 -> 46) ==

  Additional (1): fi-skl-guc 
  Missing    (6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4793 -> Patchwork_10138

  CI_DRM_4793: 8c3078ff800467d16aea5622b2fa325826d167c2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10138: 4c677e951cdc744cbc43b7c1fbbc32561c53bab3 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4c677e951cdc drm/i915: Make 48bit full ppgtt configuration generic (v3)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10138/issues.html
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:

> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> > 
> > Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> > describe that a 4 level walk table extended range PPGTT is being
> > used. Add a new device info field that specifies the number of
> > bits to prepare for cases where the range is not 32 or 48 bits.
> > 
> > v2: keep USES_FULL_PPGTT() unchanged (Chris)
> > v3: Simplify condition in gen8_ppgtt_create() (Chris)
> >     Remove unecessary line coninuations (Bob)
> >     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > CC: Michel Thierry <michel.thierry@intel.com>
> > CC: Chris Wilson <chris@chris-wilson.co.uk>
> > 
> > Additional work to rename 48bit to 4 level  
> 
> Thanks for the additional work.
> Bikeshed on this comment here: Shouldn't this be mentioned on the
> "v3" portion directly instead of the middle of tags' block?

Oops, that was just a rebase squash failure on my part and shouldn't be
there at all. 

> 
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
> >  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
> >  drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
> >  drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
> >  drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
> >  drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
> >  drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
> >  drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
> >  drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
> >  drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  13 files changed, 39 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> > index a4e8e3cf74fd..52bebd67173a 100644
> > --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> > @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> >  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
> >  
> > -	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> > +	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> >  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5a4da5b723fd..a367686fd735 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
> >  #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)  
> 
> another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

I don't have any strong opinion here but can see that "FULL" is a bit
redundant when thinking of this an option/enhancement to FULL_PPGTT.

> 
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >  	GEM_BUG_ON((sizes) == 0); \
> >  	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..1add339ca6be 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
> >  	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> >  
> >  	address_mode = INTEL_LEGACY_32B_CONTEXT;
> > -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> > +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> >  		address_mode = INTEL_LEGACY_64B_CONTEXT;
> >  	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index eb0e446d6482..c66bbf409791 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  			       	int enable_ppgtt)
> >  {
> >  	bool has_full_ppgtt;
> > -	bool has_full_48bit_ppgtt;
> > +	bool has_full_4lvl_ppgtt;
> >  
> >  	if (!dev_priv->info.has_aliasing_ppgtt)
> >  		return 0;
> >  
> >  	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > -	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > +	has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
> >  
> >  	if (intel_vgpu_active(dev_priv)) {
> >  		/* GVT-g has no support for 32bit ppgtt */
> >  		has_full_ppgtt = false;
> > -		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > +		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
> >  	}
> >  
> >  	/*
> > @@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  	if (enable_ppgtt == 2 && has_full_ppgtt)
> >  		return 2;
> >  
> > -	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > +	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	/* Disable ppgtt on SNB if VT-d is on. */
> > @@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >  		return 0;
> >  	}
> >  
> > -	if (has_full_48bit_ppgtt)
> > +	if (has_full_4lvl_ppgtt)
> >  		return 3;
> >  
> >  	if (has_full_ppgtt)
> > @@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> >  	 * page-table operating in 64K mode must point to a properly aligned 64K
> >  	 * region, including any PTEs which happen to point to scratch.
> >  	 *
> > -	 * This is only relevant for the 48b PPGTT where we support
> > +	 * This is only relevant for the 4-level PPGTT where we support
> >  	 * huge-gtt-pages, see also i915_vma_insert().
> >  	 *
> >  	 * TODO: we should really consider write-protecting the scratch-page and
> >  	 * sharing between ppgtt
> >  	 */
> >  	size = I915_GTT_PAGE_SIZE_4K;
> > -	if (i915_vm_is_48bit(vm) &&
> > +	if (i915_vm_is_4lvl(vm) &&
> >  	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
> >  		size = I915_GTT_PAGE_SIZE_64K;
> >  		gfp |= __GFP_NOWARN;
> > @@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
> >  
> >  static inline bool use_4lvl(const struct i915_address_space *vm)
> >  {
> > -	return i915_vm_is_48bit(vm);
> > +	return i915_vm_is_4lvl(vm);
> >  }
> >  
> >  static struct i915_page_directory_pointer *
> > @@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> >  	ppgtt->vm.i915 = i915;
> >  	ppgtt->vm.dma = &i915->drm.pdev->dev;
> >  
> > -	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > -		1ULL << 48 :
> > -		1ULL << 32;
> > +	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
> > +	if (i915_modparams.enable_ppgtt < 3)
> > +		ppgtt->vm.total = min(ppgtt->vm.total, SZ_4G);  
> 
> but actually this is the only real thing that holds me from putting the rv-b
> right now...
> I think this change deserves a separated patch, but maybe it is because
> I simply didn't understand why start using this min SZ_4G and I miss
> some explanation...

This was based on Chris's suggestion. But if it makes more sense to
force it to 32 bit now with:

if (i915_modeparams.enable_ppgtt < 3)
	ppgtt->vm.total = 1ULL << 32

I can make that change.

> 
> The rest of the patch lgtm ;)
> 
> Thanks a lot,
> Rodrigo.
> 
> >  
> >  	/*
> >  	 * From bdw, there is support for read-only pages in the PPGTT.
> > @@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> >  	enum intel_engine_id id;
> >  
> >  	for_each_engine(engine, dev_priv, id) {
> > -		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > +		u32 four_level = USES_FULL_4LVL_PPGTT(dev_priv) ?
> >  				 GEN8_GFX_PPGTT_48B : 0;
> >  		I915_WRITE(RING_MODE_GEN7(engine),
> >  			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > index 7e2af5f4f39b..b2a709a27cb9 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > @@ -363,7 +363,7 @@ struct i915_address_space {
> >  #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> >  
> >  static inline bool
> > -i915_vm_is_48bit(const struct i915_address_space *vm)
> > +i915_vm_is_4lvl(const struct i915_address_space *vm)
> >  {
> >  	return (vm->total - 1) >> 32;
> >  }
> > @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
> >  static inline unsigned int
> >  i915_pdpes_per_pdp(const struct i915_address_space *vm)
> >  {
> > -	if (i915_vm_is_48bit(vm))
> > +	if (i915_vm_is_4lvl(vm))
> >  		return GEN8_PML4ES_PER_PML4;
> >  
> >  	return GEN8_3LVL_PDPES;
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> >  	.has_rc6p = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > +	.full_ppgtt_bits = 32, \
> >  	GEN_DEFAULT_PIPEOFFSETS, \
> >  	GEN_DEFAULT_PAGE_SIZES, \
> >  	IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> >  	.has_hotplug = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32,
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> >  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> > @@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> >  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
> >  		      I915_GTT_PAGE_SIZE_2M, \
> >  	.has_logical_ring_contexts = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_64bit_reloc = 1, \
> >  	.has_reset_engine = 1
> >  
> > @@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
> >  	.has_gmch_display = 1,
> >  	.has_aliasing_ppgtt = 1,
> >  	.has_full_ppgtt = 1,
> > +	.full_ppgtt_bits = 32,
> >  	.has_reset_engine = 1,
> >  	.has_snoop = true,
> >  	.has_coherent_ggtt = false,
> > @@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> >  	.has_guc = 1, \
> >  	.has_aliasing_ppgtt = 1, \
> >  	.has_full_ppgtt = 1, \
> > -	.has_full_48bit_ppgtt = 1, \
> > +	.full_ppgtt_bits = 48, \
> >  	.has_reset_engine = 1, \
> >  	.has_snoop = true, \
> >  	.has_coherent_ggtt = false, \
> > diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> > index eeaa3d506d95..6d2f9f06ab57 100644
> > --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> > +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> > @@ -52,7 +52,7 @@ enum vgt_g2v_type {
> >  /*
> >   * VGT capabilities type
> >   */
> > -#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
> > +#define VGT_CAPS_FULL_4LVL_PPGTT	BIT(2)
> >  #define VGT_CAPS_HWSP_EMULATION		BIT(3)
> >  #define VGT_CAPS_HUGE_GTT		BIT(4)
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> > index 869cf4a3b6de..180f2dca1223 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.c
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> > @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> >  	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> >  }
> >  
> > -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> > +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
> >  {
> > -	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> > +	return dev_priv->vgpu.caps & VGT_CAPS_FULL_4LVL_PPGTT;
> >  }
> >  
> >  struct _balloon_info_ {
> > diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> > index 551acc390046..b830a7b5064f 100644
> > --- a/drivers/gpu/drm/i915/i915_vgpu.h
> > +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> > @@ -28,7 +28,7 @@
> >  
> >  void i915_check_vgpu(struct drm_i915_private *dev_priv);
> >  
> > -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> > +bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
> >  
> >  static inline bool
> >  intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 6eecd64734d5..50acb0463e9a 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -88,7 +88,6 @@ enum intel_platform {
> >  	func(has_fbc); \
> >  	func(has_fpga_dbg); \
> >  	func(has_full_ppgtt); \
> > -	func(has_full_48bit_ppgtt); \
> >  	func(has_gmch_display); \
> >  	func(has_guc); \
> >  	func(has_guc_ct); \
> > @@ -182,6 +181,9 @@ struct intel_device_info {
> >  		u16 degamma_lut_size;
> >  		u16 gamma_lut_size;
> >  	} color;
> > +
> > +	/* PPGTT bit size */
> > +	int full_ppgtt_bits;
> >  };
> >  
> >  struct intel_driver_caps {
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index def467c2451b..52a86a8c06b7 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
> >  	 * PML4 is allocated during ppgtt init, so this is not needed
> >  	 * in 48-bit mode.
> >  	 */
> > -	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
> > +	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
> >  		execlists_update_context_pdps(ppgtt, reg_state);
> >  
> >  	return ce->lrc_desc;
> > @@ -2019,7 +2019,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
> >  	 * not needed in 48-bit.*/
> >  	if (rq->gem_context->ppgtt &&
> >  	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> > -	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> > +	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
> >  	    !intel_vgpu_active(rq->i915)) {
> >  		ret = intel_logical_ring_emit_pdps(rq);
> >  		if (ret)
> > @@ -2688,8 +2688,8 @@ static void execlists_init_reg_state(u32 *regs,
> >  	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
> >  	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
> >  
> > -	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
> > -		/* 64b PPGTT (48bit canonical)
> > +	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
> > +		/* > 32b PPGTT
> >  		 * PDP0_DESCRIPTOR contains the base address to PML4 and
> >  		 * other PDP Descriptors are ignored.
> >  		 */
> > diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > index e272127783fe..b065630bf672 100644
> > --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > @@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
> >  	 * huge-gtt-pages.
> >  	 */
> >  
> > -	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > -		pr_info("48b PPGTT not supported, skipping\n");
> > +	if (!USES_FULL_4LVL_PPGTT(dev_priv)) {
> > +		pr_info("Extended range PPGTT not supported, skipping\n");
> >  		return 0;
> >  	}
> >  
> > @@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
> >  		goto out_unlock;
> >  	}
> >  
> > -	if (!i915_vm_is_48bit(&ppgtt->vm)) {
> > -		pr_err("failed to create 48b PPGTT\n");
> > +	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
> > +		pr_err("failed to create extended PPGTT\n");
> >  		err = -EINVAL;
> >  		goto out_close;
> >  	}
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> >  		I915_GTT_PAGE_SIZE_64K |
> >  		I915_GTT_PAGE_SIZE_2M;
> >  
> > +	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
> > +
> >  	mock_uncore_init(i915);
> >  	i915_gem_init__mm(i915);
> >  
> > -- 
> > 2.14.4
> >   



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-10 18:12:25)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>         .has_rc6p = 1, \
>         .has_aliasing_ppgtt = 1, \
>         .has_full_ppgtt = 1, \
> +       .full_ppgtt_bits = 32, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
>         .has_hotplug = 1,
>         .has_aliasing_ppgtt = 1,
>         .has_full_ppgtt = 1,
> +       .full_ppgtt_bits = 32,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,

To be pedant, .bits = 31 for gen6/7.
-Chris
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> >         .has_rc6p = 1, \
> >         .has_aliasing_ppgtt = 1, \
> >         .has_full_ppgtt = 1, \
> > +       .full_ppgtt_bits = 32, \
> >         GEN_DEFAULT_PIPEOFFSETS, \
> >         GEN_DEFAULT_PAGE_SIZES, \
> >         IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> >         .has_hotplug = 1,
> >         .has_aliasing_ppgtt = 1,
> >         .has_full_ppgtt = 1,
> > +       .full_ppgtt_bits = 32,
> >         .has_snoop = true,
> >         .has_coherent_ggtt = false,
> >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> 
> To be pedant, .bits = 31 for gen6/7.
> -Chris

If I'm reading the code right, these use a different method of setting
the vm.total so won't use the .full_ppgtt_bits.

I don't know enough about this, but would it make sense to modify
gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
31) or maybe just not set .full_ppgtt_bits for those platforms or set
the value correctly and ignore it for now?

Bob

-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-10 21:34:00)
> On Mon, 10 Sep 2018 20:56:51 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
> 
> > Quoting Bob Paauwe (2018-09-10 18:12:25)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index d6f7b9fe1d26..e0619952ff52 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> > >         .has_rc6p = 1, \
> > >         .has_aliasing_ppgtt = 1, \
> > >         .has_full_ppgtt = 1, \
> > > +       .full_ppgtt_bits = 32, \
> > >         GEN_DEFAULT_PIPEOFFSETS, \
> > >         GEN_DEFAULT_PAGE_SIZES, \
> > >         IVB_CURSOR_OFFSETS
> > > @@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
> > >         .has_hotplug = 1,
> > >         .has_aliasing_ppgtt = 1,
> > >         .has_full_ppgtt = 1,
> > > +       .full_ppgtt_bits = 32,
> > >         .has_snoop = true,
> > >         .has_coherent_ggtt = false,
> > >         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> > 
> > To be pedant, .bits = 31 for gen6/7.
> > -Chris
> 
> If I'm reading the code right, these use a different method of setting
> the vm.total so won't use the .full_ppgtt_bits.
> 
> I don't know enough about this, but would it make sense to modify
> gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
> 31) or maybe just not set .full_ppgtt_bits for those platforms or set
> the value correctly and ignore it for now?

One of our goals is to remove the differences where none exist...
-Chris
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[PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change USES_FULL_48BIT_PPGTT() to USES_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

v2: keep USES_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---

Beyond this, there are two follow on patches I'd like to work on:

1) Move parts of gen6_create_ppgtt() and gen8_create_ppgtt() that
   are common into a single function. This will make gen6)_create_ppgtt()
   use the device_info field for number of address bits.

2) Remove enable_ppgtt module parameter.

 drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 24 ++++++++++++------------
 drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c                  |  7 +++++--
 drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c                 |  8 ++++----
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 13 files changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..ab33208e59d6 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ea442033a57..ac86000a1027 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2572,7 +2572,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define USES_4LVL_PPGTT(dev_priv)	((dev_priv)->info.full_ppgtt_bits > 32)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f772593b99ab..561f8e30ea36 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..561a911d09d2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 			       	int enable_ppgtt)
 {
 	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
+	bool has_full_4lvl_ppgtt;
 
 	if (!dev_priv->info.has_aliasing_ppgtt)
 		return 0;
 
 	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+	has_full_4lvl_ppgtt = USES_4LVL_PPGTT(dev_priv);
 
 	if (intel_vgpu_active(dev_priv)) {
 		/* GVT-g has no support for 32bit ppgtt */
 		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+		has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
 	}
 
 	/*
@@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+	if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 		return 3;
 
 	/* Disable ppgtt on SNB if VT-d is on. */
@@ -173,7 +173,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (has_full_48bit_ppgtt)
+	if (has_full_4lvl_ppgtt)
 		return 3;
 
 	if (has_full_ppgtt)
@@ -628,14 +628,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -780,7 +780,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1647,9 +1647,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	ppgtt->vm.total = BIT_ULL(i915->info.full_ppgtt_bits);
+	if (i915_modparams.enable_ppgtt < 3)
+		ppgtt->vm.total = 1ULL << 32;
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
@@ -1788,7 +1788,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
 	enum intel_engine_id id;
 
 	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
+		u32 four_level = USES_4LVL_PPGTT(dev_priv) ?
 				 GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..5f62578224a3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -299,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
+	.full_ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -353,6 +354,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_hotplug = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -445,6 +447,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_gmch_display = 1,
 	.has_aliasing_ppgtt = 1,
 	.has_full_ppgtt = 1,
+	.full_ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -520,7 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_guc = 1, \
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.full_ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..bc7cbdca02aa 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_4LVL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..edf9159f894c 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..b830a7b5064f 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_full_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..50acb0463e9a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -88,7 +88,6 @@ enum intel_platform {
 	func(has_fbc); \
 	func(has_fpga_dbg); \
 	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -182,6 +181,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT bit size */
+	int full_ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b1f0e5211a0..4bc2e86abb50 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -429,7 +429,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && !i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -2027,7 +2027,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not needed in 48-bit.*/
 	if (rq->gem_context->ppgtt &&
 	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2696,8 +2696,8 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
-		/* 64b PPGTT (48bit canonical)
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm)) {
+		/* > 32b PPGTT
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
 		 */
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e272127783fe..b2cbad7f398b 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1434,8 +1434,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!USES_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1708,8 +1708,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..33d7225edbbb 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->full_ppgtt_bits = 48;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-12 17:04:30)
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 43ed8b28aeaa..33d7225edbbb 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
>                 I915_GTT_PAGE_SIZE_64K |
>                 I915_GTT_PAGE_SIZE_2M;
>  
> +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;

Actually the mock ppgtt is 64b.
-Chris
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✓ Fi.CI.BAT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev4)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4813 -> Patchwork_10159 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/4/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10159 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-bdw-samus:       PASS -> INCOMPLETE (fdo#107773)
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       PASS -> DMESG-WARN (fdo#102614)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-cfl-guc:         DMESG-FAIL (fdo#107710) -> PASS

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       DMESG-WARN (fdo#107139, fdo#105128) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107710 https://bugs.freedesktop.org/show_bug.cgi?id=107710
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773


== Participating hosts (51 -> 46) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4813 -> Patchwork_10159

  CI_DRM_4813: 3c13515b12339366b414637b69227a4e3cbe21ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4640: 9a8da36e708f9ed15b20689dfe305e41f9a19008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10159: dcdfffbe599f3e59b296fd9891a9fd36dd9d6104 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

dcdfffbe599f drm/i915: Make 48bit full ppgtt configuration generic (v4)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10159/issues.html
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✓ Fi.CI.IGT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev4)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4813_full -> Patchwork_10159_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10159_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#105363)

    
    ==== Possible fixes ====

    igt@gem_exec_await@wide-contexts:
      shard-glk:          FAIL (fdo#106680) -> PASS

    
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4813 -> Patchwork_10159

  CI_DRM_4813: 3c13515b12339366b414637b69227a4e3cbe21ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4640: 9a8da36e708f9ed15b20689dfe305e41f9a19008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10159: dcdfffbe599f3e59b296fd9891a9fd36dd9d6104 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10159/shards.html
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Bob Paauwe]

On Wed, 12 Sep 2018 17:10:58 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Quoting Bob Paauwe (2018-09-12 17:04:30)
> > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > index 43ed8b28aeaa..33d7225edbbb 100644
> > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> >                 I915_GTT_PAGE_SIZE_64K |
> >                 I915_GTT_PAGE_SIZE_2M;
> >  
> > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;  
> 
> Actually the mock ppgtt is 64b.
> -Chris

Setting it 64 bit causes mock_hugepages to fail. I don't believe the
current driver code ever uses anything other than 32 or 48 bit so this
may mean there's a bug somewhere if we go over 48 bit.

Bob
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Ville Syrjälä]

On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> On Wed, 12 Sep 2018 17:10:58 +0100
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
> 
> > Quoting Bob Paauwe (2018-09-12 17:04:30)
> > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > index 43ed8b28aeaa..33d7225edbbb 100644
> > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> > >                 I915_GTT_PAGE_SIZE_64K |
> > >                 I915_GTT_PAGE_SIZE_2M;
> > >  
> > > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;  
> > 
> > Actually the mock ppgtt is 64b.
> > -Chris
> 
> Setting it 64 bit causes mock_hugepages to fail.

1<<64 somewhere?

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Bob Paauwe]

On Thu, 13 Sep 2018 20:05:54 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> > On Wed, 12 Sep 2018 17:10:58 +0100
> > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >   
> > > Quoting Bob Paauwe (2018-09-12 17:04:30)  
> > > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > index 43ed8b28aeaa..33d7225edbbb 100644
> > > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> > > >                 I915_GTT_PAGE_SIZE_64K |
> > > >                 I915_GTT_PAGE_SIZE_2M;
> > > >  
> > > > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;    
> > > 
> > > Actually the mock ppgtt is 64b.
> > > -Chris  
> > 
> > Setting it 64 bit causes mock_hugepages to fail.  
> 
> 1<<64 somewhere?
> 

Doh, yeah, there is that. So what does 64b mean for ppgtt->vm.total?
Should it really be 63b?


--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Ville Syrjälä]

On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> On Thu, 13 Sep 2018 20:05:54 +0300
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> 
> > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:
> > > On Wed, 12 Sep 2018 17:10:58 +0100
> > > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >   
> > > > Quoting Bob Paauwe (2018-09-12 17:04:30)  
> > > > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > index 43ed8b28aeaa..33d7225edbbb 100644
> > > > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> > > > >                 I915_GTT_PAGE_SIZE_64K |
> > > > >                 I915_GTT_PAGE_SIZE_2M;
> > > > >  
> > > > > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;    
> > > > 
> > > > Actually the mock ppgtt is 64b.
> > > > -Chris  
> > > 
> > > Setting it 64 bit causes mock_hugepages to fail.  
> > 
> > 1<<64 somewhere?
> > 
> 
> Doh, yeah, there is that. So what does 64b mean for ppgtt->vm.total?
> Should it really be 63b?

GENMASK() & ~(GTT_PAGE_SIZE-1) maybe?

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Bob Paauwe]

On Thu, 13 Sep 2018 20:22:14 +0300
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> > On Thu, 13 Sep 2018 20:05:54 +0300
> > Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >   
> > > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:  
> > > > On Wed, 12 Sep 2018 17:10:58 +0100
> > > > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > >     
> > > > > Quoting Bob Paauwe (2018-09-12 17:04:30)    
> > > > > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > index 43ed8b28aeaa..33d7225edbbb 100644
> > > > > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> > > > > >                 I915_GTT_PAGE_SIZE_64K |
> > > > > >                 I915_GTT_PAGE_SIZE_2M;
> > > > > >  
> > > > > > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;      
> > > > > 
> > > > > Actually the mock ppgtt is 64b.
> > > > > -Chris    
> > > > 
> > > > Setting it 64 bit causes mock_hugepages to fail.    
> > > 
> > > 1<<64 somewhere?
> > >   
> > 
> > Doh, yeah, there is that. So what does 64b mean for ppgtt->vm.total?
> > Should it really be 63b?  
> 
> GENMASK() & ~(GTT_PAGE_SIZE-1) maybe?

This seems to be getting somewhat outside the scope of this patch, but
I did some experimenting and tried to get a better understanding of
how the ppgtt-vm.total value is used.

The hugepages selftest will work if this is set to 1 << 63 for the mock
device. It also seems to work if I do something like what Ville
suggests and set it to ((1 << 64) - 1) & ~(I915_GTT_PAGE_SIZE - 1)
which, if I don't typo it, is 0xfffffffffffff000.

So I could change the way ppgtt->vm.total is set to something like:

GENMASK_ULL(bits - 1, 0) & ~(I915_GTT_PAGE_SIZE - 1)

and it would set it to a slightly smaller value than what we do now, but
even if that passes the regression tests, it is a change in behavior
and I don't think that should be part of this patch.

My preference would be to leave the mock device configured to 48 bits
since that what it has been using.  If it's important to actually test
larger values, that could be a separate change to the mock device.

Bob

--
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[PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v6)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

v2: keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: mock device is 64b(63b) not 48b (Chris)
v6: rebase to latest drm-tip (Bob)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
 drivers/gpu/drm/i915/i915_drv.c                  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 10 ++++------
 drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c                  |  5 +++++
 drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c                 |  6 +++---
 drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 14 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1b028f429e92..3b4852a89441 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1365,7 +1365,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30191523c309..54a44270d350 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2602,7 +2602,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 15c92f75b1b8..5de54ae949c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 29ca9007a704..06a91f67bc14 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1598,9 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
+	ppgtt->vm.total = BIT_ULL(i915->info.ppgtt_bits);
 
 	/*
 	 * From bdw, there is support for read-only pages in the PPGTT.
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9ddd2db906ce..acc33504ece0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -298,6 +298,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,6 +352,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -398,6 +400,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -442,6 +445,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,6 +522,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..bc7cbdca02aa 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_4LVL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..4ecb4d6e67f8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..1b14d7df324b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,6 +189,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* PPGTT address limit */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 15345e74d8ce..b88951592bc3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -424,7 +424,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -2050,7 +2050,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2722,7 +2722,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 09ea65a29d98..60b012781002 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,8 +1436,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1709,8 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v4)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-14 16:51:34)
> On Thu, 13 Sep 2018 20:22:14 +0300
> Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> 
> > On Thu, Sep 13, 2018 at 10:12:06AM -0700, Bob Paauwe wrote:
> > > On Thu, 13 Sep 2018 20:05:54 +0300
> > > Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > >   
> > > > On Thu, Sep 13, 2018 at 10:02:57AM -0700, Bob Paauwe wrote:  
> > > > > On Wed, 12 Sep 2018 17:10:58 +0100
> > > > > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > > >     
> > > > > > Quoting Bob Paauwe (2018-09-12 17:04:30)    
> > > > > > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > > index 43ed8b28aeaa..33d7225edbbb 100644
> > > > > > > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> > > > > > > @@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
> > > > > > >                 I915_GTT_PAGE_SIZE_64K |
> > > > > > >                 I915_GTT_PAGE_SIZE_2M;
> > > > > > >  
> > > > > > > +       mkwrite_device_info(i915)->full_ppgtt_bits = 48;      
> > > > > > 
> > > > > > Actually the mock ppgtt is 64b.
> > > > > > -Chris    
> > > > > 
> > > > > Setting it 64 bit causes mock_hugepages to fail.    
> > > > 
> > > > 1<<64 somewhere?
> > > >   
> > > 
> > > Doh, yeah, there is that. So what does 64b mean for ppgtt->vm.total?
> > > Should it really be 63b?  
> > 
> > GENMASK() & ~(GTT_PAGE_SIZE-1) maybe?
> 
> This seems to be getting somewhat outside the scope of this patch, but
> I did some experimenting and tried to get a better understanding of
> how the ppgtt-vm.total value is used.
> 
> The hugepages selftest will work if this is set to 1 << 63 for the mock
> device. It also seems to work if I do something like what Ville
> suggests and set it to ((1 << 64) - 1) & ~(I915_GTT_PAGE_SIZE - 1)
> which, if I don't typo it, is 0xfffffffffffff000.
> 
> So I could change the way ppgtt->vm.total is set to something like:
> 
> GENMASK_ULL(bits - 1, 0) & ~(I915_GTT_PAGE_SIZE - 1)
> 
> and it would set it to a slightly smaller value than what we do now, but
> even if that passes the regression tests, it is a change in behavior
> and I don't think that should be part of this patch.
> 
> My preference would be to leave the mock device configured to 48 bits
> since that what it has been using.

The mock device was intentionally meant to be testing the full range
that the driver supports, not the hw. (That it has to be limited to fit
in memory is another matter for some tests.)
-Chris
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v6)

[Chris Wilson]

Quoting Bob Paauwe (2018-10-02 18:39:14)
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> Also rename other functions and comments from 48bit to 4-level.
> 
> v2: keep HAS_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
>     Remove unnecessary line coninuations (Bob)
>     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
>     Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
>     Gen 7 is 31 bits, not 32 (Chris)
> v5: mock device is 64b(63b) not 48b (Chris)
> v6: rebase to latest drm-tip (Bob)
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c                  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.c                  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c          |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c              | 10 ++++------
>  drivers/gpu/drm/i915/i915_gem_gtt.h              |  4 ++--
>  drivers/gpu/drm/i915/i915_pci.c                  |  5 +++++
>  drivers/gpu/drm/i915/i915_pvinfo.h               |  2 +-
>  drivers/gpu/drm/i915/i915_vgpu.c                 |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.h                 |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.h         |  3 +++
>  drivers/gpu/drm/i915/intel_lrc.c                 |  6 +++---
>  drivers/gpu/drm/i915/selftests/huge_pages.c      |  8 ++++----
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  14 files changed, 31 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index c628be05fbfe..6002ded0042b 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
>         vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
>         vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>  
> -       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> +       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
>         vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
>         vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1b028f429e92..3b4852a89441 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1365,7 +1365,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  
>         if (HAS_PPGTT(dev_priv)) {
>                 if (intel_vgpu_active(dev_priv) &&
> -                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> +                   !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
>                         i915_report_error(dev_priv,
>                                           "incompatible vGPU found, support for isolated ppGTT required\n");
>                         return -ENXIO;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 30191523c309..54a44270d350 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2602,7 +2602,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
>  #define HAS_FULL_PPGTT(dev_priv) \
>         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> -#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> +#define HAS_4LVL_PPGTT(dev_priv)       \
>         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
>  
>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 15c92f75b1b8..5de54ae949c3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
>         desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>  
>         address_mode = INTEL_LEGACY_32B_CONTEXT;
> -       if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> +       if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
>                 address_mode = INTEL_LEGACY_64B_CONTEXT;
>         desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 29ca9007a704..06a91f67bc14 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
>          * page-table operating in 64K mode must point to a properly aligned 64K
>          * region, including any PTEs which happen to point to scratch.
>          *
> -        * This is only relevant for the 48b PPGTT where we support
> +        * This is only relevant for the 4-level PPGTT where we support
>          * huge-gtt-pages, see also i915_vma_insert().
>          *
>          * TODO: we should really consider write-protecting the scratch-page and
>          * sharing between ppgtt
>          */
>         size = I915_GTT_PAGE_SIZE_4K;
> -       if (i915_vm_is_48bit(vm) &&
> +       if (i915_vm_is_4lvl(vm) &&
>             HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
>                 size = I915_GTT_PAGE_SIZE_64K;
>                 gfp |= __GFP_NOWARN;
> @@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
>  
>  static inline bool use_4lvl(const struct i915_address_space *vm)
>  {
> -       return i915_vm_is_48bit(vm);
> +       return i915_vm_is_4lvl(vm);
>  }
>  
>  static struct i915_page_directory_pointer *
> @@ -1598,9 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>         ppgtt->vm.i915 = i915;
>         ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> -               1ULL << 48 :
> -               1ULL << 32;
> +       ppgtt->vm.total = BIT_ULL(i915->info.ppgtt_bits);
>  
>         /*
>          * From bdw, there is support for read-only pages in the PPGTT.
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 7e2af5f4f39b..b2a709a27cb9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -363,7 +363,7 @@ struct i915_address_space {
>  #define i915_is_ggtt(vm) ((vm)->is_ggtt)
>  
>  static inline bool
> -i915_vm_is_48bit(const struct i915_address_space *vm)
> +i915_vm_is_4lvl(const struct i915_address_space *vm)
>  {
>         return (vm->total - 1) >> 32;
>  }
> @@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
>  static inline unsigned int
>  i915_pdpes_per_pdp(const struct i915_address_space *vm)
>  {
> -       if (i915_vm_is_48bit(vm))
> +       if (i915_vm_is_4lvl(vm))
>                 return GEN8_PML4ES_PER_PML4;
>  
>         return GEN8_3LVL_PDPES;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9ddd2db906ce..acc33504ece0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -298,6 +298,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>         .has_rc6 = 1, \
>         .has_rc6p = 1, \
>         .ppgtt = INTEL_PPGTT_FULL, \
> +       .ppgtt_bits = 31, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         IVB_CURSOR_OFFSETS
> @@ -351,6 +352,7 @@ static const struct intel_device_info intel_valleyview_info = {
>         .has_gmch_display = 1,
>         .has_hotplug = 1,
>         .ppgtt = INTEL_PPGTT_FULL,
> +       .ppgtt_bits = 31,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -398,6 +400,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>                       I915_GTT_PAGE_SIZE_2M, \
>         .has_logical_ring_contexts = 1, \
>         .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> +       .ppgtt_bits = 48, \
>         .has_64bit_reloc = 1, \
>         .has_reset_engine = 1
>  
> @@ -442,6 +445,7 @@ static const struct intel_device_info intel_cherryview_info = {
>         .has_logical_ring_contexts = 1,
>         .has_gmch_display = 1,
>         .ppgtt = INTEL_PPGTT_FULL,
> +       .ppgtt_bits = 32,
>         .has_reset_engine = 1,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
> @@ -518,6 +522,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>         .has_logical_ring_preemption = 1, \
>         .has_guc = 1, \
>         .ppgtt = INTEL_PPGTT_FULL_4LVL, \

You appear to have only written half the patch.

> +       .ppgtt_bits = 48, \
>         .has_reset_engine = 1, \
>         .has_snoop = true, \
>         .has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..bc7cbdca02aa 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
>  /*
>   * VGT capabilities type
>   */
> -#define VGT_CAPS_FULL_48BIT_PPGTT      BIT(2)
> +#define VGT_CAPS_4LVL_PPGTT            BIT(2)
>  #define VGT_CAPS_HWSP_EMULATION                BIT(3)
>  #define VGT_CAPS_HUGE_GTT              BIT(4)
>  
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..4ecb4d6e67f8 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>         DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
>  }
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
>  {
> -       return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> +       return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
>  }
>  
>  struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..5265b6357fba 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>  
>  void i915_check_vgpu(struct drm_i915_private *dev_priv);
>  
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
>  
>  static inline bool
>  intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index af7002640cdf..1b14d7df324b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -189,6 +189,9 @@ struct intel_device_info {
>                 u16 degamma_lut_size;
>                 u16 gamma_lut_size;
>         } color;
> +
> +       /* PPGTT address limit */
> +       int ppgtt_bits;

Comment doesn't help very much, should be associated with the
ppgtt_type.
-Chris
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✗ Fi.CI.SPARSE: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev5)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Make 48bit full ppgtt configuration generic (v6)
+drivers/gpu/drm/i915/i915_gem_gtt.c:3480:34: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:3480:34: warning: expression using sizeof(void)

_______________________________________________
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✓ Fi.CI.BAT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev5)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4915 -> Patchwork_10327 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10327 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10327, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10327:

  === IGT changes ===

    ==== Warnings ====

    igt@drv_selftest@live_guc:
      fi-glk-j4005:       SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10327 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-kbl-7560u:       PASS -> INCOMPLETE (fdo#108044)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_coherency:
      fi-gdg-551:         DMESG-FAIL (fdo#107164) -> PASS

    igt@drv_selftest@live_execlists:
      fi-glk-j4005:       INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-skl-guc:         FAIL (fdo#103191) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (46 -> 43) ==

  Missing    (3): fi-bsw-cyan fi-byt-squawks fi-icl-u2 


== Build changes ==

    * Linux: CI_DRM_4915 -> Patchwork_10327

  CI_DRM_4915: 26e7a7d954a9c28b97af8ca7813f430fd9117232 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4660: d0975646c50568e66e65b44b81d28232d059b94e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10327: 2aa31655991f71141ddda3d1b7ffd252e3a72f78 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2aa31655991f drm/i915: Make 48bit full ppgtt configuration generic (v6)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10327/issues.html
_______________________________________________
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✗ Fi.CI.IGT: failure for drm/i915: Rename full ppgtt configuration to be more generic (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev5)
URL   : https://patchwork.freedesktop.org/series/49021/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4915_full -> Patchwork_10327_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10327_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10327_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10327_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          PASS -> FAIL

    {igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
      shard-skl:          NOTRUN -> FAIL

    
== Known issues ==

  Here are the changes found in Patchwork_10327_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106886)

    igt@gem_exec_await@wide-contexts:
      shard-skl:          PASS -> FAIL (fdo#106680)

    igt@gem_exec_big:
      shard-hsw:          PASS -> TIMEOUT (fdo#107937)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-skl:          NOTRUN -> FAIL (fdo#103158)

    igt@gem_workarounds@suspend-resume:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#104108)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)
      shard-kbl:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_crc@cursor-64x21-sliding:
      shard-apl:          PASS -> FAIL (fdo#103232)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
      shard-apl:          PASS -> FAIL (fdo#103167) +2

    igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_setmode@basic:
      shard-snb:          NOTRUN -> FAIL (fdo#99912)

    igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
      shard-apl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +9

    igt@pm_rpm@basic-rte:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807)

    igt@pm_rpm@gem-execbuf:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807, fdo#107803)

    igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
      shard-skl:          SKIP -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@kms_ccs@pipe-b-missing-ccs-buffer:
      shard-kbl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +14

    igt@kms_chv_cursor_fail@pipe-a-256x256-top-edge:
      shard-skl:          FAIL (fdo#104671) -> PASS

    igt@kms_color@pipe-b-ctm-max:
      shard-apl:          FAIL -> PASS +1

    igt@kms_cursor_crc@cursor-256x85-onscreen:
      shard-apl:          FAIL (fdo#103232) -> PASS +3

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-apl:          FAIL (fdo#103191, fdo#103232) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-apl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
      shard-skl:          FAIL (fdo#103167) -> PASS +2

    igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
      shard-skl:          FAIL (fdo#105682) -> PASS

    igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
      shard-skl:          FAIL (fdo#103167) -> SKIP

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      shard-skl:          FAIL (fdo#103191) -> PASS

    igt@kms_plane@plane-panning-top-left-pipe-a-planes:
      shard-skl:          FAIL (fdo#103166) -> PASS

    {igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
      shard-skl:          FAIL -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107803 https://bugs.freedesktop.org/show_bug.cgi?id=107803
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing    (1): shard-glk 


== Build changes ==

    * Linux: CI_DRM_4915 -> Patchwork_10327

  CI_DRM_4915: 26e7a7d954a9c28b97af8ca7813f430fd9117232 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4660: d0975646c50568e66e65b44b81d28232d059b94e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10327: 2aa31655991f71141ddda3d1b7ffd252e3a72f78 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10327/shards.html
_______________________________________________
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Rename full ppgtt configuration to be more generic (rev5)

[Martin Peres]

On 03/10/2018 11:29, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Rename full ppgtt configuration to be more generic (rev5)
> URL   : https://patchwork.freedesktop.org/series/49021/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_4915_full -> Patchwork_10327_full =
> 
> == Summary - FAILURE ==
> 
>   Serious unknown changes coming with Patchwork_10327_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_10327_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> == Possible new issues ==
> 
>   Here are the unknown changes that may have been introduced in Patchwork_10327_full:
> 
>   === IGT changes ===
> 
>     ==== Possible regressions ====
> 
>     igt@kms_color@pipe-a-ctm-max:
>       shard-apl:          PASS -> FAIL

Known issue: https://bugs.freedesktop.org/show_bug.cgi?id=108147

Martin

> 
>     {igt@kms_plane_alpha_blend@pipe-b-coverage-7efc}:
>       shard-skl:          NOTRUN -> FAIL
> 
>     
> == Known issues ==
> 
>   Here are the changes found in Patchwork_10327_full that come from known issues:
> 
>   === IGT changes ===
> 
>     ==== Issues hit ====
> 
>     igt@drv_suspend@shrink:
>       shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106886)
> 
>     igt@gem_exec_await@wide-contexts:
>       shard-skl:          PASS -> FAIL (fdo#106680)
> 
>     igt@gem_exec_big:
>       shard-hsw:          PASS -> TIMEOUT (fdo#107937)
> 
>     igt@gem_exec_schedule@pi-ringfull-bsd:
>       shard-skl:          NOTRUN -> FAIL (fdo#103158)
> 
>     igt@gem_workarounds@suspend-resume:
>       shard-skl:          NOTRUN -> INCOMPLETE (fdo#104108)
> 
>     igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
>       shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)
>       shard-kbl:          PASS -> DMESG-WARN (fdo#107956)
> 
>     igt@kms_cursor_crc@cursor-64x21-sliding:
>       shard-apl:          PASS -> FAIL (fdo#103232)
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
>       shard-apl:          PASS -> FAIL (fdo#103167) +2
> 
>     igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
>       shard-apl:          PASS -> FAIL (fdo#103166)
> 
>     igt@kms_setmode@basic:
>       shard-snb:          NOTRUN -> FAIL (fdo#99912)
> 
>     igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
>       shard-apl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +9
> 
>     igt@pm_rpm@basic-rte:
>       shard-skl:          PASS -> INCOMPLETE (fdo#107807)
> 
>     igt@pm_rpm@gem-execbuf:
>       shard-skl:          PASS -> INCOMPLETE (fdo#107807, fdo#107803)
> 
>     igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
>       shard-skl:          SKIP -> INCOMPLETE (fdo#107807)
> 
>     
>     ==== Possible fixes ====
> 
>     igt@kms_ccs@pipe-b-missing-ccs-buffer:
>       shard-kbl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +14
> 
>     igt@kms_chv_cursor_fail@pipe-a-256x256-top-edge:
>       shard-skl:          FAIL (fdo#104671) -> PASS
> 
>     igt@kms_color@pipe-b-ctm-max:
>       shard-apl:          FAIL -> PASS +1
> 
>     igt@kms_cursor_crc@cursor-256x85-onscreen:
>       shard-apl:          FAIL (fdo#103232) -> PASS +3
> 
>     igt@kms_cursor_crc@cursor-64x64-suspend:
>       shard-apl:          FAIL (fdo#103191, fdo#103232) -> PASS
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
>       shard-apl:          FAIL (fdo#103167) -> PASS +1
> 
>     igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
>       shard-skl:          FAIL (fdo#103167) -> PASS +2
> 
>     igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
>       shard-skl:          FAIL (fdo#105682) -> PASS
> 
>     igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
>       shard-skl:          FAIL (fdo#103167) -> SKIP
> 
>     igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
>       shard-skl:          FAIL (fdo#103191) -> PASS
> 
>     igt@kms_plane@plane-panning-top-left-pipe-a-planes:
>       shard-skl:          FAIL (fdo#103166) -> PASS
> 
>     {igt@kms_plane_alpha_blend@pipe-a-coverage-7efc}:
>       shard-skl:          FAIL -> PASS
> 
>     igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
>       shard-apl:          FAIL (fdo#103166) -> PASS +1
> 
>     igt@kms_setmode@basic:
>       shard-apl:          FAIL (fdo#99912) -> PASS
>       shard-kbl:          FAIL (fdo#99912) -> PASS
> 
>     
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
>   fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
>   fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
>   fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
>   fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
>   fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
>   fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
>   fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
>   fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
>   fdo#107803 https://bugs.freedesktop.org/show_bug.cgi?id=107803
>   fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
>   fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937
>   fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
>   fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> == Participating hosts (6 -> 5) ==
> 
>   Missing    (1): shard-glk 
> 
> 
> == Build changes ==
> 
>     * Linux: CI_DRM_4915 -> Patchwork_10327
> 
>   CI_DRM_4915: 26e7a7d954a9c28b97af8ca7813f430fd9117232 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4660: d0975646c50568e66e65b44b81d28232d059b94e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_10327: 2aa31655991f71141ddda3d1b7ffd252e3a72f78 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10327/shards.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
_______________________________________________
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[PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v7)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.

v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
    Improve comment on device info field (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---

Chris, is this what you were looking for WRT handling GEN6/7? 

 drivers/gpu/drm/i915/gvt/vgpu.c                  |   2 +-
 drivers/gpu/drm/i915/i915_drv.c                  |   2 +-
 drivers/gpu/drm/i915/i915_drv.h                  |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c          |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c              | 139 ++++++++++-------------
 drivers/gpu/drm/i915/i915_gem_gtt.h              |   4 +-
 drivers/gpu/drm/i915/i915_pci.c                  |   6 +
 drivers/gpu/drm/i915/i915_pvinfo.h               |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c                 |   4 +-
 drivers/gpu/drm/i915/i915_vgpu.h                 |   2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |   3 +
 drivers/gpu/drm/i915/intel_lrc.c                 |   6 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c      |   8 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |   2 +
 14 files changed, 89 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1b028f429e92..3b4852a89441 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1365,7 +1365,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 30191523c309..54a44270d350 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2602,7 +2602,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 15c92f75b1b8..5de54ae949c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 29ca9007a704..2f603ce94ad4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1584,42 +1584,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
  * space.
  *
  */
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
 {
-	struct i915_hw_ppgtt *ppgtt;
+	struct drm_i915_private *i915 = ppgtt->vm.i915;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->ref);
-
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
-
-	/*
-	 * From bdw, there is support for read-only pages in the PPGTT.
-	 *
-	 * XXX GVT is not honouring the lack of RW in the PTE bits.
-	 */
-	ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
-
-	i915_address_space_init(&ppgtt->vm, i915);
-
-	/* There are only few exceptions for gen >=6. chv and bxt.
-	 * And we are not sure about the latter so play safe for now.
-	 */
-	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
-
 	err = gen8_init_scratch(&ppgtt->vm);
 	if (err)
-		goto err_free;
+		return err;
 
 	if (use_4lvl(&ppgtt->vm)) {
 		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1643,7 +1615,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 				goto err_scratch;
 			}
 		}
-
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1655,18 +1626,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
-	return ppgtt;
+	return 0;
 
 err_scratch:
 	gen8_free_scratch(&ppgtt->vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return err;
 }
 
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
@@ -2087,55 +2051,31 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
 	i915_vma_unpin(ppgtt->vma);
 }
 
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+			     struct i915_ggtt * const ggtt)
 {
-	struct i915_ggtt * const ggtt = &i915->ggtt;
-	struct gen6_hw_ppgtt *ppgtt;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->base.ref);
-
-	ppgtt->base.vm.i915 = i915;
-	ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
-	i915_address_space_init(&ppgtt->base.vm, i915);
-
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.debug_dump = gen6_dump_ppgtt;
 
-	ppgtt->base.vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->base.vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->base.vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 
 	err = gen6_ppgtt_init_scratch(ppgtt);
 	if (err)
-		goto err_free;
+		return err;
 
 	ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 	if (IS_ERR(ppgtt->vma)) {
 		err = PTR_ERR(ppgtt->vma);
-		goto err_scratch;
+		gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+		return err;
 	}
 
-	return &ppgtt->base;
-
-err_scratch:
-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return 0;
 }
 
 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2187,10 +2127,53 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 static struct i915_hw_ppgtt *
 __hw_ppgtt_create(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) < 8)
-		return gen6_ppgtt_create(i915);
-	else
-		return gen8_ppgtt_create(i915);
+	struct gen6_hw_ppgtt *ppgtt;
+	struct i915_address_space *vm;
+	int err;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+
+	vm = &ppgtt->base.vm;
+
+	kref_init(&ppgtt->base.ref);
+
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+
+	vm->total = BIT_ULL(i915->info.ppgtt_bits);
+
+	/*
+	 * From bdw, there is support for read-only pages in the PPGTT.
+	 *
+	 * XXX GVT is not honoring the lack of RW in the PTE bits.
+	 */
+	vm->has_read_only =
+		(INTEL_GEN(i915) < 8) ? false :!intel_vgpu_active(i915);
+
+	i915_address_space_init(vm, i915);
+
+	/* There are only few exceptions for gen >= 6. chv and bxt.
+	 * And we are not sure abou the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+		vm->pt_kmap_wc = true;
+
+	err = (INTEL_GEN(i915) < 8) ?  gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+		gen8_ppgtt_create(&ppgtt->base);
+
+	if (err) {
+		kfree(ppgtt);
+		return ERR_PTR(err);
+	}
+
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
+
+	return &ppgtt->base;
 }
 
 struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9ddd2db906ce..07d77d2e79d8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -253,6 +253,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_ALIASING, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -298,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,6 +353,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -398,6 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -442,6 +446,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,6 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..bc7cbdca02aa 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_4LVL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..4ecb4d6e67f8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..4980da8ccfc3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,6 +189,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* Full PPGTT address range size */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 15345e74d8ce..b88951592bc3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -424,7 +424,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -2050,7 +2050,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2722,7 +2722,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 09ea65a29d98..60b012781002 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,8 +1436,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1709,8 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.14.4

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev6)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bcd9b888d547 drm/i915: Make 48bit full ppgtt configuration generic (v7)
-:286: ERROR:SPACING: spaces required around that ':' (ctx:WxO)
#286: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:2153:
+		(INTEL_GEN(i915) < 8) ? false :!intel_vgpu_active(i915);
 		                              ^

-:286: ERROR:SPACING: space required before that '!' (ctx:OxV)
#286: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:2153:
+		(INTEL_GEN(i915) < 8) ? false :!intel_vgpu_active(i915);
 		                               ^

total: 2 errors, 0 warnings, 0 checks, 392 lines checked

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✗ Fi.CI.SPARSE: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev6)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Make 48bit full ppgtt configuration generic (v7)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev6)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4950 -> Patchwork_10391 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10391 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10391, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10391:

  === IGT changes ===

    ==== Warnings ====

    igt@drv_selftest@live_requests:
      fi-bxt-j4205:       PASS -> SKIP +14

    
== Known issues ==

  Here are the changes found in Patchwork_10391 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-bxt-j4205:       SKIP -> TIMEOUT (fdo#108075) +1

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       NOTRUN -> INCOMPLETE (fdo#107718)

    igt@gem_exec_suspend@basic-s3:
      fi-cfl-8109u:       PASS -> DMESG-WARN (fdo#107345) +2
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE (fdo#107556, fdo#107859, fdo#107774)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-cfl-8109u:       PASS -> INCOMPLETE (fdo#108126, fdo#106070)

    igt@pm_rpm@module-reload:
      fi-bxt-j4205:       PASS -> FAIL (fdo#107712)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       DMESG-WARN (fdo#105128, fdo#107139) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-hsw-4770r:       DMESG-WARN (fdo#105602) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107712 https://bugs.freedesktop.org/show_bug.cgi?id=107712
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
  fdo#108075 https://bugs.freedesktop.org/show_bug.cgi?id=108075
  fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126


== Participating hosts (50 -> 45) ==

  Additional (1): fi-kbl-soraka 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4950 -> Patchwork_10391

  CI_DRM_4950: a9abc43bebfb6de62c2c3747a22fadfa17b61d8b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4671: b121f7d42c260ae3a050c3f440d1c11f7cff7d1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10391: bcd9b888d547f6f6d8c03194e0c337bb09cc5863 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bcd9b888d547 drm/i915: Make 48bit full ppgtt configuration generic (v7)

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10391/issues.html
_______________________________________________
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✓ Fi.CI.IGT: success for drm/i915: Rename full ppgtt configuration to be more generic (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev6)
URL   : https://patchwork.freedesktop.org/series/49021/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4950_full -> Patchwork_10391_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10391_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10391_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10391_full:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10391_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_cpu_reloc@full:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#108073)

    igt@gem_exec_big:
      shard-hsw:          PASS -> TIMEOUT (fdo#107937)

    igt@kms_atomic@atomic_invalid_params:
      shard-apl:          PASS -> DMESG-WARN (fdo#103558, fdo#105602) +5

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          PASS -> FAIL (fdo#106641)

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-glk:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-64x21-random:
      shard-apl:          PASS -> FAIL (fdo#103232) +4

    igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
      shard-glk:          NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133)

    igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
      shard-apl:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
      shard-glk:          PASS -> FAIL (fdo#103167) +2

    {igt@kms_plane_alpha_blend@pipe-c-alpha-basic}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_rotation_crc@primary-rotation-180:
      shard-kbl:          PASS -> DMESG-WARN (fdo#103558, fdo#105602) +10

    igt@pm_rpm@debugfs-forcewake-user:
      shard-skl:          PASS -> INCOMPLETE (fdo#107807)

    igt@pm_rpm@gem-execbuf:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#107803, fdo#107807)

    
    ==== Possible fixes ====

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
      shard-hsw:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_color@pipe-a-legacy-gamma:
      shard-apl:          FAIL (fdo#104782, fdo#108145) -> PASS

    igt@kms_color@pipe-b-legacy-gamma:
      shard-apl:          FAIL (fdo#104782) -> PASS

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
      shard-skl:          FAIL (fdo#103184) -> PASS

    igt@kms_flip@2x-flip-vs-rmfb-interruptible:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-skl:          FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
      shard-skl:          FAIL (fdo#103167) -> PASS +2

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
      shard-apl:          FAIL (fdo#103167) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +6

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
      shard-skl:          INCOMPLETE (fdo#104108) -> PASS

    {igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb}:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          FAIL (fdo#103166) -> PASS +2
      shard-apl:          FAIL (fdo#103166) -> PASS +1

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    
    ==== Warnings ====

    igt@kms_frontbuffer_tracking@fbc-1p-rte:
      shard-apl:          FAIL (fdo#105682, fdo#103167) -> DMESG-WARN (fdo#103558, fdo#108131)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#107803 https://bugs.freedesktop.org/show_bug.cgi?id=107803
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107937 https://bugs.freedesktop.org/show_bug.cgi?id=107937
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
  fdo#108131 https://bugs.freedesktop.org/show_bug.cgi?id=108131
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4950 -> Patchwork_10391

  CI_DRM_4950: a9abc43bebfb6de62c2c3747a22fadfa17b61d8b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4671: b121f7d42c260ae3a050c3f440d1c11f7cff7d1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10391: bcd9b888d547f6f6d8c03194e0c337bb09cc5863 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10391/shards.html
_______________________________________________
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Re: [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v7)

[Chris Wilson]

Quoting Bob Paauwe (2018-10-08 19:14:06)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 30191523c309..54a44270d350 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2602,7 +2602,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
>  #define HAS_FULL_PPGTT(dev_priv) \
>         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> -#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> +#define HAS_4LVL_PPGTT(dev_priv)       \
>         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)

Keep going, your job here is to eliminate INTEL_PPGTT_FULL_4LVL.
-Chris
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[PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v7)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.

v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
    Improve comment on device info field (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gvt/vgpu.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c       |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 139 ++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   4 +-
 drivers/gpu/drm/i915/i915_pci.c               |   6 +
 drivers/gpu/drm/i915/i915_pvinfo.h            |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |   4 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   3 +
 drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |   8 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +
 15 files changed, 90 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6571044c9286..393e89e2b309 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1367,7 +1367,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..b109fc0c29be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,7 +2587,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..1853e82cebd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1eb1ed2..e818d3c00bba 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1584,42 +1584,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
  * space.
  *
  */
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
 {
-	struct i915_hw_ppgtt *ppgtt;
+	struct drm_i915_private *i915 = ppgtt->vm.i915;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->ref);
-
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
-
-	/*
-	 * From bdw, there is support for read-only pages in the PPGTT.
-	 *
-	 * XXX GVT is not honouring the lack of RW in the PTE bits.
-	 */
-	ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
-
-	i915_address_space_init(&ppgtt->vm, i915);
-
-	/* There are only few exceptions for gen >=6. chv and bxt.
-	 * And we are not sure about the latter so play safe for now.
-	 */
-	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
-
 	err = gen8_init_scratch(&ppgtt->vm);
 	if (err)
-		goto err_free;
+		return err;
 
 	if (use_4lvl(&ppgtt->vm)) {
 		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1643,7 +1615,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 				goto err_scratch;
 			}
 		}
-
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1655,18 +1626,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
-	return ppgtt;
+	return 0;
 
 err_scratch:
 	gen8_free_scratch(&ppgtt->vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return err;
 }
 
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
@@ -2087,55 +2051,31 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
 	i915_vma_unpin(ppgtt->vma);
 }
 
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+			     struct i915_ggtt * const ggtt)
 {
-	struct i915_ggtt * const ggtt = &i915->ggtt;
-	struct gen6_hw_ppgtt *ppgtt;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->base.ref);
-
-	ppgtt->base.vm.i915 = i915;
-	ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
-	i915_address_space_init(&ppgtt->base.vm, i915);
-
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.debug_dump = gen6_dump_ppgtt;
 
-	ppgtt->base.vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->base.vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->base.vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 
 	err = gen6_ppgtt_init_scratch(ppgtt);
 	if (err)
-		goto err_free;
+		return err;
 
 	ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 	if (IS_ERR(ppgtt->vma)) {
 		err = PTR_ERR(ppgtt->vma);
-		goto err_scratch;
+		gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+		return err;
 	}
 
-	return &ppgtt->base;
-
-err_scratch:
-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return 0;
 }
 
 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2187,10 +2127,53 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 static struct i915_hw_ppgtt *
 __hw_ppgtt_create(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) < 8)
-		return gen6_ppgtt_create(i915);
-	else
-		return gen8_ppgtt_create(i915);
+	struct gen6_hw_ppgtt *ppgtt;
+	struct i915_address_space *vm;
+	int err;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+
+	vm = &ppgtt->base.vm;
+
+	kref_init(&ppgtt->base.ref);
+
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+
+	vm->total = BIT_ULL(i915->info.ppgtt_bits);
+
+	/*
+	 * From bdw, there is support for read-only pages in the PPGTT.
+	 *
+	 * XXX GVT is not honoring the lack of RW in the PTE bits.
+	 */
+	vm->has_read_only =
+		(INTEL_GEN(i915) < 8) ? false : !intel_vgpu_active(i915);
+
+	i915_address_space_init(vm, i915);
+
+	/* There are only few exceptions for gen >= 6. chv and bxt.
+	 * And we are not sure abou the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+		vm->pt_kmap_wc = true;
+
+	err = (INTEL_GEN(i915) < 8) ?  gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+		gen8_ppgtt_create(&ppgtt->base);
+
+	if (err) {
+		kfree(ppgtt);
+		return ERR_PTR(err);
+	}
+
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
+
+	return &ppgtt->base;
 }
 
 struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..7fd1150d4baf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -253,6 +253,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_ALIASING, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -298,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,6 +353,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -398,6 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -442,6 +446,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,6 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..bc7cbdca02aa 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_4LVL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..4ecb4d6e67f8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_4LVL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6d9ea541a09c..3e873c2e0220 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -122,6 +122,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
 		   info->gen);
 
 	intel_device_info_dump_flags(info, p);
+	drm_printf(p, "ppgttbits=0x%02x\n", info->ppgtt_bits);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..4980da8ccfc3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,6 +189,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* Full PPGTT address range size */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..540a4e344176 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -385,7 +385,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -1866,7 +1866,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2538,7 +2538,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 09ea65a29d98..60b012781002 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,8 +1436,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1709,8 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.17.1

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[PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT

[Bob Paauwe]

We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h             | 2 --
 drivers/gpu/drm/i915/i915_pci.c             | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.h    | 1 -
 drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b109fc0c29be..5b104dad75d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv)	\
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7fd1150d4baf..fac4c69cb5db 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -400,7 +400,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -522,7 +522,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4980da8ccfc3..dc60be4b1435 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-	INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 60b012781002..95abf8475464 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_4LVL_PPGTT(dev_priv)) {
+	if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
 		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1697,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
-- 
2.17.1

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[PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum

[Bob Paauwe]

The distincsion between aliasing, full, and 4 level ppgtt is primarily
the size of the address range. Now that we have that specified for
each platform, having a separate enum that specifies the ppgtt type is
redundant. A platform either has support for ppgtt or it doesn't.
This means we can now remove the HAS_FULL_PPGTT macro and the devcie
info ppgtt type.

However, there are still a few places where GEN 6's aliasing ppgtt
differences matter. For those cases, it makes just as much sense to
check if we're running on GEN 6 as it does to check a device info flag.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c                 | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h                 | 8 +++++---
 drivers/gpu/drm/i915/i915_gem_context.c         | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c             | 2 +-
 drivers/gpu/drm/i915/i915_pci.c                 | 6 ------
 drivers/gpu/drm/i915/intel_device_info.c        | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h        | 9 +--------
 drivers/gpu/drm/i915/selftests/huge_pages.c     | 4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   | 2 +-
 10 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 393e89e2b309..eafb70407356 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+		if (INTEL_GEN(dev_priv) < 6)
+			value = I915_GEM_PPGTT_NONE;
+		else if (IS_GEN6(dev_priv))
+			value = I915_GEM_PPGTT_ALIASING;
+		else
+			value = I915_GEM_PPGTT_FULL;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b104dad75d8..3acdda232ea1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
 #define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+	(INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
 #define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+	(INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (HAS_FULL_PPGTT(dev_priv)) {
+	if (INTEL_GEN(dev_priv) > 6) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e818d3c00bba..1272f7d9e915 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2861,7 +2861,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+	if (IS_GEN6(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fac4c69cb5db..76d3c96733b0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -252,7 +252,6 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_ALIASING, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -298,7 +297,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -352,7 +350,6 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -400,7 +397,6 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -445,7 +441,6 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
@@ -522,7 +517,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3e873c2e0220..570fc4720b10 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -857,7 +857,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 
 	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 		DRM_INFO("Disabling ppGTT for VT-d support\n");
-		info->ppgtt = INTEL_PPGTT_NONE;
+		info->ppgtt_bits = 0;
 	}
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index dc60be4b1435..a7f29cf098d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,12 +76,6 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
-	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
-	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
-	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-};
-
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
@@ -159,7 +153,6 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
-	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
@@ -189,7 +182,7 @@ struct intel_device_info {
 		u16 gamma_lut_size;
 	} color;
 
-	/* Full PPGTT address range size */
+	/* PPGTT address range size in number of bits */
 	int ppgtt_bits;
 };
 
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 95abf8475464..11973452fed6 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1696,8 +1696,8 @@ int i915_gem_huge_page_mock_selftests(void)
 	if (!dev_priv)
 		return -ENOMEM;
 
-	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
+	/* Pretend to be a device which supports the 63b PPGTT */
+	mkwrite_device_info(dev_priv)->ppgtt_bits = 63;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 4365979d8222..e63ee21c2317 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!HAS_FULL_PPGTT(i915))
+	if (INTEL_GEN(i915) <= 6)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 17b5aaaa7a50..af7309aee610 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!HAS_FULL_PPGTT(dev_priv))
+	if (INTEL_GEN(dev_priv) <= 6)
 		return 0;
 
 	file = mock_file(dev_priv);
-- 
2.17.1

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Re: [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum

[Chris Wilson]

Quoting Bob Paauwe (2018-10-29 21:39:51)
> The distincsion between aliasing, full, and 4 level ppgtt is primarily
No, it is not. The distinction is the HW capability of the platform. snb
would be doing full-ppgtt but can't handle a mm switch...
-Chris
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Re: [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v7)

[Chris Wilson]

Quoting Bob Paauwe (2018-10-29 21:39:49)
> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> Also rename other functions and comments from 48bit to 4-level.
> 
> Making use of the device info address range for gen6 highlights
> simularities in the gen6 and gen8 code paths so move the common
> code in to a common function.
> 
> v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
>     Remove unnecessary line coninuations (Bob)
>     Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
>     Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
>     Gen 7 is 31 bits, not 32 (Chris)
> v5: Mock device is 64b(63b) not 48b (Chris)
> v6: Rebase to latest drm-tip (Bob)
> v7: Combine common code for gen6/gen8 ppgtt create (Chris)
>     Improve comment on device info field (Chris)
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Michel Thierry <michel.thierry@intel.com>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c               |   2 +-
>  drivers/gpu/drm/i915/i915_drv.c               |   2 +-
>  drivers/gpu/drm/i915/i915_drv.h               |   2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c       |   2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           | 139 ++++++++----------
>  drivers/gpu/drm/i915/i915_gem_gtt.h           |   4 +-
>  drivers/gpu/drm/i915/i915_pci.c               |   6 +
>  drivers/gpu/drm/i915/i915_pvinfo.h            |   2 +-
>  drivers/gpu/drm/i915/i915_vgpu.c              |   4 +-
>  drivers/gpu/drm/i915/i915_vgpu.h              |   2 +-
>  drivers/gpu/drm/i915/intel_device_info.c      |   1 +
>  drivers/gpu/drm/i915/intel_device_info.h      |   3 +
>  drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
>  drivers/gpu/drm/i915/selftests/huge_pages.c   |   8 +-
>  .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +
>  15 files changed, 90 insertions(+), 95 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index c628be05fbfe..6002ded0042b 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
>         vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
>         vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>  
> -       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> +       vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;

The cap is actually full-ppgtt support. The 48b was accidental and gvt
now does both 3-lvl and 4-lvl aiui.
-Chris
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[PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v8)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.

v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
    Improve comment on device info field (Chris)
v8: gvt is actually full ppgtt (both 3-lvl and 4-lvl) so name cap
    define appropriately (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gvt/vgpu.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c       |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 139 ++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   4 +-
 drivers/gpu/drm/i915/i915_pci.c               |   6 +
 drivers/gpu/drm/i915/i915_pvinfo.h            |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |   4 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   3 +
 drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |   8 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +
 15 files changed, 90 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6571044c9286..393e89e2b309 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1367,7 +1367,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d7761b8ac07..b109fc0c29be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,7 +2587,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..1853e82cebd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1eb1ed2..e818d3c00bba 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,14 +579,14 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert().
 	 *
 	 * TODO: we should really consider write-protecting the scratch-page and
 	 * sharing between ppgtt
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -731,7 +731,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1584,42 +1584,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
  * space.
  *
  */
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
 {
-	struct i915_hw_ppgtt *ppgtt;
+	struct drm_i915_private *i915 = ppgtt->vm.i915;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->ref);
-
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
-
-	/*
-	 * From bdw, there is support for read-only pages in the PPGTT.
-	 *
-	 * XXX GVT is not honouring the lack of RW in the PTE bits.
-	 */
-	ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
-
-	i915_address_space_init(&ppgtt->vm, i915);
-
-	/* There are only few exceptions for gen >=6. chv and bxt.
-	 * And we are not sure about the latter so play safe for now.
-	 */
-	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
-
 	err = gen8_init_scratch(&ppgtt->vm);
 	if (err)
-		goto err_free;
+		return err;
 
 	if (use_4lvl(&ppgtt->vm)) {
 		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1643,7 +1615,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 				goto err_scratch;
 			}
 		}
-
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1655,18 +1626,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
-	return ppgtt;
+	return 0;
 
 err_scratch:
 	gen8_free_scratch(&ppgtt->vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return err;
 }
 
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
@@ -2087,55 +2051,31 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
 	i915_vma_unpin(ppgtt->vma);
 }
 
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+			     struct i915_ggtt * const ggtt)
 {
-	struct i915_ggtt * const ggtt = &i915->ggtt;
-	struct gen6_hw_ppgtt *ppgtt;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->base.ref);
-
-	ppgtt->base.vm.i915 = i915;
-	ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
-	i915_address_space_init(&ppgtt->base.vm, i915);
-
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.debug_dump = gen6_dump_ppgtt;
 
-	ppgtt->base.vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->base.vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->base.vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 
 	err = gen6_ppgtt_init_scratch(ppgtt);
 	if (err)
-		goto err_free;
+		return err;
 
 	ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 	if (IS_ERR(ppgtt->vma)) {
 		err = PTR_ERR(ppgtt->vma);
-		goto err_scratch;
+		gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+		return err;
 	}
 
-	return &ppgtt->base;
-
-err_scratch:
-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return 0;
 }
 
 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2187,10 +2127,53 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 static struct i915_hw_ppgtt *
 __hw_ppgtt_create(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) < 8)
-		return gen6_ppgtt_create(i915);
-	else
-		return gen8_ppgtt_create(i915);
+	struct gen6_hw_ppgtt *ppgtt;
+	struct i915_address_space *vm;
+	int err;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+
+	vm = &ppgtt->base.vm;
+
+	kref_init(&ppgtt->base.ref);
+
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+
+	vm->total = BIT_ULL(i915->info.ppgtt_bits);
+
+	/*
+	 * From bdw, there is support for read-only pages in the PPGTT.
+	 *
+	 * XXX GVT is not honoring the lack of RW in the PTE bits.
+	 */
+	vm->has_read_only =
+		(INTEL_GEN(i915) < 8) ? false : !intel_vgpu_active(i915);
+
+	i915_address_space_init(vm, i915);
+
+	/* There are only few exceptions for gen >= 6. chv and bxt.
+	 * And we are not sure abou the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+		vm->pt_kmap_wc = true;
+
+	err = (INTEL_GEN(i915) < 8) ?  gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+		gen8_ppgtt_create(&ppgtt->base);
+
+	if (err) {
+		kfree(ppgtt);
+		return ERR_PTR(err);
+	}
+
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
+
+	return &ppgtt->base;
 }
 
 struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7e2af5f4f39b..b2a709a27cb9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -363,7 +363,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -506,7 +506,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..7fd1150d4baf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -253,6 +253,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_ALIASING, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -298,6 +299,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,6 +353,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -398,6 +401,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -442,6 +446,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,6 +523,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..969e514916ab 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_FULL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..0ef78fef5422 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6d9ea541a09c..3e873c2e0220 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -122,6 +122,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
 		   info->gen);
 
 	intel_device_info_dump_flags(info, p);
+	drm_printf(p, "ppgttbits=0x%02x\n", info->ppgtt_bits);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..4980da8ccfc3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -189,6 +189,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* Full PPGTT address range size */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..540a4e344176 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -385,7 +385,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -1866,7 +1866,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2538,7 +2538,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 09ea65a29d98..60b012781002 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,8 +1436,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1709,8 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.17.1

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[PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT

[Bob Paauwe]

We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h             | 2 --
 drivers/gpu/drm/i915/i915_pci.c             | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.h    | 1 -
 drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b109fc0c29be..5b104dad75d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv)	\
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7fd1150d4baf..fac4c69cb5db 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -400,7 +400,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -522,7 +522,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4980da8ccfc3..dc60be4b1435 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-	INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 60b012781002..95abf8475464 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_4LVL_PPGTT(dev_priv)) {
+	if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
 		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1697,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
-- 
2.17.1

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[PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v2)

[Bob Paauwe]

With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and the device info ppgtt field.

Aliasing PPGTT used by GEN 6 is a bit of an exception.  For those cases,
it makes just as much sense to check if we're running on GEN 6 as it
does to check a device info flag.

v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c                 | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h                 | 8 +++++---
 drivers/gpu/drm/i915/i915_gem_context.c         | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c             | 2 +-
 drivers/gpu/drm/i915/i915_pci.c                 | 6 ------
 drivers/gpu/drm/i915/intel_device_info.c        | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h        | 9 +--------
 drivers/gpu/drm/i915/selftests/huge_pages.c     | 4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   | 2 +-
 10 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 393e89e2b309..eafb70407356 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+		if (INTEL_GEN(dev_priv) < 6)
+			value = I915_GEM_PPGTT_NONE;
+		else if (IS_GEN6(dev_priv))
+			value = I915_GEM_PPGTT_ALIASING;
+		else
+			value = I915_GEM_PPGTT_FULL;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b104dad75d8..3acdda232ea1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
 #define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+	(INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
 #define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+	(INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (HAS_FULL_PPGTT(dev_priv)) {
+	if (INTEL_GEN(dev_priv) > 6) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e818d3c00bba..1272f7d9e915 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2861,7 +2861,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+	if (IS_GEN6(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fac4c69cb5db..76d3c96733b0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -252,7 +252,6 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_ALIASING, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -298,7 +297,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -352,7 +350,6 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -400,7 +397,6 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -445,7 +441,6 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
@@ -522,7 +517,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3e873c2e0220..570fc4720b10 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -857,7 +857,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 
 	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 		DRM_INFO("Disabling ppGTT for VT-d support\n");
-		info->ppgtt = INTEL_PPGTT_NONE;
+		info->ppgtt_bits = 0;
 	}
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index dc60be4b1435..a7f29cf098d9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,12 +76,6 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
-	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
-	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
-	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-};
-
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
@@ -159,7 +153,6 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
-	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
@@ -189,7 +182,7 @@ struct intel_device_info {
 		u16 gamma_lut_size;
 	} color;
 
-	/* Full PPGTT address range size */
+	/* PPGTT address range size in number of bits */
 	int ppgtt_bits;
 };
 
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 95abf8475464..11973452fed6 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1696,8 +1696,8 @@ int i915_gem_huge_page_mock_selftests(void)
 	if (!dev_priv)
 		return -ENOMEM;
 
-	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
+	/* Pretend to be a device which supports the 63b PPGTT */
+	mkwrite_device_info(dev_priv)->ppgtt_bits = 63;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 4365979d8222..e63ee21c2317 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!HAS_FULL_PPGTT(i915))
+	if (INTEL_GEN(i915) <= 6)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 17b5aaaa7a50..af7309aee610 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!HAS_FULL_PPGTT(dev_priv))
+	if (INTEL_GEN(dev_priv) <= 6)
 		return 0;
 
 	file = mock_file(dev_priv);
-- 
2.17.1

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✗ Fi.CI.BAT: failure for drm/i915: Rename full ppgtt configuration to be more generic (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev6)
URL   : https://patchwork.freedesktop.org/series/49021/
State : failure

== Summary ==

Applying: drm/i915: Make 48bit full ppgtt configuration generic (v7)
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_drv.c
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_gem_context.c
M	drivers/gpu/drm/i915/i915_gem_gtt.c
M	drivers/gpu/drm/i915/i915_gem_gtt.h
M	drivers/gpu/drm/i915/i915_pci.c
M	drivers/gpu/drm/i915/intel_device_info.h
M	drivers/gpu/drm/i915/intel_lrc.c
M	drivers/gpu/drm/i915/selftests/huge_pages.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/selftests/huge_pages.c
Auto-merging drivers/gpu/drm/i915/intel_lrc.c
Auto-merging drivers/gpu/drm/i915/intel_device_info.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.h
Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c
Auto-merging drivers/gpu/drm/i915/i915_gem_context.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/i915_drv.c
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915: Make 48bit full ppgtt configuration generic (v7)
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10391/issues.html
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[PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v9)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.

v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
    Improve comment on device info field (Chris)
v8: gvt is actually full ppgtt (both 3-lvl and 4-lvl) so name cap
    define appropriately (Chris)
v9: rebase on latest

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gvt/vgpu.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c       |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 130 ++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   4 +-
 drivers/gpu/drm/i915/i915_pci.c               |   6 +
 drivers/gpu/drm/i915/i915_pvinfo.h            |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |   4 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   3 +
 drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |   8 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +
 15 files changed, 85 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..6002ded0042b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index acb516308262..05fe8e2852bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1367,7 +1367,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0c8438de3c1b..97649c5614c9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,7 +2587,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..1853e82cebd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a98c29147d5e..b4d5f28474a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,13 +579,13 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the
 	 * scratch (read-only) between all vm, we create one 64k scratch page
 	 * for all.
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -729,7 +729,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1607,38 +1607,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
  * space.
  *
  */
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
 {
-	struct i915_hw_ppgtt *ppgtt;
+	struct drm_i915_private *i915 = ppgtt->vm.i915;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->ref);
-
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
-
-	/* From bdw, there is support for read-only pages in the PPGTT. */
-	ppgtt->vm.has_read_only = true;
-
-	i915_address_space_init(&ppgtt->vm, i915);
-
-	/* There are only few exceptions for gen >=6. chv and bxt.
-	 * And we are not sure about the latter so play safe for now.
-	 */
-	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
-
 	err = gen8_init_scratch(&ppgtt->vm);
 	if (err)
-		goto err_free;
+		return err;
 
 	if (use_4lvl(&ppgtt->vm)) {
 		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1662,7 +1638,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 				goto err_scratch;
 			}
 		}
-
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1674,18 +1649,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
-	return ppgtt;
+	return 0;
 
 err_scratch:
 	gen8_free_scratch(&ppgtt->vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return err;
 }
 
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
@@ -2106,55 +2074,31 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
 	i915_vma_unpin(ppgtt->vma);
 }
 
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+			     struct i915_ggtt * const ggtt)
 {
-	struct i915_ggtt * const ggtt = &i915->ggtt;
-	struct gen6_hw_ppgtt *ppgtt;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->base.ref);
-
-	ppgtt->base.vm.i915 = i915;
-	ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
-	i915_address_space_init(&ppgtt->base.vm, i915);
-
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.debug_dump = gen6_dump_ppgtt;
 
-	ppgtt->base.vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->base.vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->base.vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 
 	err = gen6_ppgtt_init_scratch(ppgtt);
 	if (err)
-		goto err_free;
+		return err;
 
 	ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 	if (IS_ERR(ppgtt->vma)) {
 		err = PTR_ERR(ppgtt->vma);
-		goto err_scratch;
+		gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+		return err;
 	}
 
-	return &ppgtt->base;
-
-err_scratch:
-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return 0;
 }
 
 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2206,10 +2150,48 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 static struct i915_hw_ppgtt *
 __hw_ppgtt_create(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) < 8)
-		return gen6_ppgtt_create(i915);
-	else
-		return gen8_ppgtt_create(i915);
+	struct gen6_hw_ppgtt *ppgtt;
+	struct i915_address_space *vm;
+	int err;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+
+	vm = &ppgtt->base.vm;
+
+	kref_init(&ppgtt->base.ref);
+
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+
+	vm->total = BIT_ULL(i915->info.ppgtt_bits);
+
+	/* From bdw, there is support for read-only pages in the PPGTT.  */
+	vm->has_read_only = (INTEL_GEN(i915) < 8) ? false : true;
+
+	i915_address_space_init(vm, i915);
+
+	/* There are only few exceptions for gen >= 6. chv and bxt.
+	 * And we are not sure abou the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+		vm->pt_kmap_wc = true;
+
+	err = (INTEL_GEN(i915) < 8) ?  gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+		gen8_ppgtt_create(&ppgtt->base);
+
+	if (err) {
+		kfree(ppgtt);
+		return ERR_PTR(err);
+	}
+
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
+
+	return &ppgtt->base;
 }
 
 struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4874da09a3c4..11d2c8b7f28e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -365,7 +365,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -507,7 +507,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4ccab8372dd4..d9686bc22f68 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,6 +250,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_ALIASING, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -295,6 +296,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -348,6 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -395,6 +398,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -439,6 +443,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -515,6 +520,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..969e514916ab 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_FULL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..0ef78fef5422 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 89ed3a84a4fa..d002f54269af 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -122,6 +122,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
 		   info->gen);
 
 	intel_device_info_dump_flags(info, p);
+	drm_printf(p, "ppgttbits=0x%02x\n", info->ppgtt_bits);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 86ce1db1b33a..78df4de37665 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -192,6 +192,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* Full PPGTT address range size */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..540a4e344176 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -385,7 +385,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -1866,7 +1866,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2538,7 +2538,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..8cc8ed75f941 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1450,8 +1450,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1723,8 +1723,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT

[Bob Paauwe]

We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h             | 2 --
 drivers/gpu/drm/i915/i915_pci.c             | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.h    | 1 -
 drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97649c5614c9..3ee0d3a283e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv)	\
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d9686bc22f68..f6e76635c970 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -397,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -519,7 +519,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 78df4de37665..4d45d5eab65d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-	INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8cc8ed75f941..c49ace1a4685 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1450,7 +1450,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_4LVL_PPGTT(dev_priv)) {
+	if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
 		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
-- 
2.17.1

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[PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v2)

[Bob Paauwe]

With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and the device info ppgtt field.

Aliasing PPGTT used by GEN 6 is a bit of an exception.  For those cases,
it makes just as much sense to check if we're running on GEN 6 as it
does to check a device info flag.

v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c                 | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h                 | 8 +++++---
 drivers/gpu/drm/i915/i915_gem_context.c         | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c             | 2 +-
 drivers/gpu/drm/i915/i915_pci.c                 | 6 ------
 drivers/gpu/drm/i915/intel_device_info.c        | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h        | 9 +--------
 drivers/gpu/drm/i915/selftests/huge_pages.c     | 4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   | 2 +-
 10 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 05fe8e2852bd..b957677fbbf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+		if (INTEL_GEN(dev_priv) < 6)
+			value = I915_GEM_PPGTT_NONE;
+		else if (IS_GEN6(dev_priv))
+			value = I915_GEM_PPGTT_ALIASING;
+		else
+			value = I915_GEM_PPGTT_FULL;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ee0d3a283e9..950b0f50ee4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
 #define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+	(INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
 #define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+	(INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (HAS_FULL_PPGTT(dev_priv)) {
+	if (INTEL_GEN(dev_priv) > 6) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b4d5f28474a2..76bb88c8fe6d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2877,7 +2877,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+	if (IS_GEN6(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6e76635c970..816b41674e01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -249,7 +249,6 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_ALIASING, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -295,7 +294,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -349,7 +347,6 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -397,7 +394,6 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -442,7 +438,6 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
@@ -519,7 +514,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d002f54269af..25138654ff99 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -857,7 +857,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 
 	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 		DRM_INFO("Disabling ppGTT for VT-d support\n");
-		info->ppgtt = INTEL_PPGTT_NONE;
+		info->ppgtt_bits = 0;
 	}
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4d45d5eab65d..5dfab991ca14 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,12 +76,6 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
-	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
-	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
-	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-};
-
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
@@ -159,7 +153,6 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
-	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
@@ -192,7 +185,7 @@ struct intel_device_info {
 		u16 gamma_lut_size;
 	} color;
 
-	/* Full PPGTT address range size */
+	/* PPGTT address range size in number of bits */
 	int ppgtt_bits;
 };
 
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index c49ace1a4685..dfee0a09efa9 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1710,8 +1710,8 @@ int i915_gem_huge_page_mock_selftests(void)
 	if (!dev_priv)
 		return -ENOMEM;
 
-	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
+	/* Pretend to be a device which supports the 63b PPGTT */
+	mkwrite_device_info(dev_priv)->ppgtt_bits = 63;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 4365979d8222..e63ee21c2317 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!HAS_FULL_PPGTT(i915))
+	if (INTEL_GEN(i915) <= 6)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 69fe86b30fbb..417f2dc705f3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!HAS_FULL_PPGTT(dev_priv))
+	if (INTEL_GEN(dev_priv) <= 6)
 		return 0;
 
 	file = mock_file(dev_priv);
-- 
2.17.1

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Re: [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v9)

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3221 bytes --]

Hi Bob,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20181107]
[cannot apply to v4.20-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-Make-48bit-full-ppgtt-configuration-generic-v9/20181108-104436
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/gvt/vgpu.c: In function 'populate_pvinfo_page':
>> drivers/gpu/drm/i915/gvt/vgpu.c:47:43: error: 'VGT_CAPS_4LVL_PPGTT' undeclared (first use in this function); did you mean 'VGT_CAPS_FULL_PPGTT'?
     vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
                                              ^~~~~~~~~~~~~~~~~~~
                                              VGT_CAPS_FULL_PPGTT
   drivers/gpu/drm/i915/gvt/vgpu.c:47:43: note: each undeclared identifier is reported only once for each function it appears in

vim +47 drivers/gpu/drm/i915/gvt/vgpu.c

    37	
    38	void populate_pvinfo_page(struct intel_vgpu *vgpu)
    39	{
    40		/* setup the ballooning information */
    41		vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
    42		vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
    43		vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
    44		vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
    45		vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
    46	
  > 47		vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
    48		vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
    49		vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
    50	
    51		vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
    52			vgpu_aperture_gmadr_base(vgpu);
    53		vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
    54			vgpu_aperture_sz(vgpu);
    55		vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
    56			vgpu_hidden_gmadr_base(vgpu);
    57		vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
    58			vgpu_hidden_sz(vgpu);
    59	
    60		vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
    61	
    62		vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
    63		vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
    64	
    65		gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
    66		gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
    67			vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
    68		gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
    69			vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
    70		gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
    71	
    72		WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
    73	}
    74	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65820 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v2)

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4727 bytes --]

Hi Bob,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20181107]
[cannot apply to v4.20-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-Make-48bit-full-ppgtt-configuration-generic-v9/20181108-104436
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gvt/vgpu.c:47:50: error: undefined identifier 'VGT_CAPS_4LVL_PPGTT'
   drivers/gpu/drm/i915/gvt/vgpu.c: In function 'populate_pvinfo_page':
   drivers/gpu/drm/i915/gvt/vgpu.c:47:43: error: 'VGT_CAPS_4LVL_PPGTT' undeclared (first use in this function); did you mean 'VGT_CAPS_FULL_PPGTT'?
     vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
                                              ^~~~~~~~~~~~~~~~~~~
                                              VGT_CAPS_FULL_PPGTT
   drivers/gpu/drm/i915/gvt/vgpu.c:47:43: note: each undeclared identifier is reported only once for each function it appears in

vim +/VGT_CAPS_4LVL_PPGTT +47 drivers/gpu/drm/i915/gvt/vgpu.c

82d375d1 Zhi Wang    2016-07-05  37  
23736d1b Ping Gao    2016-10-26  38  void populate_pvinfo_page(struct intel_vgpu *vgpu)
82d375d1 Zhi Wang    2016-07-05  39  {
82d375d1 Zhi Wang    2016-07-05  40  	/* setup the ballooning information */
90551a12 Zhenyu Wang 2017-12-19  41  	vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
90551a12 Zhenyu Wang 2017-12-19  42  	vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
90551a12 Zhenyu Wang 2017-12-19  43  	vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
90551a12 Zhenyu Wang 2017-12-19  44  	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
90551a12 Zhenyu Wang 2017-12-19  45  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
a2ae95af Weinan Li   2017-10-20  46  
a449bba0 Bob Paauwe  2018-11-07 @47  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_4LVL_PPGTT;
90551a12 Zhenyu Wang 2017-12-19  48  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
aa36ed6d Changbin Du 2018-05-15  49  	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
a2ae95af Weinan Li   2017-10-20  50  
90551a12 Zhenyu Wang 2017-12-19  51  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
82d375d1 Zhi Wang    2016-07-05  52  		vgpu_aperture_gmadr_base(vgpu);
90551a12 Zhenyu Wang 2017-12-19  53  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
82d375d1 Zhi Wang    2016-07-05  54  		vgpu_aperture_sz(vgpu);
90551a12 Zhenyu Wang 2017-12-19  55  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
82d375d1 Zhi Wang    2016-07-05  56  		vgpu_hidden_gmadr_base(vgpu);
90551a12 Zhenyu Wang 2017-12-19  57  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
82d375d1 Zhi Wang    2016-07-05  58  		vgpu_hidden_sz(vgpu);
82d375d1 Zhi Wang    2016-07-05  59  
90551a12 Zhenyu Wang 2017-12-19  60  	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
82d375d1 Zhi Wang    2016-07-05  61  
1c6ccad8 Tina Zhang  2018-05-14  62  	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
1c6ccad8 Tina Zhang  2018-05-14  63  	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
1c6ccad8 Tina Zhang  2018-05-14  64  
82d375d1 Zhi Wang    2016-07-05  65  	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
82d375d1 Zhi Wang    2016-07-05  66  	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
82d375d1 Zhi Wang    2016-07-05  67  		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  68  	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
82d375d1 Zhi Wang    2016-07-05  69  		vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  70  	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
82d375d1 Zhi Wang    2016-07-05  71  
82d375d1 Zhi Wang    2016-07-05  72  	WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
82d375d1 Zhi Wang    2016-07-05  73  }
82d375d1 Zhi Wang    2016-07-05  74  

:::::: The code at line 47 was first introduced by commit
:::::: a449bba075f4efa6186f8c3930a11100d0185740 drm/i915: Make 48bit full ppgtt configuration generic (v9)

:::::: TO: Bob Paauwe <bob.j.paauwe@intel.com>
:::::: CC: 0day robot <lkp@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v10)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.

Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.

v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
    Remove unnecessary line coninuations (Bob)
    Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
    Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
    Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
    Improve comment on device info field (Chris)
v8: gvt is actually full ppgtt (both 3-lvl and 4-lvl) so name cap
    define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Michel Thierry <michel.thierry@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gvt/vgpu.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c       |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 130 ++++++++----------
 drivers/gpu/drm/i915/i915_gem_gtt.h           |   4 +-
 drivers/gpu/drm/i915/i915_pci.c               |   6 +
 drivers/gpu/drm/i915/i915_pvinfo.h            |   2 +-
 drivers/gpu/drm/i915/i915_vgpu.c              |   4 +-
 drivers/gpu/drm/i915/i915_vgpu.h              |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   3 +
 drivers/gpu/drm/i915/intel_lrc.c              |   6 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |   8 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   2 +
 15 files changed, 85 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be05fbfe..fb0f46bec9e6 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index acb516308262..05fe8e2852bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1367,7 +1367,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	if (HAS_PPGTT(dev_priv)) {
 		if (intel_vgpu_active(dev_priv) &&
-		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+		    !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
 			i915_report_error(dev_priv,
 					  "incompatible vGPU found, support for isolated ppGTT required\n");
 			return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0c8438de3c1b..97649c5614c9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,7 +2587,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+#define HAS_4LVL_PPGTT(dev_priv)	\
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..1853e82cebd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -307,7 +307,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
 	desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
 	address_mode = INTEL_LEGACY_32B_CONTEXT;
-	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+	if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
 		address_mode = INTEL_LEGACY_64B_CONTEXT;
 	desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a98c29147d5e..b4d5f28474a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -579,13 +579,13 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
 	 * page-table operating in 64K mode must point to a properly aligned 64K
 	 * region, including any PTEs which happen to point to scratch.
 	 *
-	 * This is only relevant for the 48b PPGTT where we support
+	 * This is only relevant for the 4-level PPGTT where we support
 	 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the
 	 * scratch (read-only) between all vm, we create one 64k scratch page
 	 * for all.
 	 */
 	size = I915_GTT_PAGE_SIZE_4K;
-	if (i915_vm_is_48bit(vm) &&
+	if (i915_vm_is_4lvl(vm) &&
 	    HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
 		size = I915_GTT_PAGE_SIZE_64K;
 		gfp |= __GFP_NOWARN;
@@ -729,7 +729,7 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 
 static inline bool use_4lvl(const struct i915_address_space *vm)
 {
-	return i915_vm_is_48bit(vm);
+	return i915_vm_is_4lvl(vm);
 }
 
 static struct i915_page_directory_pointer *
@@ -1607,38 +1607,14 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
  * space.
  *
  */
-static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
+static int gen8_ppgtt_create(struct i915_hw_ppgtt *ppgtt)
 {
-	struct i915_hw_ppgtt *ppgtt;
+	struct drm_i915_private *i915 = ppgtt->vm.i915;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->ref);
-
-	ppgtt->vm.i915 = i915;
-	ppgtt->vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
-		1ULL << 48 :
-		1ULL << 32;
-
-	/* From bdw, there is support for read-only pages in the PPGTT. */
-	ppgtt->vm.has_read_only = true;
-
-	i915_address_space_init(&ppgtt->vm, i915);
-
-	/* There are only few exceptions for gen >=6. chv and bxt.
-	 * And we are not sure about the latter so play safe for now.
-	 */
-	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
-		ppgtt->vm.pt_kmap_wc = true;
-
 	err = gen8_init_scratch(&ppgtt->vm);
 	if (err)
-		goto err_free;
+		return err;
 
 	if (use_4lvl(&ppgtt->vm)) {
 		err = setup_px(&ppgtt->vm, &ppgtt->pml4);
@@ -1662,7 +1638,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 				goto err_scratch;
 			}
 		}
-
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
@@ -1674,18 +1649,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 
-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
-	return ppgtt;
+	return 0;
 
 err_scratch:
 	gen8_free_scratch(&ppgtt->vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return err;
 }
 
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *base, struct seq_file *m)
@@ -2106,55 +2074,31 @@ void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
 	i915_vma_unpin(ppgtt->vma);
 }
 
-static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
+static int gen6_ppgtt_create(struct gen6_hw_ppgtt *ppgtt,
+			     struct i915_ggtt * const ggtt)
 {
-	struct i915_ggtt * const ggtt = &i915->ggtt;
-	struct gen6_hw_ppgtt *ppgtt;
 	int err;
 
-	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
-	if (!ppgtt)
-		return ERR_PTR(-ENOMEM);
-
-	kref_init(&ppgtt->base.ref);
-
-	ppgtt->base.vm.i915 = i915;
-	ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
-	ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
-
-	i915_address_space_init(&ppgtt->base.vm, i915);
-
 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.debug_dump = gen6_dump_ppgtt;
 
-	ppgtt->base.vm.vma_ops.bind_vma    = ppgtt_bind_vma;
-	ppgtt->base.vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
-	ppgtt->base.vm.vma_ops.set_pages   = ppgtt_set_pages;
-	ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 
 	err = gen6_ppgtt_init_scratch(ppgtt);
 	if (err)
-		goto err_free;
+		return err;
 
 	ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 	if (IS_ERR(ppgtt->vma)) {
 		err = PTR_ERR(ppgtt->vma);
-		goto err_scratch;
+		gen6_ppgtt_free_scratch(&ppgtt->base.vm);
+		return err;
 	}
 
-	return &ppgtt->base;
-
-err_scratch:
-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
-err_free:
-	kfree(ppgtt);
-	return ERR_PTR(err);
+	return 0;
 }
 
 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
@@ -2206,10 +2150,48 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 static struct i915_hw_ppgtt *
 __hw_ppgtt_create(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) < 8)
-		return gen6_ppgtt_create(i915);
-	else
-		return gen8_ppgtt_create(i915);
+	struct gen6_hw_ppgtt *ppgtt;
+	struct i915_address_space *vm;
+	int err;
+
+	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+	if (!ppgtt)
+		return ERR_PTR(-ENOMEM);
+
+	vm = &ppgtt->base.vm;
+
+	kref_init(&ppgtt->base.ref);
+
+	vm->i915 = i915;
+	vm->dma = &i915->drm.pdev->dev;
+
+	vm->total = BIT_ULL(i915->info.ppgtt_bits);
+
+	/* From bdw, there is support for read-only pages in the PPGTT.  */
+	vm->has_read_only = (INTEL_GEN(i915) < 8) ? false : true;
+
+	i915_address_space_init(vm, i915);
+
+	/* There are only few exceptions for gen >= 6. chv and bxt.
+	 * And we are not sure abou the latter so play safe for now.
+	 */
+	if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
+		vm->pt_kmap_wc = true;
+
+	err = (INTEL_GEN(i915) < 8) ?  gen6_ppgtt_create(ppgtt, &i915->ggtt) :
+		gen8_ppgtt_create(&ppgtt->base);
+
+	if (err) {
+		kfree(ppgtt);
+		return ERR_PTR(err);
+	}
+
+	vm->vma_ops.bind_vma    = ppgtt_bind_vma;
+	vm->vma_ops.unbind_vma  = ppgtt_unbind_vma;
+	vm->vma_ops.set_pages   = ppgtt_set_pages;
+	vm->vma_ops.clear_pages = clear_pages;
+
+	return &ppgtt->base;
 }
 
 struct i915_hw_ppgtt *
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4874da09a3c4..11d2c8b7f28e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -365,7 +365,7 @@ struct i915_address_space {
 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
 
 static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
 {
 	return (vm->total - 1) >> 32;
 }
@@ -507,7 +507,7 @@ static inline u32 gen6_pde_index(u32 addr)
 static inline unsigned int
 i915_pdpes_per_pdp(const struct i915_address_space *vm)
 {
-	if (i915_vm_is_48bit(vm))
+	if (i915_vm_is_4lvl(vm))
 		return GEN8_PML4ES_PER_PML4;
 
 	return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4ccab8372dd4..d9686bc22f68 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,6 +250,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_ALIASING, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -295,6 +296,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.ppgtt = INTEL_PPGTT_FULL, \
+	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -348,6 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -395,6 +398,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -439,6 +443,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
 	.ppgtt = INTEL_PPGTT_FULL,
+	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -515,6 +520,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
 	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d506d95..969e514916ab 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -52,7 +52,7 @@ enum vgt_g2v_type {
 /*
  * VGT capabilities type
  */
-#define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
+#define VGT_CAPS_FULL_PPGTT		BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a3b6de..0ef78fef5422 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
 }
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv)
 {
-	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
+	return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
 }
 
 struct _balloon_info_ {
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 551acc390046..5265b6357fba 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -28,7 +28,7 @@
 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
-bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_4lvl_ppgtt(struct drm_i915_private *dev_priv);
 
 static inline bool
 intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 89ed3a84a4fa..d002f54269af 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -122,6 +122,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
 		   info->gen);
 
 	intel_device_info_dump_flags(info, p);
+	drm_printf(p, "ppgttbits=0x%02x\n", info->ppgtt_bits);
 }
 
 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 86ce1db1b33a..78df4de37665 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -192,6 +192,9 @@ struct intel_device_info {
 		u16 degamma_lut_size;
 		u16 gamma_lut_size;
 	} color;
+
+	/* Full PPGTT address range size */
+	int ppgtt_bits;
 };
 
 struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8926fc..540a4e344176 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -385,7 +385,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 	 * PML4 is allocated during ppgtt init, so this is not needed
 	 * in 48-bit mode.
 	 */
-	if (!i915_vm_is_48bit(&ppgtt->vm))
+	if (!i915_vm_is_4lvl(&ppgtt->vm))
 		execlists_update_context_pdps(ppgtt, reg_state);
 
 	return ce->lrc_desc;
@@ -1866,7 +1866,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
 	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
-	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
+	    !i915_vm_is_4lvl(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
 		if (ret)
@@ -2538,7 +2538,7 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
+	if (i915_vm_is_4lvl(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..8cc8ed75f941 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1450,8 +1450,8 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
-		pr_info("48b PPGTT not supported, skipping\n");
+	if (!HAS_4LVL_PPGTT(dev_priv)) {
+		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
 
@@ -1723,8 +1723,8 @@ int i915_gem_huge_page_mock_selftests(void)
 		goto out_unlock;
 	}
 
-	if (!i915_vm_is_48bit(&ppgtt->vm)) {
-		pr_err("failed to create 48b PPGTT\n");
+	if (!i915_vm_is_4lvl(&ppgtt->vm)) {
+		pr_err("failed to create extended PPGTT\n");
 		err = -EINVAL;
 		goto out_close;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 43ed8b28aeaa..77155dd6e2a9 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -181,6 +181,8 @@ struct drm_i915_private *mock_gem_device(void)
 		I915_GTT_PAGE_SIZE_64K |
 		I915_GTT_PAGE_SIZE_2M;
 
+	mkwrite_device_info(i915)->ppgtt_bits = 63;
+
 	mock_uncore_init(i915);
 	i915_gem_init__mm(i915);
 
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT

[Bob Paauwe]

We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h             | 2 --
 drivers/gpu/drm/i915/i915_pci.c             | 4 ++--
 drivers/gpu/drm/i915/intel_device_info.h    | 1 -
 drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
 4 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97649c5614c9..3ee0d3a283e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2587,8 +2587,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 #define HAS_FULL_PPGTT(dev_priv) \
 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv)	\
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d9686bc22f68..f6e76635c970 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -397,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -519,7 +519,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 78df4de37665..4d45d5eab65d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-	INTEL_PPGTT_FULL_4LVL,
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8cc8ed75f941..c49ace1a4685 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1450,7 +1450,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!HAS_4LVL_PPGTT(dev_priv)) {
+	if (INTEL_INFO(dev_priv)->ppgtt_bits <= 32) {
 		pr_info("Extended range PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1711,7 +1711,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v2)

[Bob Paauwe]

With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and the device info ppgtt field.

Aliasing PPGTT used by GEN 6 is a bit of an exception.  For those cases,
it makes just as much sense to check if we're running on GEN 6 as it
does to check a device info flag.

v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris)

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c                 | 7 ++++++-
 drivers/gpu/drm/i915/i915_drv.h                 | 8 +++++---
 drivers/gpu/drm/i915/i915_gem_context.c         | 2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c             | 2 +-
 drivers/gpu/drm/i915/i915_pci.c                 | 6 ------
 drivers/gpu/drm/i915/intel_device_info.c        | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h        | 9 +--------
 drivers/gpu/drm/i915/selftests/huge_pages.c     | 4 ++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c   | 2 +-
 10 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 05fe8e2852bd..b957677fbbf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+		if (INTEL_GEN(dev_priv) < 6)
+			value = I915_GEM_PPGTT_NONE;
+		else if (IS_GEN6(dev_priv))
+			value = I915_GEM_PPGTT_ALIASING;
+		else
+			value = I915_GEM_PPGTT_FULL;
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ee0d3a283e9..950b0f50ee4a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,11 +2582,13 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
 #define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+	(INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
 #define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+	(INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
 
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 1853e82cebd5..7bab4754b20c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (HAS_FULL_PPGTT(dev_priv)) {
+	if (INTEL_GEN(dev_priv) > 6) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b4d5f28474a2..76bb88c8fe6d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2877,7 +2877,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+	if (IS_GEN6(dev_priv)) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6e76635c970..816b41674e01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -249,7 +249,6 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_ALIASING, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -295,7 +294,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 31, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
@@ -349,7 +347,6 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -397,7 +394,6 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
@@ -442,7 +438,6 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.ppgtt = INTEL_PPGTT_FULL,
 	.ppgtt_bits = 32,
 	.has_reset_engine = 1,
 	.has_snoop = true,
@@ -519,7 +514,6 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.ppgtt = INTEL_PPGTT_FULL, \
 	.ppgtt_bits = 48, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d002f54269af..25138654ff99 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -857,7 +857,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 
 	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
 		DRM_INFO("Disabling ppGTT for VT-d support\n");
-		info->ppgtt = INTEL_PPGTT_NONE;
+		info->ppgtt_bits = 0;
 	}
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4d45d5eab65d..5dfab991ca14 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,12 +76,6 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
-enum intel_ppgtt {
-	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
-	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
-	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
-};
-
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
@@ -159,7 +153,6 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
-	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
@@ -192,7 +185,7 @@ struct intel_device_info {
 		u16 gamma_lut_size;
 	} color;
 
-	/* Full PPGTT address range size */
+	/* PPGTT address range size in number of bits */
 	int ppgtt_bits;
 };
 
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index c49ace1a4685..dfee0a09efa9 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1710,8 +1710,8 @@ int i915_gem_huge_page_mock_selftests(void)
 	if (!dev_priv)
 		return -ENOMEM;
 
-	/* Pretend to be a device which supports the 48b PPGTT */
-	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
+	/* Pretend to be a device which supports the 63b PPGTT */
+	mkwrite_device_info(dev_priv)->ppgtt_bits = 63;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 4365979d8222..e63ee21c2317 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!HAS_FULL_PPGTT(i915))
+	if (INTEL_GEN(i915) <= 6)
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 69fe86b30fbb..417f2dc705f3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!HAS_FULL_PPGTT(dev_priv))
+	if (INTEL_GEN(dev_priv) <= 6)
 		return 0;
 
 	file = mock_file(dev_priv);
-- 
2.17.1

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