[PATCH v5 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

[PATCH v5 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

[Tomasz Lis]

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

v2: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
    to MOCS_ENTRIES. (Joonas)

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 86 ++++++++++++++++-----------------------
 1 file changed, 36 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..8d08a7b 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,71 +96,57 @@ struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+
+#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \
+	(LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \
+	LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \
+	LE_PFM(pfm) | LE_SCF(scf))
+
+#define MOCS_L3CC_VALUE(esc, scc, l3cc) \
+	(L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc))
+
+#define GEN9_MOCS_ENTRIES \
+	[I915_MOCS_UNCACHED] = { \
+	  /* 0x00000009 */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC, \
+					      0, 0, 0, 0, 0, 0), \
+	  /* 0x0010 */ \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[I915_MOCS_PTE] = { \
+	  /* 0x00000038 */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC_ELLC, \
+					      3, 0, 0, 0, 0, 0), \
+	  /* 0x0030 */ \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
 	},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+	GEN9_MOCS_ENTRIES
 	[I915_MOCS_CACHED] = {
 	  /* 0x0000003b */
-	  .control_value = LE_CACHEABILITY(LE_WB) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC_ELLC,
+					      3, 0, 0, 0, 0, 0),
 	  /* 0x0030 */
-	  .l3cc_value =   L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
 	},
 };
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
-	},
+	GEN9_MOCS_ENTRIES
 	[I915_MOCS_CACHED] = {
 	  /* 0x00000039 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC_ELLC,
+					      3, 0, 0, 0, 0, 0),
 	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB),
 	},
 };
 
+#undef MOCS_CONTROL_VALUE
+#undef MOCS_L3CC_VALUE
+
 /**
  * get_mocs_settings()
  * @dev_priv:	i915 device.
-- 
2.7.4

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[PATCH v5 2/2] drm/i915/icl: Define MOCS table for Icelake

[Tomasz Lis]

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.

Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.

v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)
v4: Moved new entries below gen9 ones. Put common entries into
    definition to be used in multiple arrays. (Lucas)
v5: Made defines for or-ing flags. Renamed macros from MOCS_TABLE
    to MOCS_ENTRIES. Switched LE_CoS to upper case. (Joonas)

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v4)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 206 +++++++++++++++++++++++++++++++++++---
 1 file changed, 192 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 8d08a7b..030a61d 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)		((value) << 8)
 #define LE_PFM(value)		((value) << 11)
 #define LE_SCF(value)		((value) << 14)
+#define LE_COS(value)		((value) << 15)
+#define LE_SSE(value)		((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)		((value) << 0)
@@ -80,21 +82,21 @@ struct drm_i915_mocs_table {
  * LNCFCMOCS0 - LNCFCMOCS32 registers.
  *
  * These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
  *
  * Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon.  For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * userspace is concerned and shouldn't be relied upon.
  *
- * NOTE: These tables MUST start with being uncached and the length
- *       MUST be less than 63 as the last two registers are reserved
- *       by the hardware.  These tables are part of the kernel ABI and
- *       may only be updated incrementally by adding entries at the
- *       end.
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
+ *
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ *       interface for ICL+. For older platforms, they are part of kernel
+ *       ABI. It is expected that existing entries will remain constant
+ *       and the tables will only be updated by adding new entries.
  */
 
 #define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf) \
@@ -147,6 +149,179 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
 #undef MOCS_CONTROL_VALUE
 #undef MOCS_L3CC_VALUE
 
+#define MOCS_CONTROL_VALUE(lecc, tc, lrum, daom, ersc, scc, pfm, scf, cos, sse) \
+	(LE_CACHEABILITY(lecc) | LE_TGT_CACHE(tc) | \
+	LE_LRUM(lrum) | LE_AOM(daom) | LE_RSC(ersc) | LE_SCC(scc) | \
+	LE_PFM(pfm) | LE_SCF(scf) | LE_COS(cos) | LE_SSE(sse))
+
+#define MOCS_L3CC_VALUE(esc, scc, l3cc) \
+	(L3_ESC(esc) | L3_SCC(scc) | L3_CACHEABILITY(l3cc))
+
+#define GEN11_MOCS_ENTRIES \
+	[0] = { \
+	  /* Base - Uncached (Deprecated) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+					      0, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[1] = { \
+	  /* Base - L3 + LeCC:PAT (Deprecated) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_LLC, \
+					      0, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[2] = { \
+	  /* Base - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[3] = { \
+	  /* Base - Uncached */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+					      0, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[4] = { \
+	  /* Base - L3 */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_UC, LE_TC_LLC, \
+					      0, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[5] = { \
+	  /* Base - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[6] = { \
+	  /* Age 0 - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      1, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[7] = { \
+	  /* Age 0 - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      1, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[8] = { \
+	  /* Age: Don't Chg. - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      2, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[9] = { \
+	  /* Age: Don't Chg. - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      2, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[10] = { \
+	  /* No AOM - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[11] = { \
+	  /* No AOM - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[12] = { \
+	  /* No AOM; Age 0 - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      1, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[13] = { \
+	  /* No AOM; Age 0 - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      1, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[14] = { \
+	  /* No AOM; Age:DC - LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      2, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[15] = { \
+	  /* No AOM; Age:DC - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      2, 1, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[18] = { \
+	  /* Self-Snoop - L3 + LLC */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 0, 0, 0, 0, 3), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[19] = { \
+	  /* Skip Caching - L3 + LLC(12.5%) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 7, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[20] = { \
+	  /* Skip Caching - L3 + LLC(25%) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 3, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[21] = { \
+	  /* Skip Caching - L3 + LLC(50%) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 1, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[22] = { \
+	  /* Skip Caching - L3 + LLC(75%) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 1, 3, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[23] = { \
+	  /* Skip Caching - L3 + LLC(87.5%) */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 1, 7, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_WB), \
+	}, \
+	[62] = { \
+	  /* HW Reserved - SW program but never use */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	}, \
+	[63] = { \
+	  /* HW Reserved - SW program but never use */ \
+	  .control_value = MOCS_CONTROL_VALUE(LE_WB, LE_TC_LLC, \
+					      3, 0, 0, 0, 0, 0, 0, 0), \
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_UC), \
+	},
+
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+	GEN11_MOCS_ENTRIES
+	[16] = {
+	  /* Reserved - For future use */
+	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
+					      0, 0, 0, 0, 0, 0, 0, 0),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT),
+	},
+	[17] = {
+	  /* Reserved - For future use */
+	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
+					      0, 0, 0, 0, 0, 0, 0, 0),
+	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT),
+	},
+};
+
+#undef MOCS_CONTROL_VALUE
+#undef MOCS_L3CC_VALUE
+
 /**
  * get_mocs_settings()
  * @dev_priv:	i915 device.
@@ -164,8 +339,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
-	    IS_ICELAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		table->size  = ARRAY_SIZE(icelake_mocs_table);
+		table->table = icelake_mocs_table;
+		result = true;
+	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-- 
2.7.4

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Re: [PATCH v5 2/2] drm/i915/icl: Define MOCS table for Icelake

[Michal Wajdeczko]

On Tue, 06 Nov 2018 17:47:27 +0100, Tomasz Lis <tomasz.lis@intel.com>  
wrote:

[snip]

> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> +	GEN11_MOCS_ENTRIES
> +	[16] = {
> +	  /* Reserved - For future use */
> +	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
> +					      0, 0, 0, 0, 0, 0, 0, 0),
> +	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT),
> +	},
> +	[17] = {
> +	  /* Reserved - For future use */
> +	  .control_value = MOCS_CONTROL_VALUE(LE_PAGETABLE, LE_TC_PAGETABLE,
> +					      0, 0, 0, 0, 0, 0, 0, 0),
> +	  .l3cc_value = MOCS_L3CC_VALUE(0, 0, L3_DIRECT),
> +	},

Hmm, these 2 entries are reserved (and all zeros) so maybe there so no need
to define them explicitly ? No one shall use them right now (same as  
entries
24-61). If in the future these entries will be unreserved and correctly  
defined
(table v2) then we can provide meaningful definitions back here.

Michal
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✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL   : https://patchwork.freedesktop.org/series/52108/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5096 -> Patchwork_10740 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/52108/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10740 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-blb-e6850:       NOTRUN -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       DMESG-WARN (fdo#106248, fdo#106725) -> PASS

    igt@drv_module_reload@basic-reload-inject:
      fi-byt-clapper:     WARN (fdo#108688) -> PASS

    igt@drv_selftest@live_contexts:
      fi-bsw-n3050:       DMESG-FAIL (fdo#108626) -> PASS

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    igt@pm_rpm@module-reload:
      fi-byt-clapper:     FAIL (fdo#108675) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#108626 https://bugs.freedesktop.org/show_bug.cgi?id=108626
  fdo#108675 https://bugs.freedesktop.org/show_bug.cgi?id=108675
  fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688


== Participating hosts (51 -> 45) ==

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_5096 -> Patchwork_10740

  CI_DRM_5096: 9dd45e92a3e9b238d044adde1061a8ee0ce24b73 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4711: cc41f4c921e56c62c85ec5349c47022ae9b5f008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10740: 3ffac1d9dea70d87022ac4099aa0527be0827cb8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3ffac1d9dea7 drm/i915/icl: Define MOCS table for Icelake
53cfc8f22cc8 drm/i915/skl: Rework MOCS tables to keep common part in a define

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10740/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL   : https://patchwork.freedesktop.org/series/52108/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5097 -> Patchwork_10752 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/52108/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10752 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-ctg-p8600:       PASS -> INCOMPLETE (fdo#102997)

    igt@kms_chamelium@common-hpd-after-suspend:
      fi-skl-6700k2:      PASS -> WARN (fdo#108680)

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-byt-squawks:     PASS -> FAIL (fdo#107362, fdo#107119, fdo#103191)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-byt-squawks:     FAIL (fdo#107362, fdo#107119, fdo#103191) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
      fi-byt-squawks:     FAIL (fdo#107362, fdo#107119) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-cfl-8109u:       DMESG-WARN (fdo#107345) -> PASS +2

    
  fdo#102997 https://bugs.freedesktop.org/show_bug.cgi?id=102997
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107119 https://bugs.freedesktop.org/show_bug.cgi?id=107119
  fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#108680 https://bugs.freedesktop.org/show_bug.cgi?id=108680


== Participating hosts (52 -> 50) ==

  Missing    (2): fi-byt-j1900 fi-icl-u2 


== Build changes ==

    * Linux: CI_DRM_5097 -> Patchwork_10752

  CI_DRM_5097: c20dfc4f015dfd41246beb7d72338aa50543a5ef @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4711: cc41f4c921e56c62c85ec5349c47022ae9b5f008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10752: 0ecd8854b2f2c61aaeb7084fe3e912557dc3fb19 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0ecd8854b2f2 drm/i915/icl: Define MOCS table for Icelake
f6ae01ab78e3 drm/i915/skl: Rework MOCS tables to keep common part in a define

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10752/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
URL   : https://patchwork.freedesktop.org/series/52108/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5097_full -> Patchwork_10752_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10752_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10752_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10752_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-hsw:          PASS -> SKIP

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          PASS -> SKIP
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10752_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@shrink:
      shard-skl:          PASS -> INCOMPLETE (fdo#106886)

    igt@gem_cpu_reloc@full:
      shard-skl:          PASS -> INCOMPLETE (fdo#108073)

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-apl:          PASS -> DMESG-WARN (fdo#103558, fdo#105602) +8

    igt@kms_busy@extended-modeset-hang-newfb-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956) +1

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
      shard-apl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_cursor_crc@cursor-256x256-offscreen:
      shard-skl:          NOTRUN -> FAIL (fdo#103232)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-skl:          PASS -> FAIL (fdo#105363)

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-skl:          PASS -> FAIL (fdo#100368)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
      shard-glk:          PASS -> FAIL (fdo#103167) +2

    igt@kms_plane@plane-position-covered-pipe-b-planes:
      shard-apl:          PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +1

    igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
      shard-glk:          PASS -> FAIL (fdo#103166) +1

    igt@kms_properties@connector-properties-atomic:
      shard-skl:          NOTRUN -> FAIL (fdo#108642)

    igt@pm_rpm@system-suspend-execbuf:
      shard-skl:          PASS -> INCOMPLETE (fdo#104108, fdo#107773, fdo#107807)

    
    ==== Possible fixes ====

    igt@gem_ctx_isolation@vecs0-s3:
      shard-skl:          INCOMPLETE (fdo#104108, fdo#107773) -> PASS

    igt@gem_exec_reuse@baggage:
      shard-apl:          DMESG-WARN -> PASS

    igt@kms_color@pipe-a-ctm-max:
      shard-apl:          FAIL (fdo#108147) -> PASS

    igt@kms_cursor_crc@cursor-256x256-random:
      shard-apl:          FAIL (fdo#103232) -> PASS +3

    igt@kms_flip_tiling@flip-to-yf-tiled:
      shard-skl:          FAIL (fdo#107931) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
      shard-skl:          FAIL (fdo#105682) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-apl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
      shard-glk:          FAIL (fdo#103167) -> PASS +2

    igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite:
      shard-skl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      shard-apl:          INCOMPLETE (fdo#103927) -> PASS +1

    igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
      shard-skl:          FAIL (fdo#107815) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-apl:          FAIL (fdo#103166) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
      shard-glk:          FAIL (fdo#103166) -> PASS

    igt@kms_vblank@pipe-a-accuracy-idle:
      shard-skl:          FAIL (fdo#102583) -> PASS

    igt@pm_rpm@dpms-lpsp:
      shard-skl:          INCOMPLETE (fdo#107807) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107931 https://bugs.freedesktop.org/show_bug.cgi?id=107931
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108073 https://bugs.freedesktop.org/show_bug.cgi?id=108073
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147
  fdo#108642 https://bugs.freedesktop.org/show_bug.cgi?id=108642


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5097 -> Patchwork_10752

  CI_DRM_5097: c20dfc4f015dfd41246beb7d72338aa50543a5ef @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4711: cc41f4c921e56c62c85ec5349c47022ae9b5f008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10752: 0ecd8854b2f2c61aaeb7084fe3e912557dc3fb19 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10752/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx