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From: Jerome Brunet <jbrunet@baylibre.com>
To: Kevin Hilman <khilman@baylibre.com>, Carlo Caione <carlo@caione.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
	devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] arm64: dts: meson-axg: enable SCPI
Date: Thu,  8 Nov 2018 14:53:52 +0100	[thread overview]
Message-ID: <20181108135352.8459-5-jbrunet@baylibre.com> (raw)
In-Reply-To: <20181108135352.8459-1-jbrunet@baylibre.com>

Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b8893675e39c..5f512c91471e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -79,6 +79,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu1: cpu@1 {
@@ -87,6 +88,7 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu2: cpu@2 {
@@ -95,6 +97,7 @@
 			reg = <0x0 0x2>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu3: cpu@3 {
@@ -103,6 +106,7 @@
 			reg = <0x0 0x3>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		l2: l2-cache0 {
@@ -137,6 +141,28 @@
 		};
 	};
 
+	scpi {
+		compatible = "arm,scpi-pre-1.0";
+		mboxes = <&mailbox 1 &mailbox 2>;
+		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+		scpi_clocks: clocks {
+			compatible = "arm,scpi-clocks";
+
+			scpi_dvfs: clock-controller {
+				compatible = "arm,scpi-dvfs-clocks";
+				#clock-cells = <1>;
+				clock-indices = <0>;
+				clock-output-names = "vcpu";
+			};
+		};
+
+		scpi_sensors: sensors {
+			compatible = "amlogic,meson-gxbb-scpi-sensors";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.19.1


WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] arm64: dts: meson-axg: enable SCPI
Date: Thu,  8 Nov 2018 14:53:52 +0100	[thread overview]
Message-ID: <20181108135352.8459-5-jbrunet@baylibre.com> (raw)
In-Reply-To: <20181108135352.8459-1-jbrunet@baylibre.com>

Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b8893675e39c..5f512c91471e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -79,6 +79,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu1: cpu at 1 {
@@ -87,6 +88,7 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu2: cpu at 2 {
@@ -95,6 +97,7 @@
 			reg = <0x0 0x2>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu3: cpu at 3 {
@@ -103,6 +106,7 @@
 			reg = <0x0 0x3>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		l2: l2-cache0 {
@@ -137,6 +141,28 @@
 		};
 	};
 
+	scpi {
+		compatible = "arm,scpi-pre-1.0";
+		mboxes = <&mailbox 1 &mailbox 2>;
+		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+		scpi_clocks: clocks {
+			compatible = "arm,scpi-clocks";
+
+			scpi_dvfs: clock-controller {
+				compatible = "arm,scpi-dvfs-clocks";
+				#clock-cells = <1>;
+				clock-indices = <0>;
+				clock-output-names = "vcpu";
+			};
+		};
+
+		scpi_sensors: sensors {
+			compatible = "amlogic,meson-gxbb-scpi-sensors";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.19.1

WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 4/4] arm64: dts: meson-axg: enable SCPI
Date: Thu,  8 Nov 2018 14:53:52 +0100	[thread overview]
Message-ID: <20181108135352.8459-5-jbrunet@baylibre.com> (raw)
In-Reply-To: <20181108135352.8459-1-jbrunet@baylibre.com>

Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b8893675e39c..5f512c91471e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -79,6 +79,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu1: cpu at 1 {
@@ -87,6 +88,7 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu2: cpu at 2 {
@@ -95,6 +97,7 @@
 			reg = <0x0 0x2>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		cpu3: cpu at 3 {
@@ -103,6 +106,7 @@
 			reg = <0x0 0x3>;
 			enable-method = "psci";
 			next-level-cache = <&l2>;
+			clocks = <&scpi_dvfs 0>;
 		};
 
 		l2: l2-cache0 {
@@ -137,6 +141,28 @@
 		};
 	};
 
+	scpi {
+		compatible = "arm,scpi-pre-1.0";
+		mboxes = <&mailbox 1 &mailbox 2>;
+		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+		scpi_clocks: clocks {
+			compatible = "arm,scpi-clocks";
+
+			scpi_dvfs: clock-controller {
+				compatible = "arm,scpi-dvfs-clocks";
+				#clock-cells = <1>;
+				clock-indices = <0>;
+				clock-output-names = "vcpu";
+			};
+		};
+
+		scpi_sensors: sensors {
+			compatible = "amlogic,meson-gxbb-scpi-sensors";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.19.1

  parent reply	other threads:[~2018-11-08 13:54 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-08 13:53 [PATCH 0/4] arm64: dts: meson-axg: enable SCPI Jerome Brunet
2018-11-08 13:53 ` Jerome Brunet
2018-11-08 13:53 ` Jerome Brunet
2018-11-08 13:53 ` [PATCH 1/4] arm64: dts: meson-axg: fix mailbox address Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-09  9:37   ` Neil Armstrong
2018-11-09  9:37     ` Neil Armstrong
2018-11-09  9:37     ` Neil Armstrong
2018-11-08 13:53 ` [PATCH 2/4] arm64: dts: meson-axg: correct sram shared mem unit-address Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-09  9:38   ` Neil Armstrong
2018-11-09  9:38     ` Neil Armstrong
2018-11-09  9:38     ` Neil Armstrong
2018-11-08 13:53 ` [PATCH 3/4] Documentation: bindings: Add missing Amlogic SCPI sensor bindings Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-08 16:04   ` Sudeep Holla
2018-11-08 16:04     ` Sudeep Holla
2018-11-08 16:04     ` Sudeep Holla
2018-11-08 16:29     ` jbrunet
2018-11-08 16:29       ` jbrunet at baylibre.com
2018-11-08 16:29       ` jbrunet at baylibre.com
2018-11-17 16:21   ` Rob Herring
2018-11-17 16:21     ` Rob Herring
2018-11-17 16:21     ` Rob Herring
2018-11-17 16:21     ` Rob Herring
2018-11-08 13:53 ` Jerome Brunet [this message]
2018-11-08 13:53   ` [PATCH 4/4] arm64: dts: meson-axg: enable SCPI Jerome Brunet
2018-11-08 13:53   ` Jerome Brunet
2018-11-09  9:39   ` Neil Armstrong
2018-11-09  9:39     ` Neil Armstrong
2018-11-09  9:39     ` Neil Armstrong
2018-11-15 20:07 ` [PATCH 0/4] " Kevin Hilman
2018-11-15 20:07   ` Kevin Hilman
2018-11-15 20:07   ` Kevin Hilman
2018-11-15 20:07   ` Kevin Hilman

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