From: leo.yan@linaro.org
To: Robert Walker <robert.walker@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, CoreSight@lists.linaro.org
Subject: Re: [PATCH v4] perf: Support for Arm A32/T32 instruction sets in CoreSight trace
Date: Fri, 9 Nov 2018 10:35:37 +0800 [thread overview]
Message-ID: <20181109023537.GB4219@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <1541588652-17380-1-git-send-email-robert.walker@arm.com>
On Wed, Nov 07, 2018 at 11:04:12AM +0000, Robert Walker wrote:
> This patch adds support for generating instruction samples from trace of
> AArch32 programs using the A32 and T32 instruction sets.
>
> T32 has variable 2 or 4 byte instruction size, so the conversion between
> addresses and instruction counts requires extra information from the trace
> decoder, requiring version 0.10.0 of OpenCSD. A check for the OpenCSD
> library version has been added to the feature check for OpenCSD.
I have applied this patch on latest mainline kernel and tested for
A64/A32/T32 insntructions.
Tested-by: Leo Yan <leo.yan@linaro.org>
WARNING: multiple messages have this Message-ID (diff)
From: leo.yan@linaro.org (leo.yan at linaro.org)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4] perf: Support for Arm A32/T32 instruction sets in CoreSight trace
Date: Fri, 9 Nov 2018 10:35:37 +0800 [thread overview]
Message-ID: <20181109023537.GB4219@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <1541588652-17380-1-git-send-email-robert.walker@arm.com>
On Wed, Nov 07, 2018 at 11:04:12AM +0000, Robert Walker wrote:
> This patch adds support for generating instruction samples from trace of
> AArch32 programs using the A32 and T32 instruction sets.
>
> T32 has variable 2 or 4 byte instruction size, so the conversion between
> addresses and instruction counts requires extra information from the trace
> decoder, requiring version 0.10.0 of OpenCSD. A check for the OpenCSD
> library version has been added to the feature check for OpenCSD.
I have applied this patch on latest mainline kernel and tested for
A64/A32/T32 insntructions.
Tested-by: Leo Yan <leo.yan@linaro.org>
next prev parent reply other threads:[~2018-11-09 2:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-07 11:04 [PATCH v4] perf: Support for Arm A32/T32 instruction sets in CoreSight trace Robert Walker
2018-11-07 11:04 ` Robert Walker
2018-11-08 20:48 ` Mathieu Poirier
2018-11-08 20:48 ` Mathieu Poirier
2018-11-09 2:35 ` leo.yan [this message]
2018-11-09 2:35 ` leo.yan at linaro.org
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