* [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
@ 2018-11-09 14:58 Imre Deak
2018-11-09 14:58 ` [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs Imre Deak
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-09 14:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
A DMC bug on GEN9 big core machines fails to restore the driver's
request bits for the PW1 and MISC_IO power wells after a DC5/6
entry->exit sequence. As a consequence the driver's subsequent check for
the enabled status of these power wells will fail, as the check
considers the power wells being enabled only if both the status and
request bits are set. To work around this borrow the request bits from
BIOS's own request register in which DMC forces on the request bits when
exiting from DC5/6.
This fixes a problem reported by Ramalingam, where HDCP init failed,
since PW1 reported itself as being disabled, while in reality it was
enabled.
Reported-by: Ramalingam C <ramalingam.c@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f945db6ea420..9c49b876055d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -493,11 +493,25 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ enum i915_power_well_id id = power_well->desc->id;
int pw_idx = power_well->desc->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
HSW_PWR_WELL_CTL_STATE(pw_idx);
+ u32 val;
+
+ val = I915_READ(regs->driver);
+
+ /*
+ * On GEN9 big core due to a DMC bug the driver's request bits for PW1
+ * and the MISC_IO PW will be not restored, so check instead for the
+ * BIOS's own request bits, which are forced-on for these power wells
+ * when exiting DC5/6.
+ */
+ if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
+ (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
+ val |= I915_READ(regs->bios);
- return (I915_READ(regs->driver) & mask) == mask;
+ return (val & mask) == mask;
}
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
@ 2018-11-09 14:58 ` Imre Deak
2018-11-12 17:12 ` Ville Syrjälä
2018-11-09 14:58 ` [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification Imre Deak
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2018-11-09 14:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
We can just use a proper true/false initializer even for bitfields,
which is more descriptive.
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9c49b876055d..44a77de439f2 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2098,7 +2098,7 @@ static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2115,7 +2115,7 @@ static const struct i915_power_well_ops i830_pipes_power_well_ops = {
static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2159,7 +2159,7 @@ static const struct i915_power_well_regs hsw_power_well_regs = {
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2180,7 +2180,7 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
static const struct i915_power_well_desc bdw_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2223,7 +2223,7 @@ static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2299,7 +2299,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
static const struct i915_power_well_desc chv_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2350,7 +2350,7 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2442,7 +2442,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
static const struct i915_power_well_desc bxt_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2500,7 +2500,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2628,7 +2628,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
static const struct i915_power_well_desc cnl_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -2795,7 +2795,7 @@ static const struct i915_power_well_regs icl_ddi_power_well_regs = {
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
- .always_on = 1,
+ .always_on = true,
.domains = POWER_DOMAIN_MASK,
.ops = &i9xx_always_on_power_well_ops,
.id = DISP_PW_ID_NONE,
--
2.13.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
2018-11-09 14:58 ` [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs Imre Deak
@ 2018-11-09 14:58 ` Imre Deak
2018-11-12 17:19 ` Ville Syrjälä
2018-11-09 15:04 ` [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Ville Syrjälä
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2018-11-09 14:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
Even though PW#1 and the MISC_IO power wells are managed by the
DMC firmware (toggled dynamically if conditions allow it) from the
driver's POV they are always on if the display core is initialized
(always restored by DMC to the enabled state after exiting from DC5/6
for instance b/c of MMIO access). Accordingly we can just mark them as
always-on and remove the special casing for them during state
verification (thus enabling verification for these power wells too).
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 44a77de439f2..6b1576ae778f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2358,6 +2358,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "power well 1",
/* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
@@ -2370,6 +2371,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "MISC IO power well",
/* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_MISC_IO,
@@ -2449,6 +2451,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
{
.name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
@@ -2508,6 +2512,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "power well 1",
/* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
@@ -2636,6 +2641,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
{
.name = "power well 1",
/* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
@@ -2803,6 +2809,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "power well 1",
/* Handled by the DMC firmware */
+ .always_on = true,
.domains = 0,
.ops = &hsw_power_well_ops,
.id = SKL_DISP_PW_1,
@@ -3936,14 +3943,6 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
int domains_count;
bool enabled;
- /*
- * Power wells not belonging to any domain (like the MISC_IO
- * and PW1 power wells) are under FW control, so ignore them,
- * since their state can change asynchronously.
- */
- if (!power_well->desc->domains)
- continue;
-
enabled = power_well->desc->ops->is_enabled(dev_priv,
power_well);
if ((power_well->count || power_well->desc->always_on) !=
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
2018-11-09 14:58 ` [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs Imre Deak
2018-11-09 14:58 ` [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification Imre Deak
@ 2018-11-09 15:04 ` Ville Syrjälä
2018-11-09 17:48 ` Imre Deak
2018-11-09 17:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2018-11-10 0:57 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2018-11-09 15:04 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, Daniel Vetter
On Fri, Nov 09, 2018 at 04:58:20PM +0200, Imre Deak wrote:
> A DMC bug on GEN9 big core machines fails to restore the driver's
> request bits for the PW1 and MISC_IO power wells after a DC5/6
> entry->exit sequence. As a consequence the driver's subsequent check for
> the enabled status of these power wells will fail, as the check
> considers the power wells being enabled only if both the status and
> request bits are set. To work around this borrow the request bits from
> BIOS's own request register in which DMC forces on the request bits when
> exiting from DC5/6.
>
> This fixes a problem reported by Ramalingam, where HDCP init failed,
> since PW1 reported itself as being disabled, while in reality it was
> enabled.
>
> Reported-by: Ramalingam C <ramalingam.c@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f945db6ea420..9c49b876055d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -493,11 +493,25 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> + enum i915_power_well_id id = power_well->desc->id;
> int pw_idx = power_well->desc->hsw.idx;
> u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
> HSW_PWR_WELL_CTL_STATE(pw_idx);
> + u32 val;
> +
> + val = I915_READ(regs->driver);
> +
> + /*
> + * On GEN9 big core due to a DMC bug the driver's request bits for PW1
> + * and the MISC_IO PW will be not restored, so check instead for the
> + * BIOS's own request bits, which are forced-on for these power wells
> + * when exiting DC5/6.
> + */
> + if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
IS_GEN9_BC() ?
Apart from that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> + val |= I915_READ(regs->bios);
>
> - return (I915_READ(regs->driver) & mask) == mask;
> + return (val & mask) == mask;
> }
>
> static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> --
> 2.13.2
--
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
` (2 preceding siblings ...)
2018-11-09 15:04 ` [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Ville Syrjälä
@ 2018-11-09 17:18 ` Patchwork
2018-11-10 0:57 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-11-09 17:18 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
URL : https://patchwork.freedesktop.org/series/52302/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5115 -> Patchwork_10795 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10795 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10795, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52302/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10795:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_guc:
fi-icl-u: PASS -> SKIP +2
== Known issues ==
Here are the changes found in Patchwork_10795 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: PASS -> FAIL (fdo#107362)
==== Possible fixes ====
igt@kms_frontbuffer_tracking@basic:
fi-icl-u2: FAIL (fdo#103167) -> PASS
==== Warnings ====
igt@drv_selftest@live_contexts:
fi-icl-u: DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108315)
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
== Participating hosts (52 -> 47) ==
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5115 -> Patchwork_10795
CI_DRM_5115: 95830469c0077bb86031e794106fdd7781369625 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10795: 3ee8d9251fe6ab2126286deb5710dfb7789fe5f0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3ee8d9251fe6 drm/i915: Remove special case for power well 1/MISC_IO state verification
41c5c0fe774c drm/i915: Use proper bool bitfield initializer in power well descs
426d5741f641 drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10795/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
2018-11-09 15:04 ` [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Ville Syrjälä
@ 2018-11-09 17:48 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-09 17:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Daniel Vetter
On Fri, Nov 09, 2018 at 05:04:40PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 04:58:20PM +0200, Imre Deak wrote:
> > A DMC bug on GEN9 big core machines fails to restore the driver's
> > request bits for the PW1 and MISC_IO power wells after a DC5/6
> > entry->exit sequence. As a consequence the driver's subsequent check for
> > the enabled status of these power wells will fail, as the check
> > considers the power wells being enabled only if both the status and
> > request bits are set. To work around this borrow the request bits from
> > BIOS's own request register in which DMC forces on the request bits when
> > exiting from DC5/6.
> >
> > This fixes a problem reported by Ramalingam, where HDCP init failed,
> > since PW1 reported itself as being disabled, while in reality it was
> > enabled.
> >
> > Reported-by: Ramalingam C <ramalingam.c@intel.com>
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
> > 1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index f945db6ea420..9c49b876055d 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -493,11 +493,25 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> > + enum i915_power_well_id id = power_well->desc->id;
> > int pw_idx = power_well->desc->hsw.idx;
> > u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
> > HSW_PWR_WELL_CTL_STATE(pw_idx);
> > + u32 val;
> > +
> > + val = I915_READ(regs->driver);
> > +
> > + /*
> > + * On GEN9 big core due to a DMC bug the driver's request bits for PW1
> > + * and the MISC_IO PW will be not restored, so check instead for the
> > + * BIOS's own request bits, which are forced-on for these power wells
> > + * when exiting DC5/6.
> > + */
> > + if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
>
> IS_GEN9_BC() ?
Yep, should've known there must be a macro for this already :/
>
> Apart from that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > + (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> > + val |= I915_READ(regs->bios);
> >
> > - return (I915_READ(regs->driver) & mask) == mask;
> > + return (val & mask) == mask;
> > }
> >
> > static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
` (3 preceding siblings ...)
2018-11-09 17:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
@ 2018-11-10 0:57 ` Patchwork
2018-11-14 11:55 ` Imre Deak
4 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2018-11-10 0:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
URL : https://patchwork.freedesktop.org/series/52302/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5115_full -> Patchwork_10795_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10795_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10795_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10795_full:
=== IGT changes ===
==== Warnings ====
igt@kms_frontbuffer_tracking@fbc-badstride:
shard-snb: SKIP -> PASS
igt@perf_pmu@rc6:
shard-kbl: SKIP -> PASS
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP
igt@tools_test@tools_test:
shard-skl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10795_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@forcewake:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@gem_softpin@noreloc-s3:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
igt@gem_userptr_blits@readonly-unsync:
shard-skl: PASS -> INCOMPLETE (fdo#108074)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-apl: PASS -> DMESG-WARN (fdo#107956)
igt@kms_chv_cursor_fail@pipe-c-256x256-top-edge:
shard-skl: PASS -> FAIL (fdo#104671)
igt@kms_color@pipe-c-ctm-blue-to-red:
shard-skl: PASS -> FAIL (fdo#107201)
igt@kms_color@pipe-c-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-128x128-sliding:
shard-apl: PASS -> FAIL (fdo#103232)
igt@kms_flip@flip-vs-expired-vblank:
shard-skl: PASS -> FAIL (fdo#105363)
igt@kms_flip@flip-vs-modeset-vs-hang-interruptible:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-skl: PASS -> FAIL (fdo#100368)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-glk: PASS -> FAIL (fdo#103166)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
igt@pm_rpm@modeset-stress-extra-wait:
shard-skl: PASS -> INCOMPLETE (fdo#107807) +2
igt@pm_rpm@system-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107807, fdo#107773)
==== Possible fixes ====
igt@drv_suspend@shrink:
shard-glk: INCOMPLETE (fdo#103359, fdo#106886, k.org#198133) -> PASS
igt@gem_ctx_isolation@vecs0-s3:
shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS
igt@gem_ppgtt@blt-vs-render-ctx0:
shard-kbl: INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) -> PASS
igt@gem_pwrite@big-gtt-fbr:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_busy@extended-pageflip-hang-newfb-render-c:
shard-apl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_color@pipe-c-legacy-gamma:
shard-apl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-128x128-random:
shard-apl: FAIL (fdo#103232) -> PASS +2
igt@kms_cursor_crc@cursor-256x256-suspend:
shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS
igt@kms_cursor_legacy@cursor-vs-flip-toggle:
shard-hsw: FAIL (fdo#103355) -> PASS
igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
shard-skl: FAIL (fdo#106081) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
shard-skl: FAIL (fdo#105682) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
shard-apl: FAIL (fdo#103167) -> PASS +2
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
shard-skl: FAIL (fdo#103167) -> PASS
igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
shard-skl: FAIL (fdo#103166) -> PASS
igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
shard-skl: FAIL (fdo#108145, fdo#107815) -> PASS
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
shard-apl: FAIL (fdo#103166) -> PASS
igt@kms_setmode@basic:
shard-apl: FAIL (fdo#99912) -> PASS
igt@perf@oa-exponents:
shard-glk: FAIL (fdo#105483) -> PASS
==== Warnings ====
igt@kms_content_protection@atomic:
shard-kbl: DMESG-FAIL (fdo#108550) -> FAIL (fdo#108597) +1
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483
fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106081 https://bugs.freedesktop.org/show_bug.cgi?id=106081
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
fdo#107201 https://bugs.freedesktop.org/show_bug.cgi?id=107201
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108550 https://bugs.freedesktop.org/show_bug.cgi?id=108550
fdo#108597 https://bugs.freedesktop.org/show_bug.cgi?id=108597
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5115 -> Patchwork_10795
CI_DRM_5115: 95830469c0077bb86031e794106fdd7781369625 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10795: 3ee8d9251fe6ab2126286deb5710dfb7789fe5f0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10795/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs
2018-11-09 14:58 ` [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs Imre Deak
@ 2018-11-12 17:12 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-11-12 17:12 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, Daniel Vetter
On Fri, Nov 09, 2018 at 04:58:21PM +0200, Imre Deak wrote:
> We can just use a proper true/false initializer even for bitfields,
> which is more descriptive.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 9c49b876055d..44a77de439f2 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2098,7 +2098,7 @@ static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
> static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2115,7 +2115,7 @@ static const struct i915_power_well_ops i830_pipes_power_well_ops = {
> static const struct i915_power_well_desc i830_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2159,7 +2159,7 @@ static const struct i915_power_well_regs hsw_power_well_regs = {
> static const struct i915_power_well_desc hsw_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2180,7 +2180,7 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
> static const struct i915_power_well_desc bdw_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2223,7 +2223,7 @@ static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
> static const struct i915_power_well_desc vlv_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2299,7 +2299,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
> static const struct i915_power_well_desc chv_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2350,7 +2350,7 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2442,7 +2442,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> static const struct i915_power_well_desc bxt_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2500,7 +2500,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> static const struct i915_power_well_desc glk_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2628,7 +2628,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> static const struct i915_power_well_desc cnl_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> @@ -2795,7 +2795,7 @@ static const struct i915_power_well_regs icl_ddi_power_well_regs = {
> static const struct i915_power_well_desc icl_power_wells[] = {
> {
> .name = "always-on",
> - .always_on = 1,
> + .always_on = true,
> .domains = POWER_DOMAIN_MASK,
> .ops = &i9xx_always_on_power_well_ops,
> .id = DISP_PW_ID_NONE,
> --
> 2.13.2
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification
2018-11-09 14:58 ` [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification Imre Deak
@ 2018-11-12 17:19 ` Ville Syrjälä
2018-11-14 11:43 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2018-11-12 17:19 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, Daniel Vetter
On Fri, Nov 09, 2018 at 04:58:22PM +0200, Imre Deak wrote:
> Even though PW#1 and the MISC_IO power wells are managed by the
> DMC firmware (toggled dynamically if conditions allow it) from the
> driver's POV they are always on if the display core is initialized
> (always restored by DMC to the enabled state after exiting from DC5/6
> for instance b/c of MMIO access). Accordingly we can just mark them as
> always-on and remove the special casing for them during state
> verification (thus enabling verification for these power wells too).
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 44a77de439f2..6b1576ae778f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2358,6 +2358,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "power well 1",
> /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
First I was wondering if this somehow changes the behaviour of
__intel_display_power_is_enabled(), but it won't since all these
wells have domains==0 and so would be skipped there anyway.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_1,
> @@ -2370,6 +2371,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> {
> .name = "MISC IO power well",
> /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_MISC_IO,
> @@ -2449,6 +2451,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> },
> {
> .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_1,
> @@ -2508,6 +2512,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> {
> .name = "power well 1",
> /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_1,
> @@ -2636,6 +2641,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
> {
> .name = "power well 1",
> /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_1,
> @@ -2803,6 +2809,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> {
> .name = "power well 1",
> /* Handled by the DMC firmware */
> + .always_on = true,
> .domains = 0,
> .ops = &hsw_power_well_ops,
> .id = SKL_DISP_PW_1,
> @@ -3936,14 +3943,6 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
> int domains_count;
> bool enabled;
>
> - /*
> - * Power wells not belonging to any domain (like the MISC_IO
> - * and PW1 power wells) are under FW control, so ignore them,
> - * since their state can change asynchronously.
> - */
> - if (!power_well->desc->domains)
> - continue;
> -
> enabled = power_well->desc->ops->is_enabled(dev_priv,
> power_well);
> if ((power_well->count || power_well->desc->always_on) !=
> --
> 2.13.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification
2018-11-12 17:19 ` Ville Syrjälä
@ 2018-11-14 11:43 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-14 11:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Daniel Vetter
On Mon, Nov 12, 2018 at 07:19:44PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 04:58:22PM +0200, Imre Deak wrote:
> > Even though PW#1 and the MISC_IO power wells are managed by the
> > DMC firmware (toggled dynamically if conditions allow it) from the
> > driver's POV they are always on if the display core is initialized
> > (always restored by DMC to the enabled state after exiting from DC5/6
> > for instance b/c of MMIO access). Accordingly we can just mark them as
> > always-on and remove the special casing for them during state
> > verification (thus enabling verification for these power wells too).
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 15 +++++++--------
> > 1 file changed, 7 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 44a77de439f2..6b1576ae778f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2358,6 +2358,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > {
> > .name = "power well 1",
> > /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
>
> First I was wondering if this somehow changes the behaviour of
> __intel_display_power_is_enabled(), but it won't since all these
> wells have domains==0 and so would be skipped there anyway.
Yes, it should only affect the verification, otherwise doesn't change
the behaviour.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_1,
> > @@ -2370,6 +2371,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
> > {
> > .name = "MISC IO power well",
> > /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_MISC_IO,
> > @@ -2449,6 +2451,8 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
> > },
> > {
> > .name = "power well 1",
> > + /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_1,
> > @@ -2508,6 +2512,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
> > {
> > .name = "power well 1",
> > /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_1,
> > @@ -2636,6 +2641,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
> > {
> > .name = "power well 1",
> > /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_1,
> > @@ -2803,6 +2809,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
> > {
> > .name = "power well 1",
> > /* Handled by the DMC firmware */
> > + .always_on = true,
> > .domains = 0,
> > .ops = &hsw_power_well_ops,
> > .id = SKL_DISP_PW_1,
> > @@ -3936,14 +3943,6 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
> > int domains_count;
> > bool enabled;
> >
> > - /*
> > - * Power wells not belonging to any domain (like the MISC_IO
> > - * and PW1 power wells) are under FW control, so ignore them,
> > - * since their state can change asynchronously.
> > - */
> > - if (!power_well->desc->domains)
> > - continue;
> > -
> > enabled = power_well->desc->ops->is_enabled(dev_priv,
> > power_well);
> > if ((power_well->count || power_well->desc->always_on) !=
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
2018-11-10 0:57 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-11-14 11:55 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-14 11:55 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä; +Cc: Daniel Vetter
On Sat, Nov 10, 2018 at 12:57:13AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests
> URL : https://patchwork.freedesktop.org/series/52302/
> State : success
Pushed to -dinq, thanks for the reviews.
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5115_full -> Patchwork_10795_full =
>
> == Summary - WARNING ==
>
> Minor unknown changes coming with Patchwork_10795_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10795_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in Patchwork_10795_full:
>
> === IGT changes ===
>
> ==== Warnings ====
>
> igt@kms_frontbuffer_tracking@fbc-badstride:
> shard-snb: SKIP -> PASS
>
> igt@perf_pmu@rc6:
> shard-kbl: SKIP -> PASS
>
> igt@pm_rc6_residency@rc6-accuracy:
> shard-kbl: PASS -> SKIP
>
> igt@tools_test@tools_test:
> shard-skl: PASS -> SKIP
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_10795_full that come from known issues:
>
> === IGT changes ===
>
> ==== Issues hit ====
>
> igt@drv_suspend@forcewake:
> shard-kbl: PASS -> INCOMPLETE (fdo#103665)
>
> igt@gem_softpin@noreloc-s3:
> shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
>
> igt@gem_userptr_blits@readonly-unsync:
> shard-skl: PASS -> INCOMPLETE (fdo#108074)
>
> igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
> shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956)
>
> igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
> shard-apl: PASS -> DMESG-WARN (fdo#107956)
>
> igt@kms_chv_cursor_fail@pipe-c-256x256-top-edge:
> shard-skl: PASS -> FAIL (fdo#104671)
>
> igt@kms_color@pipe-c-ctm-blue-to-red:
> shard-skl: PASS -> FAIL (fdo#107201)
>
> igt@kms_color@pipe-c-degamma:
> shard-apl: PASS -> FAIL (fdo#104782)
>
> igt@kms_cursor_crc@cursor-128x128-sliding:
> shard-apl: PASS -> FAIL (fdo#103232)
>
> igt@kms_flip@flip-vs-expired-vblank:
> shard-skl: PASS -> FAIL (fdo#105363)
>
> igt@kms_flip@flip-vs-modeset-vs-hang-interruptible:
> shard-apl: PASS -> INCOMPLETE (fdo#103927)
>
> igt@kms_flip@plain-flip-ts-check-interruptible:
> shard-skl: PASS -> FAIL (fdo#100368)
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
> shard-apl: PASS -> FAIL (fdo#103167)
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
> shard-glk: PASS -> FAIL (fdo#103167)
>
> igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> shard-skl: PASS -> FAIL (fdo#107815)
>
> igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
> shard-glk: PASS -> FAIL (fdo#103166)
>
> igt@perf@polling:
> shard-hsw: PASS -> FAIL (fdo#102252)
>
> igt@pm_rpm@modeset-stress-extra-wait:
> shard-skl: PASS -> INCOMPLETE (fdo#107807) +2
>
> igt@pm_rpm@system-suspend:
> shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107807, fdo#107773)
>
>
> ==== Possible fixes ====
>
> igt@drv_suspend@shrink:
> shard-glk: INCOMPLETE (fdo#103359, fdo#106886, k.org#198133) -> PASS
>
> igt@gem_ctx_isolation@vecs0-s3:
> shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS
>
> igt@gem_ppgtt@blt-vs-render-ctx0:
> shard-kbl: INCOMPLETE (fdo#103665, fdo#106887, fdo#106023) -> PASS
>
> igt@gem_pwrite@big-gtt-fbr:
> shard-apl: INCOMPLETE (fdo#103927) -> PASS
>
> igt@kms_busy@extended-pageflip-hang-newfb-render-c:
> shard-apl: DMESG-WARN (fdo#107956) -> PASS
>
> igt@kms_color@pipe-c-legacy-gamma:
> shard-apl: FAIL (fdo#104782) -> PASS
>
> igt@kms_cursor_crc@cursor-128x128-random:
> shard-apl: FAIL (fdo#103232) -> PASS +2
>
> igt@kms_cursor_crc@cursor-256x256-suspend:
> shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS
>
> igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> shard-hsw: FAIL (fdo#103355) -> PASS
>
> igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
> shard-skl: FAIL (fdo#106081) -> PASS
>
> igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
> shard-skl: FAIL (fdo#105682) -> PASS +1
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
> shard-apl: FAIL (fdo#103167) -> PASS +2
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
> shard-glk: FAIL (fdo#103167) -> PASS
>
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
> shard-skl: FAIL (fdo#103167) -> PASS
>
> igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
> shard-skl: FAIL (fdo#103166) -> PASS
>
> igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> shard-skl: FAIL (fdo#108145, fdo#107815) -> PASS
>
> igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> shard-glk: FAIL (fdo#103166) -> PASS +1
>
> igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
> shard-apl: FAIL (fdo#103166) -> PASS
>
> igt@kms_setmode@basic:
> shard-apl: FAIL (fdo#99912) -> PASS
>
> igt@perf@oa-exponents:
> shard-glk: FAIL (fdo#105483) -> PASS
>
>
> ==== Warnings ====
>
> igt@kms_content_protection@atomic:
> shard-kbl: DMESG-FAIL (fdo#108550) -> FAIL (fdo#108597) +1
>
>
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
> fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
> fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
> fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
> fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
> fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
> fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
> fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
> fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
> fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
> fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
> fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
> fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
> fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483
> fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
> fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
> fdo#106081 https://bugs.freedesktop.org/show_bug.cgi?id=106081
> fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
> fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
> fdo#107201 https://bugs.freedesktop.org/show_bug.cgi?id=107201
> fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
> fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
> fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
> fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
> fdo#108074 https://bugs.freedesktop.org/show_bug.cgi?id=108074
> fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
> fdo#108550 https://bugs.freedesktop.org/show_bug.cgi?id=108550
> fdo#108597 https://bugs.freedesktop.org/show_bug.cgi?id=108597
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
>
>
> == Participating hosts (6 -> 6) ==
>
> No changes in participating hosts
>
>
> == Build changes ==
>
> * Linux: CI_DRM_5115 -> Patchwork_10795
>
> CI_DRM_5115: 95830469c0077bb86031e794106fdd7781369625 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4714: cab148ca3ec904a94d0cd43476cf7e1f8663f906 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_10795: 3ee8d9251fe6ab2126286deb5710dfb7789fe5f0 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10795/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-11-14 11:55 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-09 14:58 [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Imre Deak
2018-11-09 14:58 ` [PATCH 2/3] drm/i915: Use proper bool bitfield initializer in power well descs Imre Deak
2018-11-12 17:12 ` Ville Syrjälä
2018-11-09 14:58 ` [PATCH 3/3] drm/i915: Remove special case for power well 1/MISC_IO state verification Imre Deak
2018-11-12 17:19 ` Ville Syrjälä
2018-11-14 11:43 ` Imre Deak
2018-11-09 15:04 ` [PATCH 1/3] drm/i915/gen9_bc: Work around DMC bug zeroing power well requests Ville Syrjälä
2018-11-09 17:48 ` Imre Deak
2018-11-09 17:18 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2018-11-10 0:57 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-14 11:55 ` Imre Deak
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