[PATCH v2 0/4] media: sun6i: Add support for the H3 CSI controller

[PATCH v2 0/4] media: sun6i: Add support for the H3 CSI controller

[Maxime Ripard]

Hi,

The H3 and H5 have a CSI controller based on the one previously found
in the A31, that is currently supported by the sun6i-csi driver.

Add the compatibles to the device tree bindings and to the driver to
make it work properly.

This obviously depends on the serie "Initial Allwinner V3s CSI
Support" by Yong Deng.

Let me know what you think,
Maxime

Changes from v1:
  - Rebased on top of latest Yong's series

Maxime Ripard (2):
  dt-bindings: media: sun6i: Add A31 and H3 compatibles
  media: sun6i: Add A31 compatible

Mylène Josserand (2):
  ARM: dts: sun8i: Add the H3/H5 CSI controller
  [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano
    Pi M1+

 .../devicetree/bindings/media/sun6i-csi.txt   |  5 +-
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi            | 22 +++++
 .../platform/sunxi/sun6i-csi/sun6i_csi.c      |  1 +
 4 files changed, 112 insertions(+), 1 deletion(-)

-- 
2.19.1

[PATCH v2 0/4] media: sun6i: Add support for the H3 CSI controller

[Maxime Ripard]

Hi,

The H3 and H5 have a CSI controller based on the one previously found
in the A31, that is currently supported by the sun6i-csi driver.

Add the compatibles to the device tree bindings and to the driver to
make it work properly.

This obviously depends on the serie "Initial Allwinner V3s CSI
Support" by Yong Deng.

Let me know what you think,
Maxime

Changes from v1:
  - Rebased on top of latest Yong's series

Maxime Ripard (2):
  dt-bindings: media: sun6i: Add A31 and H3 compatibles
  media: sun6i: Add A31 compatible

Myl?ne Josserand (2):
  ARM: dts: sun8i: Add the H3/H5 CSI controller
  [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano
    Pi M1+

 .../devicetree/bindings/media/sun6i-csi.txt   |  5 +-
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi            | 22 +++++
 .../platform/sunxi/sun6i-csi/sun6i_csi.c      |  1 +
 4 files changed, 112 insertions(+), 1 deletion(-)

-- 
2.19.1

[PATCH v2 1/4] dt-bindings: media: sun6i: Add A31 and H3 compatibles

[Maxime Ripard]

The H3 has a slightly different CSI controller (no BT656, no CCI) which
looks a lot like the original A31 controller. Add a compatible for the A31,
and more specific compatible the for the H3 to be used in combination for
the A31.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 Documentation/devicetree/bindings/media/sun6i-csi.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
index 2ff47a9507a6..3f8eb0296382 100644
--- a/Documentation/devicetree/bindings/media/sun6i-csi.txt
+++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
@@ -5,7 +5,10 @@ Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
 interface and CSI1 is used for parallel interface.
 
 Required properties:
-  - compatible: value must be "allwinner,sun8i-v3s-csi"
+  - compatible: value must be one of:
+    * "allwinner,sun6i-a31-csi"
+    * "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi"
+    * "allwinner,sun8i-v3s-csi"
   - reg: base address and size of the memory-mapped region.
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the CSI
-- 
2.19.1

[PATCH v2 1/4] dt-bindings: media: sun6i: Add A31 and H3 compatibles

[Maxime Ripard]

The H3 has a slightly different CSI controller (no BT656, no CCI) which
looks a lot like the original A31 controller. Add a compatible for the A31,
and more specific compatible the for the H3 to be used in combination for
the A31.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 Documentation/devicetree/bindings/media/sun6i-csi.txt | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
index 2ff47a9507a6..3f8eb0296382 100644
--- a/Documentation/devicetree/bindings/media/sun6i-csi.txt
+++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
@@ -5,7 +5,10 @@ Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
 interface and CSI1 is used for parallel interface.
 
 Required properties:
-  - compatible: value must be "allwinner,sun8i-v3s-csi"
+  - compatible: value must be one of:
+    * "allwinner,sun6i-a31-csi"
+    * "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi"
+    * "allwinner,sun8i-v3s-csi"
   - reg: base address and size of the memory-mapped region.
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the CSI
-- 
2.19.1

[PATCH v2 2/4] media: sun6i: Add A31 compatible

[Maxime Ripard]

The first device that used that IP was the A31. Add it to our list of
compatibles.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 7af55ad142dc..9813bca38939 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -892,6 +892,7 @@ static int sun6i_csi_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id sun6i_csi_of_match[] = {
+	{ .compatible = "allwinner,sun6i-a31-csi", },
 	{ .compatible = "allwinner,sun8i-v3s-csi", },
 	{},
 };
-- 
2.19.1

[PATCH v2 2/4] media: sun6i: Add A31 compatible

[Maxime Ripard]

The first device that used that IP was the A31. Add it to our list of
compatibles.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 7af55ad142dc..9813bca38939 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -892,6 +892,7 @@ static int sun6i_csi_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id sun6i_csi_of_match[] = {
+	{ .compatible = "allwinner,sun6i-a31-csi", },
 	{ .compatible = "allwinner,sun8i-v3s-csi", },
 	{},
 };
-- 
2.19.1

[PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Maxime Ripard]

From: Mylène Josserand <mylene.josserand@bootlin.com>

The H3 and H5 features the same CSI controller that was initially found on
the A31.

Add a DT node for it.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b1530ebe427..8779ee750bd8 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -393,6 +393,13 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			csi_pins: csi {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+				       "PE5", "PE6", "PE7", "PE8", "PE9",
+				       "PE10", "PE11";
+				function = "csi";
+			};
+
 			emac_rgmii_pins: emac0 {
 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 				       "PD5", "PD7", "PD8", "PD9", "PD10",
@@ -744,6 +751,21 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		csi: camera@1cb0000 {
+			compatible = "allwinner,sun8i-h3-csi",
+				     "allwinner,sun6i-a31-csi";
+			reg = <0x01cb0000 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CSI>,
+				 <&ccu CLK_CSI_SCLK>,
+				 <&ccu CLK_DRAM_CSI>;
+			clock-names = "bus", "mod", "ram";
+			resets = <&ccu RST_BUS_CSI>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&csi_pins>;
+			status = "disabled";
+		};
+
 		hdmi: hdmi@1ee0000 {
 			compatible = "allwinner,sun8i-h3-dw-hdmi",
 				     "allwinner,sun8i-a83t-dw-hdmi";
-- 
2.19.1

[PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Maxime Ripard]

From: Myl?ne Josserand <mylene.josserand@bootlin.com>

The H3 and H5 features the same CSI controller that was initially found on
the A31.

Add a DT node for it.

Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b1530ebe427..8779ee750bd8 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -393,6 +393,13 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			csi_pins: csi {
+				pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+				       "PE5", "PE6", "PE7", "PE8", "PE9",
+				       "PE10", "PE11";
+				function = "csi";
+			};
+
 			emac_rgmii_pins: emac0 {
 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 				       "PD5", "PD7", "PD8", "PD9", "PD10",
@@ -744,6 +751,21 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		csi: camera at 1cb0000 {
+			compatible = "allwinner,sun8i-h3-csi",
+				     "allwinner,sun6i-a31-csi";
+			reg = <0x01cb0000 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CSI>,
+				 <&ccu CLK_CSI_SCLK>,
+				 <&ccu CLK_DRAM_CSI>;
+			clock-names = "bus", "mod", "ram";
+			resets = <&ccu RST_BUS_CSI>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&csi_pins>;
+			status = "disabled";
+		};
+
 		hdmi: hdmi at 1ee0000 {
 			compatible = "allwinner,sun8i-h3-dw-hdmi",
 				     "allwinner,sun8i-a83t-dw-hdmi";
-- 
2.19.1

[PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Maxime Ripard]

From: Mylène Josserand <mylene.josserand@bootlin.com>

The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
Omnivision. Enable the support for it in the DT.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 06010a9afba0..2ac62d109285 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -52,6 +52,37 @@
 		ethernet1 = &sdio_wifi;
 	};
 
+	cam_xclk: cam-xclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "cam-xclk";
+        };
+
+        reg_cam_avdd: cam-avdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-avdd";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
+        reg_cam_dovdd: cam-dovdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-dovdd";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
+        reg_cam_dvdd: cam-dvdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-dvdd";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "gmac-3v3";
@@ -69,6 +100,26 @@
 	};
 };
 
+&csi {
+        status = "okay";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* Parallel bus endpoint */
+                csi_from_ov5640: endpoint {
+                        remote-endpoint = <&ov5640_to_csi>;
+                        bus-width = <8>;
+                        data-shift = <2>;
+                        hsync-active = <1>; /* Active high */
+                        vsync-active = <0>; /* Active low */
+                        data-active = <1>;  /* Active high */
+                        pclk-sample = <1>;  /* Rising */
+                };
+        };
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -94,6 +145,40 @@
 	};
 };
 
+&i2c2 {
+	status = "okay";
+
+	ov5640: camera@3c {
+                compatible = "ovti,ov5640";
+                reg = <0x3c>;
+                clocks = <&cam_xclk>;
+                clock-names = "xclk";
+
+                reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>;
+                powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>;
+                AVDD-supply = <&reg_cam_avdd>;
+                DOVDD-supply = <&reg_cam_dovdd>;
+                DVDD-supply = <&reg_cam_dvdd>;
+
+                port {
+                        ov5640_to_csi: endpoint {
+                                remote-endpoint = <&csi_from_ov5640>;
+                                bus-width = <8>;
+                                data-shift = <2>;
+                                hsync-active = <1>; /* Active high */
+                                vsync-active = <0>; /* Active low */
+                                data-active = <1>;  /* Active high */
+                                pclk-sample = <1>;  /* Rising */
+                        };
+                };
+        };
+
+};
+
+&i2c2_pins {
+	bias-pull-up;
+};
+
 &ir {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ir_pins_a>;
-- 
2.19.1

[PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Maxime Ripard]

From: Myl?ne Josserand <mylene.josserand@bootlin.com>

The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
Omnivision. Enable the support for it in the DT.

Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 06010a9afba0..2ac62d109285 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -52,6 +52,37 @@
 		ethernet1 = &sdio_wifi;
 	};
 
+	cam_xclk: cam-xclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "cam-xclk";
+        };
+
+        reg_cam_avdd: cam-avdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-avdd";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
+        reg_cam_dovdd: cam-dovdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-dovdd";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
+        reg_cam_dvdd: cam-dvdd {
+                compatible = "regulator-fixed";
+                regulator-name = "cam500b-dvdd";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                vin-supply = <&reg_vcc3v3>;
+        };
+
 	reg_gmac_3v3: gmac-3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "gmac-3v3";
@@ -69,6 +100,26 @@
 	};
 };
 
+&csi {
+        status = "okay";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* Parallel bus endpoint */
+                csi_from_ov5640: endpoint {
+                        remote-endpoint = <&ov5640_to_csi>;
+                        bus-width = <8>;
+                        data-shift = <2>;
+                        hsync-active = <1>; /* Active high */
+                        vsync-active = <0>; /* Active low */
+                        data-active = <1>;  /* Active high */
+                        pclk-sample = <1>;  /* Rising */
+                };
+        };
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -94,6 +145,40 @@
 	};
 };
 
+&i2c2 {
+	status = "okay";
+
+	ov5640: camera at 3c {
+                compatible = "ovti,ov5640";
+                reg = <0x3c>;
+                clocks = <&cam_xclk>;
+                clock-names = "xclk";
+
+                reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>;
+                powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>;
+                AVDD-supply = <&reg_cam_avdd>;
+                DOVDD-supply = <&reg_cam_dovdd>;
+                DVDD-supply = <&reg_cam_dvdd>;
+
+                port {
+                        ov5640_to_csi: endpoint {
+                                remote-endpoint = <&csi_from_ov5640>;
+                                bus-width = <8>;
+                                data-shift = <2>;
+                                hsync-active = <1>; /* Active high */
+                                vsync-active = <0>; /* Active low */
+                                data-active = <1>;  /* Active high */
+                                pclk-sample = <1>;  /* Rising */
+                        };
+                };
+        };
+
+};
+
+&i2c2_pins {
+	bias-pull-up;
+};
+
 &ir {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ir_pins_a>;
-- 
2.19.1

Re: [PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Chen-Yu Tsai]

Hi,

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> From: Mylène Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 4b1530ebe427..8779ee750bd8 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -393,6 +393,13 @@
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
>
> +                       csi_pins: csi {
> +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",

You should separate out PE1, which provides the MCLK. Not all camera modules
need it. Some might have a standalone crystal to provide the reference clock.
Designs could then use that pin for other purposes.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

> +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> +                                      "PE10", "PE11";
> +                               function = "csi";
> +                       };
> +
>                         emac_rgmii_pins: emac0 {
>                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> @@ -744,6 +751,21 @@
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
>
> +               csi: camera@1cb0000 {
> +                       compatible = "allwinner,sun8i-h3-csi",
> +                                    "allwinner,sun6i-a31-csi";
> +                       reg = <0x01cb0000 0x1000>;
> +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_CSI>,
> +                                <&ccu CLK_CSI_SCLK>,
> +                                <&ccu CLK_DRAM_CSI>;
> +                       clock-names = "bus", "mod", "ram";
> +                       resets = <&ccu RST_BUS_CSI>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&csi_pins>;
> +                       status = "disabled";
> +               };
> +
>                 hdmi: hdmi@1ee0000 {
>                         compatible = "allwinner,sun8i-h3-dw-hdmi",
>                                      "allwinner,sun8i-a83t-dw-hdmi";
> --
> 2.19.1
>

[PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Chen-Yu Tsai]

Hi,

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> From: Myl?ne Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 4b1530ebe427..8779ee750bd8 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -393,6 +393,13 @@
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
>
> +                       csi_pins: csi {
> +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",

You should separate out PE1, which provides the MCLK. Not all camera modules
need it. Some might have a standalone crystal to provide the reference clock.
Designs could then use that pin for other purposes.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

> +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> +                                      "PE10", "PE11";
> +                               function = "csi";
> +                       };
> +
>                         emac_rgmii_pins: emac0 {
>                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> @@ -744,6 +751,21 @@
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
>
> +               csi: camera at 1cb0000 {
> +                       compatible = "allwinner,sun8i-h3-csi",
> +                                    "allwinner,sun6i-a31-csi";
> +                       reg = <0x01cb0000 0x1000>;
> +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_CSI>,
> +                                <&ccu CLK_CSI_SCLK>,
> +                                <&ccu CLK_DRAM_CSI>;
> +                       clock-names = "bus", "mod", "ram";
> +                       resets = <&ccu RST_BUS_CSI>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&csi_pins>;
> +                       status = "disabled";
> +               };
> +
>                 hdmi: hdmi at 1ee0000 {
>                         compatible = "allwinner,sun8i-h3-dw-hdmi",
>                                      "allwinner,sun8i-a83t-dw-hdmi";
> --
> 2.19.1
>

Re: [PATCH v2 2/4] media: sun6i: Add A31 compatible

[Chen-Yu Tsai]

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> The first device that used that IP was the A31. Add it to our list of
> compatibles.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v2 2/4] media: sun6i: Add A31 compatible

[Chen-Yu Tsai]

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> The first device that used that IP was the A31. Add it to our list of
> compatibles.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 1/4] dt-bindings: media: sun6i: Add A31 and H3 compatibles

[Chen-Yu Tsai]

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> The H3 has a slightly different CSI controller (no BT656, no CCI) which
> looks a lot like the original A31 controller. Add a compatible for the A31,
> and more specific compatible the for the H3 to be used in combination for
> the A31.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v2 1/4] dt-bindings: media: sun6i: Add A31 and H3 compatibles

[Chen-Yu Tsai]

On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard
<maxime.ripard@bootlin.com> wrote:
>
> The H3 has a slightly different CSI controller (no BT656, no CCI) which
> looks a lot like the original A31 controller. Add a compatible for the A31,
> and more specific compatible the for the H3 to be used in combination for
> the A31.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Jagan Teki]

On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Mylène Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 4b1530ebe427..8779ee750bd8 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -393,6 +393,13 @@
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
>
> +                       csi_pins: csi {
> +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> +                                      "PE10", "PE11";
> +                               function = "csi";
> +                       };
> +
>                         emac_rgmii_pins: emac0 {
>                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> @@ -744,6 +751,21 @@
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
>
> +               csi: camera@1cb0000 {
> +                       compatible = "allwinner,sun8i-h3-csi",
> +                                    "allwinner,sun6i-a31-csi";
> +                       reg = <0x01cb0000 0x1000>;
> +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_CSI>,
> +                                <&ccu CLK_CSI_SCLK>,
> +                                <&ccu CLK_DRAM_CSI>;
> +                       clock-names = "bus", "mod", "ram";

Don't we need CLK_CSI_MCLK which can be pinout via PE1?

[PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Jagan Teki]

On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Myl?ne Josserand <mylene.josserand@bootlin.com>
>
> The H3 and H5 features the same CSI controller that was initially found on
> the A31.
>
> Add a DT node for it.
>
> Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 4b1530ebe427..8779ee750bd8 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -393,6 +393,13 @@
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
>
> +                       csi_pins: csi {
> +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> +                                      "PE10", "PE11";
> +                               function = "csi";
> +                       };
> +
>                         emac_rgmii_pins: emac0 {
>                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> @@ -744,6 +751,21 @@
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
>
> +               csi: camera at 1cb0000 {
> +                       compatible = "allwinner,sun8i-h3-csi",
> +                                    "allwinner,sun6i-a31-csi";
> +                       reg = <0x01cb0000 0x1000>;
> +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_CSI>,
> +                                <&ccu CLK_CSI_SCLK>,
> +                                <&ccu CLK_DRAM_CSI>;
> +                       clock-names = "bus", "mod", "ram";

Don't we need CLK_CSI_MCLK which can be pinout via PE1?

Re: [PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Chen-Yu Tsai]

On Thu, Nov 22, 2018 at 7:45 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > From: Mylène Josserand <mylene.josserand@bootlin.com>
> >
> > The H3 and H5 features the same CSI controller that was initially found on
> > the A31.
> >
> > Add a DT node for it.
> >
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> >  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 4b1530ebe427..8779ee750bd8 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -393,6 +393,13 @@
> >                         interrupt-controller;
> >                         #interrupt-cells = <3>;
> >
> > +                       csi_pins: csi {
> > +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> > +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> > +                                      "PE10", "PE11";
> > +                               function = "csi";
> > +                       };
> > +
> >                         emac_rgmii_pins: emac0 {
> >                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> >                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> > @@ -744,6 +751,21 @@
> >                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> >                 };
> >
> > +               csi: camera@1cb0000 {
> > +                       compatible = "allwinner,sun8i-h3-csi",
> > +                                    "allwinner,sun6i-a31-csi";
> > +                       reg = <0x01cb0000 0x1000>;
> > +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_CSI>,
> > +                                <&ccu CLK_CSI_SCLK>,
> > +                                <&ccu CLK_DRAM_CSI>;
> > +                       clock-names = "bus", "mod", "ram";
>
> Don't we need CLK_CSI_MCLK which can be pinout via PE1?

The CSI hardware block does not have any controls for MCLK.
It's simply routed from the CCU directly to the pin.

ChenYu

[PATCH v2 3/4] ARM: dts: sun8i: Add the H3/H5 CSI controller

[Chen-Yu Tsai]

On Thu, Nov 22, 2018 at 7:45 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> >
> > The H3 and H5 features the same CSI controller that was initially found on
> > the A31.
> >
> > Add a DT node for it.
> >
> > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> >  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 4b1530ebe427..8779ee750bd8 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -393,6 +393,13 @@
> >                         interrupt-controller;
> >                         #interrupt-cells = <3>;
> >
> > +                       csi_pins: csi {
> > +                               pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> > +                                      "PE5", "PE6", "PE7", "PE8", "PE9",
> > +                                      "PE10", "PE11";
> > +                               function = "csi";
> > +                       };
> > +
> >                         emac_rgmii_pins: emac0 {
> >                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> >                                        "PD5", "PD7", "PD8", "PD9", "PD10",
> > @@ -744,6 +751,21 @@
> >                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> >                 };
> >
> > +               csi: camera at 1cb0000 {
> > +                       compatible = "allwinner,sun8i-h3-csi",
> > +                                    "allwinner,sun6i-a31-csi";
> > +                       reg = <0x01cb0000 0x1000>;
> > +                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_CSI>,
> > +                                <&ccu CLK_CSI_SCLK>,
> > +                                <&ccu CLK_DRAM_CSI>;
> > +                       clock-names = "bus", "mod", "ram";
>
> Don't we need CLK_CSI_MCLK which can be pinout via PE1?

The CSI hardware block does not have any controls for MCLK.
It's simply routed from the CCU directly to the pin.

ChenYu

Re: [PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Jagan Teki]

On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Mylène Josserand <mylene.josserand@bootlin.com>
>
> The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
> Omnivision. Enable the support for it in the DT.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index 06010a9afba0..2ac62d109285 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -52,6 +52,37 @@
>                 ethernet1 = &sdio_wifi;
>         };
>
> +       cam_xclk: cam-xclk {
> +                #clock-cells = <0>;
> +                compatible = "fixed-clock";
> +                clock-frequency = <24000000>;
> +                clock-output-names = "cam-xclk";
> +        };
> +
> +        reg_cam_avdd: cam-avdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-avdd";
> +                regulator-min-microvolt = <2800000>;
> +                regulator-max-microvolt = <2800000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
> +        reg_cam_dovdd: cam-dovdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-dovdd";
> +                regulator-min-microvolt = <1800000>;
> +                regulator-max-microvolt = <1800000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
> +        reg_cam_dvdd: cam-dvdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-dvdd";
> +                regulator-min-microvolt = <1500000>;
> +                regulator-max-microvolt = <1500000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
>         reg_gmac_3v3: gmac-3v3 {
>                 compatible = "regulator-fixed";
>                 regulator-name = "gmac-3v3";
> @@ -69,6 +100,26 @@
>         };
>  };
>
> +&csi {
> +        status = "okay";
> +
> +        port {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                /* Parallel bus endpoint */
> +                csi_from_ov5640: endpoint {
> +                        remote-endpoint = <&ov5640_to_csi>;
> +                        bus-width = <8>;
> +                        data-shift = <2>;
> +                        hsync-active = <1>; /* Active high */
> +                        vsync-active = <0>; /* Active low */
> +                        data-active = <1>;  /* Active high */
> +                        pclk-sample = <1>;  /* Rising */
> +                };
> +        };
> +};
> +
>  &ehci1 {
>         status = "okay";
>  };
> @@ -94,6 +145,40 @@
>         };
>  };
>
> +&i2c2 {
> +       status = "okay";
> +
> +       ov5640: camera@3c {
> +                compatible = "ovti,ov5640";
> +                reg = <0x3c>;
> +                clocks = <&cam_xclk>;

I think we can directly use existing 24MHz oscillator, &osc24M

[PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Jagan Teki]

On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> From: Myl?ne Josserand <mylene.josserand@bootlin.com>
>
> The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
> Omnivision. Enable the support for it in the DT.
>
> Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
>  arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> index 06010a9afba0..2ac62d109285 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> @@ -52,6 +52,37 @@
>                 ethernet1 = &sdio_wifi;
>         };
>
> +       cam_xclk: cam-xclk {
> +                #clock-cells = <0>;
> +                compatible = "fixed-clock";
> +                clock-frequency = <24000000>;
> +                clock-output-names = "cam-xclk";
> +        };
> +
> +        reg_cam_avdd: cam-avdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-avdd";
> +                regulator-min-microvolt = <2800000>;
> +                regulator-max-microvolt = <2800000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
> +        reg_cam_dovdd: cam-dovdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-dovdd";
> +                regulator-min-microvolt = <1800000>;
> +                regulator-max-microvolt = <1800000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
> +        reg_cam_dvdd: cam-dvdd {
> +                compatible = "regulator-fixed";
> +                regulator-name = "cam500b-dvdd";
> +                regulator-min-microvolt = <1500000>;
> +                regulator-max-microvolt = <1500000>;
> +                vin-supply = <&reg_vcc3v3>;
> +        };
> +
>         reg_gmac_3v3: gmac-3v3 {
>                 compatible = "regulator-fixed";
>                 regulator-name = "gmac-3v3";
> @@ -69,6 +100,26 @@
>         };
>  };
>
> +&csi {
> +        status = "okay";
> +
> +        port {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                /* Parallel bus endpoint */
> +                csi_from_ov5640: endpoint {
> +                        remote-endpoint = <&ov5640_to_csi>;
> +                        bus-width = <8>;
> +                        data-shift = <2>;
> +                        hsync-active = <1>; /* Active high */
> +                        vsync-active = <0>; /* Active low */
> +                        data-active = <1>;  /* Active high */
> +                        pclk-sample = <1>;  /* Rising */
> +                };
> +        };
> +};
> +
>  &ehci1 {
>         status = "okay";
>  };
> @@ -94,6 +145,40 @@
>         };
>  };
>
> +&i2c2 {
> +       status = "okay";
> +
> +       ov5640: camera at 3c {
> +                compatible = "ovti,ov5640";
> +                reg = <0x3c>;
> +                clocks = <&cam_xclk>;

I think we can directly use existing 24MHz oscillator, &osc24M

Re: [PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Maxime Ripard]

On Fri, Nov 23, 2018 at 11:51:38AM +0530, Jagan Teki wrote:
> On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > From: Mylène Josserand <mylene.josserand@bootlin.com>
> >
> > The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
> > Omnivision. Enable the support for it in the DT.
> >
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> >  arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
> >  1 file changed, 85 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > index 06010a9afba0..2ac62d109285 100644
> > --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > @@ -52,6 +52,37 @@
> >                 ethernet1 = &sdio_wifi;
> >         };
> >
> > +       cam_xclk: cam-xclk {
> > +                #clock-cells = <0>;
> > +                compatible = "fixed-clock";
> > +                clock-frequency = <24000000>;
> > +                clock-output-names = "cam-xclk";
> > +        };
> > +
> > +        reg_cam_avdd: cam-avdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-avdd";
> > +                regulator-min-microvolt = <2800000>;
> > +                regulator-max-microvolt = <2800000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> > +        reg_cam_dovdd: cam-dovdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-dovdd";
> > +                regulator-min-microvolt = <1800000>;
> > +                regulator-max-microvolt = <1800000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> > +        reg_cam_dvdd: cam-dvdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-dvdd";
> > +                regulator-min-microvolt = <1500000>;
> > +                regulator-max-microvolt = <1500000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> >         reg_gmac_3v3: gmac-3v3 {
> >                 compatible = "regulator-fixed";
> >                 regulator-name = "gmac-3v3";
> > @@ -69,6 +100,26 @@
> >         };
> >  };
> >
> > +&csi {
> > +        status = "okay";
> > +
> > +        port {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +
> > +                /* Parallel bus endpoint */
> > +                csi_from_ov5640: endpoint {
> > +                        remote-endpoint = <&ov5640_to_csi>;
> > +                        bus-width = <8>;
> > +                        data-shift = <2>;
> > +                        hsync-active = <1>; /* Active high */
> > +                        vsync-active = <0>; /* Active low */
> > +                        data-active = <1>;  /* Active high */
> > +                        pclk-sample = <1>;  /* Rising */
> > +                };
> > +        };
> > +};
> > +
> >  &ehci1 {
> >         status = "okay";
> >  };
> > @@ -94,6 +145,40 @@
> >         };
> >  };
> >
> > +&i2c2 {
> > +       status = "okay";
> > +
> > +       ov5640: camera@3c {
> > +                compatible = "ovti,ov5640";
> > +                reg = <0x3c>;
> > +                clocks = <&cam_xclk>;
> 
> I think we can directly use existing 24MHz oscillator, &osc24M

That's not how the hardware is built, so not really.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH v2 4/4] [DO NOT MERGE] ARM: dts: sun8i: Add CAM500B camera module to the Nano Pi M1+

[Maxime Ripard]

On Fri, Nov 23, 2018 at 11:51:38AM +0530, Jagan Teki wrote:
> On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > From: Myl?ne Josserand <mylene.josserand@bootlin.com>
> >
> > The Nano Pi M1+ comes with an optional sensor based on the ov5640 from
> > Omnivision. Enable the support for it in the DT.
> >
> > Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> > ---
> >  arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 85 +++++++++++++++++++
> >  1 file changed, 85 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > index 06010a9afba0..2ac62d109285 100644
> > --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
> > @@ -52,6 +52,37 @@
> >                 ethernet1 = &sdio_wifi;
> >         };
> >
> > +       cam_xclk: cam-xclk {
> > +                #clock-cells = <0>;
> > +                compatible = "fixed-clock";
> > +                clock-frequency = <24000000>;
> > +                clock-output-names = "cam-xclk";
> > +        };
> > +
> > +        reg_cam_avdd: cam-avdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-avdd";
> > +                regulator-min-microvolt = <2800000>;
> > +                regulator-max-microvolt = <2800000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> > +        reg_cam_dovdd: cam-dovdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-dovdd";
> > +                regulator-min-microvolt = <1800000>;
> > +                regulator-max-microvolt = <1800000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> > +        reg_cam_dvdd: cam-dvdd {
> > +                compatible = "regulator-fixed";
> > +                regulator-name = "cam500b-dvdd";
> > +                regulator-min-microvolt = <1500000>;
> > +                regulator-max-microvolt = <1500000>;
> > +                vin-supply = <&reg_vcc3v3>;
> > +        };
> > +
> >         reg_gmac_3v3: gmac-3v3 {
> >                 compatible = "regulator-fixed";
> >                 regulator-name = "gmac-3v3";
> > @@ -69,6 +100,26 @@
> >         };
> >  };
> >
> > +&csi {
> > +        status = "okay";
> > +
> > +        port {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +
> > +                /* Parallel bus endpoint */
> > +                csi_from_ov5640: endpoint {
> > +                        remote-endpoint = <&ov5640_to_csi>;
> > +                        bus-width = <8>;
> > +                        data-shift = <2>;
> > +                        hsync-active = <1>; /* Active high */
> > +                        vsync-active = <0>; /* Active low */
> > +                        data-active = <1>;  /* Active high */
> > +                        pclk-sample = <1>;  /* Rising */
> > +                };
> > +        };
> > +};
> > +
> >  &ehci1 {
> >         status = "okay";
> >  };
> > @@ -94,6 +145,40 @@
> >         };
> >  };
> >
> > +&i2c2 {
> > +       status = "okay";
> > +
> > +       ov5640: camera at 3c {
> > +                compatible = "ovti,ov5640";
> > +                reg = <0x3c>;
> > +                clocks = <&cam_xclk>;
> 
> I think we can directly use existing 24MHz oscillator, &osc24M

That's not how the hardware is built, so not really.

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com