* [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
@ 2018-11-20 9:23 Imre Deak
2018-11-20 9:23 ` [PATCH v3 2/3] drm/i915: Make EDP PSR flags " Imre Deak
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-20 9:23 UTC (permalink / raw)
To: intel-gfx
Depending on the transcoder enum values to translate from transcoder
to pipe/transcoder register addresses can easily break if we add a new
transcoder. So remove the dependency by using named initializers.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 52 ++++++++++++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 983ae7fd8217..1b81d7cb209e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -33,16 +33,30 @@
#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
#define GEN_DEFAULT_PIPEOFFSETS \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ }
#define GEN_CHV_PIPEOFFSETS \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- CHV_PIPE_C_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- CHV_TRANSCODER_C_OFFSET }
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
+ }
#define CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
@@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = {
#define GEN11_FEATURES \
GEN10_FEATURES, \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
- PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
- TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }, \
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] drm/i915: Make EDP PSR flags not depend on enum values
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
@ 2018-11-20 9:23 ` Imre Deak
2018-11-20 9:23 ` [PATCH v3 3/3] drm/i915: Add code comment on assumption of pipe==transcoder Imre Deak
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Depending on the transcoder enum values to translate from transcoder
to EDP PSR flags can easily break if we add a new transcoder. So remove
the dependency by using an explicit mapping.
While at it also add a WARN for unexpected trancoders.
v2:
- Simplify things by defining flag shift values instead of indices.
- s/trans/cpu_transcoder/ (Ville)
v3:
- Define flags to look like seperate bits instead of the values of
the same bitfield. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 +++++---
drivers/gpu/drm/i915/intel_psr.c | 55 +++++++++++++++++++++++++++-------------
2 files changed, 44 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index edb58af1e903..e6b371e986ee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4150,9 +4150,13 @@ enum {
/* Bspec claims those aren't shifted but stay at 0x64800 */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
-#define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31))
-#define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31))
-#define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31))
+#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
+#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
+#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
+#define EDP_PSR_TRANSCODER_C_SHIFT 24
+#define EDP_PSR_TRANSCODER_B_SHIFT 16
+#define EDP_PSR_TRANSCODER_A_SHIFT 8
+#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 48df16a02fac..26292961d693 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -83,25 +83,42 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
+static int edp_psr_shift(enum transcoder cpu_transcoder)
+{
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ return EDP_PSR_TRANSCODER_A_SHIFT;
+ case TRANSCODER_B:
+ return EDP_PSR_TRANSCODER_B_SHIFT;
+ case TRANSCODER_C:
+ return EDP_PSR_TRANSCODER_C_SHIFT;
+ default:
+ MISSING_CASE(cpu_transcoder);
+ /* fallthrough */
+ case TRANSCODER_EDP:
+ return EDP_PSR_TRANSCODER_EDP_SHIFT;
+ }
+}
+
void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
u32 debug_mask, mask;
+ enum transcoder cpu_transcoder;
+ u32 transcoders = BIT(TRANSCODER_EDP);
- mask = EDP_PSR_ERROR(TRANSCODER_EDP);
- debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) |
- EDP_PSR_PRE_ENTRY(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8) {
- mask |= EDP_PSR_ERROR(TRANSCODER_A) |
- EDP_PSR_ERROR(TRANSCODER_B) |
- EDP_PSR_ERROR(TRANSCODER_C);
-
- debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) |
- EDP_PSR_PRE_ENTRY(TRANSCODER_A) |
- EDP_PSR_POST_EXIT(TRANSCODER_B) |
- EDP_PSR_PRE_ENTRY(TRANSCODER_B) |
- EDP_PSR_POST_EXIT(TRANSCODER_C) |
- EDP_PSR_PRE_ENTRY(TRANSCODER_C);
+ if (INTEL_GEN(dev_priv) >= 8)
+ transcoders |= BIT(TRANSCODER_A) |
+ BIT(TRANSCODER_B) |
+ BIT(TRANSCODER_C);
+
+ debug_mask = 0;
+ mask = 0;
+ for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ int shift = edp_psr_shift(cpu_transcoder);
+
+ mask |= EDP_PSR_ERROR(shift);
+ debug_mask |= EDP_PSR_POST_EXIT(shift) |
+ EDP_PSR_PRE_ENTRY(shift);
}
if (debug & I915_PSR_DEBUG_IRQ)
@@ -159,18 +176,20 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
BIT(TRANSCODER_C);
for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
+ int shift = edp_psr_shift(cpu_transcoder);
+
/* FIXME: Exit PSR and link train manually when this happens. */
- if (psr_iir & EDP_PSR_ERROR(cpu_transcoder))
+ if (psr_iir & EDP_PSR_ERROR(shift))
DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",
transcoder_name(cpu_transcoder));
- if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
dev_priv->psr.last_entry_attempt = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
transcoder_name(cpu_transcoder));
}
- if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
transcoder_name(cpu_transcoder));
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] drm/i915: Add code comment on assumption of pipe==transcoder
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
2018-11-20 9:23 ` [PATCH v3 2/3] drm/i915: Make EDP PSR flags " Imre Deak
@ 2018-11-20 9:23 ` Imre Deak
2018-11-20 10:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-20 9:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Add a comment to the pipe and transcoder enum definitions about our
assumption in the code about enum values for pipes and transcoders
with a 1:1 transcoder -> pipe mapping.
v2:
- Clarify more what are the assumptions about the enum values. (Ville)
v3: (Lucas)
- s/->/ -> / so it looks less like pointer dereferencing.
- Use pipe enums as initializers in the transcoder enum definition.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
---
drivers/gpu/drm/i915/intel_display.h | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 43eb4ebbcc35..5f2955b944da 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -43,6 +43,11 @@ enum i915_gpio {
GPIOM,
};
+/*
+ * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
+ * rest have consecutive values and match the enum values of transcoders
+ * with a 1:1 transcoder -> pipe mapping.
+ */
enum pipe {
INVALID_PIPE = -1,
@@ -57,9 +62,20 @@ enum pipe {
#define pipe_name(p) ((p) + 'A')
enum transcoder {
- TRANSCODER_A = 0,
- TRANSCODER_B,
- TRANSCODER_C,
+ /*
+ * The following transcoders have a 1:1 transcoder -> pipe mapping,
+ * keep their values fixed: the code assumes that TRANSCODER_A=0, the
+ * rest have consecutive values and match the enum values of the pipes
+ * they map to.
+ */
+ TRANSCODER_A = PIPE_A,
+ TRANSCODER_B = PIPE_B,
+ TRANSCODER_C = PIPE_C,
+
+ /*
+ * The following transcoders can map to any pipe, their enum value
+ * doesn't need to stay fixed.
+ */
TRANSCODER_EDP,
TRANSCODER_DSI_0,
TRANSCODER_DSI_1,
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
2018-11-20 9:23 ` [PATCH v3 2/3] drm/i915: Make EDP PSR flags " Imre Deak
2018-11-20 9:23 ` [PATCH v3 3/3] drm/i915: Add code comment on assumption of pipe==transcoder Imre Deak
@ 2018-11-20 10:36 ` Patchwork
2018-11-20 11:01 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-20 13:53 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-11-20 10:36 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
URL : https://patchwork.freedesktop.org/series/52742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9eb72bdc9a6 drm/i915: Make pipe/transcoder offsets not depend on enum values
e61284bcc665 drm/i915: Make EDP PSR flags not depend on enum values
-:19: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'?
#19:
- Define flags to look like seperate bits instead of the values of
total: 0 errors, 1 warnings, 0 checks, 96 lines checked
e57fe9da9a20 drm/i915: Add code comment on assumption of pipe==transcoder
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
` (2 preceding siblings ...)
2018-11-20 10:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Patchwork
@ 2018-11-20 11:01 ` Patchwork
2018-11-20 13:53 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-11-20 11:01 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
URL : https://patchwork.freedesktop.org/series/52742/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5169 -> Patchwork_10857 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52742/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10857:
=== IGT changes ===
==== Warnings ====
igt@kms_busy@basic-flip-a:
{fi-kbl-7567u}: SKIP -> PASS +2
== Known issues ==
Here are the changes found in Patchwork_10857 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@i915_selftest@live_sanitycheck:
fi-gdg-551: PASS -> INCOMPLETE (fdo#108789)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
{fi-kbl-7567u}: DMESG-WARN (fdo#103558, fdo#105602) -> PASS
igt@gem_ctx_create@basic-files:
fi-bsw-kefka: FAIL (fdo#108656) -> PASS
igt@gem_exec_suspend@basic-s3:
{fi-kbl-7567u}: DMESG-WARN (fdo#103558, fdo#105602, fdo#105079) -> PASS
igt@i915_selftest@live_hangcheck:
fi-bwr-2160: DMESG-FAIL (fdo#108735) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-byt-clapper: INCOMPLETE (fdo#102657) -> PASS
==== Warnings ====
igt@kms_chamelium@common-hpd-after-suspend:
{fi-kbl-7567u}: FAIL (fdo#108755) -> DMESG-FAIL (fdo#105079)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102657 https://bugs.freedesktop.org/show_bug.cgi?id=102657
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#105079 https://bugs.freedesktop.org/show_bug.cgi?id=105079
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656
fdo#108735 https://bugs.freedesktop.org/show_bug.cgi?id=108735
fdo#108755 https://bugs.freedesktop.org/show_bug.cgi?id=108755
fdo#108789 https://bugs.freedesktop.org/show_bug.cgi?id=108789
== Participating hosts (52 -> 45) ==
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-kbl-7560u
== Build changes ==
* Linux: CI_DRM_5169 -> Patchwork_10857
CI_DRM_5169: ed08968fdc2130ba3cb6f3d7dbe82b6a8c39973d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10857: e57fe9da9a20d3e7fc3135f388d0c9c697f84ba2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e57fe9da9a20 drm/i915: Add code comment on assumption of pipe==transcoder
e61284bcc665 drm/i915: Make EDP PSR flags not depend on enum values
c9eb72bdc9a6 drm/i915: Make pipe/transcoder offsets not depend on enum values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10857/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
` (3 preceding siblings ...)
2018-11-20 11:01 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-11-20 13:53 ` Patchwork
2018-11-21 11:43 ` Imre Deak
4 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2018-11-20 13:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
URL : https://patchwork.freedesktop.org/series/52742/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5169_full -> Patchwork_10857_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10857_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10857_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10857_full:
=== IGT changes ===
==== Warnings ====
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10857_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drm_import_export@import-close-race-flink:
shard-skl: NOTRUN -> TIMEOUT (fdo#108667)
igt@gem_eio@in-flight-1us:
shard-glk: PASS -> FAIL (fdo#107799)
igt@gem_exec_schedule@pi-ringfull-bsd:
{shard-iclb}: NOTRUN -> FAIL (fdo#103158) +2
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: NOTRUN -> TIMEOUT (fdo#108039)
igt@i915_suspend@shrink:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
igt@kms_available_modes_crc@available_mode_test_crc:
{shard-iclb}: NOTRUN -> FAIL (fdo#106641)
igt@kms_busy@extended-modeset-hang-newfb-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-hsw: PASS -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956) +5
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
{shard-iclb}: NOTRUN -> FAIL (fdo#107725) +4
igt@kms_chv_cursor_fail@pipe-b-256x256-top-edge:
shard-skl: PASS -> FAIL (fdo#104671)
igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
shard-skl: NOTRUN -> FAIL (fdo#104671)
igt@kms_cursor_crc@cursor-128x128-sliding:
shard-apl: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-256x256-random:
{shard-iclb}: NOTRUN -> FAIL (fdo#103232) +9
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108) +1
igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
shard-glk: PASS -> FAIL (fdo#106509, fdo#105454)
igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
{shard-iclb}: PASS -> WARN (fdo#108336) +3
igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
{shard-iclb}: NOTRUN -> WARN (fdo#108336)
igt@kms_fbcon_fbt@psr:
{shard-iclb}: NOTRUN -> FAIL (fdo#107882)
shard-skl: NOTRUN -> FAIL (fdo#107882)
igt@kms_flip@busy-flip:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724) +16
igt@kms_frontbuffer_tracking@basic:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724, fdo#108336) +5
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
{shard-iclb}: PASS -> DMESG-FAIL (fdo#107724) +4
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
{shard-iclb}: NOTRUN -> DMESG-FAIL (fdo#107724) +4
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-skl: NOTRUN -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
{shard-iclb}: PASS -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
{shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724, fdo#108336) +6
igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
{shard-iclb}: NOTRUN -> FAIL (fdo#103167) +4
igt@kms_hdmi_inject@inject-audio:
{shard-iclb}: NOTRUN -> FAIL (fdo#102370)
igt@kms_panel_fitting@legacy:
shard-skl: NOTRUN -> FAIL (fdo#105456)
igt@kms_plane@plane-position-covered-pipe-c-planes:
shard-apl: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
shard-skl: PASS -> FAIL (fdo#107815)
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
shard-skl: NOTRUN -> FAIL (fdo#108145) +4
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
{shard-iclb}: NOTRUN -> FAIL (fdo#103166) +4
igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
{shard-iclb}: PASS -> FAIL (fdo#103166) +1
igt@kms_psr@no_drrs:
{shard-iclb}: PASS -> FAIL (fdo#108341)
igt@kms_rotation_crc@primary-rotation-180:
shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103925)
igt@kms_vblank@pipe-a-ts-continuation-idle:
{shard-iclb}: PASS -> DMESG-WARN (fdo#107724) +11
igt@pm_backlight@fade_with_suspend:
shard-skl: NOTRUN -> FAIL (fdo#107847)
igt@pm_rps@min-max-config-loaded:
{shard-iclb}: NOTRUN -> FAIL (fdo#102250)
==== Possible fixes ====
igt@gem_eio@in-flight-10ms:
shard-glk: FAIL (fdo#107799) -> PASS
igt@gem_exec_async@concurrent-writes-vebox:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
shard-skl: FAIL (fdo#107815, fdo#108470) -> PASS
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: FAIL (fdo#106641) -> PASS
igt@kms_busy@extended-modeset-hang-newfb-render-c:
shard-kbl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_chv_cursor_fail@pipe-a-128x128-left-edge:
shard-skl: FAIL (fdo#104671) -> PASS
igt@kms_color@pipe-c-gamma:
shard-skl: FAIL (fdo#108228, fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-glk: FAIL (fdo#103232) -> PASS +3
igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
shard-skl: FAIL (fdo#103184) -> PASS
igt@kms_flip@flip-vs-absolute-wf_vblank:
shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +16
igt@kms_flip_tiling@flip-changes-tiling-yf:
shard-kbl: DMESG-WARN (fdo#105604) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
shard-skl: FAIL (fdo#103167) -> PASS
igt@kms_plane@plane-panning-bottom-right-pipe-c-planes:
shard-skl: FAIL (fdo#103166) -> PASS
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-skl: INCOMPLETE (fdo#107773, fdo#104108) -> PASS
igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
shard-glk: FAIL (fdo#108145) -> PASS
igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
shard-apl: FAIL (fdo#103166) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
shard-glk: FAIL (fdo#103166) -> PASS +1
igt@perf@polling:
shard-hsw: FAIL (fdo#102252) -> PASS
igt@pm_rpm@legacy-planes:
shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS +1
{shard-iclb}: DMESG-WARN (fdo#108654) -> PASS
igt@pm_rpm@system-suspend-modeset:
shard-skl: INCOMPLETE (fdo#104108, fdo#107807) -> PASS
==== Warnings ====
igt@i915_suspend@shrink:
shard-skl: INCOMPLETE (fdo#106886) -> DMESG-WARN (fdo#108784)
igt@kms_ccs@pipe-c-crc-primary-basic:
{shard-iclb}: FAIL (fdo#107725) -> DMESG-WARN (fdo#107724, fdo#108336)
igt@kms_content_protection@atomic:
shard-apl: FAIL (fdo#108597) -> INCOMPLETE (fdo#103927)
igt@kms_cursor_crc@cursor-64x64-random:
shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> FAIL (fdo#103232)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102370 https://bugs.freedesktop.org/show_bug.cgi?id=102370
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105604 https://bugs.freedesktop.org/show_bug.cgi?id=105604
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
fdo#107725 https://bugs.freedesktop.org/show_bug.cgi?id=107725
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107799 https://bugs.freedesktop.org/show_bug.cgi?id=107799
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108228 https://bugs.freedesktop.org/show_bug.cgi?id=108228
fdo#108336 https://bugs.freedesktop.org/show_bug.cgi?id=108336
fdo#108341 https://bugs.freedesktop.org/show_bug.cgi?id=108341
fdo#108470 https://bugs.freedesktop.org/show_bug.cgi?id=108470
fdo#108597 https://bugs.freedesktop.org/show_bug.cgi?id=108597
fdo#108654 https://bugs.freedesktop.org/show_bug.cgi?id=108654
fdo#108667 https://bugs.freedesktop.org/show_bug.cgi?id=108667
fdo#108784 https://bugs.freedesktop.org/show_bug.cgi?id=108784
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (7 -> 7) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5169 -> Patchwork_10857
CI_DRM_5169: ed08968fdc2130ba3cb6f3d7dbe82b6a8c39973d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10857: e57fe9da9a20d3e7fc3135f388d0c9c697f84ba2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10857/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-20 13:53 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-11-21 11:43 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-11-21 11:43 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä, Lucas De Marchi
On Tue, Nov 20, 2018 at 01:53:06PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
> URL : https://patchwork.freedesktop.org/series/52742/
> State : success
Pushed to -dinq, thanks for the reviews.
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5169_full -> Patchwork_10857_full =
>
> == Summary - WARNING ==
>
> Minor unknown changes coming with Patchwork_10857_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10857_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in Patchwork_10857_full:
>
> === IGT changes ===
>
> ==== Warnings ====
>
> igt@pm_rc6_residency@rc6-accuracy:
> shard-snb: PASS -> SKIP
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_10857_full that come from known issues:
>
> === IGT changes ===
>
> ==== Issues hit ====
>
> igt@drm_import_export@import-close-race-flink:
> shard-skl: NOTRUN -> TIMEOUT (fdo#108667)
>
> igt@gem_eio@in-flight-1us:
> shard-glk: PASS -> FAIL (fdo#107799)
>
> igt@gem_exec_schedule@pi-ringfull-bsd:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103158) +2
>
> igt@gem_ppgtt@blt-vs-render-ctxn:
> shard-skl: NOTRUN -> TIMEOUT (fdo#108039)
>
> igt@i915_suspend@shrink:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#108784)
>
> igt@kms_available_modes_crc@available_mode_test_crc:
> {shard-iclb}: NOTRUN -> FAIL (fdo#106641)
>
> igt@kms_busy@extended-modeset-hang-newfb-render-a:
> shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +2
>
> igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
> shard-hsw: PASS -> DMESG-WARN (fdo#107956)
>
> igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107956) +5
>
> igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
> {shard-iclb}: NOTRUN -> FAIL (fdo#107725) +4
>
> igt@kms_chv_cursor_fail@pipe-b-256x256-top-edge:
> shard-skl: PASS -> FAIL (fdo#104671)
>
> igt@kms_chv_cursor_fail@pipe-c-128x128-bottom-edge:
> shard-skl: NOTRUN -> FAIL (fdo#104671)
>
> igt@kms_cursor_crc@cursor-128x128-sliding:
> shard-apl: PASS -> FAIL (fdo#103232) +2
>
> igt@kms_cursor_crc@cursor-256x256-random:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103232) +9
>
> igt@kms_cursor_crc@cursor-64x64-suspend:
> shard-skl: PASS -> INCOMPLETE (fdo#104108) +1
>
> igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
> shard-glk: PASS -> FAIL (fdo#106509, fdo#105454)
>
> igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
> {shard-iclb}: PASS -> WARN (fdo#108336) +3
>
> igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
> {shard-iclb}: NOTRUN -> WARN (fdo#108336)
>
> igt@kms_fbcon_fbt@psr:
> {shard-iclb}: NOTRUN -> FAIL (fdo#107882)
> shard-skl: NOTRUN -> FAIL (fdo#107882)
>
> igt@kms_flip@busy-flip:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724) +16
>
> igt@kms_frontbuffer_tracking@basic:
> {shard-iclb}: PASS -> DMESG-WARN (fdo#107724, fdo#108336) +5
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
> {shard-iclb}: PASS -> DMESG-FAIL (fdo#107724) +4
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
> shard-glk: PASS -> FAIL (fdo#103167)
>
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
> {shard-iclb}: NOTRUN -> DMESG-FAIL (fdo#107724) +4
>
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
> shard-skl: NOTRUN -> FAIL (fdo#103167)
>
> igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
> {shard-iclb}: PASS -> FAIL (fdo#103167) +2
>
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
> {shard-iclb}: NOTRUN -> DMESG-WARN (fdo#107724, fdo#108336) +6
>
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103167) +4
>
> igt@kms_hdmi_inject@inject-audio:
> {shard-iclb}: NOTRUN -> FAIL (fdo#102370)
>
> igt@kms_panel_fitting@legacy:
> shard-skl: NOTRUN -> FAIL (fdo#105456)
>
> igt@kms_plane@plane-position-covered-pipe-c-planes:
> shard-apl: PASS -> FAIL (fdo#103166) +2
>
> igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> shard-skl: PASS -> FAIL (fdo#107815)
>
> igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
> shard-skl: NOTRUN -> FAIL (fdo#108145) +4
>
> igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> {shard-iclb}: NOTRUN -> FAIL (fdo#103166) +4
>
> igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
> {shard-iclb}: PASS -> FAIL (fdo#103166) +1
>
> igt@kms_psr@no_drrs:
> {shard-iclb}: PASS -> FAIL (fdo#108341)
>
> igt@kms_rotation_crc@primary-rotation-180:
> shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#103925)
>
> igt@kms_vblank@pipe-a-ts-continuation-idle:
> {shard-iclb}: PASS -> DMESG-WARN (fdo#107724) +11
>
> igt@pm_backlight@fade_with_suspend:
> shard-skl: NOTRUN -> FAIL (fdo#107847)
>
> igt@pm_rps@min-max-config-loaded:
> {shard-iclb}: NOTRUN -> FAIL (fdo#102250)
>
>
> ==== Possible fixes ====
>
> igt@gem_eio@in-flight-10ms:
> shard-glk: FAIL (fdo#107799) -> PASS
>
> igt@gem_exec_async@concurrent-writes-vebox:
> shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1
>
> igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
> shard-skl: FAIL (fdo#107815, fdo#108470) -> PASS
>
> igt@kms_available_modes_crc@available_mode_test_crc:
> shard-apl: FAIL (fdo#106641) -> PASS
>
> igt@kms_busy@extended-modeset-hang-newfb-render-c:
> shard-kbl: DMESG-WARN (fdo#107956) -> PASS
>
> igt@kms_chv_cursor_fail@pipe-a-128x128-left-edge:
> shard-skl: FAIL (fdo#104671) -> PASS
>
> igt@kms_color@pipe-c-gamma:
> shard-skl: FAIL (fdo#108228, fdo#104782) -> PASS
>
> igt@kms_cursor_crc@cursor-64x64-suspend:
> shard-glk: FAIL (fdo#103232) -> PASS +3
>
> igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
> shard-skl: FAIL (fdo#103184) -> PASS
>
> igt@kms_flip@flip-vs-absolute-wf_vblank:
> shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +16
>
> igt@kms_flip_tiling@flip-changes-tiling-yf:
> shard-kbl: DMESG-WARN (fdo#105604) -> PASS
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
> shard-apl: FAIL (fdo#103167) -> PASS
>
> igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
> shard-glk: FAIL (fdo#103167) -> PASS +1
>
> igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move:
> shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
>
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
> shard-skl: FAIL (fdo#103167) -> PASS
>
> igt@kms_plane@plane-panning-bottom-right-pipe-c-planes:
> shard-skl: FAIL (fdo#103166) -> PASS
>
> igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
> shard-skl: INCOMPLETE (fdo#107773, fdo#104108) -> PASS
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
> shard-glk: FAIL (fdo#108145) -> PASS
>
> igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
> shard-apl: FAIL (fdo#103166) -> PASS +1
>
> igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
> shard-glk: FAIL (fdo#103166) -> PASS +1
>
> igt@perf@polling:
> shard-hsw: FAIL (fdo#102252) -> PASS
>
> igt@pm_rpm@legacy-planes:
> shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS +1
> {shard-iclb}: DMESG-WARN (fdo#108654) -> PASS
>
> igt@pm_rpm@system-suspend-modeset:
> shard-skl: INCOMPLETE (fdo#104108, fdo#107807) -> PASS
>
>
> ==== Warnings ====
>
> igt@i915_suspend@shrink:
> shard-skl: INCOMPLETE (fdo#106886) -> DMESG-WARN (fdo#108784)
>
> igt@kms_ccs@pipe-c-crc-primary-basic:
> {shard-iclb}: FAIL (fdo#107725) -> DMESG-WARN (fdo#107724, fdo#108336)
>
> igt@kms_content_protection@atomic:
> shard-apl: FAIL (fdo#108597) -> INCOMPLETE (fdo#103927)
>
> igt@kms_cursor_crc@cursor-64x64-random:
> shard-apl: DMESG-WARN (fdo#103558, fdo#105602) -> FAIL (fdo#103232)
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
> fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
> fdo#102370 https://bugs.freedesktop.org/show_bug.cgi?id=102370
> fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
> fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
> fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
> fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
> fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
> fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
> fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
> fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
> fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
> fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
> fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
> fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
> fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
> fdo#105456 https://bugs.freedesktop.org/show_bug.cgi?id=105456
> fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
> fdo#105604 https://bugs.freedesktop.org/show_bug.cgi?id=105604
> fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
> fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
> fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
> fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
> fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
> fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
> fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
> fdo#107725 https://bugs.freedesktop.org/show_bug.cgi?id=107725
> fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
> fdo#107799 https://bugs.freedesktop.org/show_bug.cgi?id=107799
> fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
> fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
> fdo#107847 https://bugs.freedesktop.org/show_bug.cgi?id=107847
> fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
> fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
> fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
> fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
> fdo#108228 https://bugs.freedesktop.org/show_bug.cgi?id=108228
> fdo#108336 https://bugs.freedesktop.org/show_bug.cgi?id=108336
> fdo#108341 https://bugs.freedesktop.org/show_bug.cgi?id=108341
> fdo#108470 https://bugs.freedesktop.org/show_bug.cgi?id=108470
> fdo#108597 https://bugs.freedesktop.org/show_bug.cgi?id=108597
> fdo#108654 https://bugs.freedesktop.org/show_bug.cgi?id=108654
> fdo#108667 https://bugs.freedesktop.org/show_bug.cgi?id=108667
> fdo#108784 https://bugs.freedesktop.org/show_bug.cgi?id=108784
> k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
>
>
> == Participating hosts (7 -> 7) ==
>
> No changes in participating hosts
>
>
> == Build changes ==
>
> * Linux: CI_DRM_5169 -> Patchwork_10857
>
> CI_DRM_5169: ed08968fdc2130ba3cb6f3d7dbe82b6a8c39973d @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4720: c27aaca295d3ca2a38521e571c012449371e4bb5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_10857: e57fe9da9a20d3e7fc3135f388d0c9c697f84ba2 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10857/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-19 18:54 ` Imre Deak
@ 2018-11-20 2:38 ` Zhenyu Wang
0 siblings, 0 replies; 11+ messages in thread
From: Zhenyu Wang @ 2018-11-20 2:38 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5178 bytes --]
On 2018.11.19 20:54:30 +0200, Imre Deak wrote:
> On Mon, Nov 19, 2018 at 05:29:26PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> > > Depending on the transcoder enum values to translate from transcoder
> > > to pipe/transcoder register addresses can easily break if we add a new
> > > transcoder. So remove the dependency by using named initializers.
> > >
> > > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_pci.c | 52 ++++++++++++++++++++++++++++++-----------
> > > 1 file changed, 38 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index 983ae7fd8217..1b81d7cb209e 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -33,16 +33,30 @@
> > > #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
> > >
> > > #define GEN_DEFAULT_PIPEOFFSETS \
> > > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > > - PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
> > > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
> > > + .pipe_offsets = { \
> > > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > > + [TRANSCODER_C] = PIPE_C_OFFSET, \
> > > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> >
> > Hmm. We do define this as int pipe_offsets[I915_MAX_TRANSCODERS], and
> > PIPECONF/TRANSCONF is per-transcoder so I suppose using TRANSCODER_foo
> > here make sense.
> >
> > Couple of things that came to mind while thinking about this:
> > - pipe_offsets[] & co. could probably be u32 since we don't
> > need negative values
>
> Ok, can follow up with that.
>
> > - _PIPE_EDP could be removed, which would maybe shrink a few
> > arrays based on I915_MAX_PIPES
>
> Agreed. Looks like all the users are in gvt:
>
> - PIPECONF(_PIPE_EDP) should use PIPECONF(TRANSCODER_EDP) instead. The
> current code would also break if we added a new transcoder.
yeah, agreed.
> - AFAICS
> PIPEDSL(_PIPE_EDP)
> PIPESTAT(_PIPE_EDP)
> PIPE_FRMCOUNT_G4X(_PIPE_EDP)
> PIPE_FLIPCOUNT_G4X(_PIPE_EDP)
> are bogus, since these registers don't exist.
>
Thanks for pointing this out, looks they were added in very beginning,
will remove those after double check.
thanks
> Adding gvt folks for these.
>
> >
> > Patch is
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > > + }, \
> > > + .trans_offsets = { \
> > > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> > > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> > > + }
> > >
> > > #define GEN_CHV_PIPEOFFSETS \
> > > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > > - CHV_PIPE_C_OFFSET }, \
> > > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > > - CHV_TRANSCODER_C_OFFSET }
> > > + .pipe_offsets = { \
> > > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > > + [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> > > + }, \
> > > + .trans_offsets = { \
> > > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > > + [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> > > + }
> > >
> > > #define CURSOR_OFFSETS \
> > > .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
> > > @@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = {
> > >
> > > #define GEN11_FEATURES \
> > > GEN10_FEATURES, \
> > > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > > - PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
> > > - PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
> > > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
> > > - TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> > > + .pipe_offsets = { \
> > > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > > + [TRANSCODER_C] = PIPE_C_OFFSET, \
> > > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> > > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> > > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> > > + }, \
> > > + .trans_offsets = { \
> > > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> > > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> > > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> > > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> > > + }, \
> > > GEN(11), \
> > > .ddb_size = 2048, \
> > > .has_logical_ring_elsq = 1
> > > --
> > > 2.13.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-19 15:29 ` Ville Syrjälä
@ 2018-11-19 18:54 ` Imre Deak
2018-11-20 2:38 ` Zhenyu Wang
0 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2018-11-19 18:54 UTC (permalink / raw)
To: Ville Syrjälä, Zhi Wang, Zhenyu Wang; +Cc: intel-gfx
On Mon, Nov 19, 2018 at 05:29:26PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> > Depending on the transcoder enum values to translate from transcoder
> > to pipe/transcoder register addresses can easily break if we add a new
> > transcoder. So remove the dependency by using named initializers.
> >
> > Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 52 ++++++++++++++++++++++++++++++-----------
> > 1 file changed, 38 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 983ae7fd8217..1b81d7cb209e 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -33,16 +33,30 @@
> > #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
> >
> > #define GEN_DEFAULT_PIPEOFFSETS \
> > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > - PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
> > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
> > + .pipe_offsets = { \
> > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > + [TRANSCODER_C] = PIPE_C_OFFSET, \
> > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
>
> Hmm. We do define this as int pipe_offsets[I915_MAX_TRANSCODERS], and
> PIPECONF/TRANSCONF is per-transcoder so I suppose using TRANSCODER_foo
> here make sense.
>
> Couple of things that came to mind while thinking about this:
> - pipe_offsets[] & co. could probably be u32 since we don't
> need negative values
Ok, can follow up with that.
> - _PIPE_EDP could be removed, which would maybe shrink a few
> arrays based on I915_MAX_PIPES
Agreed. Looks like all the users are in gvt:
- PIPECONF(_PIPE_EDP) should use PIPECONF(TRANSCODER_EDP) instead. The
current code would also break if we added a new transcoder.
- AFAICS
PIPEDSL(_PIPE_EDP)
PIPESTAT(_PIPE_EDP)
PIPE_FRMCOUNT_G4X(_PIPE_EDP)
PIPE_FLIPCOUNT_G4X(_PIPE_EDP)
are bogus, since these registers don't exist.
Adding gvt folks for these.
>
> Patch is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > + }, \
> > + .trans_offsets = { \
> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> > + }
> >
> > #define GEN_CHV_PIPEOFFSETS \
> > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > - CHV_PIPE_C_OFFSET }, \
> > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > - CHV_TRANSCODER_C_OFFSET }
> > + .pipe_offsets = { \
> > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > + [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> > + }, \
> > + .trans_offsets = { \
> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > + [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> > + }
> >
> > #define CURSOR_OFFSETS \
> > .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
> > @@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = {
> >
> > #define GEN11_FEATURES \
> > GEN10_FEATURES, \
> > - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> > - PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
> > - PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
> > - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> > - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
> > - TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> > + .pipe_offsets = { \
> > + [TRANSCODER_A] = PIPE_A_OFFSET, \
> > + [TRANSCODER_B] = PIPE_B_OFFSET, \
> > + [TRANSCODER_C] = PIPE_C_OFFSET, \
> > + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> > + }, \
> > + .trans_offsets = { \
> > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> > + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> > + }, \
> > GEN(11), \
> > .ddb_size = 2048, \
> > .has_logical_ring_elsq = 1
> > --
> > 2.13.2
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
2018-11-19 14:41 [PATCH 1/3] " Imre Deak
@ 2018-11-19 15:29 ` Ville Syrjälä
2018-11-19 18:54 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: Ville Syrjälä @ 2018-11-19 15:29 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Nov 19, 2018 at 04:41:07PM +0200, Imre Deak wrote:
> Depending on the transcoder enum values to translate from transcoder
> to pipe/transcoder register addresses can easily break if we add a new
> transcoder. So remove the dependency by using named initializers.
>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 52 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 38 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 983ae7fd8217..1b81d7cb209e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -33,16 +33,30 @@
> #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>
> #define GEN_DEFAULT_PIPEOFFSETS \
> - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> - PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
> - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
Hmm. We do define this as int pipe_offsets[I915_MAX_TRANSCODERS], and
PIPECONF/TRANSCONF is per-transcoder so I suppose using TRANSCODER_foo
here make sense.
Couple of things that came to mind while thinking about this:
- pipe_offsets[] & co. could probably be u32 since we don't
need negative values
- _PIPE_EDP could be removed, which would maybe shrink a few
arrays based on I915_MAX_PIPES
Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> + }
>
> #define GEN_CHV_PIPEOFFSETS \
> - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> - CHV_PIPE_C_OFFSET }, \
> - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> - CHV_TRANSCODER_C_OFFSET }
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
> + }
>
> #define CURSOR_OFFSETS \
> .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
> @@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = {
>
> #define GEN11_FEATURES \
> GEN10_FEATURES, \
> - .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> - PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
> - PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
> - .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
> - TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> + .pipe_offsets = { \
> + [TRANSCODER_A] = PIPE_A_OFFSET, \
> + [TRANSCODER_B] = PIPE_B_OFFSET, \
> + [TRANSCODER_C] = PIPE_C_OFFSET, \
> + [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
> + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
> + }, \
> + .trans_offsets = { \
> + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
> + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
> + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
> + [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
> + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> + }, \
> GEN(11), \
> .ddb_size = 2048, \
> .has_logical_ring_elsq = 1
> --
> 2.13.2
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values
@ 2018-11-19 14:41 Imre Deak
2018-11-19 15:29 ` Ville Syrjälä
0 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2018-11-19 14:41 UTC (permalink / raw)
To: intel-gfx
Depending on the transcoder enum values to translate from transcoder
to pipe/transcoder register addresses can easily break if we add a new
transcoder. So remove the dependency by using named initializers.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 52 ++++++++++++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 983ae7fd8217..1b81d7cb209e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -33,16 +33,30 @@
#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
#define GEN_DEFAULT_PIPEOFFSETS \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ }
#define GEN_CHV_PIPEOFFSETS \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- CHV_PIPE_C_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- CHV_TRANSCODER_C_OFFSET }
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
+ }
#define CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
@@ -592,12 +606,22 @@ static const struct intel_device_info intel_cannonlake_info = {
#define GEN11_FEATURES \
GEN10_FEATURES, \
- .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
- PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
- PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
- .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
- TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
+ }, \
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1
--
2.13.2
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^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-11-21 11:43 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-20 9:23 [PATCH 1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Imre Deak
2018-11-20 9:23 ` [PATCH v3 2/3] drm/i915: Make EDP PSR flags " Imre Deak
2018-11-20 9:23 ` [PATCH v3 3/3] drm/i915: Add code comment on assumption of pipe==transcoder Imre Deak
2018-11-20 10:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Make pipe/transcoder offsets not depend on enum values Patchwork
2018-11-20 11:01 ` ✓ Fi.CI.BAT: success " Patchwork
2018-11-20 13:53 ` ✓ Fi.CI.IGT: " Patchwork
2018-11-21 11:43 ` Imre Deak
-- strict thread matches above, loose matches on Subject: below --
2018-11-19 14:41 [PATCH 1/3] " Imre Deak
2018-11-19 15:29 ` Ville Syrjälä
2018-11-19 18:54 ` Imre Deak
2018-11-20 2:38 ` Zhenyu Wang
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