* [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET
@ 2018-11-20 10:19 Peng Fan
2018-11-20 10:19 ` [U-Boot] [PATCH V2 02/15] imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M Peng Fan
` (13 more replies)
0 siblings, 14 replies; 28+ messages in thread
From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw)
To: u-boot
Introduce CONFIG_FIT_EXTERNAL_OFFSET to give user a choice to choose
where to put the external data.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V2:
Add more help information
Kconfig | 10 ++++++++++
Makefile | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Kconfig b/Kconfig
index dca9bb4e43..f74d662358 100644
--- a/Kconfig
+++ b/Kconfig
@@ -248,6 +248,16 @@ config FIT
if FIT
+config FIT_EXTERNAL_OFFSET
+ hex "Text Base"
+ default 0x0
+ help
+ This specifies a data offset in fit image.
+ The offset is from data payload offset to the beginning of
+ fit image header. When specifies a offset, specific data
+ could be put in the hole between data payload and fit image
+ header, such as CSF data on i.MX platform.
+
config FIT_ENABLE_SHA256_SUPPORT
bool "Support SHA256 checksum of FIT image contents"
default y
diff --git a/Makefile b/Makefile
index 552687db53..ee97601ec3 100644
--- a/Makefile
+++ b/Makefile
@@ -893,7 +893,7 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_mkfitimage = MKIMAGE $@
-cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ -p $(CONFIG_FIT_EXTERNAL_OFFSET)\
>$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT))
quiet_cmd_cat = CAT $@
--
2.14.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH V2 02/15] imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 03/15] imx: cpu: add CHIP_REV_2_1 macro Peng Fan ` (12 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> If we don't define CONFIG_SPL_FIT_IMAGE_TINY, when loading images from FIT, the SPL will record all loadables' info to u-boot's FDT. This causes problem when HAB is enabled, because FDT's content is modified before we authenticate it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index d0564621d4..5071fe89d0 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -257,6 +257,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 + default y if ARCH_IMX8M help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 03/15] imx: cpu: add CHIP_REV_2_1 macro 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 02/15] imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 04/15] imx: introduce is_imx8mq helper Peng Fan ` (11 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Introduce CHIP_REV_2_1 macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None arch/arm/include/asm/arch-imx/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 2af79659d2..46431b72ed 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -41,6 +41,7 @@ #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 04/15] imx: introduce is_imx8mq helper 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 02/15] imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 03/15] imx: cpu: add CHIP_REV_2_1 macro Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M Peng Fan ` (10 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Introduce is_imx8mq header macro Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None arch/arm/include/asm/mach-imx/sys_proto.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index f8890b57da..e3dd5f5064 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -42,6 +42,7 @@ #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #ifdef CONFIG_MX6 -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (2 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 04/15] imx: introduce is_imx8mq helper Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-29 5:01 ` Jon Nettleton 2018-11-20 10:19 ` [U-Boot] [PATCH V2 06/15] imx: spl: add MMC BOOT Device for i.MX8M Peng Fan ` (9 subsequent siblings) 13 siblings, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Rename mx8m,MX8M to imx8m,IMX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None arch/arm/Kconfig | 4 ++-- arch/arm/Makefile | 4 ++-- arch/arm/include/asm/arch-imx/cpu.h | 4 ++-- arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h | 0 .../include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h | 4 ++-- arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h | 4 ++-- arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h | 4 ++-- .../include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h | 4 ++-- .../mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} | 4 ++-- .../include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h | 4 ++-- arch/arm/include/asm/mach-imx/iomux-v3.h | 2 +- arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++--- arch/arm/include/asm/mach-imx/sys_proto.h | 2 +- arch/arm/mach-imx/Makefile | 8 ++++---- arch/arm/mach-imx/cpu.c | 16 ++++++++-------- arch/arm/mach-imx/{mx8m => imx8m}/Kconfig | 6 +++--- arch/arm/mach-imx/{mx8m => imx8m}/Makefile | 0 arch/arm/mach-imx/{mx8m => imx8m}/clock.c | 4 ++-- arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c | 0 arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S | 0 arch/arm/mach-imx/{mx8m => imx8m}/soc.c | 0 arch/arm/mach-imx/imx_bootaux.c | 4 ++-- arch/arm/mach-imx/spl.c | 6 +++--- drivers/gpio/mxc_gpio.c | 18 +++++++++--------- drivers/misc/mxc_ocotp.c | 6 +++--- drivers/mmc/fsl_esdhc.c | 8 ++++---- drivers/net/fec_mxc.c | 2 +- 27 files changed, 62 insertions(+), 62 deletions(-) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h (100%) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h (65%) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h (98%) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h (63%) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h (99%) rename arch/arm/include/asm/{arch-mx8m/mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} (99%) rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h (82%) rename arch/arm/mach-imx/{mx8m => imx8m}/Kconfig (57%) rename arch/arm/mach-imx/{mx8m => imx8m}/Makefile (100%) rename arch/arm/mach-imx/{mx8m => imx8m}/clock.c (99%) rename arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c (100%) rename arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S (100%) rename arch/arm/mach-imx/{mx8m => imx8m}/soc.c (100%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0e7fde137..1a58adc1fb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -674,7 +674,7 @@ config ARCH_IMX8 select DM select OF_CONTROL -config ARCH_MX8M +config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select DM @@ -1427,7 +1427,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig" source "arch/arm/mach-imx/imx8/Kconfig" -source "arch/arm/mach-imx/mx8m/Kconfig" +source "arch/arm/mach-imx/imx8m/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1935..63c2a5a0a0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -102,11 +102,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 46431b72ed..667badbc06 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -24,7 +24,7 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 -#define MXC_CPU_MX8MQ 0x82 +#define MXC_CPU_IMX8MQ 0x82 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ @@ -32,7 +32,7 @@ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 -#define MXC_SOC_MX8M 0x80 +#define MXC_SOC_IMX8M 0x80 #define MXC_SOC_IMX8 0x90 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h similarity index 100% rename from arch/arm/include/asm/arch-mx8m/clock.h rename to arch/arm/include/asm/arch-imx8m/clock.h diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h similarity index 65% rename from arch/arm/include/asm/arch-mx8m/crm_regs.h rename to arch/arm/include/asm/arch-imx8m/crm_regs.h index c128931289..c42e6685de 100644 --- a/arch/arm/include/asm/arch-mx8m/crm_regs.h +++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h @@ -3,7 +3,7 @@ * Copyright 2017 NXP */ -#ifndef _ASM_ARCH_MX8M_CRM_REGS_H -#define _ASM_ARCH_MX8M_CRM_REGS_H +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H +#define _ASM_ARCH_IMX8M_CRM_REGS_H /* Dummy header, some imx-common code needs this file */ #endif diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h similarity index 98% rename from arch/arm/include/asm/arch-mx8m/ddr.h rename to arch/arm/include/asm/arch-imx8m/ddr.h index 7e4f6fbb64..1a5cbabdaf 100644 --- a/arch/arm/include/asm/arch-mx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -3,8 +3,8 @@ * Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_DDR_H -#define __ASM_ARCH_MX8M_DDR_H +#ifndef __ASM_ARCH_IMX8M_DDR_H +#define __ASM_ARCH_IMX8M_DDR_H #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR_0 0x3f400000 diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h similarity index 63% rename from arch/arm/include/asm/arch-mx8m/gpio.h rename to arch/arm/include/asm/arch-imx8m/gpio.h index 2ba5643d05..2d9fbcb0e4 100644 --- a/arch/arm/include/asm/arch-mx8m/gpio.h +++ b/arch/arm/include/asm/arch-imx8m/gpio.h @@ -3,8 +3,8 @@ * Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_GPIO_H -#define __ASM_ARCH_MX8M_GPIO_H +#ifndef __ASM_ARCH_IMX8M_GPIO_H +#define __ASM_ARCH_IMX8M_GPIO_H #include <asm/mach-imx/gpio.h> diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h similarity index 99% rename from arch/arm/include/asm/arch-mx8m/imx-regs.h rename to arch/arm/include/asm/arch-imx8m/imx-regs.h index a3b06282b0..3facd5450c 100644 --- a/arch/arm/include/asm/arch-mx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -3,8 +3,8 @@ * Copyright 2017 NXP */ -#ifndef __ASM_ARCH_MX8M_REGS_H__ -#define __ASM_ARCH_MX8M_REGS_H__ +#ifndef __ASM_ARCH_IMX8M_REGS_H__ +#define __ASM_ARCH_IMX8M_REGS_H__ #include <asm/mach-imx/regs-lcdif.h> diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h similarity index 99% rename from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h rename to arch/arm/include/asm/arch-imx8m/imx8mq_pins.h index 3ba4d15a2a..c71913f209 100644 --- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h @@ -3,8 +3,8 @@ * Copyright (C) 2017 NXP */ -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ -#define __ASM_ARCH_MX8MQ_PINS_H__ +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ +#define __ASM_ARCH_IMX8MQ_PINS_H__ #include <asm/mach-imx/iomux-v3.h> diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h similarity index 82% rename from arch/arm/include/asm/arch-mx8m/sys_proto.h rename to arch/arm/include/asm/arch-imx8m/sys_proto.h index 01d6cd76c1..d328542ece 100644 --- a/arch/arm/include/asm/arch-mx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -3,8 +3,8 @@ * Copyright (C) 2017 NXP */ -#ifndef __ARCH_MX8M_SYS_PROTO_H -#define __ARCH_MX8M_SYS_PROTO_H +#ifndef __ARCH_IMX8M_SYS_PROTO_H +#define __ARCH_NMX8M_SYS_PROTO_H #include <asm/mach-imx/sys_proto.h> diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 63f4b33aeb..b899a4ff6f 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t; #define IOMUX_CONFIG_LPSR 0x20 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M #define PAD_CTL_DSE0 (0x0 << 0) #define PAD_CTL_DSE1 (0x1 << 0) #define PAD_CTL_DSE2 (0x2 << 0) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index d294c90646..b4c430a35c 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -73,7 +73,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_MX8M) + defined(CONFIG_IMX8M) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index e3dd5f5064..8d6832a331 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -26,7 +26,7 @@ #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() (is_soc_type(MXC_SOC_MX7)) -#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index eb84315d9d..34e380e0b3 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -5,11 +5,11 @@ # # (C) Copyright 2011 Freescale Semiconductor, Inc. -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) obj-y = iomux-v3.o endif -ifeq ($(SOC),$(filter $(SOC),mx8m)) +ifeq ($(SOC),$(filter $(SOC),imx8m)) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o @@ -22,7 +22,7 @@ obj-y += cpu.o speed.o obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) obj-y += misc.o obj-$(CONFIG_SPL_BUILD) += spl.o endif @@ -169,5 +169,5 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ -obj-$(CONFIG_MX8M) += mx8m/ +obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index dcdaced991..80d9ff48a4 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -62,7 +62,7 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) case 0x00100: return "WDOG2"; case 0x00200: @@ -142,8 +142,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_MX8MQ: - return "8MQ"; /* Quad-core version of the mx8m */ + case MXC_CPU_IMX8MQ: + return "8MQ"; /* Quad-core version of the imx8m */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) } #endif -#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -300,7 +300,7 @@ void arch_preboot_os(void) #endif } -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M void set_chipselect_size(int const cs_size) { unsigned int reg; @@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) /* * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) * defines a 2-bit SPEED_GRADING @@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) enum boot_device get_boot_device(void) { struct bootrom_sw_info **p = @@ -438,7 +438,7 @@ enum boot_device get_boot_device(void) case BOOT_TYPE_SPINOR: boot_dev = SPI_NOR_BOOT; break; -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M case BOOT_TYPE_USB: boot_dev = USB_BOOT; break; diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig similarity index 57% rename from arch/arm/mach-imx/mx8m/Kconfig rename to arch/arm/mach-imx/imx8m/Kconfig index 3a84c2f2b0..98d79c3179 100644 --- a/arch/arm/mach-imx/mx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -1,10 +1,10 @@ -if ARCH_MX8M +if ARCH_IMX8M -config MX8M +config IMX8M bool select ROM_UNIFIED_SECTIONS config SYS_SOC - default "mx8m" + default "imx8m" endif diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile similarity index 100% rename from arch/arm/mach-imx/mx8m/Makefile rename to arch/arm/mach-imx/imx8m/Makefile diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c similarity index 99% rename from arch/arm/mach-imx/mx8m/clock.c rename to arch/arm/mach-imx/imx8m/clock.c index fe32e1c3f1..f2cb4e1030 100644 --- a/arch/arm/mach-imx/mx8m/clock.c +++ b/arch/arm/mach-imx/imx8m/clock.c @@ -730,7 +730,7 @@ int clock_init(void) * Dump some clockes. */ #ifndef CONFIG_SPL_BUILD -int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, +int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; @@ -785,7 +785,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, + clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, "display clocks", "" ); diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c similarity index 100% rename from arch/arm/mach-imx/mx8m/clock_slice.c rename to arch/arm/mach-imx/imx8m/clock_slice.c diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S similarity index 100% rename from arch/arm/mach-imx/mx8m/lowlevel_init.S rename to arch/arm/mach-imx/imx8m/lowlevel_init.S diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c similarity index 100% rename from arch/arm/mach-imx/mx8m/soc.c rename to arch/arm/mach-imx/imx8m/soc.c diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index a1ea5c13f1..ae3734ecb9 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -25,7 +25,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) writel(pc, M4_BOOTROM_BASE_ADDR + 4); /* Enable M4 */ -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); #else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) int arch_auxiliary_core_check_up(u32 core_id) { -#ifdef CONFIG_MX8M +#ifdef CONFIG_IMX8M return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); #else unsigned int val; diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6f0b5cdb4c..e82eaa5682 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -96,8 +96,8 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) +/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { #if defined(CONFIG_MX7) @@ -143,7 +143,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index b820160ae7..8bd30c75b2 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [3] = GPIO4_BASE_ADDR, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) [4] = GPIO5_BASE_ADDR, -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) [5] = GPIO6_BASE_ADDR, #endif #endif @@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif @@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { { "gpio_mxc", &mxc_plat[2] }, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, -#ifndef CONFIG_MX8M +#ifndef CONFIG_IMX8M { "gpio_mxc", &mxc_plat[5] }, #endif #endif diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 9ff475d925..f84fe88db1 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -34,7 +34,7 @@ #define BM_OUT_STATUS_DED 0x00000400 #define BM_OUT_STATUS_LOCKED 0x00000800 #define BM_OUT_STATUS_PROGFAIL 0x00001000 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define BM_CTRL_ADDR 0x000000ff #else #define BM_CTRL_ADDR 0x0000007f @@ -80,7 +80,7 @@ #elif defined(CONFIG_MX7ULP) #define FUSE_BANK_SIZE 0x80 #define FUSE_BANKS 31 -#elif defined(CONFIG_MX8M) +#elif defined(CONFIG_IMX8M) #define FUSE_BANK_SIZE 0x40 #define FUSE_BANKS 64 #else @@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef CONFIG_MX7 u32 addr = bank; -#elif defined CONFIG_MX8M +#elif defined CONFIG_IMX8M u32 addr = bank << 2 | word; #else u32 addr; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 3cdfa7f5a6..74007e2ad4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; #endif uint wml_value; @@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 99c5c649a0..32fb34b793 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M 2018-11-20 10:19 ` [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M Peng Fan @ 2018-11-29 5:01 ` Jon Nettleton 2018-12-03 12:33 ` Peng Fan 0 siblings, 1 reply; 28+ messages in thread From: Jon Nettleton @ 2018-11-29 5:01 UTC (permalink / raw) To: u-boot On Tue, Nov 20, 2018 at 11:21 AM Peng Fan <peng.fan@nxp.com> wrote: > > Rename mx8m,MX8M to imx8m,IMX8M > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > > V2: > None > > arch/arm/Kconfig | 4 ++-- > arch/arm/Makefile | 4 ++-- > arch/arm/include/asm/arch-imx/cpu.h | 4 ++-- > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h | 0 > .../include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h | 4 ++-- > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h | 4 ++-- > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h | 4 ++-- > .../include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h | 4 ++-- > .../mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} | 4 ++-- > .../include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h | 4 ++-- > arch/arm/include/asm/mach-imx/iomux-v3.h | 2 +- > arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++--- > arch/arm/include/asm/mach-imx/sys_proto.h | 2 +- > arch/arm/mach-imx/Makefile | 8 ++++---- > arch/arm/mach-imx/cpu.c | 16 ++++++++-------- > arch/arm/mach-imx/{mx8m => imx8m}/Kconfig | 6 +++--- > arch/arm/mach-imx/{mx8m => imx8m}/Makefile | 0 > arch/arm/mach-imx/{mx8m => imx8m}/clock.c | 4 ++-- > arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c | 0 > arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S | 0 > arch/arm/mach-imx/{mx8m => imx8m}/soc.c | 0 > arch/arm/mach-imx/imx_bootaux.c | 4 ++-- > arch/arm/mach-imx/spl.c | 6 +++--- > drivers/gpio/mxc_gpio.c | 18 +++++++++--------- > drivers/misc/mxc_ocotp.c | 6 +++--- > drivers/mmc/fsl_esdhc.c | 8 ++++---- > drivers/net/fec_mxc.c | 2 +- > 27 files changed, 62 insertions(+), 62 deletions(-) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h (100%) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h (65%) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h (98%) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h (63%) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h (99%) > rename arch/arm/include/asm/{arch-mx8m/mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} (99%) > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h (82%) > rename arch/arm/mach-imx/{mx8m => imx8m}/Kconfig (57%) > rename arch/arm/mach-imx/{mx8m => imx8m}/Makefile (100%) > rename arch/arm/mach-imx/{mx8m => imx8m}/clock.c (99%) > rename arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c (100%) > rename arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S (100%) > rename arch/arm/mach-imx/{mx8m => imx8m}/soc.c (100%) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index f0e7fde137..1a58adc1fb 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -674,7 +674,7 @@ config ARCH_IMX8 > select DM > select OF_CONTROL > > -config ARCH_MX8M > +config ARCH_IMX8M > bool "NXP i.MX8M platform" > select ARM64 > select DM > @@ -1427,7 +1427,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig" > > source "arch/arm/mach-imx/imx8/Kconfig" > > -source "arch/arm/mach-imx/mx8m/Kconfig" > +source "arch/arm/mach-imx/imx8m/Kconfig" > > source "arch/arm/mach-imx/mxs/Kconfig" > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 4b6c5e1935..63c2a5a0a0 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -102,11 +102,11 @@ libs-y += arch/arm/cpu/ > libs-y += arch/arm/lib/ > > ifeq ($(CONFIG_SPL_BUILD),y) > -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m)) > +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m)) > libs-y += arch/arm/mach-imx/ > endif > else > -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610)) > +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610)) > libs-y += arch/arm/mach-imx/ > endif > endif > diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h > index 46431b72ed..667badbc06 100644 > --- a/arch/arm/include/asm/arch-imx/cpu.h > +++ b/arch/arm/include/asm/arch-imx/cpu.h > @@ -24,7 +24,7 @@ > #define MXC_CPU_MX6QP 0x69 > #define MXC_CPU_MX7S 0x71 /* dummy ID */ > #define MXC_CPU_MX7D 0x72 > -#define MXC_CPU_MX8MQ 0x82 > +#define MXC_CPU_IMX8MQ 0x82 > #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ > #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ > #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ > @@ -32,7 +32,7 @@ > > #define MXC_SOC_MX6 0x60 > #define MXC_SOC_MX7 0x70 > -#define MXC_SOC_MX8M 0x80 > +#define MXC_SOC_IMX8M 0x80 > #define MXC_SOC_IMX8 0x90 /* dummy */ > #define MXC_SOC_MX7ULP 0xE0 /* dummy */ > > diff --git a/arch/arm/include/asm/arch-mx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h > similarity index 100% > rename from arch/arm/include/asm/arch-mx8m/clock.h > rename to arch/arm/include/asm/arch-imx8m/clock.h > diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h > similarity index 65% > rename from arch/arm/include/asm/arch-mx8m/crm_regs.h > rename to arch/arm/include/asm/arch-imx8m/crm_regs.h > index c128931289..c42e6685de 100644 > --- a/arch/arm/include/asm/arch-mx8m/crm_regs.h > +++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h > @@ -3,7 +3,7 @@ > * Copyright 2017 NXP > */ > > -#ifndef _ASM_ARCH_MX8M_CRM_REGS_H > -#define _ASM_ARCH_MX8M_CRM_REGS_H > +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H > +#define _ASM_ARCH_IMX8M_CRM_REGS_H > /* Dummy header, some imx-common code needs this file */ > #endif > diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h > similarity index 98% > rename from arch/arm/include/asm/arch-mx8m/ddr.h > rename to arch/arm/include/asm/arch-imx8m/ddr.h > index 7e4f6fbb64..1a5cbabdaf 100644 > --- a/arch/arm/include/asm/arch-mx8m/ddr.h > +++ b/arch/arm/include/asm/arch-imx8m/ddr.h > @@ -3,8 +3,8 @@ > * Copyright 2017 NXP > */ > > -#ifndef __ASM_ARCH_MX8M_DDR_H > -#define __ASM_ARCH_MX8M_DDR_H > +#ifndef __ASM_ARCH_IMX8M_DDR_H > +#define __ASM_ARCH_IMX8M_DDR_H > > #define DDRC_DDR_SS_GPR0 0x3d000000 > #define DDRC_IPS_BASE_ADDR_0 0x3f400000 > diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h > similarity index 63% > rename from arch/arm/include/asm/arch-mx8m/gpio.h > rename to arch/arm/include/asm/arch-imx8m/gpio.h > index 2ba5643d05..2d9fbcb0e4 100644 > --- a/arch/arm/include/asm/arch-mx8m/gpio.h > +++ b/arch/arm/include/asm/arch-imx8m/gpio.h > @@ -3,8 +3,8 @@ > * Copyright 2017 NXP > */ > > -#ifndef __ASM_ARCH_MX8M_GPIO_H > -#define __ASM_ARCH_MX8M_GPIO_H > +#ifndef __ASM_ARCH_IMX8M_GPIO_H > +#define __ASM_ARCH_IMX8M_GPIO_H > > #include <asm/mach-imx/gpio.h> > > diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h > similarity index 99% > rename from arch/arm/include/asm/arch-mx8m/imx-regs.h > rename to arch/arm/include/asm/arch-imx8m/imx-regs.h > index a3b06282b0..3facd5450c 100644 > --- a/arch/arm/include/asm/arch-mx8m/imx-regs.h > +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h > @@ -3,8 +3,8 @@ > * Copyright 2017 NXP > */ > > -#ifndef __ASM_ARCH_MX8M_REGS_H__ > -#define __ASM_ARCH_MX8M_REGS_H__ > +#ifndef __ASM_ARCH_IMX8M_REGS_H__ > +#define __ASM_ARCH_IMX8M_REGS_H__ > > #include <asm/mach-imx/regs-lcdif.h> > > diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > similarity index 99% > rename from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h > rename to arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > index 3ba4d15a2a..c71913f209 100644 > --- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h > +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > @@ -3,8 +3,8 @@ > * Copyright (C) 2017 NXP > */ > > -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ > -#define __ASM_ARCH_MX8MQ_PINS_H__ > +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ > +#define __ASM_ARCH_IMX8MQ_PINS_H__ > > #include <asm/mach-imx/iomux-v3.h> > > diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h > similarity index 82% > rename from arch/arm/include/asm/arch-mx8m/sys_proto.h > rename to arch/arm/include/asm/arch-imx8m/sys_proto.h > index 01d6cd76c1..d328542ece 100644 > --- a/arch/arm/include/asm/arch-mx8m/sys_proto.h > +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h > @@ -3,8 +3,8 @@ > * Copyright (C) 2017 NXP > */ > > -#ifndef __ARCH_MX8M_SYS_PROTO_H > -#define __ARCH_MX8M_SYS_PROTO_H > +#ifndef __ARCH_IMX8M_SYS_PROTO_H > +#define __ARCH_NMX8M_SYS_PROTO_H > > #include <asm/mach-imx/sys_proto.h> > > diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h > index 63f4b33aeb..b899a4ff6f 100644 > --- a/arch/arm/include/asm/mach-imx/iomux-v3.h > +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h > @@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t; > #define IOMUX_CONFIG_LPSR 0x20 > #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ > MUX_MODE_SHIFT) > -#ifdef CONFIG_MX8M > +#ifdef CONFIG_IMX8M > #define PAD_CTL_DSE0 (0x0 << 0) > #define PAD_CTL_DSE1 (0x1 << 0) > #define PAD_CTL_DSE2 (0x2 << 0) > diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h > index d294c90646..b4c430a35c 100644 > --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h > +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h > @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > - defined(CONFIG_MX8M) > + defined(CONFIG_IMX8M) > mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ > #endif > mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ > @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > - defined(CONFIG_MX8M) > + defined(CONFIG_IMX8M) > mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ > #endif > mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ > @@ -73,7 +73,7 @@ struct mxs_lcdif_regs { > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > - defined(CONFIG_MX8M) > + defined(CONFIG_IMX8M) > mxs_reg_32(hw_lcdif_thres) > mxs_reg_32(hw_lcdif_as_ctrl) > mxs_reg_32(hw_lcdif_as_buf) > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h > index e3dd5f5064..8d6832a331 100644 > --- a/arch/arm/include/asm/mach-imx/sys_proto.h > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h > @@ -26,7 +26,7 @@ > > #define is_mx6() (is_soc_type(MXC_SOC_MX6)) > #define is_mx7() (is_soc_type(MXC_SOC_MX7)) > -#define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) > +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) > #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) > > #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index eb84315d9d..34e380e0b3 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -5,11 +5,11 @@ > # > # (C) Copyright 2011 Freescale Semiconductor, Inc. > > -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) > +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) > obj-y = iomux-v3.o > endif > > -ifeq ($(SOC),$(filter $(SOC),mx8m)) > +ifeq ($(SOC),$(filter $(SOC),imx8m)) > obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o > obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o > obj-$(CONFIG_FEC_MXC) += mac.o > @@ -22,7 +22,7 @@ obj-y += cpu.o speed.o > obj-$(CONFIG_GPT_TIMER) += timer.o > obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o > endif > -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m)) > +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) > obj-y += misc.o > obj-$(CONFIG_SPL_BUILD) += spl.o > endif > @@ -169,5 +169,5 @@ obj-$(CONFIG_MX5) += mx5/ > obj-$(CONFIG_MX6) += mx6/ > obj-$(CONFIG_MX7) += mx7/ > obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ > -obj-$(CONFIG_MX8M) += mx8m/ > +obj-$(CONFIG_IMX8M) += imx8m/ > obj-$(CONFIG_ARCH_IMX8) += imx8/ > diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c > index dcdaced991..80d9ff48a4 100644 > --- a/arch/arm/mach-imx/cpu.c > +++ b/arch/arm/mach-imx/cpu.c > @@ -62,7 +62,7 @@ static char *get_reset_cause(void) > return "WDOG4"; > case 0x00200: > return "TEMPSENSE"; > -#elif defined(CONFIG_MX8M) > +#elif defined(CONFIG_IMX8M) > case 0x00100: > return "WDOG2"; > case 0x00200: > @@ -142,8 +142,8 @@ unsigned imx_ddr_size(void) > const char *get_imx_type(u32 imxtype) > { > switch (imxtype) { > - case MXC_CPU_MX8MQ: > - return "8MQ"; /* Quad-core version of the mx8m */ > + case MXC_CPU_IMX8MQ: > + return "8MQ"; /* Quad-core version of the imx8m */ > case MXC_CPU_MX7S: > return "7S"; /* Single-core version of the mx7 */ > case MXC_CPU_MX7D: > @@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) > } > #endif > > -#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) > +#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) > u32 get_ahb_clk(void) > { > struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > @@ -300,7 +300,7 @@ void arch_preboot_os(void) > #endif > } > > -#ifndef CONFIG_MX8M > +#ifndef CONFIG_IMX8M > void set_chipselect_size(int const cs_size) > { > unsigned int reg; > @@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size) > } > #endif > > -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) > +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > /* > * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) > * defines a 2-bit SPEED_GRADING > @@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) > } > #endif > > -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) > +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > enum boot_device get_boot_device(void) > { > struct bootrom_sw_info **p = > @@ -438,7 +438,7 @@ enum boot_device get_boot_device(void) > case BOOT_TYPE_SPINOR: > boot_dev = SPI_NOR_BOOT; > break; > -#ifdef CONFIG_MX8M > +#ifdef CONFIG_IMX8M > case BOOT_TYPE_USB: > boot_dev = USB_BOOT; > break; > diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig > similarity index 57% > rename from arch/arm/mach-imx/mx8m/Kconfig > rename to arch/arm/mach-imx/imx8m/Kconfig > index 3a84c2f2b0..98d79c3179 100644 > --- a/arch/arm/mach-imx/mx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -1,10 +1,10 @@ > -if ARCH_MX8M > +if ARCH_IMX8M > > -config MX8M > +config IMX8M > bool > select ROM_UNIFIED_SECTIONS > > config SYS_SOC > - default "mx8m" > + default "imx8m" > > endif > diff --git a/arch/arm/mach-imx/mx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile > similarity index 100% > rename from arch/arm/mach-imx/mx8m/Makefile > rename to arch/arm/mach-imx/imx8m/Makefile > diff --git a/arch/arm/mach-imx/mx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c > similarity index 99% > rename from arch/arm/mach-imx/mx8m/clock.c > rename to arch/arm/mach-imx/imx8m/clock.c > index fe32e1c3f1..f2cb4e1030 100644 > --- a/arch/arm/mach-imx/mx8m/clock.c > +++ b/arch/arm/mach-imx/imx8m/clock.c > @@ -730,7 +730,7 @@ int clock_init(void) > * Dump some clockes. > */ > #ifndef CONFIG_SPL_BUILD > -int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, > +int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, > char * const argv[]) > { > u32 freq; > @@ -785,7 +785,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, > } > > U_BOOT_CMD( > - clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, > + clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, > "display clocks", > "" > ); > diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c > similarity index 100% > rename from arch/arm/mach-imx/mx8m/clock_slice.c > rename to arch/arm/mach-imx/imx8m/clock_slice.c > diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S b/arch/arm/mach-imx/imx8m/lowlevel_init.S > similarity index 100% > rename from arch/arm/mach-imx/mx8m/lowlevel_init.S > rename to arch/arm/mach-imx/imx8m/lowlevel_init.S > diff --git a/arch/arm/mach-imx/mx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c > similarity index 100% > rename from arch/arm/mach-imx/mx8m/soc.c > rename to arch/arm/mach-imx/imx8m/soc.c > diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c > index a1ea5c13f1..ae3734ecb9 100644 > --- a/arch/arm/mach-imx/imx_bootaux.c > +++ b/arch/arm/mach-imx/imx_bootaux.c > @@ -25,7 +25,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) > writel(pc, M4_BOOTROM_BASE_ADDR + 4); > > /* Enable M4 */ > -#ifdef CONFIG_MX8M > +#ifdef CONFIG_IMX8M > call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); > #else > clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, > @@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) > > int arch_auxiliary_core_check_up(u32 core_id) > { > -#ifdef CONFIG_MX8M > +#ifdef CONFIG_IMX8M > return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0); > #else > unsigned int val; > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c > index 6f0b5cdb4c..e82eaa5682 100644 > --- a/arch/arm/mach-imx/spl.c > +++ b/arch/arm/mach-imx/spl.c > @@ -96,8 +96,8 @@ u32 spl_boot_device(void) > return BOOT_DEVICE_NONE; > } > > -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) > -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ > +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > +/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */ > u32 spl_boot_device(void) > { > #if defined(CONFIG_MX7) > @@ -143,7 +143,7 @@ u32 spl_boot_device(void) > return BOOT_DEVICE_NONE; > } > } > -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ > +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */ > > #ifdef CONFIG_SPL_USB_GADGET_SUPPORT > int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) > diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c > index b820160ae7..8bd30c75b2 100644 > --- a/drivers/gpio/mxc_gpio.c > +++ b/drivers/gpio/mxc_gpio.c > @@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { > [2] = GPIO3_BASE_ADDR, > #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ > + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ > defined(CONFIG_ARCH_IMX8) > [3] = GPIO4_BASE_ADDR, > #endif > #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ > + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ > defined(CONFIG_ARCH_IMX8) > [4] = GPIO5_BASE_ADDR, > -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) > +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M)) > [5] = GPIO6_BASE_ADDR, > #endif > #endif > @@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { > { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, > #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) > + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) > { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, > #endif > #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) > + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) > { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, > -#ifndef CONFIG_MX8M > +#ifndef CONFIG_IMX8M > { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, > #endif > #endif > @@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { > { "gpio_mxc", &mxc_plat[2] }, > #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) > + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) > { "gpio_mxc", &mxc_plat[3] }, > #endif > #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > - defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) > + defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) > { "gpio_mxc", &mxc_plat[4] }, > -#ifndef CONFIG_MX8M > +#ifndef CONFIG_IMX8M > { "gpio_mxc", &mxc_plat[5] }, > #endif > #endif > diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c > index 9ff475d925..f84fe88db1 100644 > --- a/drivers/misc/mxc_ocotp.c > +++ b/drivers/misc/mxc_ocotp.c > @@ -34,7 +34,7 @@ > #define BM_OUT_STATUS_DED 0x00000400 > #define BM_OUT_STATUS_LOCKED 0x00000800 > #define BM_OUT_STATUS_PROGFAIL 0x00001000 > -#elif defined(CONFIG_MX8M) > +#elif defined(CONFIG_IMX8M) > #define BM_CTRL_ADDR 0x000000ff > #else > #define BM_CTRL_ADDR 0x0000007f > @@ -80,7 +80,7 @@ > #elif defined(CONFIG_MX7ULP) > #define FUSE_BANK_SIZE 0x80 > #define FUSE_BANKS 31 > -#elif defined(CONFIG_MX8M) > +#elif defined(CONFIG_IMX8M) > #define FUSE_BANK_SIZE 0x40 > #define FUSE_BANKS 64 > #else > @@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, > u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; > #ifdef CONFIG_MX7 > u32 addr = bank; > -#elif defined CONFIG_MX8M > +#elif defined CONFIG_IMX8M > u32 addr = bank << 2 | word; > #else > u32 addr; > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 3cdfa7f5a6..74007e2ad4 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, > int timeout; > struct fsl_esdhc *regs = priv->esdhc_regs; > #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > dma_addr_t addr; > #endif > uint wml_value; > @@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, > esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); > #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO > #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > addr = virt_to_phys((void *)(data->dest)); > if (upper_32_bits(addr)) > printf("Error found for upper 32 bits\n"); > @@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, > wml_value << 16); > #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO > #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > addr = virt_to_phys((void *)(data->src)); > if (upper_32_bits(addr)) > printf("Error found for upper 32 bits\n"); > @@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range > unsigned size = roundup(ARCH_DMA_MINALIGN, > data->blocks*data->blocksize); > #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > dma_addr_t addr; > > addr = virt_to_phys((void *)(data->dest)); > diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c > index 99c5c649a0..32fb34b793 100644 > --- a/drivers/net/fec_mxc.c > +++ b/drivers/net/fec_mxc.c > @@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) > writel(0x00000000, &fec->eth->gaddr2); > > /* Do not access reserved register */ > - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { > + if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { > /* clear MIB RAM */ > for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) > writel(0, i); > -- > 2.14.1 > This patch leaves out the driver changes that depend on this naming change. If this patch accepted then we also need the following changes. -Jon -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-imx-fixup-Kconfig-to-align-with-MX8M-to-IMX8M-change.patch Type: text/x-patch Size: 1639 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181129/4bd3fe7e/attachment-0001.bin> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M 2018-11-29 5:01 ` Jon Nettleton @ 2018-12-03 12:33 ` Peng Fan 0 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-12-03 12:33 UTC (permalink / raw) To: u-boot Hi Jon, Your patch could not be applied to master branch, seems this patch is based on NXP vendor tree? Thanks, Peng. > -----Original Message----- > From: Jon Nettleton [mailto:jon at solid-run.com] > Sent: 2018年11月29日 13:02 > To: Peng Fan <peng.fan@nxp.com> > Cc: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com>; U-Boot > Mailing List <u-boot@lists.denx.de>; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to > imx8m,IMX8M > > On Tue, Nov 20, 2018 at 11:21 AM Peng Fan <peng.fan@nxp.com> wrote: > > > > Rename mx8m,MX8M to imx8m,IMX8M > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > > > V2: > > None > > > > arch/arm/Kconfig | 4 > ++-- > > arch/arm/Makefile | 4 > ++-- > > arch/arm/include/asm/arch-imx/cpu.h | 4 ++-- > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h | 0 > > .../include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h | 4 ++-- > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h | 4 ++-- > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h | 4 ++-- > > .../include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h | 4 ++-- > > .../mx8mq_pins.h => arch-imx8m/imx8mq_pins.h} | 4 ++-- > > .../include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h | 4 ++-- > > arch/arm/include/asm/mach-imx/iomux-v3.h | 2 +- > > arch/arm/include/asm/mach-imx/regs-lcdif.h | 6 +++--- > > arch/arm/include/asm/mach-imx/sys_proto.h | 2 +- > > arch/arm/mach-imx/Makefile | 8 > ++++---- > > arch/arm/mach-imx/cpu.c | 16 > ++++++++-------- > > arch/arm/mach-imx/{mx8m => imx8m}/Kconfig | 6 > +++--- > > arch/arm/mach-imx/{mx8m => imx8m}/Makefile | 0 > > arch/arm/mach-imx/{mx8m => imx8m}/clock.c | 4 > ++-- > > arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c | 0 > > arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S | 0 > > arch/arm/mach-imx/{mx8m => imx8m}/soc.c | 0 > > arch/arm/mach-imx/imx_bootaux.c | 4 > ++-- > > arch/arm/mach-imx/spl.c | 6 > +++--- > > drivers/gpio/mxc_gpio.c | 18 > +++++++++--------- > > drivers/misc/mxc_ocotp.c | 6 > +++--- > > drivers/mmc/fsl_esdhc.c | 8 > ++++---- > > drivers/net/fec_mxc.c | 2 +- > > 27 files changed, 62 insertions(+), 62 deletions(-) rename > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/clock.h (100%) > rename > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/crm_regs.h (65%) > > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/ddr.h (98%) > > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/gpio.h (63%) > > rename arch/arm/include/asm/{arch-mx8m => arch-imx8m}/imx-regs.h > (99%) > > rename arch/arm/include/asm/{arch-mx8m/mx8mq_pins.h => > > arch-imx8m/imx8mq_pins.h} (99%) rename > > arch/arm/include/asm/{arch-mx8m => arch-imx8m}/sys_proto.h (82%) > > rename arch/arm/mach-imx/{mx8m => imx8m}/Kconfig (57%) rename > > arch/arm/mach-imx/{mx8m => imx8m}/Makefile (100%) rename > > arch/arm/mach-imx/{mx8m => imx8m}/clock.c (99%) rename > > arch/arm/mach-imx/{mx8m => imx8m}/clock_slice.c (100%) rename > > arch/arm/mach-imx/{mx8m => imx8m}/lowlevel_init.S (100%) rename > > arch/arm/mach-imx/{mx8m => imx8m}/soc.c (100%) > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > f0e7fde137..1a58adc1fb 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -674,7 +674,7 @@ config ARCH_IMX8 > > select DM > > select OF_CONTROL > > > > -config ARCH_MX8M > > +config ARCH_IMX8M > > bool "NXP i.MX8M platform" > > select ARM64 > > select DM > > @@ -1427,7 +1427,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig" > > > > source "arch/arm/mach-imx/imx8/Kconfig" > > > > -source "arch/arm/mach-imx/mx8m/Kconfig" > > +source "arch/arm/mach-imx/imx8m/Kconfig" > > > > source "arch/arm/mach-imx/mxs/Kconfig" > > > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile index > > 4b6c5e1935..63c2a5a0a0 100644 > > --- a/arch/arm/Makefile > > +++ b/arch/arm/Makefile > > @@ -102,11 +102,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ > > > > ifeq ($(CONFIG_SPL_BUILD),y) > > -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), > > mx25 mx5 mx6 mx7 mx35 mx8m)) > > +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), > > +mx25 mx5 mx6 mx7 mx35 imx8m)) > > libs-y += arch/arm/mach-imx/ > > endif > > else > > -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs > > mx8m imx8 vf610)) > > +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs > > +imx8m imx8 vf610)) > > libs-y += arch/arm/mach-imx/ > > endif > > endif > > diff --git a/arch/arm/include/asm/arch-imx/cpu.h > > b/arch/arm/include/asm/arch-imx/cpu.h > > index 46431b72ed..667badbc06 100644 > > --- a/arch/arm/include/asm/arch-imx/cpu.h > > +++ b/arch/arm/include/asm/arch-imx/cpu.h > > @@ -24,7 +24,7 @@ > > #define MXC_CPU_MX6QP 0x69 > > #define MXC_CPU_MX7S 0x71 /* dummy ID */ > > #define MXC_CPU_MX7D 0x72 > > -#define MXC_CPU_MX8MQ 0x82 > > +#define MXC_CPU_IMX8MQ 0x82 > > #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ > > #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ > > #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ > > @@ -32,7 +32,7 @@ > > > > #define MXC_SOC_MX6 0x60 > > #define MXC_SOC_MX7 0x70 > > -#define MXC_SOC_MX8M 0x80 > > +#define MXC_SOC_IMX8M 0x80 > > #define MXC_SOC_IMX8 0x90 /* dummy */ > > #define MXC_SOC_MX7ULP 0xE0 /* dummy */ > > > > diff --git a/arch/arm/include/asm/arch-mx8m/clock.h > > b/arch/arm/include/asm/arch-imx8m/clock.h > > similarity index 100% > > rename from arch/arm/include/asm/arch-mx8m/clock.h > > rename to arch/arm/include/asm/arch-imx8m/clock.h > > diff --git a/arch/arm/include/asm/arch-mx8m/crm_regs.h > > b/arch/arm/include/asm/arch-imx8m/crm_regs.h > > similarity index 65% > > rename from arch/arm/include/asm/arch-mx8m/crm_regs.h > > rename to arch/arm/include/asm/arch-imx8m/crm_regs.h > > index c128931289..c42e6685de 100644 > > --- a/arch/arm/include/asm/arch-mx8m/crm_regs.h > > +++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h > > @@ -3,7 +3,7 @@ > > * Copyright 2017 NXP > > */ > > > > -#ifndef _ASM_ARCH_MX8M_CRM_REGS_H > > -#define _ASM_ARCH_MX8M_CRM_REGS_H > > +#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H > > +#define _ASM_ARCH_IMX8M_CRM_REGS_H > > /* Dummy header, some imx-common code needs this file */ #endif diff > > --git a/arch/arm/include/asm/arch-mx8m/ddr.h > > b/arch/arm/include/asm/arch-imx8m/ddr.h > > similarity index 98% > > rename from arch/arm/include/asm/arch-mx8m/ddr.h > > rename to arch/arm/include/asm/arch-imx8m/ddr.h > > index 7e4f6fbb64..1a5cbabdaf 100644 > > --- a/arch/arm/include/asm/arch-mx8m/ddr.h > > +++ b/arch/arm/include/asm/arch-imx8m/ddr.h > > @@ -3,8 +3,8 @@ > > * Copyright 2017 NXP > > */ > > > > -#ifndef __ASM_ARCH_MX8M_DDR_H > > -#define __ASM_ARCH_MX8M_DDR_H > > +#ifndef __ASM_ARCH_IMX8M_DDR_H > > +#define __ASM_ARCH_IMX8M_DDR_H > > > > #define DDRC_DDR_SS_GPR0 0x3d000000 > > #define DDRC_IPS_BASE_ADDR_0 0x3f400000 > > diff --git a/arch/arm/include/asm/arch-mx8m/gpio.h > > b/arch/arm/include/asm/arch-imx8m/gpio.h > > similarity index 63% > > rename from arch/arm/include/asm/arch-mx8m/gpio.h > > rename to arch/arm/include/asm/arch-imx8m/gpio.h > > index 2ba5643d05..2d9fbcb0e4 100644 > > --- a/arch/arm/include/asm/arch-mx8m/gpio.h > > +++ b/arch/arm/include/asm/arch-imx8m/gpio.h > > @@ -3,8 +3,8 @@ > > * Copyright 2017 NXP > > */ > > > > -#ifndef __ASM_ARCH_MX8M_GPIO_H > > -#define __ASM_ARCH_MX8M_GPIO_H > > +#ifndef __ASM_ARCH_IMX8M_GPIO_H > > +#define __ASM_ARCH_IMX8M_GPIO_H > > > > #include <asm/mach-imx/gpio.h> > > > > diff --git a/arch/arm/include/asm/arch-mx8m/imx-regs.h > > b/arch/arm/include/asm/arch-imx8m/imx-regs.h > > similarity index 99% > > rename from arch/arm/include/asm/arch-mx8m/imx-regs.h > > rename to arch/arm/include/asm/arch-imx8m/imx-regs.h > > index a3b06282b0..3facd5450c 100644 > > --- a/arch/arm/include/asm/arch-mx8m/imx-regs.h > > +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h > > @@ -3,8 +3,8 @@ > > * Copyright 2017 NXP > > */ > > > > -#ifndef __ASM_ARCH_MX8M_REGS_H__ > > -#define __ASM_ARCH_MX8M_REGS_H__ > > +#ifndef __ASM_ARCH_IMX8M_REGS_H__ > > +#define __ASM_ARCH_IMX8M_REGS_H__ > > > > #include <asm/mach-imx/regs-lcdif.h> > > > > diff --git a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h > > b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > > similarity index 99% > > rename from arch/arm/include/asm/arch-mx8m/mx8mq_pins.h > > rename to arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > > index 3ba4d15a2a..c71913f209 100644 > > --- a/arch/arm/include/asm/arch-mx8m/mx8mq_pins.h > > +++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h > > @@ -3,8 +3,8 @@ > > * Copyright (C) 2017 NXP > > */ > > > > -#ifndef __ASM_ARCH_MX8MQ_PINS_H__ > > -#define __ASM_ARCH_MX8MQ_PINS_H__ > > +#ifndef __ASM_ARCH_IMX8MQ_PINS_H__ > > +#define __ASM_ARCH_IMX8MQ_PINS_H__ > > > > #include <asm/mach-imx/iomux-v3.h> > > > > diff --git a/arch/arm/include/asm/arch-mx8m/sys_proto.h > > b/arch/arm/include/asm/arch-imx8m/sys_proto.h > > similarity index 82% > > rename from arch/arm/include/asm/arch-mx8m/sys_proto.h > > rename to arch/arm/include/asm/arch-imx8m/sys_proto.h > > index 01d6cd76c1..d328542ece 100644 > > --- a/arch/arm/include/asm/arch-mx8m/sys_proto.h > > +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h > > @@ -3,8 +3,8 @@ > > * Copyright (C) 2017 NXP > > */ > > > > -#ifndef __ARCH_MX8M_SYS_PROTO_H > > -#define __ARCH_MX8M_SYS_PROTO_H > > +#ifndef __ARCH_IMX8M_SYS_PROTO_H > > +#define __ARCH_NMX8M_SYS_PROTO_H > > > > #include <asm/mach-imx/sys_proto.h> > > > > diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h > > b/arch/arm/include/asm/mach-imx/iomux-v3.h > > index 63f4b33aeb..b899a4ff6f 100644 > > --- a/arch/arm/include/asm/mach-imx/iomux-v3.h > > +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h > > @@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t; > > #define IOMUX_CONFIG_LPSR 0x20 > > #define MUX_MODE_LPSR > ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ > > MUX_MODE_SHIFT) -#ifdef > CONFIG_MX8M > > +#ifdef CONFIG_IMX8M > > #define PAD_CTL_DSE0 (0x0 << 0) > > #define PAD_CTL_DSE1 (0x1 << 0) > > #define PAD_CTL_DSE2 (0x2 << 0) > > diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h > > b/arch/arm/include/asm/mach-imx/regs-lcdif.h > > index d294c90646..b4c430a35c 100644 > > --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h > > +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h > > @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { > > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > > - defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8M) > > mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ > > #endif > > mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ > > @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { > > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > > - defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8M) > > mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ > > #endif > > mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ > > @@ -73,7 +73,7 @@ struct mxs_lcdif_regs { > > defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ > > defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ > > defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ > > - defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8M) > > mxs_reg_32(hw_lcdif_thres) > > mxs_reg_32(hw_lcdif_as_ctrl) > > mxs_reg_32(hw_lcdif_as_buf) > > diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h > > b/arch/arm/include/asm/mach-imx/sys_proto.h > > index e3dd5f5064..8d6832a331 100644 > > --- a/arch/arm/include/asm/mach-imx/sys_proto.h > > +++ b/arch/arm/include/asm/mach-imx/sys_proto.h > > @@ -26,7 +26,7 @@ > > > > #define is_mx6() (is_soc_type(MXC_SOC_MX6)) #define is_mx7() > > (is_soc_type(MXC_SOC_MX7)) -#define is_mx8m() > > (is_soc_type(MXC_SOC_MX8M)) > > +#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) > > #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) > > > > #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || > > is_cpu_type(MXC_CPU_MX6DP)) diff --git a/arch/arm/mach-imx/Makefile > > b/arch/arm/mach-imx/Makefile index eb84315d9d..34e380e0b3 100644 > > --- a/arch/arm/mach-imx/Makefile > > +++ b/arch/arm/mach-imx/Makefile > > @@ -5,11 +5,11 @@ > > # > > # (C) Copyright 2011 Freescale Semiconductor, Inc. > > > > -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610)) > > +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610)) > > obj-y = iomux-v3.o > > endif > > > > -ifeq ($(SOC),$(filter $(SOC),mx8m)) > > +ifeq ($(SOC),$(filter $(SOC),imx8m)) > > obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o > > obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o > > obj-$(CONFIG_FEC_MXC) += mac.o > > @@ -22,7 +22,7 @@ obj-y += cpu.o speed.o > > obj-$(CONFIG_GPT_TIMER) += timer.o > > obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter > > $(SOC),mx7 mx6 mxs mx8m)) > > +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m)) > > obj-y += misc.o > > obj-$(CONFIG_SPL_BUILD) += spl.o > > endif > > @@ -169,5 +169,5 @@ obj-$(CONFIG_MX5) += mx5/ > > obj-$(CONFIG_MX6) += mx6/ > > obj-$(CONFIG_MX7) += mx7/ > > obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ > > -obj-$(CONFIG_MX8M) += mx8m/ > > +obj-$(CONFIG_IMX8M) += imx8m/ > > obj-$(CONFIG_ARCH_IMX8) += imx8/ > > diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index > > dcdaced991..80d9ff48a4 100644 > > --- a/arch/arm/mach-imx/cpu.c > > +++ b/arch/arm/mach-imx/cpu.c > > @@ -62,7 +62,7 @@ static char *get_reset_cause(void) > > return "WDOG4"; > > case 0x00200: > > return "TEMPSENSE"; > > -#elif defined(CONFIG_MX8M) > > +#elif defined(CONFIG_IMX8M) > > case 0x00100: > > return "WDOG2"; > > case 0x00200: > > @@ -142,8 +142,8 @@ unsigned imx_ddr_size(void) const char > > *get_imx_type(u32 imxtype) { > > switch (imxtype) { > > - case MXC_CPU_MX8MQ: > > - return "8MQ"; /* Quad-core version of the mx8m */ > > + case MXC_CPU_IMX8MQ: > > + return "8MQ"; /* Quad-core version of the imx8m */ > > case MXC_CPU_MX7S: > > return "7S"; /* Single-core version of the mx7 */ > > case MXC_CPU_MX7D: > > @@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis) } #endif > > > > -#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M)) > > +#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) > > u32 get_ahb_clk(void) > > { > > struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg > > *)CCM_BASE_ADDR; @@ -300,7 +300,7 @@ void arch_preboot_os(void) > > #endif } > > > > -#ifndef CONFIG_MX8M > > +#ifndef CONFIG_IMX8M > > void set_chipselect_size(int const cs_size) { > > unsigned int reg; > > @@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size) } > > #endif > > > > -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) > > +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > > /* > > * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440) > > * defines a 2-bit SPEED_GRADING > > @@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } > > #endif > > > > -#if defined(CONFIG_MX7) || defined(CONFIG_MX8M) > > +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > > enum boot_device get_boot_device(void) { > > struct bootrom_sw_info **p = > > @@ -438,7 +438,7 @@ enum boot_device get_boot_device(void) > > case BOOT_TYPE_SPINOR: > > boot_dev = SPI_NOR_BOOT; > > break; > > -#ifdef CONFIG_MX8M > > +#ifdef CONFIG_IMX8M > > case BOOT_TYPE_USB: > > boot_dev = USB_BOOT; > > break; > > diff --git a/arch/arm/mach-imx/mx8m/Kconfig > > b/arch/arm/mach-imx/imx8m/Kconfig similarity index 57% rename from > > arch/arm/mach-imx/mx8m/Kconfig rename to > > arch/arm/mach-imx/imx8m/Kconfig index 3a84c2f2b0..98d79c3179 > 100644 > > --- a/arch/arm/mach-imx/mx8m/Kconfig > > +++ b/arch/arm/mach-imx/imx8m/Kconfig > > @@ -1,10 +1,10 @@ > > -if ARCH_MX8M > > +if ARCH_IMX8M > > > > -config MX8M > > +config IMX8M > > bool > > select ROM_UNIFIED_SECTIONS > > > > config SYS_SOC > > - default "mx8m" > > + default "imx8m" > > > > endif > > diff --git a/arch/arm/mach-imx/mx8m/Makefile > > b/arch/arm/mach-imx/imx8m/Makefile > > similarity index 100% > > rename from arch/arm/mach-imx/mx8m/Makefile rename to > > arch/arm/mach-imx/imx8m/Makefile diff --git > > a/arch/arm/mach-imx/mx8m/clock.c > b/arch/arm/mach-imx/imx8m/clock.c > > similarity index 99% rename from arch/arm/mach-imx/mx8m/clock.c > rename > > to arch/arm/mach-imx/imx8m/clock.c index fe32e1c3f1..f2cb4e1030 > 100644 > > --- a/arch/arm/mach-imx/mx8m/clock.c > > +++ b/arch/arm/mach-imx/imx8m/clock.c > > @@ -730,7 +730,7 @@ int clock_init(void) > > * Dump some clockes. > > */ > > #ifndef CONFIG_SPL_BUILD > > -int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, > > +int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, > > char * const argv[]) { > > u32 freq; > > @@ -785,7 +785,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int > flag, > > int argc, } > > > > U_BOOT_CMD( > > - clocks, CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks, > > + clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, > > "display clocks", > > "" > > ); > > diff --git a/arch/arm/mach-imx/mx8m/clock_slice.c > > b/arch/arm/mach-imx/imx8m/clock_slice.c > > similarity index 100% > > rename from arch/arm/mach-imx/mx8m/clock_slice.c > > rename to arch/arm/mach-imx/imx8m/clock_slice.c > > diff --git a/arch/arm/mach-imx/mx8m/lowlevel_init.S > > b/arch/arm/mach-imx/imx8m/lowlevel_init.S > > similarity index 100% > > rename from arch/arm/mach-imx/mx8m/lowlevel_init.S > > rename to arch/arm/mach-imx/imx8m/lowlevel_init.S > > diff --git a/arch/arm/mach-imx/mx8m/soc.c > > b/arch/arm/mach-imx/imx8m/soc.c similarity index 100% rename from > > arch/arm/mach-imx/mx8m/soc.c rename to > arch/arm/mach-imx/imx8m/soc.c > > diff --git a/arch/arm/mach-imx/imx_bootaux.c > > b/arch/arm/mach-imx/imx_bootaux.c index a1ea5c13f1..ae3734ecb9 > 100644 > > --- a/arch/arm/mach-imx/imx_bootaux.c > > +++ b/arch/arm/mach-imx/imx_bootaux.c > > @@ -25,7 +25,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong > boot_private_data) > > writel(pc, M4_BOOTROM_BASE_ADDR + 4); > > > > /* Enable M4 */ > > -#ifdef CONFIG_MX8M > > +#ifdef CONFIG_IMX8M > > call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0); > #else > > clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ > -37,7 > > +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong > > boot_private_data) > > > > int arch_auxiliary_core_check_up(u32 core_id) { -#ifdef CONFIG_MX8M > > +#ifdef CONFIG_IMX8M > > return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, > > 0); #else > > unsigned int val; > > diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index > > 6f0b5cdb4c..e82eaa5682 100644 > > --- a/arch/arm/mach-imx/spl.c > > +++ b/arch/arm/mach-imx/spl.c > > @@ -96,8 +96,8 @@ u32 spl_boot_device(void) > > return BOOT_DEVICE_NONE; > > } > > > > -#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M) > > -/* Translate iMX7/MX8M boot device to the SPL boot device enumeration > > */ > > +#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) > > +/* Translate iMX7/i.MX8M boot device to the SPL boot device > > +enumeration */ > > u32 spl_boot_device(void) > > { > > #if defined(CONFIG_MX7) > > @@ -143,7 +143,7 @@ u32 spl_boot_device(void) > > return BOOT_DEVICE_NONE; > > } > > } > > -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */ > > +#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */ > > > > #ifdef CONFIG_SPL_USB_GADGET_SUPPORT > > int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char > > *name) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c > > index b820160ae7..8bd30c75b2 100644 > > --- a/drivers/gpio/mxc_gpio.c > > +++ b/drivers/gpio/mxc_gpio.c > > @@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = { > > [2] = GPIO3_BASE_ADDR, > > #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || > defined(CONFIG_MX51) || \ > > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ > > + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ > > defined(CONFIG_ARCH_IMX8) > > [3] = GPIO4_BASE_ADDR, > > #endif > > #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || > defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ > > + defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ > > defined(CONFIG_ARCH_IMX8) > > [4] = GPIO5_BASE_ADDR, > > -#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || > > defined(CONFIG_MX8M)) > > +#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || > > +defined(CONFIG_IMX8M)) > > [5] = GPIO6_BASE_ADDR, > > #endif > > #endif > > @@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = { > > { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, #if > > defined(CONFIG_MX25) || defined(CONFIG_MX27) || > defined(CONFIG_MX51) || \ > > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX8M) || > defined(CONFIG_ARCH_IMX8) > > + defined(CONFIG_IMX8M) || > defined(CONFIG_ARCH_IMX8) > > { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif #if > > defined(CONFIG_MX27) || defined(CONFIG_MX53) || > defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX8M) || > defined(CONFIG_ARCH_IMX8) > > + defined(CONFIG_IMX8M) || > defined(CONFIG_ARCH_IMX8) > > { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, -#ifndef > > CONFIG_MX8M > > +#ifndef CONFIG_IMX8M > > { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, #endif #endif > @@ > > -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = { > > { "gpio_mxc", &mxc_plat[2] }, > > #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || > defined(CONFIG_MX51) || \ > > defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX8M) || > defined(CONFIG_ARCH_IMX8) > > + defined(CONFIG_IMX8M) || > defined(CONFIG_ARCH_IMX8) > > { "gpio_mxc", &mxc_plat[3] }, > > #endif > > #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || > defined(CONFIG_MX6) || \ > > - defined(CONFIG_MX8M) || > defined(CONFIG_ARCH_IMX8) > > + defined(CONFIG_IMX8M) || > defined(CONFIG_ARCH_IMX8) > > { "gpio_mxc", &mxc_plat[4] }, > > -#ifndef CONFIG_MX8M > > +#ifndef CONFIG_IMX8M > > { "gpio_mxc", &mxc_plat[5] }, > > #endif > > #endif > > diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index > > 9ff475d925..f84fe88db1 100644 > > --- a/drivers/misc/mxc_ocotp.c > > +++ b/drivers/misc/mxc_ocotp.c > > @@ -34,7 +34,7 @@ > > #define BM_OUT_STATUS_DED > 0x00000400 > > #define BM_OUT_STATUS_LOCKED 0x00000800 > > #define BM_OUT_STATUS_PROGFAIL 0x00001000 > > -#elif defined(CONFIG_MX8M) > > +#elif defined(CONFIG_IMX8M) > > #define BM_CTRL_ADDR 0x000000ff > > #else > > #define BM_CTRL_ADDR 0x0000007f > > @@ -80,7 +80,7 @@ > > #elif defined(CONFIG_MX7ULP) > > #define FUSE_BANK_SIZE 0x80 > > #define FUSE_BANKS 31 > > -#elif defined(CONFIG_MX8M) > > +#elif defined(CONFIG_IMX8M) > > #define FUSE_BANK_SIZE 0x40 > > #define FUSE_BANKS 64 > > #else > > @@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs > *regs, u32 bank, u32 word, > > u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; #ifdef > > CONFIG_MX7 > > u32 addr = bank; > > -#elif defined CONFIG_MX8M > > +#elif defined CONFIG_IMX8M > > u32 addr = bank << 2 | word; > > #else > > u32 addr; > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index > > 3cdfa7f5a6..74007e2ad4 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv > *priv, struct mmc *mmc, > > int timeout; > > struct fsl_esdhc *regs = priv->esdhc_regs; #if > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > > dma_addr_t addr; > > #endif > > uint wml_value; > > @@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv > *priv, struct mmc *mmc, > > esdhc_clrsetbits32(®s->wml, > WML_RD_WML_MASK, > > wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO #if > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > > addr = virt_to_phys((void *)(data->dest)); > > if (upper_32_bits(addr)) > > printf("Error found for upper 32 bits\n"); @@ > > -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, > struct mmc *mmc, > > wml_value << 16); > #ifndef > > CONFIG_SYS_FSL_ESDHC_USE_PIO #if defined(CONFIG_FSL_LAYERSCAPE) > || > > defined(CONFIG_S32V234) || \ > > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > > addr = virt_to_phys((void *)(data->src)); > > if (upper_32_bits(addr)) > > printf("Error found for upper 32 bits\n"); @@ > > -369,7 +369,7 @@ static void check_and_invalidate_dcache_range > > unsigned size = roundup(ARCH_DMA_MINALIGN, > > data->blocks*data->blocksize); > #if > > defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \ > > - defined(CONFIG_IMX8) || defined(CONFIG_MX8M) > > + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) > > dma_addr_t addr; > > > > addr = virt_to_phys((void *)(data->dest)); diff --git > > a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index > > 99c5c649a0..32fb34b793 100644 > > --- a/drivers/net/fec_mxc.c > > +++ b/drivers/net/fec_mxc.c > > @@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) > > writel(0x00000000, &fec->eth->gaddr2); > > > > /* Do not access reserved register */ > > - if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) { > > + if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) { > > /* clear MIB RAM */ > > for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) > > writel(0, i); > > -- > > 2.14.1 > > > > This patch leaves out the driver changes that depend on this naming change. > If this patch accepted then we also need the following changes. > > -Jon ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 06/15] imx: spl: add MMC BOOT Device for i.MX8M 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (3 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 07/15] imx: imx8m: clock refactor dram pll part Peng Fan ` (8 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Add MMC BOOT Device for i.MX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: Correct comments arch/arm/mach-imx/spl.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index e82eaa5682..58a92278df 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -126,6 +126,7 @@ u32 spl_boot_device(void) enum boot_device boot_device_spl = get_boot_device(); switch (boot_device_spl) { +#if defined(CONFIG_MX7) case SD1_BOOT: case MMC1_BOOT: case SD2_BOOT: @@ -133,6 +134,14 @@ u32 spl_boot_device(void) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_IMX8M) + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; +#endif case NAND_BOOT: return BOOT_DEVICE_NAND; case SPI_NOR_BOOT: @@ -143,7 +152,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } } -#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */ +#endif /* CONFIG_MX7 || CONFIG_IMX8M */ #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 07/15] imx: imx8m: clock refactor dram pll part 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (4 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 06/15] imx: spl: add MMC BOOT Device for i.MX8M Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support Peng Fan ` (7 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Refactor dram_pll_init to accept args to configure different pll freq. Introduce dram_enable_bypass and dram_disable_bypass Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: Use freq to replace macros arch/arm/include/asm/arch-imx8m/clock.h | 22 ++++++ arch/arm/mach-imx/imx8m/clock.c | 134 ++++++++++++++++++++++++++------ 2 files changed, 132 insertions(+), 24 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index 45cfea3018..e7c1670f6b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -10,6 +10,8 @@ #include <linux/bitops.h> +#define MHZ(X) ((X) * 1000000UL) + enum pll_clocks { ANATOP_ARM_PLL, ANATOP_GPU_PLL, @@ -631,6 +633,26 @@ enum frac_pll_out_val { FRAC_PLL_OUT_1600M, }; +#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ + { \ + .clk = (_rate), \ + .alt_root_sel = (_m), \ + .alt_pre_div = (_p), \ + .apb_root_sel = (_s), \ + .apb_pre_div = (_k), \ + } + +struct dram_bypass_clk_setting { + ulong clk; + int alt_root_sel; + enum root_pre_div alt_pre_div; + int apb_root_sel; + enum root_pre_div apb_pre_div; +}; + +void dram_pll_init(ulong pll_val); +void dram_enable_bypass(ulong clk_val); +void dram_disable_bypass(void); u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); diff --git a/arch/arm/mach-imx/imx8m/clock.c b/arch/arm/mach-imx/imx8m/clock.c index f2cb4e1030..3766d988ba 100644 --- a/arch/arm/mach-imx/imx8m/clock.c +++ b/arch/arm/mach-imx/imx8m/clock.c @@ -525,41 +525,127 @@ u32 imx_get_fecclk(void) return get_root_clk(ENET_AXI_CLK_ROOT); } -#ifdef CONFIG_SPL_BUILD -void dram_pll_init(void) +static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { + DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, + CLK_ROOT_PRE_DIV2), + DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, + CLK_ROOT_PRE_DIV2), +}; + +void dram_enable_bypass(ulong clk_val) { - struct src *src = (struct src *)SRC_BASE_ADDR; - void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; - u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; - u32 val; - int ret; + int i; + struct dram_bypass_clk_setting *config; - setbits_le32(GPC_BASE_ADDR + 0xEC, BIT(7)); - setbits_le32(GPC_BASE_ADDR + 0xF8, BIT(5)); + for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { + if (clk_val == imx8mq_dram_bypass_tbl[i].clk) + break; + } + + if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { + printf("No matched freq table %lu\n", clk_val); + return; + } - pwdn_mask = SSCG_PLL_PD_MASK; - pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; - bypass1 = SSCG_PLL_BYPASS1_MASK; - bypass2 = SSCG_PLL_BYPASS2_MASK; + config = &imx8mq_dram_bypass_tbl[i]; - /* Enable DDR1 and DDR2 domain */ - writel(SRC_DDR1_ENABLE_MASK, &src->ddr1_rcr); - writel(SRC_DDR1_ENABLE_MASK, &src->ddr2_rcr); + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | + CLK_ROOT_PRE_DIV(config->alt_pre_div)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | + CLK_ROOT_PRE_DIV(config->apb_pre_div)); + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); +} + +void dram_disable_bypass(void) +{ + clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(0)); + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); +} + +#ifdef CONFIG_SPL_BUILD +void dram_pll_init(ulong pll_val) +{ + u32 val; + void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; + void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; + + /* Bypass */ + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); + setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); + + switch (pll_val) { + case MHZ(800): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(0); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(600): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(400): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(1); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); + val |= SSCG_PLL_REF_DIVR2_VAL(29); + writel(val, pll_cfg_reg2); + break; + case MHZ(167): + val = readl(pll_cfg_reg2); + val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | + SSCG_PLL_FEEDBACK_DIV_F2_MASK | + SSCG_PLL_FEEDBACK_DIV_F1_MASK | + SSCG_PLL_REF_DIVR2_MASK); + val |= SSCG_PLL_OUTPUT_DIV_VAL(3); + val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); + val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); + val |= SSCG_PLL_REF_DIVR2_VAL(30); + writel(val, pll_cfg_reg2); + break; + default: + break; + } /* Clear power down bit */ - clrbits_le32(pll_control_reg, pwdn_mask); + clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK); /* Eanble ARM_PLL/SYS_PLL */ - setbits_le32(pll_control_reg, pll_clke); + setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK); /* Clear bypass */ - clrbits_le32(pll_control_reg, bypass1); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); __udelay(100); - clrbits_le32(pll_control_reg, bypass2); + clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); /* Wait lock */ - ret = readl_poll_timeout(pll_control_reg, val, - val & SSCG_PLL_LOCK_MASK, 1); - if (ret) - printf("%s timeout\n", __func__); + while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK)) + ; } int frac_pll_init(u32 pll, enum frac_pll_out_val val) -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (5 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 07/15] imx: imx8m: clock refactor dram pll part Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-12-14 13:25 ` Stefano Babic 2018-11-20 10:19 ` [U-Boot] [PATCH V2 09/15] imx: imx8m: introduce script to generate fit image Peng Fan ` (6 subsequent siblings) 13 siblings, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot i.MX8M bootable image type is like i.MX6/7, but there is signed HDMI firmware image in front of A53 bootable image, which is also has an IVT header. Here we also include fit image to generate a bootable image. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None common/image.c | 1 + include/image.h | 1 + include/imximage.h | 17 +- tools/Makefile | 1 + tools/imagetool.h | 1 + tools/imx8mimage.c | 623 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/mkimage.c | 7 + 7 files changed, 650 insertions(+), 1 deletion(-) create mode 100644 tools/imx8mimage.c diff --git a/common/image.c b/common/image.c index 1c3a7720cb..d1cc1d11bb 100644 --- a/common/image.c +++ b/common/image.c @@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, + { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",}, { IH_TYPE_INVALID, "invalid", "Invalid Image", }, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, diff --git a/include/image.h b/include/image.h index 031c355b48..d1e0d6dfbe 100644 --- a/include/image.h +++ b/include/image.h @@ -252,6 +252,7 @@ enum { IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ + IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ diff --git a/include/imximage.h b/include/imximage.h index 6f7ca7f5e3..544babb53a 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -33,6 +33,7 @@ #define FLASH_OFFSET_NOR 0x1000 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD #define FLASH_OFFSET_QSPI 0x1000 +#define FLASH_OFFSET_FLEXSPI 0x1000 /* Initial Load Region Size */ #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF @@ -48,6 +49,7 @@ /* Command tags and parameters */ #define IVT_HEADER_TAG 0xD1 #define IVT_VERSION 0x40 +#define IVT_VERSION_V3 0x41 #define DCD_HEADER_TAG 0xD2 #define DCD_VERSION 0x40 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC @@ -71,6 +73,12 @@ enum imximage_cmd { CMD_CHECK_BITS_CLR, CMD_CSF, CMD_PLUGIN, + /* Follwoing on i.MX8MQ/MM */ + CMD_FIT, + CMD_SIGNED_HDMI, + CMD_LOADER, + CMD_SECOND_LOADER, + CMD_DDR_FW, }; enum imximage_fld_types { @@ -84,7 +92,8 @@ enum imximage_fld_types { enum imximage_version { IMXIMAGE_VER_INVALID = -1, IMXIMAGE_V1 = 1, - IMXIMAGE_V2 + IMXIMAGE_V2, + IMXIMAGE_V3 }; typedef struct { @@ -177,6 +186,12 @@ typedef struct { } data; } imx_header_v2_t; +typedef struct { + flash_header_v2_t fhdr; + boot_data_t boot_data; + uint32_t padding[5]; +} imx_header_v3_t; + /* The header must be aligned to 4k on MX53 for NAND boot */ struct imx_header { union { diff --git a/tools/Makefile b/tools/Makefile index 3c0521f655..e9b4398039 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \ imagetool.o \ imximage.o \ imx8image.o \ + imx8mimage.o \ kwbimage.o \ lib/md5.o \ lpc32xximage.o \ diff --git a/tools/imagetool.h b/tools/imagetool.h index 3fcfb4468d..71471420f9 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -233,6 +233,7 @@ time_t imagetool_get_source_date( void pbl_load_uboot(int fd, struct image_tool_params *mparams); int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); int imx8image_copy_image(int fd, struct image_tool_params *mparams); +int imx8mimage_copy_image(int fd, struct image_tool_params *mparams); #define ___cat(a, b) a ## b #define __cat(a, b) ___cat(a, b) diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c new file mode 100644 index 0000000000..50a256cbac --- /dev/null +++ b/tools/imx8mimage.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + + +#include "imagetool.h" +#include <image.h> +#include "imximage.h" +#include "compiler.h" + +static uint32_t ap_start_addr, sld_start_addr, sld_src_off; +static char *ap_img, *sld_img, *signed_hdmi; +static imx_header_v3_t imx_header[2]; /* At most there are 3 IVT headers */ +static uint32_t rom_image_offset; +static uint32_t sector_size = 0x200; +static uint32_t image_off; +static uint32_t sld_header_off; +static uint32_t ivt_offset; +static uint32_t using_fit; + +#define CSF_SIZE 0x2000 +#define HDMI_IVT_ID 0 +#define IMAGE_IVT_ID 1 + +#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */ +#define ALIGN_SIZE 0x1000 +#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a) +#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2)) + +static uint32_t get_cfg_value(char *token, char *name, int linenr) +{ + char *endptr; + uint32_t value; + + errno = 0; + value = strtoul(token, &endptr, 16); + if (errno || token == endptr) { + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", + name, linenr, token); + exit(EXIT_FAILURE); + } + return value; +} + +int imx8mimage_check_params(struct image_tool_params *params) +{ + return 0; +} + +static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ +} + +static void imx8mimage_print_header(const void *ptr) +{ +} + +static int imx8mimage_check_image_types(uint8_t type) +{ + return (type == IH_TYPE_IMX8MIMAGE) ? EXIT_SUCCESS : EXIT_FAILURE; +} + +static table_entry_t imx8mimage_cmds[] = { + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, + {CMD_FIT, "FIT", "fit image", }, + {CMD_SIGNED_HDMI, "SIGNED_HDMI", "signed hdmi image", }, + {CMD_LOADER, "LOADER", "loader image", }, + {CMD_SECOND_LOADER, "SECOND_LOADER", "2nd loader image", }, + {CMD_DDR_FW, "DDR_FW", "ddr firmware", }, + {-1, "", "", }, +}; + +static table_entry_t imx8mimage_ivt_offset[] = { + {0x400, "sd", "sd/emmc",}, + {0x400, "emmc_fastboot", "emmc fastboot",}, + {0x1000, "fspi", "flexspi", }, + {-1, "", "Invalid", }, +}; + +static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int lineno) +{ + switch (cmd) { + case CMD_BOOT_FROM: + ivt_offset = get_table_entry_id(imx8mimage_ivt_offset, + "imx8mimage ivt offset", + token); + if (!strncmp(token, "sd", 2)) + rom_image_offset = 0x8000; + break; + case CMD_LOADER: + ap_img = token; + break; + case CMD_SECOND_LOADER: + sld_img = token; + break; + case CMD_SIGNED_HDMI: + signed_hdmi = token; + case CMD_FIT: + using_fit = 1; + break; + case CMD_DDR_FW: + /* Do nothing */ + break; + } +} + +static void parse_cfg_fld(int32_t *cmd, char *token, + char *name, int lineno, int fld) +{ + switch (fld) { + case CFG_COMMAND: + *cmd = get_table_entry_id(imx8mimage_cmds, + "imx8mimage commands", token); + if (*cmd < 0) { + fprintf(stderr, "Error: %s[%d] - Invalid command" "(%s)\n", + name, lineno, token); + exit(EXIT_FAILURE); + } + break; + case CFG_REG_SIZE: + parse_cfg_cmd(*cmd, token, name, lineno); + break; + case CFG_REG_ADDRESS: + switch (*cmd) { + case CMD_LOADER: + ap_start_addr = get_cfg_value(token, name, lineno); + break; + case CMD_SECOND_LOADER: + sld_start_addr = get_cfg_value(token, name, lineno); + break; + } + break; + case CFG_REG_VALUE: + switch (*cmd) { + case CMD_SECOND_LOADER: + sld_src_off = get_cfg_value(token, name, lineno); + break; + } + default: + break; + } +} + +static uint32_t parse_cfg_file(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + int lineno = 0; + int fld; + size_t len; + int32_t cmd; + + fd = fopen(name, "r"); + if (fd == 0) { + fprintf(stderr, "Error: %s - Can't open cfg file\n", name); + exit(EXIT_FAILURE); + } + + /* + * Very simple parsing, line starting with # are comments + * and are dropped + */ + while ((getline(&line, &len, fd)) > 0) { + lineno++; + + token = strtok_r(line, "\r\n", &saveptr1); + if (!token) + continue; + + /* Check inside the single line */ + for (fld = CFG_COMMAND, cmd = CFG_INVALID, + line = token; ; line = NULL, fld++) { + token = strtok_r(line, " \t", &saveptr2); + if (!token) + break; + + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + parse_cfg_fld(&cmd, token, name, lineno, fld); + } + } + + return 0; +} + +static void fill_zero(int ifd, int size, int offset) +{ + int fill_size; + uint8_t zeros[4096]; + int ret; + + memset(zeros, 0, sizeof(zeros)); + + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "%s seek: %s\n", __func__, strerror(errno)); + exit(EXIT_FAILURE); + } + + while (size) { + if (size > 4096) + fill_size = 4096; + else + fill_size = size; + + if (write(ifd, (char *)&zeros, fill_size) != fill_size) { + fprintf(stderr, "Write error: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + size -= fill_size; + }; +} + +static void copy_file(int ifd, const char *datafile, int pad, int offset, + int datafile_offset) +{ + int dfd; + struct stat sbuf; + unsigned char *ptr; + int tail; + int zero = 0; + uint8_t zeros[4096]; + int size, ret; + + memset(zeros, 0, sizeof(zeros)); + + dfd = open(datafile, O_RDONLY | O_BINARY); + if (dfd < 0) { + fprintf(stderr, "Can't open %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(dfd, &sbuf) < 0) { + fprintf(stderr, "Can't stat %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == MAP_FAILED) { + fprintf(stderr, "Can't read %s: %s\n", + datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + + size = sbuf.st_size - datafile_offset; + ret = lseek(ifd, offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ifd fail\n"); + exit(EXIT_FAILURE); + } + + if (write(ifd, ptr + datafile_offset, size) != size) { + fprintf(stderr, "Write error %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + tail = size % 4; + pad = pad - size; + if (pad == 1 && tail != 0) { + if (write(ifd, (char *)&zero, 4 - tail) != 4 - tail) { + fprintf(stderr, "Write error on %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + } else if (pad > 1) { + while (pad > 0) { + int todo = sizeof(zeros); + + if (todo > pad) + todo = pad; + if (write(ifd, (char *)&zeros, todo) != todo) { + fprintf(stderr, "Write error: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + pad -= todo; + } + } + + munmap((void *)ptr, sbuf.st_size); + close(dfd); +} + +/* Return this IVT offset in the final output file */ +static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep, + uint32_t *fit_load_addr) +{ + image_header_t image_header; + int ret; + + uint32_t fit_size, load_addr; + int align_len = 64 - 1; /* 64 is cacheline size */ + + ret = lseek(fd, fit_offset, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek fd fail for fit\n"); + exit(EXIT_FAILURE); + } + + if (read(fd, (char *)&image_header, sizeof(image_header_t)) != + sizeof(image_header_t)) { + fprintf(stderr, "generate_ivt_for_fit read failed: %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + if (be32_to_cpu(image_header.ih_magic) != FDT_MAGIC) { + fprintf(stderr, "%s error: not a FIT file\n", __func__); + exit(EXIT_FAILURE); + } + + fit_size = fdt_totalsize(&image_header); + fit_size = (fit_size + 3) & ~3; + + fit_size = ALIGN(fit_size, ALIGN_SIZE); + + ret = lseek(fd, fit_offset + fit_size, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek fd fail for fit\n"); + exit(EXIT_FAILURE); + } + + /* + * ep is the u-boot entry. SPL loads the FIT before the u-boot + * address. 0x2000 is for CSF_SIZE + */ + load_addr = (ep - (fit_size + CSF_SIZE) - 512 - align_len) & + ~align_len; + + flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 }, + load_addr, 0, 0, 0, + (load_addr + fit_size), + (load_addr + fit_size + 0x20), + 0 }; + + if (write(fd, &ivt_header, sizeof(flash_header_v2_t)) != + sizeof(flash_header_v2_t)) { + fprintf(stderr, "IVT writing error on fit image\n"); + exit(EXIT_FAILURE); + } + + *fit_load_addr = load_addr; + + return fit_offset + fit_size; +} + +static void dump_header_v2(imx_header_v3_t *imx_header, int index) +{ + const char *ivt_name[2] = {"HDMI FW", "LOADER IMAGE"}; + + fprintf(stdout, "========= IVT HEADER [%s] =========\n", + ivt_name[index]); + fprintf(stdout, "header.tag: \t\t0x%x\n", + imx_header[index].fhdr.header.tag); + fprintf(stdout, "header.length: \t\t0x%x\n", + imx_header[index].fhdr.header.length); + fprintf(stdout, "header.version: \t0x%x\n", + imx_header[index].fhdr.header.version); + fprintf(stdout, "entry: \t\t\t0x%x\n", + imx_header[index].fhdr.entry); + fprintf(stdout, "reserved1: \t\t0x%x\n", + imx_header[index].fhdr.reserved1); + fprintf(stdout, "dcd_ptr: \t\t0x%x\n", + imx_header[index].fhdr.dcd_ptr); + fprintf(stdout, "boot_data_ptr: \t\t0x%x\n", + imx_header[index].fhdr.boot_data_ptr); + fprintf(stdout, "self: \t\t\t0x%x\n", + imx_header[index].fhdr.self); + fprintf(stdout, "csf: \t\t\t0x%x\n", + imx_header[index].fhdr.csf); + fprintf(stdout, "reserved2: \t\t0x%x\n", + imx_header[index].fhdr.reserved2); + + fprintf(stdout, "boot_data.start: \t0x%x\n", + imx_header[index].boot_data.start); + fprintf(stdout, "boot_data.size: \t0x%x\n", + imx_header[index].boot_data.size); + fprintf(stdout, "boot_data.plugin: \t0x%x\n", + imx_header[index].boot_data.plugin); +} + +void build_image(int ofd) +{ + int file_off, header_hdmi_off = 0, header_image_off; + int hdmi_fd, ap_fd, sld_fd; + uint32_t sld_load_addr = 0; + uint32_t csf_off, sld_csf_off = 0; + int ret; + struct stat sbuf; + + if (!ap_img) { + fprintf(stderr, "No LOADER image specificed\n"); + exit(EXIT_FAILURE); + } + + file_off = 0; + + if (signed_hdmi) { + header_hdmi_off = file_off + ivt_offset; + + hdmi_fd = open(signed_hdmi, O_RDONLY | O_BINARY); + if (hdmi_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + signed_hdmi, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(hdmi_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + signed_hdmi, strerror(errno)); + exit(EXIT_FAILURE); + } + close(hdmi_fd); + + /* + * Aligned to 104KB = 92KB FW image + 0x8000 + * (IVT and alignment) + 0x4000 (second IVT + CSF) + */ + file_off += ALIGN(sbuf.st_size, + HDMI_FW_SIZE + 0x2000 + 0x1000); + } + + header_image_off = file_off + ivt_offset; + + ap_fd = open(ap_img, O_RDONLY | O_BINARY); + if (ap_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + ap_img, strerror(errno)); + exit(EXIT_FAILURE); + } + if (fstat(ap_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + ap_img, strerror(errno)); + exit(EXIT_FAILURE); + } + close(ap_fd); + + imx_header[IMAGE_IVT_ID].fhdr.header.tag = IVT_HEADER_TAG; /* 0xD1 */ + imx_header[IMAGE_IVT_ID].fhdr.header.length = + cpu_to_be16(sizeof(flash_header_v2_t)); + imx_header[IMAGE_IVT_ID].fhdr.header.version = IVT_VERSION_V3; /* 0x41 */ + imx_header[IMAGE_IVT_ID].fhdr.entry = ap_start_addr; + imx_header[IMAGE_IVT_ID].fhdr.self = ap_start_addr - + sizeof(imx_header_v3_t); + imx_header[IMAGE_IVT_ID].fhdr.dcd_ptr = 0; + imx_header[IMAGE_IVT_ID].fhdr.boot_data_ptr = + imx_header[IMAGE_IVT_ID].fhdr.self + + offsetof(imx_header_v3_t, boot_data); + imx_header[IMAGE_IVT_ID].boot_data.start = + imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset; + imx_header[IMAGE_IVT_ID].boot_data.size = + ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset, + sector_size); + + image_off = header_image_off + sizeof(imx_header_v3_t); + file_off += imx_header[IMAGE_IVT_ID].boot_data.size; + + imx_header[IMAGE_IVT_ID].boot_data.plugin = 0; + imx_header[IMAGE_IVT_ID].fhdr.csf = + imx_header[IMAGE_IVT_ID].boot_data.start + + imx_header[IMAGE_IVT_ID].boot_data.size; + + imx_header[IMAGE_IVT_ID].boot_data.size += CSF_SIZE; /* 8K region dummy CSF */ + + csf_off = file_off; + file_off += CSF_SIZE; + + /* Second boot loader image */ + if (sld_img) { + if (!using_fit) { + fprintf(stderr, "Not support no fit\n"); + exit(EXIT_FAILURE); + } else { + sld_header_off = sld_src_off - rom_image_offset; + /* + * Record the second bootloader relative offset in + * image's IVT reserved1 + */ + imx_header[IMAGE_IVT_ID].fhdr.reserved1 = + sld_header_off - header_image_off; + sld_fd = open(sld_img, O_RDONLY | O_BINARY); + if (sld_fd < 0) { + fprintf(stderr, "%s: Can't open: %s\n", + sld_img, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fstat(sld_fd, &sbuf) < 0) { + fprintf(stderr, "%s: Can't stat: %s\n", + sld_img, strerror(errno)); + exit(EXIT_FAILURE); + } + + close(sld_fd); + + file_off = sld_header_off; + file_off += sbuf.st_size + sizeof(image_header_t); + } + } + + if (signed_hdmi) { + header_hdmi_off -= ivt_offset; + ret = lseek(ofd, header_hdmi_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail for hdmi\n"); + exit(EXIT_FAILURE); + } + + /* The signed HDMI FW has 0x400 IVT offset, need remove it */ + copy_file(ofd, signed_hdmi, 0, header_hdmi_off, 0x400); + } + + /* Main Image */ + header_image_off -= ivt_offset; + image_off -= ivt_offset; + ret = lseek(ofd, header_image_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail\n"); + exit(EXIT_FAILURE); + } + + /* Write image header */ + if (write(ofd, &imx_header[IMAGE_IVT_ID], sizeof(imx_header_v3_t)) != + sizeof(imx_header_v3_t)) { + fprintf(stderr, "error writing image hdr\n"); + exit(1); + } + + copy_file(ofd, ap_img, 0, image_off, 0); + + csf_off -= ivt_offset; + fill_zero(ofd, CSF_SIZE, csf_off); + + if (sld_img) { + sld_header_off -= ivt_offset; + ret = lseek(ofd, sld_header_off, SEEK_SET); + if (ret < 0) { + fprintf(stderr, "lseek ofd fail for sld_img\n"); + exit(EXIT_FAILURE); + } + + /* Write image header */ + if (!using_fit) { + /* TODO */ + } else { + copy_file(ofd, sld_img, 0, sld_header_off, 0); + sld_csf_off = + generate_ivt_for_fit(ofd, sld_header_off, + sld_start_addr, + &sld_load_addr) + 0x20; + } + } + + if (!signed_hdmi) + dump_header_v2(imx_header, 0); + dump_header_v2(imx_header, 1); + + fprintf(stdout, "========= OFFSET dump ========="); + if (signed_hdmi) { + fprintf(stdout, "\nSIGNED HDMI FW:\n"); + fprintf(stdout, " header_hdmi_off \t0x%x\n", + header_hdmi_off); + } + + fprintf(stdout, "\nLoader IMAGE:\n"); + fprintf(stdout, " header_image_off \t0x%x\n image_off \t\t0x%x\n csf_off \t\t0x%x\n", + header_image_off, image_off, csf_off); + fprintf(stdout, " spl hab block: \t0x%x 0x%x 0x%x\n", + imx_header[IMAGE_IVT_ID].fhdr.self, header_image_off, + csf_off - header_image_off); + + fprintf(stdout, "\nSecond Loader IMAGE:\n"); + fprintf(stdout, " sld_header_off \t0x%x\n", + sld_header_off); + fprintf(stdout, " sld_csf_off \t\t0x%x\n", + sld_csf_off); + fprintf(stdout, " sld hab block: \t0x%x 0x%x 0x%x\n", + sld_load_addr, sld_header_off, sld_csf_off - sld_header_off); +} + +int imx8mimage_copy_image(int outfd, struct image_tool_params *mparams) +{ + /* + * SECO FW is a container image, this is to calculate the + * 2nd container offset. + */ + fprintf(stdout, "parsing %s\n", mparams->imagename); + parse_cfg_file(mparams->imagename); + + build_image(outfd); + + return 0; +} + +/* + * imx8mimage parameters + */ +U_BOOT_IMAGE_TYPE( + imx8mimage, + "NXP i.MX8M Boot Image support", + 0, + NULL, + imx8mimage_check_params, + NULL, + imx8mimage_print_header, + imx8mimage_set_header, + NULL, + imx8mimage_check_image_types, + NULL, + NULL +); diff --git a/tools/mkimage.c b/tools/mkimage.c index 38805f0c92..ea5ed542ab 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -530,6 +530,13 @@ int main(int argc, char **argv) ret = imx8image_copy_image(ifd, ¶ms); if (ret) return ret; + } else if (params.type == IH_TYPE_IMX8MIMAGE) { + /* i.MX8M has special Image format */ + int ret; + + ret = imx8mimage_copy_image(ifd, ¶ms); + if (ret) + return ret; } else { copy_file(ifd, params.datafile, pad_len); } -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support 2018-11-20 10:19 ` [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support Peng Fan @ 2018-12-14 13:25 ` Stefano Babic 2018-12-15 3:09 ` Peng Fan 0 siblings, 1 reply; 28+ messages in thread From: Stefano Babic @ 2018-12-14 13:25 UTC (permalink / raw) To: u-boot Hi Peng, On 20/11/18 11:19, Peng Fan wrote: > i.MX8M bootable image type is like i.MX6/7, but there is signed HDMI > firmware image in front of A53 bootable image, which is also has an IVT > header. > > Here we also include fit image to generate a bootable image. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > > V2: > None > > common/image.c | 1 + > include/image.h | 1 + > include/imximage.h | 17 +- > tools/Makefile | 1 + > tools/imagetool.h | 1 + > tools/imx8mimage.c | 623 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > tools/mkimage.c | 7 + > 7 files changed, 650 insertions(+), 1 deletion(-) > create mode 100644 tools/imx8mimage.c > > diff --git a/common/image.c b/common/image.c > index 1c3a7720cb..d1cc1d11bb 100644 > --- a/common/image.c > +++ b/common/image.c > @@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = { > { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, > { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, > { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, > + { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot Image",}, > { IH_TYPE_INVALID, "invalid", "Invalid Image", }, > { IH_TYPE_MULTI, "multi", "Multi-File Image", }, > { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, > diff --git a/include/image.h b/include/image.h > index 031c355b48..d1e0d6dfbe 100644 > --- a/include/image.h > +++ b/include/image.h > @@ -252,6 +252,7 @@ enum { > IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ > IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ > IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ > + IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ I applied after moving this at the end of the list, see comment in the structure. I send a patch to move IH_TYPE_IMXIMAGE, too, because it breaks compatibility. I have applied all imx8m patches, build is fine - I will send my PR now ;-). Best regards, Stefano > IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ > IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ > IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ > diff --git a/include/imximage.h b/include/imximage.h > index 6f7ca7f5e3..544babb53a 100644 > --- a/include/imximage.h > +++ b/include/imximage.h > @@ -33,6 +33,7 @@ > #define FLASH_OFFSET_NOR 0x1000 > #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD > #define FLASH_OFFSET_QSPI 0x1000 > +#define FLASH_OFFSET_FLEXSPI 0x1000 > > /* Initial Load Region Size */ > #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF > @@ -48,6 +49,7 @@ > /* Command tags and parameters */ > #define IVT_HEADER_TAG 0xD1 > #define IVT_VERSION 0x40 > +#define IVT_VERSION_V3 0x41 > #define DCD_HEADER_TAG 0xD2 > #define DCD_VERSION 0x40 > #define DCD_WRITE_DATA_COMMAND_TAG 0xCC > @@ -71,6 +73,12 @@ enum imximage_cmd { > CMD_CHECK_BITS_CLR, > CMD_CSF, > CMD_PLUGIN, > + /* Follwoing on i.MX8MQ/MM */ > + CMD_FIT, > + CMD_SIGNED_HDMI, > + CMD_LOADER, > + CMD_SECOND_LOADER, > + CMD_DDR_FW, > }; > > enum imximage_fld_types { > @@ -84,7 +92,8 @@ enum imximage_fld_types { > enum imximage_version { > IMXIMAGE_VER_INVALID = -1, > IMXIMAGE_V1 = 1, > - IMXIMAGE_V2 > + IMXIMAGE_V2, > + IMXIMAGE_V3 > }; > > typedef struct { > @@ -177,6 +186,12 @@ typedef struct { > } data; > } imx_header_v2_t; > > +typedef struct { > + flash_header_v2_t fhdr; > + boot_data_t boot_data; > + uint32_t padding[5]; > +} imx_header_v3_t; > + > /* The header must be aligned to 4k on MX53 for NAND boot */ > struct imx_header { > union { > diff --git a/tools/Makefile b/tools/Makefile > index 3c0521f655..e9b4398039 100644 > --- a/tools/Makefile > +++ b/tools/Makefile > @@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \ > imagetool.o \ > imximage.o \ > imx8image.o \ > + imx8mimage.o \ > kwbimage.o \ > lib/md5.o \ > lpc32xximage.o \ > diff --git a/tools/imagetool.h b/tools/imagetool.h > index 3fcfb4468d..71471420f9 100644 > --- a/tools/imagetool.h > +++ b/tools/imagetool.h > @@ -233,6 +233,7 @@ time_t imagetool_get_source_date( > void pbl_load_uboot(int fd, struct image_tool_params *mparams); > int zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); > int imx8image_copy_image(int fd, struct image_tool_params *mparams); > +int imx8mimage_copy_image(int fd, struct image_tool_params *mparams); > > #define ___cat(a, b) a ## b > #define __cat(a, b) ___cat(a, b) > diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c > new file mode 100644 > index 0000000000..50a256cbac > --- /dev/null > +++ b/tools/imx8mimage.c > @@ -0,0 +1,623 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + * > + * Peng Fan <peng.fan@nxp.com> > + */ > + > + > +#include "imagetool.h" > +#include <image.h> > +#include "imximage.h" > +#include "compiler.h" > + > +static uint32_t ap_start_addr, sld_start_addr, sld_src_off; > +static char *ap_img, *sld_img, *signed_hdmi; > +static imx_header_v3_t imx_header[2]; /* At most there are 3 IVT headers */ > +static uint32_t rom_image_offset; > +static uint32_t sector_size = 0x200; > +static uint32_t image_off; > +static uint32_t sld_header_off; > +static uint32_t ivt_offset; > +static uint32_t using_fit; > + > +#define CSF_SIZE 0x2000 > +#define HDMI_IVT_ID 0 > +#define IMAGE_IVT_ID 1 > + > +#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */ > +#define ALIGN_SIZE 0x1000 > +#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a) > +#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * (mask2)) > + > +static uint32_t get_cfg_value(char *token, char *name, int linenr) > +{ > + char *endptr; > + uint32_t value; > + > + errno = 0; > + value = strtoul(token, &endptr, 16); > + if (errno || token == endptr) { > + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", > + name, linenr, token); > + exit(EXIT_FAILURE); > + } > + return value; > +} > + > +int imx8mimage_check_params(struct image_tool_params *params) > +{ > + return 0; > +} > + > +static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd, > + struct image_tool_params *params) > +{ > +} > + > +static void imx8mimage_print_header(const void *ptr) > +{ > +} > + > +static int imx8mimage_check_image_types(uint8_t type) > +{ > + return (type == IH_TYPE_IMX8MIMAGE) ? EXIT_SUCCESS : EXIT_FAILURE; > +} > + > +static table_entry_t imx8mimage_cmds[] = { > + {CMD_BOOT_FROM, "BOOT_FROM", "boot command", }, > + {CMD_FIT, "FIT", "fit image", }, > + {CMD_SIGNED_HDMI, "SIGNED_HDMI", "signed hdmi image", }, > + {CMD_LOADER, "LOADER", "loader image", }, > + {CMD_SECOND_LOADER, "SECOND_LOADER", "2nd loader image", }, > + {CMD_DDR_FW, "DDR_FW", "ddr firmware", }, > + {-1, "", "", }, > +}; > + > +static table_entry_t imx8mimage_ivt_offset[] = { > + {0x400, "sd", "sd/emmc",}, > + {0x400, "emmc_fastboot", "emmc fastboot",}, > + {0x1000, "fspi", "flexspi", }, > + {-1, "", "Invalid", }, > +}; > + > +static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int lineno) > +{ > + switch (cmd) { > + case CMD_BOOT_FROM: > + ivt_offset = get_table_entry_id(imx8mimage_ivt_offset, > + "imx8mimage ivt offset", > + token); > + if (!strncmp(token, "sd", 2)) > + rom_image_offset = 0x8000; > + break; > + case CMD_LOADER: > + ap_img = token; > + break; > + case CMD_SECOND_LOADER: > + sld_img = token; > + break; > + case CMD_SIGNED_HDMI: > + signed_hdmi = token; > + case CMD_FIT: > + using_fit = 1; > + break; > + case CMD_DDR_FW: > + /* Do nothing */ > + break; > + } > +} > + > +static void parse_cfg_fld(int32_t *cmd, char *token, > + char *name, int lineno, int fld) > +{ > + switch (fld) { > + case CFG_COMMAND: > + *cmd = get_table_entry_id(imx8mimage_cmds, > + "imx8mimage commands", token); > + if (*cmd < 0) { > + fprintf(stderr, "Error: %s[%d] - Invalid command" "(%s)\n", > + name, lineno, token); > + exit(EXIT_FAILURE); > + } > + break; > + case CFG_REG_SIZE: > + parse_cfg_cmd(*cmd, token, name, lineno); > + break; > + case CFG_REG_ADDRESS: > + switch (*cmd) { > + case CMD_LOADER: > + ap_start_addr = get_cfg_value(token, name, lineno); > + break; > + case CMD_SECOND_LOADER: > + sld_start_addr = get_cfg_value(token, name, lineno); > + break; > + } > + break; > + case CFG_REG_VALUE: > + switch (*cmd) { > + case CMD_SECOND_LOADER: > + sld_src_off = get_cfg_value(token, name, lineno); > + break; > + } > + default: > + break; > + } > +} > + > +static uint32_t parse_cfg_file(char *name) > +{ > + FILE *fd = NULL; > + char *line = NULL; > + char *token, *saveptr1, *saveptr2; > + int lineno = 0; > + int fld; > + size_t len; > + int32_t cmd; > + > + fd = fopen(name, "r"); > + if (fd == 0) { > + fprintf(stderr, "Error: %s - Can't open cfg file\n", name); > + exit(EXIT_FAILURE); > + } > + > + /* > + * Very simple parsing, line starting with # are comments > + * and are dropped > + */ > + while ((getline(&line, &len, fd)) > 0) { > + lineno++; > + > + token = strtok_r(line, "\r\n", &saveptr1); > + if (!token) > + continue; > + > + /* Check inside the single line */ > + for (fld = CFG_COMMAND, cmd = CFG_INVALID, > + line = token; ; line = NULL, fld++) { > + token = strtok_r(line, " \t", &saveptr2); > + if (!token) > + break; > + > + /* Drop all text starting with '#' as comments */ > + if (token[0] == '#') > + break; > + > + parse_cfg_fld(&cmd, token, name, lineno, fld); > + } > + } > + > + return 0; > +} > + > +static void fill_zero(int ifd, int size, int offset) > +{ > + int fill_size; > + uint8_t zeros[4096]; > + int ret; > + > + memset(zeros, 0, sizeof(zeros)); > + > + ret = lseek(ifd, offset, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "%s seek: %s\n", __func__, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + while (size) { > + if (size > 4096) > + fill_size = 4096; > + else > + fill_size = size; > + > + if (write(ifd, (char *)&zeros, fill_size) != fill_size) { > + fprintf(stderr, "Write error: %s\n", > + strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + size -= fill_size; > + }; > +} > + > +static void copy_file(int ifd, const char *datafile, int pad, int offset, > + int datafile_offset) > +{ > + int dfd; > + struct stat sbuf; > + unsigned char *ptr; > + int tail; > + int zero = 0; > + uint8_t zeros[4096]; > + int size, ret; > + > + memset(zeros, 0, sizeof(zeros)); > + > + dfd = open(datafile, O_RDONLY | O_BINARY); > + if (dfd < 0) { > + fprintf(stderr, "Can't open %s: %s\n", > + datafile, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + if (fstat(dfd, &sbuf) < 0) { > + fprintf(stderr, "Can't stat %s: %s\n", > + datafile, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); > + if (ptr == MAP_FAILED) { > + fprintf(stderr, "Can't read %s: %s\n", > + datafile, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + size = sbuf.st_size - datafile_offset; > + ret = lseek(ifd, offset, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek ifd fail\n"); > + exit(EXIT_FAILURE); > + } > + > + if (write(ifd, ptr + datafile_offset, size) != size) { > + fprintf(stderr, "Write error %s\n", > + strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + tail = size % 4; > + pad = pad - size; > + if (pad == 1 && tail != 0) { > + if (write(ifd, (char *)&zero, 4 - tail) != 4 - tail) { > + fprintf(stderr, "Write error on %s\n", > + strerror(errno)); > + exit(EXIT_FAILURE); > + } > + } else if (pad > 1) { > + while (pad > 0) { > + int todo = sizeof(zeros); > + > + if (todo > pad) > + todo = pad; > + if (write(ifd, (char *)&zeros, todo) != todo) { > + fprintf(stderr, "Write error: %s\n", > + strerror(errno)); > + exit(EXIT_FAILURE); > + } > + pad -= todo; > + } > + } > + > + munmap((void *)ptr, sbuf.st_size); > + close(dfd); > +} > + > +/* Return this IVT offset in the final output file */ > +static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep, > + uint32_t *fit_load_addr) > +{ > + image_header_t image_header; > + int ret; > + > + uint32_t fit_size, load_addr; > + int align_len = 64 - 1; /* 64 is cacheline size */ > + > + ret = lseek(fd, fit_offset, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek fd fail for fit\n"); > + exit(EXIT_FAILURE); > + } > + > + if (read(fd, (char *)&image_header, sizeof(image_header_t)) != > + sizeof(image_header_t)) { > + fprintf(stderr, "generate_ivt_for_fit read failed: %s\n", > + strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + if (be32_to_cpu(image_header.ih_magic) != FDT_MAGIC) { > + fprintf(stderr, "%s error: not a FIT file\n", __func__); > + exit(EXIT_FAILURE); > + } > + > + fit_size = fdt_totalsize(&image_header); > + fit_size = (fit_size + 3) & ~3; > + > + fit_size = ALIGN(fit_size, ALIGN_SIZE); > + > + ret = lseek(fd, fit_offset + fit_size, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek fd fail for fit\n"); > + exit(EXIT_FAILURE); > + } > + > + /* > + * ep is the u-boot entry. SPL loads the FIT before the u-boot > + * address. 0x2000 is for CSF_SIZE > + */ > + load_addr = (ep - (fit_size + CSF_SIZE) - 512 - align_len) & > + ~align_len; > + > + flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 }, > + load_addr, 0, 0, 0, > + (load_addr + fit_size), > + (load_addr + fit_size + 0x20), > + 0 }; > + > + if (write(fd, &ivt_header, sizeof(flash_header_v2_t)) != > + sizeof(flash_header_v2_t)) { > + fprintf(stderr, "IVT writing error on fit image\n"); > + exit(EXIT_FAILURE); > + } > + > + *fit_load_addr = load_addr; > + > + return fit_offset + fit_size; > +} > + > +static void dump_header_v2(imx_header_v3_t *imx_header, int index) > +{ > + const char *ivt_name[2] = {"HDMI FW", "LOADER IMAGE"}; > + > + fprintf(stdout, "========= IVT HEADER [%s] =========\n", > + ivt_name[index]); > + fprintf(stdout, "header.tag: \t\t0x%x\n", > + imx_header[index].fhdr.header.tag); > + fprintf(stdout, "header.length: \t\t0x%x\n", > + imx_header[index].fhdr.header.length); > + fprintf(stdout, "header.version: \t0x%x\n", > + imx_header[index].fhdr.header.version); > + fprintf(stdout, "entry: \t\t\t0x%x\n", > + imx_header[index].fhdr.entry); > + fprintf(stdout, "reserved1: \t\t0x%x\n", > + imx_header[index].fhdr.reserved1); > + fprintf(stdout, "dcd_ptr: \t\t0x%x\n", > + imx_header[index].fhdr.dcd_ptr); > + fprintf(stdout, "boot_data_ptr: \t\t0x%x\n", > + imx_header[index].fhdr.boot_data_ptr); > + fprintf(stdout, "self: \t\t\t0x%x\n", > + imx_header[index].fhdr.self); > + fprintf(stdout, "csf: \t\t\t0x%x\n", > + imx_header[index].fhdr.csf); > + fprintf(stdout, "reserved2: \t\t0x%x\n", > + imx_header[index].fhdr.reserved2); > + > + fprintf(stdout, "boot_data.start: \t0x%x\n", > + imx_header[index].boot_data.start); > + fprintf(stdout, "boot_data.size: \t0x%x\n", > + imx_header[index].boot_data.size); > + fprintf(stdout, "boot_data.plugin: \t0x%x\n", > + imx_header[index].boot_data.plugin); > +} > + > +void build_image(int ofd) > +{ > + int file_off, header_hdmi_off = 0, header_image_off; > + int hdmi_fd, ap_fd, sld_fd; > + uint32_t sld_load_addr = 0; > + uint32_t csf_off, sld_csf_off = 0; > + int ret; > + struct stat sbuf; > + > + if (!ap_img) { > + fprintf(stderr, "No LOADER image specificed\n"); > + exit(EXIT_FAILURE); > + } > + > + file_off = 0; > + > + if (signed_hdmi) { > + header_hdmi_off = file_off + ivt_offset; > + > + hdmi_fd = open(signed_hdmi, O_RDONLY | O_BINARY); > + if (hdmi_fd < 0) { > + fprintf(stderr, "%s: Can't open: %s\n", > + signed_hdmi, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + if (fstat(hdmi_fd, &sbuf) < 0) { > + fprintf(stderr, "%s: Can't stat: %s\n", > + signed_hdmi, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + close(hdmi_fd); > + > + /* > + * Aligned to 104KB = 92KB FW image + 0x8000 > + * (IVT and alignment) + 0x4000 (second IVT + CSF) > + */ > + file_off += ALIGN(sbuf.st_size, > + HDMI_FW_SIZE + 0x2000 + 0x1000); > + } > + > + header_image_off = file_off + ivt_offset; > + > + ap_fd = open(ap_img, O_RDONLY | O_BINARY); > + if (ap_fd < 0) { > + fprintf(stderr, "%s: Can't open: %s\n", > + ap_img, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + if (fstat(ap_fd, &sbuf) < 0) { > + fprintf(stderr, "%s: Can't stat: %s\n", > + ap_img, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + close(ap_fd); > + > + imx_header[IMAGE_IVT_ID].fhdr.header.tag = IVT_HEADER_TAG; /* 0xD1 */ > + imx_header[IMAGE_IVT_ID].fhdr.header.length = > + cpu_to_be16(sizeof(flash_header_v2_t)); > + imx_header[IMAGE_IVT_ID].fhdr.header.version = IVT_VERSION_V3; /* 0x41 */ > + imx_header[IMAGE_IVT_ID].fhdr.entry = ap_start_addr; > + imx_header[IMAGE_IVT_ID].fhdr.self = ap_start_addr - > + sizeof(imx_header_v3_t); > + imx_header[IMAGE_IVT_ID].fhdr.dcd_ptr = 0; > + imx_header[IMAGE_IVT_ID].fhdr.boot_data_ptr = > + imx_header[IMAGE_IVT_ID].fhdr.self + > + offsetof(imx_header_v3_t, boot_data); > + imx_header[IMAGE_IVT_ID].boot_data.start = > + imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset; > + imx_header[IMAGE_IVT_ID].boot_data.size = > + ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset, > + sector_size); > + > + image_off = header_image_off + sizeof(imx_header_v3_t); > + file_off += imx_header[IMAGE_IVT_ID].boot_data.size; > + > + imx_header[IMAGE_IVT_ID].boot_data.plugin = 0; > + imx_header[IMAGE_IVT_ID].fhdr.csf = > + imx_header[IMAGE_IVT_ID].boot_data.start + > + imx_header[IMAGE_IVT_ID].boot_data.size; > + > + imx_header[IMAGE_IVT_ID].boot_data.size += CSF_SIZE; /* 8K region dummy CSF */ > + > + csf_off = file_off; > + file_off += CSF_SIZE; > + > + /* Second boot loader image */ > + if (sld_img) { > + if (!using_fit) { > + fprintf(stderr, "Not support no fit\n"); > + exit(EXIT_FAILURE); > + } else { > + sld_header_off = sld_src_off - rom_image_offset; > + /* > + * Record the second bootloader relative offset in > + * image's IVT reserved1 > + */ > + imx_header[IMAGE_IVT_ID].fhdr.reserved1 = > + sld_header_off - header_image_off; > + sld_fd = open(sld_img, O_RDONLY | O_BINARY); > + if (sld_fd < 0) { > + fprintf(stderr, "%s: Can't open: %s\n", > + sld_img, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + if (fstat(sld_fd, &sbuf) < 0) { > + fprintf(stderr, "%s: Can't stat: %s\n", > + sld_img, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + > + close(sld_fd); > + > + file_off = sld_header_off; > + file_off += sbuf.st_size + sizeof(image_header_t); > + } > + } > + > + if (signed_hdmi) { > + header_hdmi_off -= ivt_offset; > + ret = lseek(ofd, header_hdmi_off, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek ofd fail for hdmi\n"); > + exit(EXIT_FAILURE); > + } > + > + /* The signed HDMI FW has 0x400 IVT offset, need remove it */ > + copy_file(ofd, signed_hdmi, 0, header_hdmi_off, 0x400); > + } > + > + /* Main Image */ > + header_image_off -= ivt_offset; > + image_off -= ivt_offset; > + ret = lseek(ofd, header_image_off, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek ofd fail\n"); > + exit(EXIT_FAILURE); > + } > + > + /* Write image header */ > + if (write(ofd, &imx_header[IMAGE_IVT_ID], sizeof(imx_header_v3_t)) != > + sizeof(imx_header_v3_t)) { > + fprintf(stderr, "error writing image hdr\n"); > + exit(1); > + } > + > + copy_file(ofd, ap_img, 0, image_off, 0); > + > + csf_off -= ivt_offset; > + fill_zero(ofd, CSF_SIZE, csf_off); > + > + if (sld_img) { > + sld_header_off -= ivt_offset; > + ret = lseek(ofd, sld_header_off, SEEK_SET); > + if (ret < 0) { > + fprintf(stderr, "lseek ofd fail for sld_img\n"); > + exit(EXIT_FAILURE); > + } > + > + /* Write image header */ > + if (!using_fit) { > + /* TODO */ > + } else { > + copy_file(ofd, sld_img, 0, sld_header_off, 0); > + sld_csf_off = > + generate_ivt_for_fit(ofd, sld_header_off, > + sld_start_addr, > + &sld_load_addr) + 0x20; > + } > + } > + > + if (!signed_hdmi) > + dump_header_v2(imx_header, 0); > + dump_header_v2(imx_header, 1); > + > + fprintf(stdout, "========= OFFSET dump ========="); > + if (signed_hdmi) { > + fprintf(stdout, "\nSIGNED HDMI FW:\n"); > + fprintf(stdout, " header_hdmi_off \t0x%x\n", > + header_hdmi_off); > + } > + > + fprintf(stdout, "\nLoader IMAGE:\n"); > + fprintf(stdout, " header_image_off \t0x%x\n image_off \t\t0x%x\n csf_off \t\t0x%x\n", > + header_image_off, image_off, csf_off); > + fprintf(stdout, " spl hab block: \t0x%x 0x%x 0x%x\n", > + imx_header[IMAGE_IVT_ID].fhdr.self, header_image_off, > + csf_off - header_image_off); > + > + fprintf(stdout, "\nSecond Loader IMAGE:\n"); > + fprintf(stdout, " sld_header_off \t0x%x\n", > + sld_header_off); > + fprintf(stdout, " sld_csf_off \t\t0x%x\n", > + sld_csf_off); > + fprintf(stdout, " sld hab block: \t0x%x 0x%x 0x%x\n", > + sld_load_addr, sld_header_off, sld_csf_off - sld_header_off); > +} > + > +int imx8mimage_copy_image(int outfd, struct image_tool_params *mparams) > +{ > + /* > + * SECO FW is a container image, this is to calculate the > + * 2nd container offset. > + */ > + fprintf(stdout, "parsing %s\n", mparams->imagename); > + parse_cfg_file(mparams->imagename); > + > + build_image(outfd); > + > + return 0; > +} > + > +/* > + * imx8mimage parameters > + */ > +U_BOOT_IMAGE_TYPE( > + imx8mimage, > + "NXP i.MX8M Boot Image support", > + 0, > + NULL, > + imx8mimage_check_params, > + NULL, > + imx8mimage_print_header, > + imx8mimage_set_header, > + NULL, > + imx8mimage_check_image_types, > + NULL, > + NULL > +); > diff --git a/tools/mkimage.c b/tools/mkimage.c > index 38805f0c92..ea5ed542ab 100644 > --- a/tools/mkimage.c > +++ b/tools/mkimage.c > @@ -530,6 +530,13 @@ int main(int argc, char **argv) > ret = imx8image_copy_image(ifd, ¶ms); > if (ret) > return ret; > + } else if (params.type == IH_TYPE_IMX8MIMAGE) { > + /* i.MX8M has special Image format */ > + int ret; > + > + ret = imx8mimage_copy_image(ifd, ¶ms); > + if (ret) > + return ret; > } else { > copy_file(ifd, params.datafile, pad_len); > } > -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support 2018-12-14 13:25 ` Stefano Babic @ 2018-12-15 3:09 ` Peng Fan 0 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-12-15 3:09 UTC (permalink / raw) To: u-boot Hi Stefano > -----Original Message----- > From: Stefano Babic [mailto:sbabic at denx.de] > Sent: 2018年12月14日 21:26 > To: Peng Fan <peng.fan@nxp.com>; sbabic at denx.de; Fabio Estevam > <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH V2 08/15] tools: add i.MX8M image support > > Hi Peng, > > On 20/11/18 11:19, Peng Fan wrote: > > i.MX8M bootable image type is like i.MX6/7, but there is signed HDMI > > firmware image in front of A53 bootable image, which is also has an > > IVT header. > > > > Here we also include fit image to generate a bootable image. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > > > V2: > > None > > > > common/image.c | 1 + > > include/image.h | 1 + > > include/imximage.h | 17 +- > > tools/Makefile | 1 + > > tools/imagetool.h | 1 + > > tools/imx8mimage.c | 623 > +++++++++++++++++++++++++++++++++++++++++++++++++++++ > > tools/mkimage.c | 7 + > > 7 files changed, 650 insertions(+), 1 deletion(-) create mode 100644 > > tools/imx8mimage.c > > > > diff --git a/common/image.c b/common/image.c index > > 1c3a7720cb..d1cc1d11bb 100644 > > --- a/common/image.c > > +++ b/common/image.c > > @@ -140,6 +140,7 @@ static const table_entry_t uimage_type[] = { > > { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, > > { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot > Image",}, > > { IH_TYPE_IMX8IMAGE, "imx8image", "NXP i.MX8 Boot Image",}, > > + { IH_TYPE_IMX8MIMAGE, "imx8mimage", "NXP i.MX8M Boot > Image",}, > > { IH_TYPE_INVALID, "invalid", "Invalid Image", }, > > { IH_TYPE_MULTI, "multi", "Multi-File Image", }, > > { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP > CH",}, > > diff --git a/include/image.h b/include/image.h index > > 031c355b48..d1e0d6dfbe 100644 > > --- a/include/image.h > > +++ b/include/image.h > > @@ -252,6 +252,7 @@ enum { > > IH_TYPE_KWBIMAGE, /* Kirkwood Boot Image */ > > IH_TYPE_IMXIMAGE, /* Freescale IMXBoot Image */ > > IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */ > > + IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */ > > I applied after moving this at the end of the list, see comment in the structure. > > I send a patch to move IH_TYPE_IMXIMAGE, too, because it breaks > compatibility. Thanks for doing this. I missed to consider the compatibility when did this patch. > > I have applied all imx8m patches, build is fine - I will send my PR now ;-). Not sure you need this https://patchwork.ozlabs.org/patch/1011510/ or not. I saw it still in patchwork. Thanks, Peng. > > Best regards, > Stefano > > > IH_TYPE_UBLIMAGE, /* Davinci UBL Image */ > > IH_TYPE_OMAPIMAGE, /* TI OMAP Config Header Image */ > > IH_TYPE_AISIMAGE, /* TI Davinci AIS Image */ > > diff --git a/include/imximage.h b/include/imximage.h index > > 6f7ca7f5e3..544babb53a 100644 > > --- a/include/imximage.h > > +++ b/include/imximage.h > > @@ -33,6 +33,7 @@ > > #define FLASH_OFFSET_NOR 0x1000 > > #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD > > #define FLASH_OFFSET_QSPI 0x1000 > > +#define FLASH_OFFSET_FLEXSPI 0x1000 > > > > /* Initial Load Region Size */ > > #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF > > @@ -48,6 +49,7 @@ > > /* Command tags and parameters */ > > #define IVT_HEADER_TAG 0xD1 > > #define IVT_VERSION 0x40 > > +#define IVT_VERSION_V3 0x41 > > #define DCD_HEADER_TAG 0xD2 > > #define DCD_VERSION 0x40 > > #define DCD_WRITE_DATA_COMMAND_TAG 0xCC > > @@ -71,6 +73,12 @@ enum imximage_cmd { > > CMD_CHECK_BITS_CLR, > > CMD_CSF, > > CMD_PLUGIN, > > + /* Follwoing on i.MX8MQ/MM */ > > + CMD_FIT, > > + CMD_SIGNED_HDMI, > > + CMD_LOADER, > > + CMD_SECOND_LOADER, > > + CMD_DDR_FW, > > }; > > > > enum imximage_fld_types { > > @@ -84,7 +92,8 @@ enum imximage_fld_types { enum > imximage_version { > > IMXIMAGE_VER_INVALID = -1, > > IMXIMAGE_V1 = 1, > > - IMXIMAGE_V2 > > + IMXIMAGE_V2, > > + IMXIMAGE_V3 > > }; > > > > typedef struct { > > @@ -177,6 +186,12 @@ typedef struct { > > } data; > > } imx_header_v2_t; > > > > +typedef struct { > > + flash_header_v2_t fhdr; > > + boot_data_t boot_data; > > + uint32_t padding[5]; > > +} imx_header_v3_t; > > + > > /* The header must be aligned to 4k on MX53 for NAND boot */ struct > > imx_header { > > union { > > diff --git a/tools/Makefile b/tools/Makefile index > > 3c0521f655..e9b4398039 100644 > > --- a/tools/Makefile > > +++ b/tools/Makefile > > @@ -94,6 +94,7 @@ dumpimage-mkimage-objs := aisimage.o \ > > imagetool.o \ > > imximage.o \ > > imx8image.o \ > > + imx8mimage.o \ > > kwbimage.o \ > > lib/md5.o \ > > lpc32xximage.o \ > > diff --git a/tools/imagetool.h b/tools/imagetool.h index > > 3fcfb4468d..71471420f9 100644 > > --- a/tools/imagetool.h > > +++ b/tools/imagetool.h > > @@ -233,6 +233,7 @@ time_t imagetool_get_source_date( void > > pbl_load_uboot(int fd, struct image_tool_params *mparams); int > > zynqmpbif_copy_image(int fd, struct image_tool_params *mparams); int > > imx8image_copy_image(int fd, struct image_tool_params *mparams); > > +int imx8mimage_copy_image(int fd, struct image_tool_params > *mparams); > > > > #define ___cat(a, b) a ## b > > #define __cat(a, b) ___cat(a, b) > > diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c new file mode > > 100644 index 0000000000..50a256cbac > > --- /dev/null > > +++ b/tools/imx8mimage.c > > @@ -0,0 +1,623 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2018 NXP > > + * > > + * Peng Fan <peng.fan@nxp.com> > > + */ > > + > > + > > +#include "imagetool.h" > > +#include <image.h> > > +#include "imximage.h" > > +#include "compiler.h" > > + > > +static uint32_t ap_start_addr, sld_start_addr, sld_src_off; static > > +char *ap_img, *sld_img, *signed_hdmi; static imx_header_v3_t > > +imx_header[2]; /* At most there are 3 IVT headers */ static uint32_t > > +rom_image_offset; static uint32_t sector_size = 0x200; static > > +uint32_t image_off; static uint32_t sld_header_off; static uint32_t > > +ivt_offset; static uint32_t using_fit; > > + > > +#define CSF_SIZE 0x2000 > > +#define HDMI_IVT_ID 0 > > +#define IMAGE_IVT_ID 1 > > + > > +#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and > CSF */ > > +#define ALIGN_SIZE 0x1000 > > +#define ALIGN(x,a) __ALIGN_MASK((x), (__typeof__(x))(a) - 1, a) > > +#define __ALIGN_MASK(x,mask,mask2) (((x) + (mask)) / (mask2) * > > +(mask2)) > > + > > +static uint32_t get_cfg_value(char *token, char *name, int linenr) { > > + char *endptr; > > + uint32_t value; > > + > > + errno = 0; > > + value = strtoul(token, &endptr, 16); > > + if (errno || token == endptr) { > > + fprintf(stderr, "Error: %s[%d] - Invalid hex data(%s)\n", > > + name, linenr, token); > > + exit(EXIT_FAILURE); > > + } > > + return value; > > +} > > + > > +int imx8mimage_check_params(struct image_tool_params *params) { > > + return 0; > > +} > > + > > +static void imx8mimage_set_header(void *ptr, struct stat *sbuf, int ifd, > > + struct image_tool_params *params) { } > > + > > +static void imx8mimage_print_header(const void *ptr) { } > > + > > +static int imx8mimage_check_image_types(uint8_t type) { > > + return (type == IH_TYPE_IMX8MIMAGE) ? EXIT_SUCCESS : > EXIT_FAILURE; } > > + > > +static table_entry_t imx8mimage_cmds[] = { > > + {CMD_BOOT_FROM, "BOOT_FROM", "boot > command", }, > > + {CMD_FIT, "FIT", "fit image", > }, > > + {CMD_SIGNED_HDMI, "SIGNED_HDMI", "signed > hdmi image", }, > > + {CMD_LOADER, "LOADER", "loader > image", }, > > + {CMD_SECOND_LOADER, "SECOND_LOADER", "2nd > loader image", }, > > + {CMD_DDR_FW, "DDR_FW", "ddr > firmware", }, > > + {-1, "", "", > }, > > +}; > > + > > +static table_entry_t imx8mimage_ivt_offset[] = { > > + {0x400, "sd", "sd/emmc",}, > > + {0x400, "emmc_fastboot", "emmc fastboot",}, > > + {0x1000, "fspi", "flexspi", }, > > + {-1, "", "Invalid", }, > > +}; > > + > > +static void parse_cfg_cmd(int32_t cmd, char *token, char *name, int > > +lineno) { > > + switch (cmd) { > > + case CMD_BOOT_FROM: > > + ivt_offset = get_table_entry_id(imx8mimage_ivt_offset, > > + "imx8mimage ivt offset", > > + token); > > + if (!strncmp(token, "sd", 2)) > > + rom_image_offset = 0x8000; > > + break; > > + case CMD_LOADER: > > + ap_img = token; > > + break; > > + case CMD_SECOND_LOADER: > > + sld_img = token; > > + break; > > + case CMD_SIGNED_HDMI: > > + signed_hdmi = token; > > + case CMD_FIT: > > + using_fit = 1; > > + break; > > + case CMD_DDR_FW: > > + /* Do nothing */ > > + break; > > + } > > +} > > + > > +static void parse_cfg_fld(int32_t *cmd, char *token, > > + char *name, int lineno, int fld) { > > + switch (fld) { > > + case CFG_COMMAND: > > + *cmd = get_table_entry_id(imx8mimage_cmds, > > + "imx8mimage commands", token); > > + if (*cmd < 0) { > > + fprintf(stderr, "Error: %s[%d] - Invalid command" "(%s)\n", > > + name, lineno, token); > > + exit(EXIT_FAILURE); > > + } > > + break; > > + case CFG_REG_SIZE: > > + parse_cfg_cmd(*cmd, token, name, lineno); > > + break; > > + case CFG_REG_ADDRESS: > > + switch (*cmd) { > > + case CMD_LOADER: > > + ap_start_addr = get_cfg_value(token, name, lineno); > > + break; > > + case CMD_SECOND_LOADER: > > + sld_start_addr = get_cfg_value(token, name, lineno); > > + break; > > + } > > + break; > > + case CFG_REG_VALUE: > > + switch (*cmd) { > > + case CMD_SECOND_LOADER: > > + sld_src_off = get_cfg_value(token, name, lineno); > > + break; > > + } > > + default: > > + break; > > + } > > +} > > + > > +static uint32_t parse_cfg_file(char *name) { > > + FILE *fd = NULL; > > + char *line = NULL; > > + char *token, *saveptr1, *saveptr2; > > + int lineno = 0; > > + int fld; > > + size_t len; > > + int32_t cmd; > > + > > + fd = fopen(name, "r"); > > + if (fd == 0) { > > + fprintf(stderr, "Error: %s - Can't open cfg file\n", name); > > + exit(EXIT_FAILURE); > > + } > > + > > + /* > > + * Very simple parsing, line starting with # are comments > > + * and are dropped > > + */ > > + while ((getline(&line, &len, fd)) > 0) { > > + lineno++; > > + > > + token = strtok_r(line, "\r\n", &saveptr1); > > + if (!token) > > + continue; > > + > > + /* Check inside the single line */ > > + for (fld = CFG_COMMAND, cmd = CFG_INVALID, > > + line = token; ; line = NULL, fld++) { > > + token = strtok_r(line, " \t", &saveptr2); > > + if (!token) > > + break; > > + > > + /* Drop all text starting with '#' as comments */ > > + if (token[0] == '#') > > + break; > > + > > + parse_cfg_fld(&cmd, token, name, lineno, fld); > > + } > > + } > > + > > + return 0; > > +} > > + > > +static void fill_zero(int ifd, int size, int offset) { > > + int fill_size; > > + uint8_t zeros[4096]; > > + int ret; > > + > > + memset(zeros, 0, sizeof(zeros)); > > + > > + ret = lseek(ifd, offset, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "%s seek: %s\n", __func__, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + while (size) { > > + if (size > 4096) > > + fill_size = 4096; > > + else > > + fill_size = size; > > + > > + if (write(ifd, (char *)&zeros, fill_size) != fill_size) { > > + fprintf(stderr, "Write error: %s\n", > > + strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + size -= fill_size; > > + }; > > +} > > + > > +static void copy_file(int ifd, const char *datafile, int pad, int offset, > > + int datafile_offset) > > +{ > > + int dfd; > > + struct stat sbuf; > > + unsigned char *ptr; > > + int tail; > > + int zero = 0; > > + uint8_t zeros[4096]; > > + int size, ret; > > + > > + memset(zeros, 0, sizeof(zeros)); > > + > > + dfd = open(datafile, O_RDONLY | O_BINARY); > > + if (dfd < 0) { > > + fprintf(stderr, "Can't open %s: %s\n", > > + datafile, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (fstat(dfd, &sbuf) < 0) { > > + fprintf(stderr, "Can't stat %s: %s\n", > > + datafile, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0); > > + if (ptr == MAP_FAILED) { > > + fprintf(stderr, "Can't read %s: %s\n", > > + datafile, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + size = sbuf.st_size - datafile_offset; > > + ret = lseek(ifd, offset, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek ifd fail\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (write(ifd, ptr + datafile_offset, size) != size) { > > + fprintf(stderr, "Write error %s\n", > > + strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + tail = size % 4; > > + pad = pad - size; > > + if (pad == 1 && tail != 0) { > > + if (write(ifd, (char *)&zero, 4 - tail) != 4 - tail) { > > + fprintf(stderr, "Write error on %s\n", > > + strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + } else if (pad > 1) { > > + while (pad > 0) { > > + int todo = sizeof(zeros); > > + > > + if (todo > pad) > > + todo = pad; > > + if (write(ifd, (char *)&zeros, todo) != todo) { > > + fprintf(stderr, "Write error: %s\n", > > + strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + pad -= todo; > > + } > > + } > > + > > + munmap((void *)ptr, sbuf.st_size); > > + close(dfd); > > +} > > + > > +/* Return this IVT offset in the final output file */ static int > > +generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep, > > + uint32_t *fit_load_addr) > > +{ > > + image_header_t image_header; > > + int ret; > > + > > + uint32_t fit_size, load_addr; > > + int align_len = 64 - 1; /* 64 is cacheline size */ > > + > > + ret = lseek(fd, fit_offset, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek fd fail for fit\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (read(fd, (char *)&image_header, sizeof(image_header_t)) != > > + sizeof(image_header_t)) { > > + fprintf(stderr, "generate_ivt_for_fit read failed: %s\n", > > + strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (be32_to_cpu(image_header.ih_magic) != FDT_MAGIC) { > > + fprintf(stderr, "%s error: not a FIT file\n", __func__); > > + exit(EXIT_FAILURE); > > + } > > + > > + fit_size = fdt_totalsize(&image_header); > > + fit_size = (fit_size + 3) & ~3; > > + > > + fit_size = ALIGN(fit_size, ALIGN_SIZE); > > + > > + ret = lseek(fd, fit_offset + fit_size, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek fd fail for fit\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + /* > > + * ep is the u-boot entry. SPL loads the FIT before the u-boot > > + * address. 0x2000 is for CSF_SIZE > > + */ > > + load_addr = (ep - (fit_size + CSF_SIZE) - 512 - align_len) & > > + ~align_len; > > + > > + flash_header_v2_t ivt_header = { { 0xd1, 0x2000, 0x40 }, > > + load_addr, 0, 0, 0, > > + (load_addr + fit_size), > > + (load_addr + fit_size + 0x20), > > + 0 }; > > + > > + if (write(fd, &ivt_header, sizeof(flash_header_v2_t)) != > > + sizeof(flash_header_v2_t)) { > > + fprintf(stderr, "IVT writing error on fit image\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + *fit_load_addr = load_addr; > > + > > + return fit_offset + fit_size; > > +} > > + > > +static void dump_header_v2(imx_header_v3_t *imx_header, int index) { > > + const char *ivt_name[2] = {"HDMI FW", "LOADER IMAGE"}; > > + > > + fprintf(stdout, "========= IVT HEADER [%s] =========\n", > > + ivt_name[index]); > > + fprintf(stdout, "header.tag: \t\t0x%x\n", > > + imx_header[index].fhdr.header.tag); > > + fprintf(stdout, "header.length: \t\t0x%x\n", > > + imx_header[index].fhdr.header.length); > > + fprintf(stdout, "header.version: \t0x%x\n", > > + imx_header[index].fhdr.header.version); > > + fprintf(stdout, "entry: \t\t\t0x%x\n", > > + imx_header[index].fhdr.entry); > > + fprintf(stdout, "reserved1: \t\t0x%x\n", > > + imx_header[index].fhdr.reserved1); > > + fprintf(stdout, "dcd_ptr: \t\t0x%x\n", > > + imx_header[index].fhdr.dcd_ptr); > > + fprintf(stdout, "boot_data_ptr: \t\t0x%x\n", > > + imx_header[index].fhdr.boot_data_ptr); > > + fprintf(stdout, "self: \t\t\t0x%x\n", > > + imx_header[index].fhdr.self); > > + fprintf(stdout, "csf: \t\t\t0x%x\n", > > + imx_header[index].fhdr.csf); > > + fprintf(stdout, "reserved2: \t\t0x%x\n", > > + imx_header[index].fhdr.reserved2); > > + > > + fprintf(stdout, "boot_data.start: \t0x%x\n", > > + imx_header[index].boot_data.start); > > + fprintf(stdout, "boot_data.size: \t0x%x\n", > > + imx_header[index].boot_data.size); > > + fprintf(stdout, "boot_data.plugin: \t0x%x\n", > > + imx_header[index].boot_data.plugin); > > +} > > + > > +void build_image(int ofd) > > +{ > > + int file_off, header_hdmi_off = 0, header_image_off; > > + int hdmi_fd, ap_fd, sld_fd; > > + uint32_t sld_load_addr = 0; > > + uint32_t csf_off, sld_csf_off = 0; > > + int ret; > > + struct stat sbuf; > > + > > + if (!ap_img) { > > + fprintf(stderr, "No LOADER image specificed\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + file_off = 0; > > + > > + if (signed_hdmi) { > > + header_hdmi_off = file_off + ivt_offset; > > + > > + hdmi_fd = open(signed_hdmi, O_RDONLY | O_BINARY); > > + if (hdmi_fd < 0) { > > + fprintf(stderr, "%s: Can't open: %s\n", > > + signed_hdmi, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (fstat(hdmi_fd, &sbuf) < 0) { > > + fprintf(stderr, "%s: Can't stat: %s\n", > > + signed_hdmi, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + close(hdmi_fd); > > + > > + /* > > + * Aligned to 104KB = 92KB FW image + 0x8000 > > + * (IVT and alignment) + 0x4000 (second IVT + CSF) > > + */ > > + file_off += ALIGN(sbuf.st_size, > > + HDMI_FW_SIZE + 0x2000 + 0x1000); > > + } > > + > > + header_image_off = file_off + ivt_offset; > > + > > + ap_fd = open(ap_img, O_RDONLY | O_BINARY); > > + if (ap_fd < 0) { > > + fprintf(stderr, "%s: Can't open: %s\n", > > + ap_img, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + if (fstat(ap_fd, &sbuf) < 0) { > > + fprintf(stderr, "%s: Can't stat: %s\n", > > + ap_img, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + close(ap_fd); > > + > > + imx_header[IMAGE_IVT_ID].fhdr.header.tag = IVT_HEADER_TAG; /* > 0xD1 */ > > + imx_header[IMAGE_IVT_ID].fhdr.header.length = > > + cpu_to_be16(sizeof(flash_header_v2_t)); > > + imx_header[IMAGE_IVT_ID].fhdr.header.version = IVT_VERSION_V3; /* > 0x41 */ > > + imx_header[IMAGE_IVT_ID].fhdr.entry = ap_start_addr; > > + imx_header[IMAGE_IVT_ID].fhdr.self = ap_start_addr - > > + sizeof(imx_header_v3_t); > > + imx_header[IMAGE_IVT_ID].fhdr.dcd_ptr = 0; > > + imx_header[IMAGE_IVT_ID].fhdr.boot_data_ptr = > > + imx_header[IMAGE_IVT_ID].fhdr.self + > > + offsetof(imx_header_v3_t, boot_data); > > + imx_header[IMAGE_IVT_ID].boot_data.start = > > + imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset; > > + imx_header[IMAGE_IVT_ID].boot_data.size = > > + ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset, > > + sector_size); > > + > > + image_off = header_image_off + sizeof(imx_header_v3_t); > > + file_off += imx_header[IMAGE_IVT_ID].boot_data.size; > > + > > + imx_header[IMAGE_IVT_ID].boot_data.plugin = 0; > > + imx_header[IMAGE_IVT_ID].fhdr.csf = > > + imx_header[IMAGE_IVT_ID].boot_data.start + > > + imx_header[IMAGE_IVT_ID].boot_data.size; > > + > > + imx_header[IMAGE_IVT_ID].boot_data.size += CSF_SIZE; /* 8K region > > +dummy CSF */ > > + > > + csf_off = file_off; > > + file_off += CSF_SIZE; > > + > > + /* Second boot loader image */ > > + if (sld_img) { > > + if (!using_fit) { > > + fprintf(stderr, "Not support no fit\n"); > > + exit(EXIT_FAILURE); > > + } else { > > + sld_header_off = sld_src_off - rom_image_offset; > > + /* > > + * Record the second bootloader relative offset in > > + * image's IVT reserved1 > > + */ > > + imx_header[IMAGE_IVT_ID].fhdr.reserved1 = > > + sld_header_off - header_image_off; > > + sld_fd = open(sld_img, O_RDONLY | O_BINARY); > > + if (sld_fd < 0) { > > + fprintf(stderr, "%s: Can't open: %s\n", > > + sld_img, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + if (fstat(sld_fd, &sbuf) < 0) { > > + fprintf(stderr, "%s: Can't stat: %s\n", > > + sld_img, strerror(errno)); > > + exit(EXIT_FAILURE); > > + } > > + > > + close(sld_fd); > > + > > + file_off = sld_header_off; > > + file_off += sbuf.st_size + sizeof(image_header_t); > > + } > > + } > > + > > + if (signed_hdmi) { > > + header_hdmi_off -= ivt_offset; > > + ret = lseek(ofd, header_hdmi_off, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek ofd fail for hdmi\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + /* The signed HDMI FW has 0x400 IVT offset, need remove it */ > > + copy_file(ofd, signed_hdmi, 0, header_hdmi_off, 0x400); > > + } > > + > > + /* Main Image */ > > + header_image_off -= ivt_offset; > > + image_off -= ivt_offset; > > + ret = lseek(ofd, header_image_off, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek ofd fail\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + /* Write image header */ > > + if (write(ofd, &imx_header[IMAGE_IVT_ID], sizeof(imx_header_v3_t)) != > > + sizeof(imx_header_v3_t)) { > > + fprintf(stderr, "error writing image hdr\n"); > > + exit(1); > > + } > > + > > + copy_file(ofd, ap_img, 0, image_off, 0); > > + > > + csf_off -= ivt_offset; > > + fill_zero(ofd, CSF_SIZE, csf_off); > > + > > + if (sld_img) { > > + sld_header_off -= ivt_offset; > > + ret = lseek(ofd, sld_header_off, SEEK_SET); > > + if (ret < 0) { > > + fprintf(stderr, "lseek ofd fail for sld_img\n"); > > + exit(EXIT_FAILURE); > > + } > > + > > + /* Write image header */ > > + if (!using_fit) { > > + /* TODO */ > > + } else { > > + copy_file(ofd, sld_img, 0, sld_header_off, 0); > > + sld_csf_off = > > + generate_ivt_for_fit(ofd, sld_header_off, > > + sld_start_addr, > > + &sld_load_addr) + 0x20; > > + } > > + } > > + > > + if (!signed_hdmi) > > + dump_header_v2(imx_header, 0); > > + dump_header_v2(imx_header, 1); > > + > > + fprintf(stdout, "========= OFFSET dump ========="); > > + if (signed_hdmi) { > > + fprintf(stdout, "\nSIGNED HDMI FW:\n"); > > + fprintf(stdout, " header_hdmi_off \t0x%x\n", > > + header_hdmi_off); > > + } > > + > > + fprintf(stdout, "\nLoader IMAGE:\n"); > > + fprintf(stdout, " header_image_off \t0x%x\n image_off \t\t0x%x\n > csf_off \t\t0x%x\n", > > + header_image_off, image_off, csf_off); > > + fprintf(stdout, " spl hab block: \t0x%x 0x%x 0x%x\n", > > + imx_header[IMAGE_IVT_ID].fhdr.self, header_image_off, > > + csf_off - header_image_off); > > + > > + fprintf(stdout, "\nSecond Loader IMAGE:\n"); > > + fprintf(stdout, " sld_header_off \t0x%x\n", > > + sld_header_off); > > + fprintf(stdout, " sld_csf_off \t\t0x%x\n", > > + sld_csf_off); > > + fprintf(stdout, " sld hab block: \t0x%x 0x%x 0x%x\n", > > + sld_load_addr, sld_header_off, sld_csf_off - sld_header_off); } > > + > > +int imx8mimage_copy_image(int outfd, struct image_tool_params > > +*mparams) { > > + /* > > + * SECO FW is a container image, this is to calculate the > > + * 2nd container offset. > > + */ > > + fprintf(stdout, "parsing %s\n", mparams->imagename); > > + parse_cfg_file(mparams->imagename); > > + > > + build_image(outfd); > > + > > + return 0; > > +} > > + > > +/* > > + * imx8mimage parameters > > + */ > > +U_BOOT_IMAGE_TYPE( > > + imx8mimage, > > + "NXP i.MX8M Boot Image support", > > + 0, > > + NULL, > > + imx8mimage_check_params, > > + NULL, > > + imx8mimage_print_header, > > + imx8mimage_set_header, > > + NULL, > > + imx8mimage_check_image_types, > > + NULL, > > + NULL > > +); > > diff --git a/tools/mkimage.c b/tools/mkimage.c index > > 38805f0c92..ea5ed542ab 100644 > > --- a/tools/mkimage.c > > +++ b/tools/mkimage.c > > @@ -530,6 +530,13 @@ int main(int argc, char **argv) > > ret = imx8image_copy_image(ifd, ¶ms); > > if (ret) > > return ret; > > + } else if (params.type == IH_TYPE_IMX8MIMAGE) { > > + /* i.MX8M has special Image format */ > > + int ret; > > + > > + ret = imx8mimage_copy_image(ifd, ¶ms); > > + if (ret) > > + return ret; > > } else { > > copy_file(ifd, params.datafile, pad_len); > > } > > > > > -- > ============================================================== > ======= > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de > ============================================================== > ======= ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 09/15] imx: imx8m: introduce script to generate fit image 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (6 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 10/15] imx: imx8m: introduce imximage cfg file Peng Fan ` (5 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Introduce script to generate fit image for i.MX8M Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: replace bl31.bin with $BL31 replace bl32.bin with $BL32 arch/arm/mach-imx/mkimage_fit_atf.sh | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100755 arch/arm/mach-imx/mkimage_fit_atf.sh diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh new file mode 100755 index 0000000000..77f7143263 --- /dev/null +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -0,0 +1,137 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for i.MX8MQ boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" +[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000" +[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000" + +if [ ! -f $BL31 ]; then + echo "ERROR: BL31 file $BL31 NOT found" >&2 + exit 0 +else + echo "$BL31 size: " >&2 + ls -lct $BL31 | awk '{print $5}' >&2 +fi + +BL32="tee.bin" + +if [ ! -f $BL32 ]; then + BL32=/dev/null +else + echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2 + echo "$BL32 size: " >&2 + ls -lct $BL32 | awk '{print $5}' >&2 +fi + +BL33="u-boot-nodtb.bin" + +if [ ! -f $BL33 ]; then + echo "ERROR: $BL33 file NOT found" >&2 + exit 0 +else + echo "u-boot-nodtb.bin size: " >&2 + ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2 +fi + +for dtname in $* +do + echo "$dtname size: " >&2 + ls -lct $dtname | awk '{print $5}' >&2 +done + + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("$BL33"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x40200000>; + }; + atf at 1 { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$ATF_LOAD_ADDR>; + entry = <$ATF_LOAD_ADDR>; + }; +__HEADER_EOF + +if [ -f $BL32 ]; then +cat << __HEADER_EOF + tee@1 { + description = "TEE firmware"; + data = /incbin/("$BL32"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <$TEE_LOAD_ADDR>; + entry = <$TEE_LOAD_ADDR>; + }; +__HEADER_EOF +fi + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config at 1"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $* +do +if [ -f $BL32 ]; then +cat << __CONF_SECTION_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf at 1", "tee at 1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION_EOF +else +cat << __CONF_SECTION1_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot at 1"; + loadables = "atf@1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION1_EOF +fi +cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 10/15] imx: imx8m: introduce imximage cfg file 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (7 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 09/15] imx: imx8m: introduce script to generate fit image Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 11/15] imx: imx8mq: build flash.bin Peng Fan ` (4 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot imximage.cfg will be used to generate the flash.bin Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None arch/arm/mach-imx/imx8m/imximage.cfg | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/arm/mach-imx/imx8m/imximage.cfg diff --git a/arch/arm/mach-imx/imx8m/imximage.cfg b/arch/arm/mach-imx/imx8m/imximage.cfg new file mode 100644 index 0000000000..714b24273b --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage.cfg @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +SIGNED_HDMI signed_hdmi_imx8m.bin +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 11/15] imx: imx8mq: build flash.bin 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (8 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 10/15] imx: imx8m: introduce imximage cfg file Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 12/15] imx: imx8m: not build bootaux when building SPL Peng Fan ` (3 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Build flash.bin for i.MX8MQ, it will include signed hdmi firmware, spl, ddr firmware, fit image(bl31.bin, u-boot-nodtb.bin, dtb). Burn it to 33KB offset of SD card. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: cleanup to let script to generate spl ddr bin Makefile | 5 +++++ arch/arm/mach-imx/Makefile | 25 +++++++++++++++++++++++++ tools/imx8m_image.sh | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100755 tools/imx8m_image.sh diff --git a/Makefile b/Makefile index ee97601ec3..ad0b139955 100644 --- a/Makefile +++ b/Makefile @@ -1169,6 +1169,11 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +ifeq ($(CONFIG_ARCH_IMX8M), y) +flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE + $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +endif + u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 34e380e0b3..6351abb185 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -105,6 +105,10 @@ ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) +else ifeq ($(CONFIG_ARCH_IMX8M), y) +IMAGE_TYPE := imx8mimage +IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh +DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi) else IMAGE_TYPE := imximage DEPFILE_EXISTS := 0 @@ -129,6 +133,26 @@ ifeq ($(DEPFILE_EXISTS),0) endif endif +ifdef CONFIG_ARM64 +ifeq ($(CONFIG_ARCH_IMX8M), y) +SPL: + +MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \ + -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) +flash.bin: MKIMAGEOUTPUT = flash.log + +spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE +ifeq ($(DEPFILE_EXISTS),0) + $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1 +endif + +flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE +ifeq ($(DEPFILE_EXISTS),0) + $(call if_changed,mkimage) +endif +endif + +else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE) SPL: MKIMAGEOUTPUT = SPL.log @@ -160,6 +184,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \ spl/u-boot-nand-spl.imx: SPL FORCE $(call if_changed,u-boot-nand-spl_imx) +endif targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) diff --git a/tools/imx8m_image.sh b/tools/imx8m_image.sh new file mode 100755 index 0000000000..6346fb64d8 --- /dev/null +++ b/tools/imx8m_image.sh @@ -0,0 +1,43 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to check whether the file exists in imximage.cfg for i.MX8M +# + +file=$1 + +post_process=$2 + +blobs=`awk '/^SIGNED_HDMI/ {print $2} /^LOADER/ {print $2} /^SECOND_LOADER/ {print $2} /^DDR_FW/ {print $2}' $file` +for f in $blobs; do + tmp=$srctree/$f + + if [ $f == "spl/u-boot-spl-ddr.bin" ] || [ $f == "u-boot.itb" ]; then + continue + fi + + if [ -f $f ]; then + continue + fi + + if [ ! -f $tmp ]; then + echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2 + exit 1 + fi + + sed -in "s;$f;$tmp;" $file +done + +if [ $post_process == 1 ]; then + if [ -f $srctree/lpddr4_pmu_train_1d_imem.bin ]; then + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_1d_imem_pad.bin + objcopy -I binary -O binary --pad-to 0x4000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_dmem_pad.bin + objcopy -I binary -O binary --pad-to 0x8000 --gap-fill=0x0 $srctree/lpddr4_pmu_train_2d_imem.bin lpddr4_pmu_train_2d_imem_pad.bin + cat lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin > lpddr4_pmu_train_1d_fw.bin + cat lpddr4_pmu_train_2d_imem_pad.bin $srctree/lpddr4_pmu_train_2d_dmem.bin > lpddr4_pmu_train_2d_fw.bin + cat spl/u-boot-spl.bin lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin > spl/u-boot-spl-ddr.bin + rm -f lpddr4_pmu_train_1d_fw.bin lpddr4_pmu_train_2d_fw.bin lpddr4_pmu_train_1d_imem_pad.bin lpddr4_pmu_train_1d_dmem_pad.bin lpddr4_pmu_train_2d_imem_pad.bin + fi +fi + +exit 0 -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 12/15] imx: imx8m: not build bootaux when building SPL 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (9 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 11/15] imx: imx8mq: build flash.bin Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 13/15] imx: imx8m: add lpddr4 header file Peng Fan ` (2 subsequent siblings) 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot No need to build bootaux in SPL stage Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: None arch/arm/mach-imx/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 6351abb185..d236e40510 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,7 +10,9 @@ obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),imx8m)) +ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 13/15] imx: imx8m: add lpddr4 header file 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (10 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 12/15] imx: imx8m: not build bootaux when building SPL Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M Peng Fan 2018-11-20 10:20 ` [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support Peng Fan 13 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Introduce lpddr4 header file Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: Update MR22 arch/arm/include/asm/arch-imx8m/lpddr4_define.h | 97 +++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8m/lpddr4_define.h diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h new file mode 100644 index 0000000000..caf5bafb6d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LPDDR4_DEFINE_H_ +#define __LPDDR4_DEFINE_H_ + +#define LPDDR4_DVFS_DBI +#define DDR_ONE_RANK +/* #define LPDDR4_DBI_ON */ +#define DFI_BUG_WR +#define M845S_4GBx2 +#define PRETRAIN + +/* DRAM MR setting */ +#ifdef LPDDR4_DBI_ON +#define LPDDR4_MR3 0xf1 +#define LPDDR4_PHY_DMIPinPresent 0x1 +#else +#define LPDDR4_MR3 0x31 +#define LPDDR4_PHY_DMIPinPresent 0x0 +#endif + +#ifdef DDR_ONE_RANK +#define LPDDR4_CS 0x1 +#else +#define LPDDR4_CS 0x3 +#endif + +/* PHY training feature */ +#define LPDDR4_HDT_CTL_2D 0xC8 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 +#define LPDDR4_HDT_CTL_400_1D 0xC8 +#define LPDDR4_HDT_CTL_100_1D 0xC8 + +/* 400/100 training seq */ +#define LPDDR4_TRAIN_SEQ_P2 0x121f +#define LPDDR4_TRAIN_SEQ_P1 0x121f +#define LPDDR4_TRAIN_SEQ_P0 0x121f +#define LPDDR4_TRAIN_SEQ_100 0x121f +#define LPDDR4_TRAIN_SEQ_400 0x121f + +/* 2D share & weight */ +#define LPDDR4_2D_WEIGHT 0x1f7f +#define LPDDR4_2D_SHARE 1 +#define LPDDR4_CATRAIN_3200_1d 0 +#define LPDDR4_CATRAIN_400 0 +#define LPDDR4_CATRAIN_100 0 +#define LPDDR4_CATRAIN_3200_2d 0 + +/* MRS parameter */ +/* for LPDDR4 Rtt */ +#define LPDDR4_RTT40 6 +#define LPDDR4_RTT48 5 +#define LPDDR4_RTT60 4 +#define LPDDR4_RTT80 3 +#define LPDDR4_RTT120 2 +#define LPDDR4_RTT240 1 +#define LPDDR4_RTT_DIS 0 + +/* for LPDDR4 Ron */ +#define LPDDR4_RON34 7 +#define LPDDR4_RON40 6 +#define LPDDR4_RON48 5 +#define LPDDR4_RON60 4 +#define LPDDR4_RON80 3 + +#define LPDDR4_PHY_ADDR_RON60 0x1 +#define LPDDR4_PHY_ADDR_RON40 0x3 +#define LPDDR4_PHY_ADDR_RON30 0x7 +#define LPDDR4_PHY_ADDR_RON24 0xf +#define LPDDR4_PHY_ADDR_RON20 0x1f + +/* for read channel */ +#define LPDDR4_RON LPDDR4_RON40 +#define LPDDR4_PHY_RTT 30 +#define LPDDR4_PHY_VREF_VALUE 17 + +/* for write channel */ +#define LPDDR4_PHY_RON 30 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40 +#define LPDDR4_RTT_DQ LPDDR4_RTT40 +#define LPDDR4_RTT_CA LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 +#define LPDDR4_VREF_VALUE_CA ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6) | (0xd)) +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6) | (0xd)) +#define LPDDR4_MR22_RANK0 ((0 << 5) | (1 << 4) | (0 << 3) | \ + (LPDDR4_RTT40)) +#define LPDDR4_MR22_RANK1 ((1 << 5) | (1 << 4) | (1 << 3) | \ + (LPDDR4_RTT40)) + +#define LPDDR4_MR3_PU_CAL 1 + +#endif /* __LPDDR4_DEFINE_H__ */ -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (11 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 13/15] imx: imx8m: add lpddr4 header file Peng Fan @ 2018-11-20 10:19 ` Peng Fan 2018-11-20 17:47 ` Troy Kisky 2018-11-20 10:20 ` [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support Peng Fan 13 siblings, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:19 UTC (permalink / raw) To: u-boot Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: Move ddr phy csr to ddr driver Drop some redundant code. arch/arm/include/asm/arch-imx8m/ddr.h | 573 ++++++++++++++++++++++++++ drivers/Makefile | 1 + drivers/ddr/Kconfig | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8m/Kconfig | 22 + drivers/ddr/imx/imx8m/Makefile | 11 + drivers/ddr/imx/imx8m/ddr4_init.c | 113 ++++++ drivers/ddr/imx/imx8m/ddrphy_csr.c | 732 ++++++++++++++++++++++++++++++++++ drivers/ddr/imx/imx8m/ddrphy_train.c | 86 ++++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 186 +++++++++ drivers/ddr/imx/imx8m/helper.c | 170 ++++++++ drivers/ddr/imx/imx8m/lpddr4_init.c | 188 +++++++++ 12 files changed, 2084 insertions(+) create mode 100644 drivers/ddr/imx/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Kconfig create mode 100644 drivers/ddr/imx/imx8m/Makefile create mode 100644 drivers/ddr/imx/imx8m/ddr4_init.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_csr.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_train.c create mode 100644 drivers/ddr/imx/imx8m/ddrphy_utils.c create mode 100644 drivers/ddr/imx/imx8m/helper.c create mode 100644 drivers/ddr/imx/imx8m/lpddr4_init.c diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 1a5cbabdaf..020f814f44 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -6,6 +6,10 @@ #ifndef __ASM_ARCH_IMX8M_DDR_H #define __ASM_ARCH_IMX8M_DDR_H +#include <asm/io.h> +#include <asm/types.h> +#include <asm/arch/ddr.h> + #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR_0 0x3f400000 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) @@ -352,4 +356,573 @@ enum msg_response { TRAIN_FAIL = 0xff, }; +#define DDRC_MSTR_0 0x3d400000 +#define DDRC_STAT_0 0x3d400004 +#define DDRC_MSTR1_0 0x3d400008 +#define DDRC_MRCTRL0_0 0x3d400010 +#define DDRC_MRCTRL1_0 0x3d400014 +#define DDRC_MRSTAT_0 0x3d400018 +#define DDRC_MRCTRL2_0 0x3d40001c +#define DDRC_DERATEEN_0 0x3d400020 +#define DDRC_DERATEINT_0 0x3d400024 +#define DDRC_MSTR2_0 0x3d400028 +#define DDRC_PWRCTL_0 0x3d400030 +#define DDRC_PWRTMG_0 0x3d400034 +#define DDRC_HWLPCTL_0 0x3d400038 +#define DDRC_HWFFCCTL_0 0x3d40003c +#define DDRC_HWFFCSTAT_0 0x3d400040 +#define DDRC_RFSHCTL0_0 0x3d400050 +#define DDRC_RFSHCTL1_0 0x3d400054 +#define DDRC_RFSHCTL2_0 0x3d400058 +#define DDRC_RFSHCTL3_0 0x3d400060 +#define DDRC_RFSHTMG_0 0x3d400064 +#define DDRC_ECCCFG0_0 0x3d400070 +#define DDRC_ECCCFG1_0 0x3d400074 +#define DDRC_ECCSTAT_0 0x3d400078 +#define DDRC_ECCCLR_0 0x3d40007c +#define DDRC_ECCERRCNT_0 0x3d400080 +#define DDRC_ECCCADDR0_0 0x3d400084 +#define DDRC_ECCCADDR1_0 0x3d400088 +#define DDRC_ECCCSYN0_0 0x3d40008c +#define DDRC_ECCCSYN1_0 0x3d400090 +#define DDRC_ECCCSYN2_0 0x3d400094 +#define DDRC_ECCBITMASK0_0 0x3d400098 +#define DDRC_ECCBITMASK1_0 0x3d40009c +#define DDRC_ECCBITMASK2_0 0x3d4000a0 +#define DDRC_ECCUADDR0_0 0x3d4000a4 +#define DDRC_ECCUADDR1_0 0x3d4000a8 +#define DDRC_ECCUSYN0_0 0x3d4000ac +#define DDRC_ECCUSYN1_0 0x3d4000b0 +#define DDRC_ECCUSYN2_0 0x3d4000b4 +#define DDRC_ECCPOISONADDR0_0 0x3d4000b8 +#define DDRC_ECCPOISONADDR1_0 0x3d4000bc +#define DDRC_CRCPARCTL0_0 0x3d4000c0 +#define DDRC_CRCPARCTL1_0 0x3d4000c4 +#define DDRC_CRCPARCTL2_0 0x3d4000c8 +#define DDRC_CRCPARSTAT_0 0x3d4000cc +#define DDRC_INIT0_0 0x3d4000d0 +#define DDRC_INIT1_0 0x3d4000d4 +#define DDRC_INIT2_0 0x3d4000d8 +#define DDRC_INIT3_0 0x3d4000dc +#define DDRC_INIT4_0 0x3d4000e0 +#define DDRC_INIT5_0 0x3d4000e4 +#define DDRC_INIT6_0 0x3d4000e8 +#define DDRC_INIT7_0 0x3d4000ec +#define DDRC_DIMMCTL_0 0x3d4000f0 +#define DDRC_RANKCTL_0 0x3d4000f4 +#define DDRC_DRAMTMG0_0 0x3d400100 +#define DDRC_DRAMTMG1_0 0x3d400104 +#define DDRC_DRAMTMG2_0 0x3d400108 +#define DDRC_DRAMTMG3_0 0x3d40010c +#define DDRC_DRAMTMG4_0 0x3d400110 +#define DDRC_DRAMTMG5_0 0x3d400114 +#define DDRC_DRAMTMG6_0 0x3d400118 +#define DDRC_DRAMTMG7_0 0x3d40011c +#define DDRC_DRAMTMG8_0 0x3d400120 +#define DDRC_DRAMTMG9_0 0x3d400124 +#define DDRC_DRAMTMG10_0 0x3d400128 +#define DDRC_DRAMTMG11_0 0x3d40012c +#define DDRC_DRAMTMG12_0 0x3d400130 +#define DDRC_DRAMTMG13_0 0x3d400134 +#define DDRC_DRAMTMG14_0 0x3d400138 +#define DDRC_DRAMTMG15_0 0x3d40013C +#define DDRC_DRAMTMG16_0 0x3d400140 +#define DDRC_DRAMTMG17_0 0x3d400144 + +#define DDRC_ZQCTL0_0 0x3d400180 +#define DDRC_ZQCTL1_0 0x3d400184 +#define DDRC_ZQCTL2_0 0x3d400188 +#define DDRC_ZQSTAT_0 0x3d40018c +#define DDRC_DFITMG0_0 0x3d400190 +#define DDRC_DFITMG1_0 0x3d400194 +#define DDRC_DFILPCFG0_0 0x3d400198 +#define DDRC_DFILPCFG1_0 0x3d40019c +#define DDRC_DFIUPD0_0 0x3d4001a0 +#define DDRC_DFIUPD1_0 0x3d4001a4 +#define DDRC_DFIUPD2_0 0x3d4001a8 + +#define DDRC_DFIMISC_0 0x3d4001b0 +#define DDRC_DFITMG2_0 0x3d4001b4 +#define DDRC_DFITMG3_0 0x3d4001b8 +#define DDRC_DFISTAT_0 0x3d4001bc + +#define DDRC_DBICTL_0 0x3d4001c0 +#define DDRC_DFIPHYMSTR_0 0x3d4001c4 +#define DDRC_TRAINCTL0_0 0x3d4001d0 +#define DDRC_TRAINCTL1_0 0x3d4001d4 +#define DDRC_TRAINCTL2_0 0x3d4001d8 +#define DDRC_TRAINSTAT_0 0x3d4001dc +#define DDRC_ADDRMAP0_0 0x3d400200 +#define DDRC_ADDRMAP1_0 0x3d400204 +#define DDRC_ADDRMAP2_0 0x3d400208 +#define DDRC_ADDRMAP3_0 0x3d40020c +#define DDRC_ADDRMAP4_0 0x3d400210 +#define DDRC_ADDRMAP5_0 0x3d400214 +#define DDRC_ADDRMAP6_0 0x3d400218 +#define DDRC_ADDRMAP7_0 0x3d40021c +#define DDRC_ADDRMAP8_0 0x3d400220 +#define DDRC_ADDRMAP9_0 0x3d400224 +#define DDRC_ADDRMAP10_0 0x3d400228 +#define DDRC_ADDRMAP11_0 0x3d40022c + +#define DDRC_ODTCFG_0 0x3d400240 +#define DDRC_ODTMAP_0 0x3d400244 +#define DDRC_SCHED_0 0x3d400250 +#define DDRC_SCHED1_0 0x3d400254 +#define DDRC_PERFHPR1_0 0x3d40025c +#define DDRC_PERFLPR1_0 0x3d400264 +#define DDRC_PERFWR1_0 0x3d40026c +#define DDRC_PERFVPR1_0 0x3d400274 + +#define DDRC_PERFVPW1_0 0x3d400278 + +#define DDRC_DQMAP0_0 0x3d400280 +#define DDRC_DQMAP1_0 0x3d400284 +#define DDRC_DQMAP2_0 0x3d400288 +#define DDRC_DQMAP3_0 0x3d40028c +#define DDRC_DQMAP4_0 0x3d400290 +#define DDRC_DQMAP5_0 0x3d400294 +#define DDRC_DBG0_0 0x3d400300 +#define DDRC_DBG1_0 0x3d400304 +#define DDRC_DBGCAM_0 0x3d400308 +#define DDRC_DBGCMD_0 0x3d40030c +#define DDRC_DBGSTAT_0 0x3d400310 + +#define DDRC_SWCTL_0 0x3d400320 +#define DDRC_SWSTAT_0 0x3d400324 +#define DDRC_OCPARCFG0_0 0x3d400330 +#define DDRC_OCPARCFG1_0 0x3d400334 +#define DDRC_OCPARCFG2_0 0x3d400338 +#define DDRC_OCPARCFG3_0 0x3d40033c +#define DDRC_OCPARSTAT0_0 0x3d400340 +#define DDRC_OCPARSTAT1_0 0x3d400344 +#define DDRC_OCPARWLOG0_0 0x3d400348 +#define DDRC_OCPARWLOG1_0 0x3d40034c +#define DDRC_OCPARWLOG2_0 0x3d400350 +#define DDRC_OCPARAWLOG0_0 0x3d400354 +#define DDRC_OCPARAWLOG1_0 0x3d400358 +#define DDRC_OCPARRLOG0_0 0x3d40035c +#define DDRC_OCPARRLOG1_0 0x3d400360 +#define DDRC_OCPARARLOG0_0 0x3d400364 +#define DDRC_OCPARARLOG1_0 0x3d400368 +#define DDRC_POISONCFG_0 0x3d40036C +#define DDRC_POISONSTAT_0 0x3d400370 +#define DDRC_ADVECCINDEX_0 0x3d400003 +#define DDRC_ADVECCSTAT_0 0x3d400003 +#define DDRC_ECCPOISONPAT0_0 0x3d400003 +#define DDRC_ECCPOISONPAT1_0 0x3d400003 +#define DDRC_ECCPOISONPAT2_0 0x3d400003 +#define DDRC_HIFCTL_0 0x3d400003 + +#define DDRC_PSTAT_0 0x3d4003fc +#define DDRC_PCCFG_0 0x3d400400 +#define DDRC_PCFGR_0_0 0x3d400404 +#define DDRC_PCFGR_1_0 0x3d4004b4 +#define DDRC_PCFGR_2_0 0x3d400564 +#define DDRC_PCFGR_3_0 0x3d400614 +#define DDRC_PCFGW_0_0 0x3d400408 +#define DDRC_PCFGW_1_0 0x3d400408 +#define DDRC_PCFGW_2_0 0x3d400568 +#define DDRC_PCFGW_3_0 0x3d400618 +#define DDRC_PCFGC_0_0 0x3d40040c +#define DDRC_PCFGIDMASKCH_0 0x3d400410 +#define DDRC_PCFGIDVALUECH_0 0x3d400414 +#define DDRC_PCTRL_0_0 0x3d400490 +#define DDRC_PCTRL_1_0 0x3d400540 +#define DDRC_PCTRL_2_0 0x3d4005f0 +#define DDRC_PCTRL_3_0 0x3d4006a0 +#define DDRC_PCFGQOS0_0_0 0x3d400494 +#define DDRC_PCFGQOS1_0_0 0x3d400498 +#define DDRC_PCFGWQOS0_0_0 0x3d40049c +#define DDRC_PCFGWQOS1_0_0 0x3d4004a0 +#define DDRC_SARBASE0_0 0x3d400f04 +#define DDRC_SARSIZE0_0 0x3d400f08 +#define DDRC_SBRCTL_0 0x3d400f24 +#define DDRC_SBRSTAT_0 0x3d400f28 +#define DDRC_SBRWDATA0_0 0x3d400f2c +#define DDRC_SBRWDATA1_0 0x3d400f30 +#define DDRC_PDCH_0 0x3d400f34 + +/**********************/ +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) +#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) +#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) +#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) +#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) +#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) +#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) +#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) +#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) +#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) +#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) +#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) +#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) +#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) +#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) +#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) +#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) +#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) +#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) +#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) +#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) +#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) +#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) +#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) +#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) +#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) +#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) +#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) +#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) +#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) +#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) +#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) +#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) +#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) +#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) +#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) +#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) +#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) +#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) +#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) +#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) +#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) +#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) +#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) +#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) +#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) +#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) +#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) +#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) +#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) +#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) +#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) +#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) +#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) +#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) +#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) +#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) +#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) +#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) +#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) +#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) +#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) +#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) +#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) +#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) +#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) +#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) +#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) +#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) +#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) +#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) +#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) +#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) +#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) +#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) +#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) +#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) +#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) +#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) +#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) +#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) +#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) +#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) +#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) +#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) +#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) +#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) +#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) +#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) +#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) +#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) +#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) +#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) +#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) +#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) +#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) +#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) +#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) +#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) +#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) +#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) +#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) +#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) +#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) +#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) +#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) +#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) +#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) +#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) +#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) +#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) +#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) +#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) +#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) +#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) +#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) +#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) +#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) +#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) +#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) +#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) +#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) +#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) +#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) +#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) +#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) +#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) +#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) +#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) +#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) +#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) +#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) +#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) +#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) +#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) +#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) +#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) +#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) +#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) +#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) +#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) +#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) + +#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) +#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) +#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) +#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) +#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) +#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) +#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) +#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) +#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) +#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) +#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) +#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) +#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) +#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) +#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) +#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) +#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) +#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) +#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) +#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) +#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) +#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) +#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) +#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) +#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) +#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) +#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) +#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) + +#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) +#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) +#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) +#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) +#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) +#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) +#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) +#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) +#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) +#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) +#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) +#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) +#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) +#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) +#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) +#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) +#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) +#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) +#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) +#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) +#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) +#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) +#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) +#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) +#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) +#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) +#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) +#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) +#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) +#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) +#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) +#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) +#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) +#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) +#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) +#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) +#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) +#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) +#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) +#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) +#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) +#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) +#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) +#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) +#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) +#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) +#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) +#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) +#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) +#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) +#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) +#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) +#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) +#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) +#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) +#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) +#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) +#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) +#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) + +#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) +#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) +#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) +#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) +#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) +#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) +#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) +#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) +#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) +#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) +#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) +#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) +#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) +#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) +#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) +#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) +#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) +#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) +#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) +#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) +#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) +#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) +#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) +#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) +#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) + +#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) +#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) +#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) +#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) +#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) +#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) +#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) +#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) +#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) +#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) +#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) + +#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097) + +#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) +#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) +#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) +#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) +#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) +#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) +#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) +#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) +#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) +#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) +#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) +#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) +#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) +#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) +#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) +#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) +#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) +#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) +#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) +#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) +#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) +#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) +#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) +#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) +#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) + +/* user data type */ +enum fw_type { + FW_1D_IMAGE, + FW_2D_IMAGE, +}; + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_fsp_msg { + unsigned int drate; + enum fw_type fw_type; + struct dram_cfg_param *fsp_cfg; + unsigned int fsp_cfg_num; +}; + +struct dram_timing_info { + /* umctl2 config */ + struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; + /* ddrphy config */ + struct dram_cfg_param *ddrphy_cfg; + unsigned int ddrphy_cfg_num; + /* ddr fsp train info */ + struct dram_fsp_msg *fsp_msg; + unsigned int fsp_msg_num; + /* ddr phy trained CSR */ + struct dram_cfg_param *ddrphy_trained_csr; + unsigned int ddrphy_trained_csr_num; + /* ddr phy PIE */ + struct dram_cfg_param *ddrphy_pie; + unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; +}; + +extern struct dram_timing_info dram_timing; + +void ddr_load_train_firmware(enum fw_type type); +void ddr_init(struct dram_timing_info *timing_info); +void ddr_cfg_phy(struct dram_timing_info *timing_info); +void load_lpddr4_phy_pie(void); +void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); +void dram_config_save(struct dram_timing_info *info, unsigned long base); + +/* utils function for ddr phy training */ +void wait_ddrphy_training_complete(void); +void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_read_msg_block(enum fw_type type); + +static inline void reg32_write(unsigned long addr, u32 val) +{ + writel(val, addr); +} + +static inline u32 reg32_read(unsigned long addr) +{ + return readl(addr); +} + +static inline void reg32setbit(unsigned long addr, u32 bit) +{ + setbits_le32(addr, (1 << bit)); +} + +#define dwc_ddrphy_apb_wr(addr, data) \ + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) +#define dwc_ddrphy_apb_rd(addr) \ + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + +extern struct dram_cfg_param ddrphy_trained_csr[]; +extern uint32_t ddrphy_trained_csr_num; + #endif diff --git a/drivers/Makefile b/drivers/Makefile index 4453c62ad3..30ca29736b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index b764add060..d4b393d25e 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1 +1,2 @@ source "drivers/ddr/altera/Kconfig" +source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig new file mode 100644 index 0000000000..7e06fb2f7d --- /dev/null +++ b/drivers/ddr/imx/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/imx/imx8m/Kconfig" diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig new file mode 100644 index 0000000000..71f466f5ec --- /dev/null +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -0,0 +1,22 @@ +config IMX8M_DRAM + bool "imx8m dram" + +config IMX8M_LPDDR4 + bool "imx8m lpddr4" + select IMX8M_DRAM + help + Select the i.MX8M LPDDR4 driver support on i.MX8M SOC. + +config IMX8M_DDR4 + bool "imx8m ddr4" + select IMX8M_DRAM + help + Select the i.MX8M DDR4 driver support on i.MX8M SOC. + +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + after DRAM is trained, need to save the dram related timming + info into memory for low power use. OCRAM_S is used for this + purpose on i.MX8MM. + default 0x180000 diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile new file mode 100644 index 0000000000..64f9ab20e6 --- /dev/null +++ b/drivers/ddr/imx/imx8m/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_init.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_init.o +endif diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c new file mode 100644 index 0000000000..031cdc57e1 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddr4_init.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8m_ddr.h> +#include <asm/arch/sys_proto.h> + +void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + volatile unsigned int tmp_t; + /* + * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, + * [4]src_system_rst_b! + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F); + /* deassert [4]src_system_rst_b! */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + + /* + * change the clock source of dram_apb_clk_root + * to source 4 --800MHz/4 + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + dram_pll_init(DRAM_PLL_OUT_600M); + + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + + while (0 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + /* config the uMCTL2's registers */ + ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + + reg32_write(DDRC_RFSHCTL3(0), 0x00000001); + /* RESET: <ctn> DEASSERTED */ + /* RESET: <a Port 0 DEASSERTED(0) */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_PWRCTL(0), 0x00000aa); + reg32_write(DDRC_SWCTL(0), 0x00000000); + + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* config the DDR PHY's registers */ + ddr_cfg_phy(dram_timing); + + do { + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + + 4 * 0x00020097); + } while (tmp_t != 0); + + reg32_write(DDRC_DFIMISC(0), 0x00000020); + + /* wait DFISTAT.dfi_init_complete to 1 */ + while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0)))) + ; + + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x0000088); + + /* + * set SWCTL.sw_done to enable quasi-dynamic register + * programming outside reset. + */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* wait SWSTAT.sw_done_ack to 1 */ + while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0)))) + ; + + /* wait STAT to normal state */ + while (0x1 != (0x7 & reg32_read(DDRC_STAT(0)))) + ; + + reg32_write(DDRC_PWRCTL(0), 0x0000088); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + /* dis_auto-refresh is set to 0 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/imx8m/ddrphy_csr.c new file mode 100644 index 0000000000..67dd4e7059 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_csr.c @@ -0,0 +1,732 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* ddr phy trained csr */ +struct dram_cfg_param ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr); diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c new file mode 100644 index 0000000000..18f7ed7fea --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_train.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +void ddr_cfg_phy(struct dram_timing_info *dram_timing) +{ + struct dram_cfg_param *dram_cfg; + struct dram_fsp_msg *fsp_msg; + unsigned int num; + int i = 0; + int j = 0; + + /* initialize PHY configuration */ + dram_cfg = dram_timing->ddrphy_cfg; + num = dram_timing->ddrphy_cfg_num; + for (i = 0; i < num; i++) { + /* config phy reg */ + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* load the frequency setpoint message block config */ + fsp_msg = dram_timing->fsp_msg; + for (i = 0; i < dram_timing->fsp_msg_num; i++) { + debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); + /* set dram PHY input clocks to desired frequency */ + ddrphy_init_set_dfi_clk(fsp_msg->drate); + + /* load the dram training firmware image */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddr_load_train_firmware(fsp_msg->fw_type); + + /* load the frequency set point message block parameter */ + dram_cfg = fsp_msg->fsp_cfg; + num = fsp_msg->fsp_cfg_num; + for (j = 0; j < num; j++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* + * -------------------- excute the firmware -------------------- + * Running the firmware is a simply process to taking the + * PMU out of reset and stall, then the firwmare will be run + * 1. reset the PMU; + * 2. begin the excution; + * 3. wait for the training done; + * 4. read the message block result. + * ------------------------------------------------------------- + */ + dwc_ddrphy_apb_wr(0xd0000, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x9); + dwc_ddrphy_apb_wr(0xd0099, 0x1); + dwc_ddrphy_apb_wr(0xd0099, 0x0); + + /* Wait for the training firmware to complete */ + wait_ddrphy_training_complete(); + + /* Halt the microcontroller. */ + dwc_ddrphy_apb_wr(0xd0099, 0x1); + + /* Read the Message Block results */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + ddrphy_init_read_msg_block(fsp_msg->fw_type); + dwc_ddrphy_apb_wr(0xd0000, 0x1); + + fsp_msg++; + } + + /* Load PHY Init Engine Image */ + dram_cfg = dram_timing->ddrphy_pie; + num = dram_timing->ddrphy_pie_num; + for (i = 0; i < num; i++) { + dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); + dram_cfg++; + } + + /* save the ddr PHY trained CSR in memory for low power use */ + ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num); +} diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c new file mode 100644 index 0000000000..4732539764 --- /dev/null +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +*/ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_receive(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + ack_pmu_message_receive(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_receive(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + debug("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + debug("PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)) { + arg = get_stream_message(); + debug("arg[%d] = 0x%08x\n", i, arg); + i++; + } + + debug("\n"); +} + +void wait_ddrphy_training_complete(void) +{ + unsigned int mail; + + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + debug("Training PASS\n"); + break; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + break; + } + } +} + +void ddrphy_init_set_dfi_clk(unsigned int drate) +{ + switch (drate) { + case 3200: + dram_pll_init(MHZ(800)); + dram_disable_bypass(); + break; + case 3000: + dram_pll_init(MHZ(750)); + dram_disable_bypass(); + break; + case 2400: + dram_pll_init(MHZ(600)); + dram_disable_bypass(); + break; + case 1600: + dram_pll_init(MHZ(400)); + dram_disable_bypass(); + break; + case 667: + dram_pll_init(MHZ(167)); + dram_disable_bypass(); + break; + case 400: + dram_enable_bypass(MHZ(400)); + break; + case 100: + dram_enable_bypass(MHZ(100)); + break; + default: + return; + } +} + +void ddrphy_init_read_msg_block(enum fw_type type) +{ +} + +void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr, + unsigned int mr_data) +{ + unsigned int tmp; + /* + * 1. Poll MRSTAT.mr_wr_busy until it is 0. + * This checks that there is no outstanding MR transaction. + * No writes should be performed to MRCTRL0 and MRCTRL1 if + * MRSTAT.mr_wr_busy = 1. + */ + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + /* + * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and + * (for MRWs) MRCTRL1.mr_data to define the MR transaction. + */ + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4)); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); + reg32setbit(DDRC_MRCTRL0(0), 31); +} + +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + tmp = tmp & 0xff; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + + return tmp; +} diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c new file mode 100644 index 0000000000..61cd4f6db1 --- /dev/null +++ b/drivers/ddr/imx/imx8m/helper.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 /* byte */ +#define DMEM_LEN 16384 /* byte */ +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_firmware(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN; ) { + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + debug("check ddr4_pmu_train_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for (i = 0x0; i < IMEM_LEN; ) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if (error) + printf("check ddr4_pmu_train_imem code fail=%d\n", error); + else + debug("check ddr4_pmu_train_imem code pass\n"); + + debug("check ddr4_pmu_train_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for (i = 0x0; i < DMEM_LEN;) { + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if (tmp32 != readl(pr_from32)) { + debug("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if (error) + printf("check ddr4_pmu_train_dmem code fail=%d", error); + else + debug("check ddr4_pmu_train_dmem code pass\n"); +} + +void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, + unsigned int num) +{ + int i = 0; + + /* enable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xd0000, 0x0); + dwc_ddrphy_apb_wr(0xc0080, 0x3); + for (i = 0; i < num; i++) { + ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); + ddrphy_csr++; + } + /* disable the ddrphy apb */ + dwc_ddrphy_apb_wr(0xc0080, 0x2); + dwc_ddrphy_apb_wr(0xd0000, 0x1); +} + +void dram_config_save(struct dram_timing_info *timing_info, + unsigned long saved_timing_base) +{ + int i = 0; + struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base; + struct dram_cfg_param *cfg; + + saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; + saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; + saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; + saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; + + /* save the fsp table */ + for (i = 0; i < 4; i++) + saved_timing->fsp_table[i] = timing_info->fsp_table[i]; + + cfg = (struct dram_cfg_param *)(saved_timing_base + + sizeof(*timing_info)); + + /* save ddrc config */ + saved_timing->ddrc_cfg = cfg; + for (i = 0; i < timing_info->ddrc_cfg_num; i++) { + cfg->reg = timing_info->ddrc_cfg[i].reg; + cfg->val = timing_info->ddrc_cfg[i].val; + cfg++; + } + + /* save ddrphy config */ + saved_timing->ddrphy_cfg = cfg; + for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { + cfg->reg = timing_info->ddrphy_cfg[i].reg; + cfg->val = timing_info->ddrphy_cfg[i].val; + cfg++; + } + + /* save the ddrphy csr */ + saved_timing->ddrphy_trained_csr = cfg; + for (i = 0; i < ddrphy_trained_csr_num; i++) { + cfg->reg = ddrphy_trained_csr[i].reg; + cfg->val = ddrphy_trained_csr[i].val; + cfg++; + } + + /* save the ddrphy pie */ + saved_timing->ddrphy_pie = cfg; + for (i = 0; i < timing_info->ddrphy_pie_num; i++) { + cfg->reg = timing_info->ddrphy_pie[i].reg; + cfg->val = timing_info->ddrphy_pie[i].val; + cfg++; + } +} diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c new file mode 100644 index 0000000000..a4bc1de8eb --- /dev/null +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* +* Copyright 2018 NXP +* +*/ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> +#include <asm/arch/sys_proto.h> + +void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) +{ + int i = 0; + + for (i = 0; i < num; i++) { + reg32_write(ddrc_cfg->reg, ddrc_cfg->val); + ddrc_cfg++; + } +} + +void ddr_init(struct dram_timing_info *dram_timing) +{ + unsigned int tmp; + + debug("DDRINFO: start lpddr4 ddr init\n"); + /* step 1: reset */ + if (is_imx8mq()) { + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + } else { + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); + } + + mdelay(100); + + debug("DDRINFO: reset done\n"); + /* + * change the clock source of dram_apb_clk_root: + * source 4 800MHz /4 = 200MHz + */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable iso */ + reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ + reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ + + debug("DDRINFO: cfg clk\n"); + dram_pll_init(MHZ(750)); + + /* + * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /*step2 Configure uMCTL2's registers */ + debug("DDRINFO: ddrc config start\n"); + lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); + debug("DDRINFO: ddrc config done\n"); + + /* + * step3 de-assert all reset + * RESET: <core_ddrc_rstn> DEASSERTED + * RESET: <aresetn> for Port 0 DEASSERT(0)ED + */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + reg32_write(DDRC_DBG1(0), 0x00000000); + /* step4 */ + /* [0]dis_auto_refresh=1 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000011); + + /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x33f) != 0x223); + + reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ + + /* step5 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step6 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000210); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000110); + else + reg32_write(DDRC_DFIMISC(0), 0x00000010); + + /* step7 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step8 Configure LPDDR4 PHY's registers */ + debug("DDRINFO:ddrphy config start\n"); + ddr_cfg_phy(dram_timing); + debug("DDRINFO: ddrphy config done\n"); + + /* + * step14 CalBusy.0 =1, indicates the calibrator is actively + * calibrating. Wait Calibrating done. + */ + do { + tmp = reg32_read(DDRPHY_CalBusy(0)); + } while ((tmp & 0x1)); + + debug("DDRINFO:ddrphy calibration done\n"); + + /* step15 [0]--0: to enable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step16 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) + reg32_write(DDRC_DFIMISC(0), 0x00000230); + else if (tmp == 0x1) + reg32_write(DDRC_DFIMISC(0), 0x00000130); + else + reg32_write(DDRC_DFIMISC(0), 0x00000030); + + /* step17 [0]--1: disable quasi-dynamic programming */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + /* step18 wait DFISTAT.dfi_init_complete to 1 */ + do { + tmp = reg32_read(DDRC_DFISTAT(0)); + } while ((tmp & 0x1) == 0x0); + + /* step19 */ + reg32_write(DDRC_SWCTL(0), 0x00000000); + + /* step20~22 */ + tmp = reg32_read(DDRC_MSTR2(0)); + if (tmp == 0x2) { + reg32_write(DDRC_DFIMISC(0), 0x00000210); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000211); + } else if (tmp == 0x1) { + reg32_write(DDRC_DFIMISC(0), 0x00000110); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000111); + } else { + /* clear DFIMISC.dfi_init_complete_en */ + reg32_write(DDRC_DFIMISC(0), 0x00000010); + /* set DFIMISC.dfi_init_complete_en again */ + reg32_write(DDRC_DFIMISC(0), 0x00000011); + } + + /* step23 [5]selfref_sw=0; */ + reg32_write(DDRC_PWRCTL(0), 0x00000008); + /* step24 sw_done=1 */ + reg32_write(DDRC_SWCTL(0), 0x00000001); + + /* step25 wait SWSTAT.sw_done_ack to 1 */ + do { + tmp = reg32_read(DDRC_SWSTAT(0)); + } while ((tmp & 0x1) == 0x0); + +#ifdef DFI_BUG_WR + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); +#endif + /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ + do { + tmp = reg32_read(DDRC_STAT(0)); + } while ((tmp & 0x3) != 0x1); + + /* step26 */ + reg32_write(DDRC_RFSHCTL3(0), 0x00000010); + + /* enable port 0 */ + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + debug("DDRINFO: ddrmix config done\n"); + + /* save the dram timing config into memory */ + dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); +} -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-20 10:19 ` [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M Peng Fan @ 2018-11-20 17:47 ` Troy Kisky 2018-11-21 2:54 ` Peng Fan 0 siblings, 1 reply; 28+ messages in thread From: Troy Kisky @ 2018-11-20 17:47 UTC (permalink / raw) To: u-boot On 11/20/2018 2:19 AM, Peng Fan wrote: > +#define DDRC_MSTR_0 0x3d400000 > +#define DDRC_STAT_0 0x3d400004 > +#define DDRC_MSTR1_0 0x3d400008 > + Are you are planning to use DDRC_xxxx_0 in .cfg files? With SPL, I doubt the above are necessary. > +/**********************/ > +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) > +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) > +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) Or, do you ever use the above without X == 0 ? ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-20 17:47 ` Troy Kisky @ 2018-11-21 2:54 ` Peng Fan 2018-11-21 12:39 ` Fabio Estevam 0 siblings, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-21 2:54 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Troy Kisky [mailto:troy.kisky at boundarydevices.com] > Sent: 2018年11月21日 1:47 > To: Peng Fan <peng.fan@nxp.com>; sbabic at denx.de; Fabio Estevam > <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for > i.MX8M > > On 11/20/2018 2:19 AM, Peng Fan wrote: > > +#define DDRC_MSTR_0 0x3d400000 > > +#define DDRC_STAT_0 0x3d400004 > > +#define DDRC_MSTR1_0 0x3d400008 > > + > > Are you are planning to use DDRC_xxxx_0 in .cfg files? No. DDRC/PHY is initialized by C code. I did not receive more comments about other patches in this patchset. Stefano, Fabio, how about creating a follow up patch to remove the unused macros, or do you expect to create a v3 patchset for this removing? > > With SPL, I doubt the above are necessary. > > > +/**********************/ > > +#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) > > +#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) > > +#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) > > Or, do you ever use the above without X == 0 ? No. There might be more DDRC in future i.MX8M family, might not. Thanks, Peng. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-21 2:54 ` Peng Fan @ 2018-11-21 12:39 ` Fabio Estevam 2018-11-28 14:45 ` Jon Nettleton 0 siblings, 1 reply; 28+ messages in thread From: Fabio Estevam @ 2018-11-21 12:39 UTC (permalink / raw) To: u-boot Hi Peng, On Wed, Nov 21, 2018 at 12:54 AM Peng Fan <peng.fan@nxp.com> wrote: > Stefano, Fabio, how about creating a follow up patch to remove the unused macros, or do you expect to create a v3 patchset for this removing? It is fine for me if you send a follow up patch removing them. Thanks ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-21 12:39 ` Fabio Estevam @ 2018-11-28 14:45 ` Jon Nettleton 2018-11-28 14:57 ` Peng Fan 2018-11-28 15:03 ` Jacky Bai 0 siblings, 2 replies; 28+ messages in thread From: Jon Nettleton @ 2018-11-28 14:45 UTC (permalink / raw) To: u-boot On Wed, Nov 21, 2018 at 1:40 PM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Peng, > > On Wed, Nov 21, 2018 at 12:54 AM Peng Fan <peng.fan@nxp.com> wrote: > > > Stefano, Fabio, how about creating a follow up patch to remove the unused macros, or do you expect to create a v3 patchset for this removing? > > It is fine for me if you send a follow up patch removing them. > > Thanks > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > https://lists.denx.de/listinfo/u-boot Peng, I have found one more piece that is missing from the lpddr4 initialization. We don't have a structure, or place to change the DDR PHY DQ lane to memory mapping registers. Our board requires this and was failing until I patched it in. According to the code generated from DDR tool this should happen after /* step7 [0]--1: disable quasi-dynamic programming */ -Jon ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-28 14:45 ` Jon Nettleton @ 2018-11-28 14:57 ` Peng Fan 2018-11-28 16:02 ` Stefano Babic 2018-11-28 15:03 ` Jacky Bai 1 sibling, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-28 14:57 UTC (permalink / raw) To: u-boot Jon, > -----Original Message----- > From: Jon Nettleton [mailto:jon at solid-run.com] > Sent: 2018年11月28日 22:46 > To: Fabio Estevam <festevam@gmail.com> > Cc: Peng Fan <peng.fan@nxp.com>; Fabio Estevam > <fabio.estevam@nxp.com>; U-Boot Mailing List <u-boot@lists.denx.de>; > dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for > i.MX8M > > On Wed, Nov 21, 2018 at 1:40 PM Fabio Estevam <festevam@gmail.com> > wrote: > > > > Hi Peng, > > > > On Wed, Nov 21, 2018 at 12:54 AM Peng Fan <peng.fan@nxp.com> wrote: > > > > > Stefano, Fabio, how about creating a follow up patch to remove the > unused macros, or do you expect to create a v3 patchset for this removing? > > > > It is fine for me if you send a follow up patch removing them. > > > > Thanks > > _______________________________________________ > > U-Boot mailing list > > U-Boot at lists.denx.de > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis > > > ts.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cpeng.fan%40nxp.c > om%7 > > > Cc5ac7e5f29394549d24008d655404621%7C686ea1d3bc2b4c6fa92cd99c5c3 > 01635%7 > > > C0%7C1%7C636790131884926464&sdata=0JOZT0tgLDCbEQHlDGRY7R7 > GpI66enbD > > 6HvRieujt%2FU%3D&reserved=0 > > Peng, > > I have found one more piece that is missing from the lpddr4 initialization. > We don't have a structure, or place to change the DDR PHY DQ lane to > memory mapping registers. Our board requires this and was failing until I > patched it in. > > According to the code generated from DDR tool this should happen after > /* step7 [0]--1: disable quasi-dynamic programming */ Would you mind submit a follow up patch? Stefano, I'll submit a follow up patch to remove the unused macros in this patch, are you ok with that? Thanks, Peng. > > -Jon ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-28 14:57 ` Peng Fan @ 2018-11-28 16:02 ` Stefano Babic 0 siblings, 0 replies; 28+ messages in thread From: Stefano Babic @ 2018-11-28 16:02 UTC (permalink / raw) To: u-boot On 28/11/18 15:57, Peng Fan wrote: > Jon, > >> -----Original Message----- >> From: Jon Nettleton [mailto:jon at solid-run.com] >> Sent: 2018年11月28日 22:46 >> To: Fabio Estevam <festevam@gmail.com> >> Cc: Peng Fan <peng.fan@nxp.com>; Fabio Estevam >> <fabio.estevam@nxp.com>; U-Boot Mailing List <u-boot@lists.denx.de>; >> dl-linux-imx <linux-imx@nxp.com> >> Subject: Re: [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for >> i.MX8M >> >> On Wed, Nov 21, 2018 at 1:40 PM Fabio Estevam <festevam@gmail.com> >> wrote: >>> >>> Hi Peng, >>> >>> On Wed, Nov 21, 2018 at 12:54 AM Peng Fan <peng.fan@nxp.com> wrote: >>> >>>> Stefano, Fabio, how about creating a follow up patch to remove the >> unused macros, or do you expect to create a v3 patchset for this removing? >>> >>> It is fine for me if you send a follow up patch removing them. >>> >>> Thanks >>> _______________________________________________ >>> U-Boot mailing list >>> U-Boot at lists.denx.de >>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis >>> >> ts.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cpeng.fan%40nxp.c >> om%7 >>> >> Cc5ac7e5f29394549d24008d655404621%7C686ea1d3bc2b4c6fa92cd99c5c3 >> 01635%7 >>> >> C0%7C1%7C636790131884926464&sdata=0JOZT0tgLDCbEQHlDGRY7R7 >> GpI66enbD >>> 6HvRieujt%2FU%3D&reserved=0 >> >> Peng, >> >> I have found one more piece that is missing from the lpddr4 initialization. >> We don't have a structure, or place to change the DDR PHY DQ lane to >> memory mapping registers. Our board requires this and was failing until I >> patched it in. >> >> According to the code generated from DDR tool this should happen after >> /* step7 [0]--1: disable quasi-dynamic programming */ > > Would you mind submit a follow up patch? > > Stefano, > > I'll submit a follow up patch to remove the unused macros in this patch, are you ok with that? > It is ok for me, thanks ! Regards, Stefano > Thanks, > Peng. > >> >> -Jon -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-28 14:45 ` Jon Nettleton 2018-11-28 14:57 ` Peng Fan @ 2018-11-28 15:03 ` Jacky Bai 2018-11-28 15:32 ` Jon Nettleton 1 sibling, 1 reply; 28+ messages in thread From: Jacky Bai @ 2018-11-28 15:03 UTC (permalink / raw) To: u-boot > > Peng, > > I have found one more piece that is missing from the lpddr4 initialization. > We don't have a structure, or place to change the DDR PHY DQ lane to > memory mapping registers. Our board requires this and was failing until I > patched it in. > > According to the code generated from DDR tool this should happen after > /* step7 [0]--1: disable quasi-dynamic programming */ > Actually, the DQ lane config is part of ddrphy config. The DDR PHY DQ lane config will be put in the ddrphy_cfg array in latest DDR tool. Jacky > -Jon ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M 2018-11-28 15:03 ` Jacky Bai @ 2018-11-28 15:32 ` Jon Nettleton 0 siblings, 0 replies; 28+ messages in thread From: Jon Nettleton @ 2018-11-28 15:32 UTC (permalink / raw) To: u-boot On Wed, Nov 28, 2018 at 4:03 PM Jacky Bai <ping.bai@nxp.com> wrote: > > > > > Peng, > > > > I have found one more piece that is missing from the lpddr4 initialization. > > We don't have a structure, or place to change the DDR PHY DQ lane to > > memory mapping registers. Our board requires this and was failing until I > > patched it in. > > > > According to the code generated from DDR tool this should happen after > > /* step7 [0]--1: disable quasi-dynamic programming */ > > > > Actually, the DQ lane config is part of ddrphy config. The DDR PHY DQ lane config will be put in the ddrphy_cfg array in latest DDR tool. > Okay, I can adjust my scripts to make this change. Any ETA as to when the new DDR tool will be available? Thanks, Jon ^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan ` (12 preceding siblings ...) 2018-11-20 10:19 ` [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M Peng Fan @ 2018-11-20 10:20 ` Peng Fan 2018-11-27 7:32 ` Peng Fan 13 siblings, 1 reply; 28+ messages in thread From: Peng Fan @ 2018-11-20 10:20 UTC (permalink / raw) To: u-boot Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty NOTICE: BL31: Built : 09:28:54, Nov 8 2018 lpddr4 swffc start NOTICE: sip svc init U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: Warning: ethernet at 30be0000 using MAC address from ROM eth0: ethernet at 30be0000 Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Rebase to master Move ddr phy csr to ddr driver reuse lpddr4_defines.h to drop some redundant code. CI build: https://travis-ci.org/MrVan/u-boot/builds/457379499 arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8mq-evk.dts | 414 ++++++++ arch/arm/mach-imx/imx8m/Kconfig | 13 + board/freescale/imx8mq_evk/Kconfig | 12 + board/freescale/imx8mq_evk/MAINTAINERS | 6 + board/freescale/imx8mq_evk/Makefile | 12 + board/freescale/imx8mq_evk/README | 36 + board/freescale/imx8mq_evk/imx8mq_evk.c | 130 +++ board/freescale/imx8mq_evk/lpddr4_timing.c | 1320 +++++++++++++++++++++++++ board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1191 ++++++++++++++++++++++ board/freescale/imx8mq_evk/spl.c | 246 +++++ configs/imx8mq_evk_defconfig | 37 + include/configs/imx8mq_evk.h | 252 +++++ 13 files changed, 3671 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts create mode 100644 board/freescale/imx8mq_evk/Kconfig create mode 100644 board/freescale/imx8mq_evk/MAINTAINERS create mode 100644 board/freescale/imx8mq_evk/Makefile create mode 100644 board/freescale/imx8mq_evk/README create mode 100644 board/freescale/imx8mq_evk/imx8mq_evk.c create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing_b0.c create mode 100644 board/freescale/imx8mq_evk/spl.c create mode 100644 configs/imx8mq_evk_defconfig create mode 100644 include/configs/imx8mq_evk.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1cbb45d679..2be31397d4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -459,6 +459,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb + dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb-u-boot.dtb \ r8a7795-salvator-x-u-boot.dtb \ diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts new file mode 100644 index 0000000000..4a08099b3c --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000; + +#include "fsl-imx8mq.dtsi" + +/ { + model = "Freescale i.MX8MQ EVK"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-evk { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100 at 08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&lcdif { + status = "okay"; + disp-dev = "mipi_dsi_northwest"; + display = <&display0>; + + display0: display at 0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: n25q256a at 0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 98d79c3179..317dee9bc1 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -7,4 +7,17 @@ config IMX8M config SYS_SOC default "imx8m" +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_IMX8MQ_EVK + bool "imx8mq_evk" + select IMX8M + select IMX8M_LPDDR4 + +endchoice + +source "board/freescale/imx8mq_evk/Kconfig" + endif diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig new file mode 100644 index 0000000000..421b081c76 --- /dev/null +++ b/board/freescale/imx8mq_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_EVK + +config SYS_BOARD + default "imx8mq_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_evk" + +endif diff --git a/board/freescale/imx8mq_evk/MAINTAINERS b/board/freescale/imx8mq_evk/MAINTAINERS new file mode 100644 index 0000000000..a2e320cb10 --- /dev/null +++ b/board/freescale/imx8mq_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8MQ EVK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8mq_evk/ +F: include/configs/imx8mq_evk.h +F: configs/imx8mq_evk_defconfig diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile new file mode 100644 index 0000000000..cf046963d2 --- /dev/null +++ b/board/freescale/imx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/freescale/imx8mq_evk/README b/board/freescale/imx8mq_evk/README new file mode 100644 index 0000000000..07dbfb01fe --- /dev/null +++ b/board/freescale/imx8mq_evk/README @@ -0,0 +1,36 @@ +U-Boot for the NXP i.MX8MQ EVK board + +Quick Start +==================== +- Build the ARM Trusted firmware binary +- Get ddr and hdmi fimware +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +==================== +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +branch: imx_4.14.62_1.0.0_beta +$ make PLAT=imx8mq bl31 + +Get the ddr and hdmi firmware +==================== +Note: srctree is U-Boot source directory +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin +$ chmod +x firmware-imx-7.9.bin +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree) +$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee) + +Build U-Boot +==================== +$ export ARCH=arm64 +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make imx8mq_evk_defconfig +$ make flash.bin + +Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 + +Boot +==================== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c new file mode 100644 index 0000000000..54e0c38431 --- /dev/null +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +int dram_init(void) +{ + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1]) + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; + else + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c new file mode 100644 index 0000000000..f7ea799343 --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -0,0 +1,1320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +#define WR_POST_EXT_3200 /* recommened to define */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + { DDRC_PERFLPR1(0), 0x00000009 }, + { DDRC_PERFWR1(0), 0x02005574 }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + { DDRC_PCFGQOS0_0(0), 0x01110d00 }, + { DDRC_PCFGQOS1_0(0), 0x00620790 }, + { DDRC_PCFGWQOS0_0(0), 0x00100001 }, + { DDRC_PCFGWQOS1_0(0), 0x0000041f }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14*/ + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, + /* MR1 */ + { 0x54038, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14 */ + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + /* { 0x5403d, 0x500 } */ + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + /* PHY Ron/Rtt */ + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + /* MR4/MR3 */ + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, + /* MR12/MR11 */ + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ }, + /* self:0x4d28//MR14/MR13 */ + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ + /* self:0x4d28//MR14/MR13 */ + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c new file mode 100644 index 0000000000..ec68edaf69 --- /dev/null +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <common.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +#define WR_POST_EXT_3200 /* recommened to define */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0xd }, + { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x4 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x70 }, + { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x1ff8 }, + { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, + { 0x900e0, 0x50 }, + { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x60 }, + { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, + { 0x900e6, 0x8 }, + { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0x8 }, + { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, + { 0x900ec, 0xa }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x6e }, + { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x0 }, + { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, + { 0x900fb, 0x1ff8 }, + { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, + { 0x90101, 0x78 }, + { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, + { 0x90104, 0x68 }, + { 0x90105, 0x790 }, + { 0x90106, 0x16a }, + { 0x90107, 0x8 }, + { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0x8 }, + { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, + { 0x9010d, 0xa }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x58 }, + { 0x90111, 0x0 }, + { 0x90112, 0x68 }, + { 0x90113, 0x0 }, + { 0x90114, 0x408 }, + { 0x90115, 0x169 }, + { 0x90116, 0x0 }, + { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, + { 0x9011c, 0x0 }, + { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, + { 0x9011f, 0x80 }, + { 0x90120, 0x790 }, + { 0x90121, 0x16a }, + { 0x90122, 0x18 }, + { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, + { 0x90125, 0xa }, + { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, + { 0x90128, 0x8 }, + { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, + { 0x9012b, 0xf }, + { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, + { 0x9012e, 0xc }, + { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, + { 0x90131, 0x9 }, + { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, + { 0x90134, 0x0 }, + { 0x90135, 0x408 }, + { 0x90136, 0x169 }, + { 0x90137, 0x0 }, + { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, + { 0x9013a, 0x8 }, + { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, + { 0x9013d, 0x0 }, + { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, + { 0x90140, 0xb7 }, + { 0x90141, 0x790 }, + { 0x90142, 0x16a }, + { 0x90143, 0x1f }, + { 0x90144, 0x0 }, + { 0x90145, 0x68 }, + { 0x90146, 0x8 }, + { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, + { 0x90149, 0xf }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0xc }, + { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x408 }, + { 0x90151, 0x169 }, + { 0x90152, 0x0 }, + { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, + { 0x90155, 0x8 }, + { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, + { 0x90158, 0x3 }, + { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, + { 0x9015b, 0x20 }, + { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, + { 0x90161, 0x8 }, + { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, + { 0x90164, 0x0 }, + { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, + { 0x90167, 0x10 }, + { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, + { 0x90170, 0x8 }, + { 0x90171, 0x448 }, + { 0x90172, 0x109 }, + { 0x90173, 0xf }, + { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x47 }, + { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, + { 0x90185, 0x8 }, + { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, + { 0x90188, 0x0 }, + { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, + { 0x9018b, 0x8 }, + { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, + { 0x9018e, 0x8 }, + { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x6c }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c new file mode 100644 index 0000000000..e6cbc34b0d --- /dev/null +++ b/board/freescale/imx8mq_evk/spl.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <spl.h> +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_b0; + +void spl_dram_init(void) +{ + /* ddr init */ + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + /* set SW3A standby mode to off */ + pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg &= ~0xf; + reg |= APS_OFF; + pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + + return 0; +} +#endif + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig new file mode 100644 index 0000000000..f216d46a8f --- /dev/null +++ b/configs/imx8mq_evk_defconfig @@ -0,0 +1,37 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" +CONFIG_OF_LIST="fsl-imx8mq-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_THERMAL=y +CONFIG_FS_FAT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h new file mode 100644 index 0000000000..35f81152f2 --- /dev/null +++ b/include/configs/imx8mq_evk.h @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_EVK_H +#define __IMX8M_EVK_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ +#endif + +#define CONFIG_SPL_TEXT_BASE 0x7E1000 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#undef CONFIG_CMD_EXPORTENV +#undef CONFIG_CMD_IMPORTENV +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=fsl-imx8mq-evk.dtb\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (64 * SZ_64K) +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_OCOTP +#define CONFIG_CMD_FUSE + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support 2018-11-20 10:20 ` [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support Peng Fan @ 2018-11-27 7:32 ` Peng Fan 0 siblings, 0 replies; 28+ messages in thread From: Peng Fan @ 2018-11-27 7:32 UTC (permalink / raw) To: u-boot Hi Stefano, Do you have any comments on this v2 patchset? Thanks, Peng. > -----Original Message----- > From: Peng Fan > Sent: 2018年11月20日 18:20 > To: sbabic at denx.de; Fabio Estevam <fabio.estevam@nxp.com> > Cc: u-boot at lists.denx.de; dl-linux-imx <linux-imx@nxp.com>; Peng Fan > <peng.fan@nxp.com> > Subject: [PATCH V2 15/15] imx: add i.MX8MQ EVK support > > Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy > firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to > DRAM. > > The boot log with Arm trusted firmware console enabled: > " > U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) > PMIC: PFUZE100 ID=0x10 > Normal Boot > Trying to boot from MMC2 > NOTICE: Configureing TZASC380 > NOTICE: BL31: > v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty > NOTICE: BL31: Built : 09:28:54, Nov 8 2018 > lpddr4 swffc start > NOTICE: sip svc init > > U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) > > CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz > Reset cause: POR > Model: Freescale i.MX8MQ EVK > DRAM: 3 GiB > MMC: FSL_SDHC: 0, FSL_SDHC: 1 > In: serial > Out: serial > Err: serial > Net: > Warning: ethernet at 30be0000 using MAC address from ROM > eth0: ethernet at 30be0000 > Hit any key to stop autoboot: 0 > " > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > Rebase to master > Move ddr phy csr to ddr driver > reuse lpddr4_defines.h to drop some redundant code. > CI build: https://travis-ci.org/MrVan/u-boot/builds/457379499 > > arch/arm/dts/Makefile | 2 + > arch/arm/dts/fsl-imx8mq-evk.dts | 414 ++++++++ > arch/arm/mach-imx/imx8m/Kconfig | 13 + > board/freescale/imx8mq_evk/Kconfig | 12 + > board/freescale/imx8mq_evk/MAINTAINERS | 6 + > board/freescale/imx8mq_evk/Makefile | 12 + > board/freescale/imx8mq_evk/README | 36 + > board/freescale/imx8mq_evk/imx8mq_evk.c | 130 +++ > board/freescale/imx8mq_evk/lpddr4_timing.c | 1320 > +++++++++++++++++++++++++ > board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1191 > ++++++++++++++++++++++ > board/freescale/imx8mq_evk/spl.c | 246 +++++ > configs/imx8mq_evk_defconfig | 37 + > include/configs/imx8mq_evk.h | 252 +++++ > 13 files changed, 3671 insertions(+) > create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts > create mode 100644 board/freescale/imx8mq_evk/Kconfig > create mode 100644 board/freescale/imx8mq_evk/MAINTAINERS > create mode 100644 board/freescale/imx8mq_evk/Makefile > create mode 100644 board/freescale/imx8mq_evk/README > create mode 100644 board/freescale/imx8mq_evk/imx8mq_evk.c > create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing.c > create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing_b0.c > create mode 100644 board/freescale/imx8mq_evk/spl.c > create mode 100644 configs/imx8mq_evk_defconfig > create mode 100644 include/configs/imx8mq_evk.h > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 1cbb45d679..2be31397d4 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -459,6 +459,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb > > dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb > > +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb > + > dtb-$(CONFIG_RCAR_GEN3) += \ > r8a7795-h3ulcb-u-boot.dtb \ > r8a7795-salvator-x-u-boot.dtb \ > diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts > b/arch/arm/dts/fsl-imx8mq-evk.dts > new file mode 100644 > index 0000000000..4a08099b3c > --- /dev/null > +++ b/arch/arm/dts/fsl-imx8mq-evk.dts > @@ -0,0 +1,414 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +/dts-v1/; > + > +/* First 128KB is for PSCI ATF. */ > +/memreserve/ 0x40000000 0x00020000; > + > +#include "fsl-imx8mq.dtsi" > + > +/ { > + model = "Freescale i.MX8MQ EVK"; > + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; > + > + chosen { > + bootargs = "console=ttymxc0,115200 > earlycon=ec_imx6q,0x30860000,115200"; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg_usdhc2_vmmc: usdhc2_vmmc { > + compatible = "regulator-fixed"; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + }; > + > + pwmleds { > + compatible = "pwm-leds"; > + > + ledpwm2 { > + label = "PWM2"; > + pwms = <&pwm2 0 50000>; > + max-brightness = <255>; > + }; > + }; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + > + imx8mq-evk { > + pinctrl_fec1: fec1grp { > + fsl,pins = < > + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 > + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 > + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f > + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f > + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f > + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f > + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 > + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 > + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 > + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 > + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f > + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 > + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL > 0x91 > + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL > 0x1f > + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f > + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f > + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f > + >; > + }; > + > + pinctrl_pwm2: pwm2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 > + >; > + }; > + > + pinctrl_qspi: qspigrp { > + fsl,pins = < > + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 > + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 > + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 > + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 > + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 > + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 > + > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 > + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 > + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 > + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 > + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 > + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 > + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 > + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 > + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 > + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 > + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 > + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > 0xc1 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 > + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 > + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 > + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 > + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 > + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 > + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 > + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 > + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 > + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 > + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 > + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > 0xc1 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 > + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 > + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 > + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 > + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 > + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 > + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 > + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 > + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 > + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 > + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 > + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > 0xc1 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2grpgpio { > + fsl,pins = < > + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 > + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 > + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 > + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 > + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 > + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 > + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 > + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { > + fsl,pins = < > + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 > + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 > + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 > + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 > + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 > + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 > + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { > + fsl,pins = < > + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 > + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 > + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 > + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 > + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 > + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 > + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 > + >; > + }; > + > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 > + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 > + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 > + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 > + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 > + >; > + }; > + > + pinctrl_wdog: wdoggrp { > + fsl,pins = < > + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 > + >; > + }; > + }; > +}; > + > +&fec1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_fec1>; > + phy-mode = "rgmii-id"; > + phy-handle = <ðphy0>; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy at 0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + at803x,led-act-blind-workaround; > + at803x,eee-disabled; > + }; > + }; > +}; > + > +&i2c1 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + pmic: pfuze100 at 08 { > + compatible = "fsl,pfuze100"; > + reg = <0x08>; > + > + regulators { > + sw1a_reg: sw1ab { > + regulator-min-microvolt = <300000>; > + regulator-max-microvolt = <1875000>; > + regulator-always-on; > + }; > + > + sw1c_reg: sw1c { > + regulator-min-microvolt = <300000>; > + regulator-max-microvolt = <1875000>; > + regulator-always-on; > + }; > + > + sw2_reg: sw2 { > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + sw3a_reg: sw3ab { > + regulator-min-microvolt = <400000>; > + regulator-max-microvolt = <1975000>; > + regulator-always-on; > + }; > + > + sw4_reg: sw4 { > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + swbst_reg: swbst { > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5150000>; > + }; > + > + snvs_reg: vsnvs { > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <3000000>; > + regulator-always-on; > + }; > + > + vref_reg: vrefddr { > + regulator-always-on; > + }; > + > + vgen1_reg: vgen1 { > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1550000>; > + }; > + > + vgen2_reg: vgen2 { > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1550000>; > + regulator-always-on; > + }; > + > + vgen3_reg: vgen3 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vgen4_reg: vgen4 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vgen5_reg: vgen5 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vgen6_reg: vgen6 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + }; > + }; > + }; > +}; > + > +&i2c2 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "disabled"; > +}; > + > +&pwm2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm2>; > + status = "okay"; > +}; > + > +&lcdif { > + status = "okay"; > + disp-dev = "mipi_dsi_northwest"; > + display = <&display0>; > + > + display0: display at 0 { > + bits-per-pixel = <24>; > + bus-width = <24>; > + > + display-timings { > + native-mode = <&timing0>; > + timing0: timing0 { > + clock-frequency = <9200000>; > + hactive = <480>; > + vactive = <272>; > + hfront-porch = <8>; > + hback-porch = <4>; > + hsync-len = <41>; > + vback-porch = <2>; > + vfront-porch = <4>; > + vsync-len = <10>; > + > + hsync-active = <0>; > + vsync-active = <0>; > + de-active = <1>; > + pixelclk-active = <0>; > + }; > + }; > + }; > +}; > + > +&qspi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi>; > + status = "okay"; > + > + flash0: n25q256a at 0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "micron,n25q256a"; > + spi-max-frequency = <29000000>; > + spi-nor,ddr-quad-read-dummy = <6>; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + bus-width = <4>; > + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&wdog1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_wdog>; > + fsl,ext-reset-output; > + status = "okay"; > +}; > diff --git a/arch/arm/mach-imx/imx8m/Kconfig > b/arch/arm/mach-imx/imx8m/Kconfig > index 98d79c3179..317dee9bc1 100644 > --- a/arch/arm/mach-imx/imx8m/Kconfig > +++ b/arch/arm/mach-imx/imx8m/Kconfig > @@ -7,4 +7,17 @@ config IMX8M > config SYS_SOC > default "imx8m" > > +choice > + prompt "NXP i.MX8M board select" > + optional > + > +config TARGET_IMX8MQ_EVK > + bool "imx8mq_evk" > + select IMX8M > + select IMX8M_LPDDR4 > + > +endchoice > + > +source "board/freescale/imx8mq_evk/Kconfig" > + > endif > diff --git a/board/freescale/imx8mq_evk/Kconfig > b/board/freescale/imx8mq_evk/Kconfig > new file mode 100644 > index 0000000000..421b081c76 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_IMX8MQ_EVK > + > +config SYS_BOARD > + default "imx8mq_evk" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_CONFIG_NAME > + default "imx8mq_evk" > + > +endif > diff --git a/board/freescale/imx8mq_evk/MAINTAINERS > b/board/freescale/imx8mq_evk/MAINTAINERS > new file mode 100644 > index 0000000000..a2e320cb10 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/MAINTAINERS > @@ -0,0 +1,6 @@ > +i.MX8MQ EVK BOARD > +M: Peng Fan <peng.fan@nxp.com> > +S: Maintained > +F: board/freescale/imx8mq_evk/ > +F: include/configs/imx8mq_evk.h > +F: configs/imx8mq_evk_defconfig > diff --git a/board/freescale/imx8mq_evk/Makefile > b/board/freescale/imx8mq_evk/Makefile > new file mode 100644 > index 0000000000..cf046963d2 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/Makefile > @@ -0,0 +1,12 @@ > +# > +# Copyright 2017 NXP > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += imx8mq_evk.o > + > +ifdef CONFIG_SPL_BUILD > +obj-y += spl.o > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o > +endif > diff --git a/board/freescale/imx8mq_evk/README > b/board/freescale/imx8mq_evk/README > new file mode 100644 > index 0000000000..07dbfb01fe > --- /dev/null > +++ b/board/freescale/imx8mq_evk/README > @@ -0,0 +1,36 @@ > +U-Boot for the NXP i.MX8MQ EVK board > + > +Quick Start > +==================== > +- Build the ARM Trusted firmware binary > +- Get ddr and hdmi fimware > +- Build U-Boot > +- Boot > + > +Get and Build the ARM Trusted firmware > +==================== > +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf > +branch: imx_4.14.62_1.0.0_beta > +$ make PLAT=imx8mq bl31 > + > +Get the ddr and hdmi firmware > +==================== > +Note: srctree is U-Boot source directory > +$ wget > https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin > +$ chmod +x firmware-imx-7.9.bin > +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin > $(srctree) > +$ cp > firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin > $(srctee) > + > +Build U-Boot > +==================== > +$ export ARCH=arm64 > +$ export CROSS_COMPILE=aarch64-poky-linux- > +$ make imx8mq_evk_defconfig > +$ make flash.bin > + > +Burn the flash.bin to MicroSD card offset 33KB > +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 > + > +Boot > +==================== > +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. > diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c > b/board/freescale/imx8mq_evk/imx8mq_evk.c > new file mode 100644 > index 0000000000..54e0c38431 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c > @@ -0,0 +1,130 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +#include <common.h> > +#include <malloc.h> > +#include <errno.h> > +#include <asm/io.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm-generic/gpio.h> > +#include <fsl_esdhc.h> > +#include <mmc.h> > +#include <asm/arch/imx8mq_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/mach-imx/gpio.h> > +#include <asm/mach-imx/mxc_i2c.h> > +#include <asm/arch/clock.h> > +#include <spl.h> > +#include <power/pmic.h> > +#include <power/pfuze100_pmic.h> > +#include "../common/pfuze.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > + > +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | > PAD_CTL_PUE) > + > +static iomux_v3_cfg_t const wdog_pads[] = { > + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | > MUX_PAD_CTRL(WDOG_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const uart_pads[] = { > + IMX8MQ_PAD_UART1_RXD__UART1_RX | > MUX_PAD_CTRL(UART_PAD_CTRL), > + IMX8MQ_PAD_UART1_TXD__UART1_TX | > MUX_PAD_CTRL(UART_PAD_CTRL), > +}; > + > +int board_early_init_f(void) > +{ > + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; > + > + imx_iomux_v3_setup_multiple_pads(wdog_pads, > ARRAY_SIZE(wdog_pads)); > + set_wdog_reset(wdog); > + > + imx_iomux_v3_setup_multiple_pads(uart_pads, > ARRAY_SIZE(uart_pads)); > + > + return 0; > +} > + > +int dram_init(void) > +{ > + /* rom_pointer[1] contains the size of TEE occupies */ > + if (rom_pointer[1]) > + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; > + else > + gd->ram_size = PHYS_SDRAM_SIZE; > + > + return 0; > +} > + > +#ifdef CONFIG_FEC_MXC > +#define FEC_RST_PAD IMX_GPIO_NR(1, 9) > +static iomux_v3_cfg_t const fec1_rst_pads[] = { > + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | > MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +static void setup_iomux_fec(void) > +{ > + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, > + ARRAY_SIZE(fec1_rst_pads)); > + > + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); > + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); > + udelay(500); > + gpio_direction_output(IMX_GPIO_NR(1, 9), 1); > +} > + > +static int setup_fec(void) > +{ > + struct iomuxc_gpr_base_regs *gpr = > + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; > + > + setup_iomux_fec(); > + > + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ > + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); > + return set_clk_enet(ENET_125MHZ); > +} > + > +int board_phy_config(struct phy_device *phydev) > +{ > + /* enable rgmii rxc skew and phy mode select to RGMII copper */ > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); > + > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); > + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); > + > + if (phydev->drv->config) > + phydev->drv->config(phydev); > + return 0; > +} > +#endif > + > +int board_init(void) > +{ > +#ifdef CONFIG_FEC_MXC > + setup_fec(); > +#endif > + > + return 0; > +} > + > +int board_mmc_get_env_dev(int devno) > +{ > + return devno; > +} > + > +int board_late_init(void) > +{ > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > + env_set("board_name", "EVK"); > + env_set("board_rev", "iMX8MQ"); > +#endif > + > + return 0; > +} > diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c > b/board/freescale/imx8mq_evk/lpddr4_timing.c > new file mode 100644 > index 0000000000..f7ea799343 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c > @@ -0,0 +1,1320 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +#include <linux/kernel.h> > +#include <common.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/lpddr4_define.h> > + > +#define WR_POST_EXT_3200 /* recommened to define */ > + > +struct dram_cfg_param lpddr4_ddrc_cfg[] = { > + /* Start to config, default 3200mbps */ > + { DDRC_DBG1(0), 0x00000001 }, > + { DDRC_PWRCTL(0), 0x00000001 }, > + { DDRC_MSTR(0), 0xa3080020 }, > + { DDRC_MSTR2(0), 0x00000000 }, > + { DDRC_RFSHTMG(0), 0x006100E0 }, > + { DDRC_INIT0(0), 0xC003061B }, > + { DDRC_INIT1(0), 0x009D0000 }, > + { DDRC_INIT3(0), 0x00D4002D }, > +#ifdef WR_POST_EXT_3200 > + { DDRC_INIT4(0), 0x00330008 }, > +#else > + { DDRC_INIT4(0), 0x00310008 }, > +#endif > + { DDRC_INIT6(0), 0x0066004a }, > + { DDRC_INIT7(0), 0x0006004a }, > + > + { DDRC_DRAMTMG0(0), 0x1A201B22 }, > + { DDRC_DRAMTMG1(0), 0x00060633 }, > + { DDRC_DRAMTMG3(0), 0x00C0C000 }, > + { DDRC_DRAMTMG4(0), 0x0F04080F }, > + { DDRC_DRAMTMG5(0), 0x02040C0C }, > + { DDRC_DRAMTMG6(0), 0x01010007 }, > + { DDRC_DRAMTMG7(0), 0x00000401 }, > + { DDRC_DRAMTMG12(0), 0x00020600 }, > + { DDRC_DRAMTMG13(0), 0x0C100002 }, > + { DDRC_DRAMTMG14(0), 0x000000E6 }, > + { DDRC_DRAMTMG17(0), 0x00A00050 }, > + > + { DDRC_ZQCTL0(0), 0x03200018 }, > + { DDRC_ZQCTL1(0), 0x028061A8 }, > + { DDRC_ZQCTL2(0), 0x00000000 }, > + > + { DDRC_DFITMG0(0), 0x0497820A }, > + { DDRC_DFITMG1(0), 0x00080303 }, > + { DDRC_DFIUPD0(0), 0xE0400018 }, > + { DDRC_DFIUPD1(0), 0x00DF00E4 }, > + { DDRC_DFIUPD2(0), 0x80000000 }, > + { DDRC_DFIMISC(0), 0x00000011 }, > + { DDRC_DFITMG2(0), 0x0000170A }, > + > + { DDRC_DBICTL(0), 0x00000001 }, > + { DDRC_DFIPHYMSTR(0), 0x00000001 }, > + { DDRC_RANKCTL(0), 0x00000c99 }, > + { DDRC_DRAMTMG2(0), 0x070E171a }, > + > + /* address mapping */ > + { DDRC_ADDRMAP0(0), 0x00000015 }, > + { DDRC_ADDRMAP3(0), 0x00000000 }, > + { DDRC_ADDRMAP4(0), 0x00001F1F }, > + /* bank interleave */ > + { DDRC_ADDRMAP1(0), 0x00080808 }, > + { DDRC_ADDRMAP5(0), 0x07070707 }, > + { DDRC_ADDRMAP6(0), 0x08080707 }, > + > + /* performance setting */ > + { DDRC_ODTCFG(0), 0x0b060908 }, > + { DDRC_ODTMAP(0), 0x00000000 }, > + { DDRC_SCHED(0), 0x29511505 }, > + { DDRC_SCHED1(0), 0x0000002c }, > + { DDRC_PERFHPR1(0), 0x5900575b }, > + { DDRC_PERFLPR1(0), 0x00000009 }, > + { DDRC_PERFWR1(0), 0x02005574 }, > + { DDRC_DBG0(0), 0x00000016 }, > + { DDRC_DBG1(0), 0x00000000 }, > + { DDRC_DBGCMD(0), 0x00000000 }, > + { DDRC_SWCTL(0), 0x00000001 }, > + { DDRC_POISONCFG(0), 0x00000011 }, > + { DDRC_PCCFG(0), 0x00000111 }, > + { DDRC_PCFGR_0(0), 0x000010f3 }, > + { DDRC_PCFGW_0(0), 0x000072ff }, > + { DDRC_PCTRL_0(0), 0x00000001 }, > + { DDRC_PCFGQOS0_0(0), 0x01110d00 }, > + { DDRC_PCFGQOS1_0(0), 0x00620790 }, > + { DDRC_PCFGWQOS0_0(0), 0x00100001 }, > + { DDRC_PCFGWQOS1_0(0), 0x0000041f }, > + > + /* Frequency 1: 400mbps */ > + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, > + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, > + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, > + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, > + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, > + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, > + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, > + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, > + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, > + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, > + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, > + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, > + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, > + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, > + { DDRC_FREQ1_INIT3(0), 0x00840000 }, > + { DDRC_FREQ1_INIT4(0), 0x00310008 }, > + { DDRC_FREQ1_INIT6(0), 0x0066004a }, > + { DDRC_FREQ1_INIT7(0), 0x0006004a }, > + > + /* Frequency 2: 100mbps */ > + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, > + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, > + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, > + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, > + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, > + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, > + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, > + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, > + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, > + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, > + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, > + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, > + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, > + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, > + { DDRC_FREQ2_INIT3(0), 0x00840000 }, > + { DDRC_FREQ2_INIT4(0), 0x00310008 }, > + { DDRC_FREQ2_INIT6(0), 0x0066004a }, > + { DDRC_FREQ2_INIT7(0), 0x0006004a }, > +}; > + > +/* PHY Initialize Configuration */ > +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { > + { 0x20110, 0x02 }, > + { 0x20111, 0x03 }, > + { 0x20112, 0x04 }, > + { 0x20113, 0x05 }, > + { 0x20114, 0x00 }, > + { 0x20115, 0x01 }, > + > + { 0x1005f, 0x1ff }, > + { 0x1015f, 0x1ff }, > + { 0x1105f, 0x1ff }, > + { 0x1115f, 0x1ff }, > + { 0x1205f, 0x1ff }, > + { 0x1215f, 0x1ff }, > + { 0x1305f, 0x1ff }, > + { 0x1315f, 0x1ff }, > + > + { 0x11005f, 0x1ff }, > + { 0x11015f, 0x1ff }, > + { 0x11105f, 0x1ff }, > + { 0x11115f, 0x1ff }, > + { 0x11205f, 0x1ff }, > + { 0x11215f, 0x1ff }, > + { 0x11305f, 0x1ff }, > + { 0x11315f, 0x1ff }, > + > + { 0x21005f, 0x1ff }, > + { 0x21015f, 0x1ff }, > + { 0x21105f, 0x1ff }, > + { 0x21115f, 0x1ff }, > + { 0x21205f, 0x1ff }, > + { 0x21215f, 0x1ff }, > + { 0x21305f, 0x1ff }, > + { 0x21315f, 0x1ff }, > + > + { 0x55, 0x1ff }, > + { 0x1055, 0x1ff }, > + { 0x2055, 0x1ff }, > + { 0x3055, 0x1ff }, > + { 0x4055, 0x1ff }, > + { 0x5055, 0x1ff }, > + { 0x6055, 0x1ff }, > + { 0x7055, 0x1ff }, > + { 0x8055, 0x1ff }, > + { 0x9055, 0x1ff }, > + > + { 0x200c5, 0x19 }, > + { 0x1200c5, 0x7 }, > + { 0x2200c5, 0x7 }, > + > + { 0x2002e, 0x2 }, > + { 0x12002e, 0x2 }, > + { 0x22002e, 0x2 }, > + > + { 0x90204, 0x0 }, > + { 0x190204, 0x0 }, > + { 0x290204, 0x0 }, > + > +#ifdef WR_POST_EXT_3200 > + { 0x20024, 0xeb }, > +#else > + { 0x20024, 0xab }, > +#endif > + { 0x2003a, 0x0 }, > + { 0x120024, 0xab }, > + { 0x2003a, 0x0 }, > + { 0x220024, 0xab }, > + { 0x2003a, 0x0 }, > + { 0x20056, 0x3 }, > + { 0x120056, 0xa }, > + { 0x220056, 0xa }, > + { 0x1004d, 0xe00 }, > + { 0x1014d, 0xe00 }, > + { 0x1104d, 0xe00 }, > + { 0x1114d, 0xe00 }, > + { 0x1204d, 0xe00 }, > + { 0x1214d, 0xe00 }, > + { 0x1304d, 0xe00 }, > + { 0x1314d, 0xe00 }, > + { 0x11004d, 0xe00 }, > + { 0x11014d, 0xe00 }, > + { 0x11104d, 0xe00 }, > + { 0x11114d, 0xe00 }, > + { 0x11204d, 0xe00 }, > + { 0x11214d, 0xe00 }, > + { 0x11304d, 0xe00 }, > + { 0x11314d, 0xe00 }, > + { 0x21004d, 0xe00 }, > + { 0x21014d, 0xe00 }, > + { 0x21104d, 0xe00 }, > + { 0x21114d, 0xe00 }, > + { 0x21204d, 0xe00 }, > + { 0x21214d, 0xe00 }, > + { 0x21304d, 0xe00 }, > + { 0x21314d, 0xe00 }, > + > + { 0x10049, 0xfbe }, > + { 0x10149, 0xfbe }, > + { 0x11049, 0xfbe }, > + { 0x11149, 0xfbe }, > + { 0x12049, 0xfbe }, > + { 0x12149, 0xfbe }, > + { 0x13049, 0xfbe }, > + { 0x13149, 0xfbe }, > + { 0x110049, 0xfbe }, > + { 0x110149, 0xfbe }, > + { 0x111049, 0xfbe }, > + { 0x111149, 0xfbe }, > + { 0x112049, 0xfbe }, > + { 0x112149, 0xfbe }, > + { 0x113049, 0xfbe }, > + { 0x113149, 0xfbe }, > + { 0x210049, 0xfbe }, > + { 0x210149, 0xfbe }, > + { 0x211049, 0xfbe }, > + { 0x211149, 0xfbe }, > + { 0x212049, 0xfbe }, > + { 0x212149, 0xfbe }, > + { 0x213049, 0xfbe }, > + { 0x213149, 0xfbe }, > + > + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, > + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | > LPDDR4_PHY_ADDR_RON) }, > + > + { 0x20018, 0x3 }, > + { 0x20075, 0x4 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x320 }, > + { 0x120008, 0x64 }, > + { 0x220008, 0x19 }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x104 }, > + { 0x10043, 0x5a1 }, > + { 0x10143, 0x5a1 }, > + { 0x11043, 0x5a1 }, > + { 0x11143, 0x5a1 }, > + { 0x12043, 0x5a1 }, > + { 0x12143, 0x5a1 }, > + { 0x13043, 0x5a1 }, > + { 0x13143, 0x5a1 }, > + { 0x1200b2, 0x104 }, > + { 0x110043, 0x5a1 }, > + { 0x110143, 0x5a1 }, > + { 0x111043, 0x5a1 }, > + { 0x111143, 0x5a1 }, > + { 0x112043, 0x5a1 }, > + { 0x112143, 0x5a1 }, > + { 0x113043, 0x5a1 }, > + { 0x113143, 0x5a1 }, > + { 0x2200b2, 0x104 }, > + { 0x210043, 0x5a1 }, > + { 0x210143, 0x5a1 }, > + { 0x211043, 0x5a1 }, > + { 0x211143, 0x5a1 }, > + { 0x212043, 0x5a1 }, > + { 0x212143, 0x5a1 }, > + { 0x213043, 0x5a1 }, > + { 0x213143, 0x5a1 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x2200fa, 0x1 }, > + { 0x20019, 0x1 }, > + { 0x120019, 0x1 }, > + { 0x220019, 0x1 }, > + { 0x200f0, 0x660 }, > + { 0x200f1, 0x0 }, > + { 0x200f2, 0x4444 }, > + { 0x200f3, 0x8888 }, > + { 0x200f4, 0x5665 }, > + { 0x200f5, 0x0 }, > + { 0x200f6, 0x0 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2002d, 0x0 }, > + { 0x12002d, 0x0 }, > + { 0x22002d, 0x0 }, > + > + { 0x200c7, 0x80 }, > + { 0x1200c7, 0x80 }, > + { 0x2200c7, 0x80 }, > + { 0x200ca, 0x106 }, > + { 0x1200ca, 0x106 }, > + { 0x2200ca, 0x106 }, > +}; > + > +/* P0 message block paremeter for training firmware */ > +struct dram_cfg_param lpddr4_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x0 }, > + { 0x54003, 0xc80 }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY > Ron/Rtt */ > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, 0x131f }, > + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, 0x0 }, > + { 0x54010, 0x0 }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + > + { 0x54019, 0x2dd4 }, > +#ifdef WR_POST_EXT_3200 > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, > +#else > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, > +#endif > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0 }, > + { 0x5401f, 0x2dd4 }, > +#ifdef WR_POST_EXT_3200 > + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, > +#else > + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, > +#endif > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0xd400 }, > + /* MR3/MR2 */ > +#ifdef WR_POST_EXT_3200 > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, > +#else > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, > +#endif > + /* MR11/MR4 */ > + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, > + /* self:0x284d//MR13/MR12 */ > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, > + /* MR16/MR14*/ > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, > + /* MR1 */ > + { 0x54038, 0xd400 }, > + /* MR3/MR2 */ > +#ifdef WR_POST_EXT_3200 > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, > +#else > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, > +#endif > + /* MR11/MR4 */ > + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, > + /* self:0x284d//MR13/MR12 */ > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, > + /* MR16/MR14 */ > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, > + /* { 0x5403d, 0x500 } */ > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P1 message block paremeter for training firmware */ > +struct dram_cfg_param lpddr4_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x101 }, > + { 0x54003, 0x190 }, > + { 0x54004, 0x2 }, > + /* PHY Ron/Rtt */ > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, > + { 0x54009, LPDDR4_HDT_CTL_400_1D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, 0x0 }, > + { 0x54010, 0x0 }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54019, 0x84 }, > + /* MR4/MR3 */ > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, > + /* MR12/MR11 */ > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | > + LPDDR4_RTT_DQ)/*0x4d46*/ }, > + /* self:0x4d28//MR14/MR13 */ > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | > 0x08)/*0x4d08*/ }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, > + { 0x5401f, 0x84 }, > + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | > + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ > + /* self:0x4d28//MR14/MR13 */ > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | > 0x08)/*0x4d08*/ }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0x8400 }, > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, > + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, > + { 0x54038, 0x8400 }, > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, > + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P2 message block paremeter for training firmware */ > +struct dram_cfg_param lpddr4_fsp2_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x102 }, > + { 0x54003, 0x64 }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, > + { 0x54009, LPDDR4_HDT_CTL_100_1D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, 0x0 }, > + { 0x54010, 0x0 }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54019, 0x84 }, > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | > + LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0 }, > + { 0x5401f, 0x84 }, > + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | > + LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0x8400 }, > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, > + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, > + { 0x54038, 0x8400 }, > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, > + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P0 2D message block paremeter for training firmware */ > +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x0 }, > + { 0x54003, 0xc80 }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, 0x61 }, > + { 0x54009, LPDDR4_HDT_CTL_2D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, > + { 0x54010, LPDDR4_2D_WEIGHT }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54019, 0x2dd4 }, > +#ifdef WR_POST_EXT_3200 > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, > +#else > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, > +#endif > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0 }, > + { 0x5401f, 0x2dd4 }, > +#ifdef WR_POST_EXT_3200 > + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, > +#else > + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, > +#endif > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + > + { 0x54032, 0xd400 }, > +#ifdef WR_POST_EXT_3200 > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > +#else > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, > +#endif > + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, > + { 0x54038, 0xd400 }, > +#ifdef WR_POST_EXT_3200 > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > +#else > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, > +#endif > + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* DRAM PHY init engine image */ > +struct dram_cfg_param lpddr4_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x0 }, > + { 0x90033, 0xe8 }, > + { 0x90034, 0x109 }, > + { 0x90035, 0x2 }, > + { 0x90036, 0x10 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0xf }, > + { 0x90039, 0x7c0 }, > + { 0x9003a, 0x139 }, > + { 0x9003b, 0x44 }, > + { 0x9003c, 0x630 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x14f }, > + { 0x9003f, 0x630 }, > + { 0x90040, 0x159 }, > + { 0x90041, 0x47 }, > + { 0x90042, 0x630 }, > + { 0x90043, 0x149 }, > + { 0x90044, 0x4f }, > + { 0x90045, 0x630 }, > + { 0x90046, 0x179 }, > + { 0x90047, 0x8 }, > + { 0x90048, 0xe0 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x7c8 }, > + { 0x9004c, 0x109 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x1 }, > + { 0x9004f, 0x8 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x45a }, > + { 0x90052, 0x9 }, > + { 0x90053, 0x0 }, > + { 0x90054, 0x448 }, > + { 0x90055, 0x109 }, > + { 0x90056, 0x40 }, > + { 0x90057, 0x630 }, > + { 0x90058, 0x179 }, > + { 0x90059, 0x1 }, > + { 0x9005a, 0x618 }, > + { 0x9005b, 0x109 }, > + { 0x9005c, 0x40c0 }, > + { 0x9005d, 0x630 }, > + { 0x9005e, 0x149 }, > + { 0x9005f, 0x8 }, > + { 0x90060, 0x4 }, > + { 0x90061, 0x48 }, > + { 0x90062, 0x4040 }, > + { 0x90063, 0x630 }, > + { 0x90064, 0x149 }, > + { 0x90065, 0x0 }, > + { 0x90066, 0x4 }, > + { 0x90067, 0x48 }, > + { 0x90068, 0x40 }, > + { 0x90069, 0x630 }, > + { 0x9006a, 0x149 }, > + { 0x9006b, 0x10 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x18 }, > + { 0x9006e, 0x0 }, > + { 0x9006f, 0x4 }, > + { 0x90070, 0x78 }, > + { 0x90071, 0x549 }, > + { 0x90072, 0x630 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0xd49 }, > + { 0x90075, 0x630 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x94a }, > + { 0x90078, 0x630 }, > + { 0x90079, 0x159 }, > + { 0x9007a, 0x441 }, > + { 0x9007b, 0x630 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x42 }, > + { 0x9007e, 0x630 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x1 }, > + { 0x90081, 0x630 }, > + { 0x90082, 0x149 }, > + { 0x90083, 0x0 }, > + { 0x90084, 0xe0 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0xa }, > + { 0x90087, 0x10 }, > + { 0x90088, 0x109 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x149 }, > + { 0x9008c, 0x9 }, > + { 0x9008d, 0x3c0 }, > + { 0x9008e, 0x159 }, > + { 0x9008f, 0x18 }, > + { 0x90090, 0x10 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x0 }, > + { 0x90093, 0x3c0 }, > + { 0x90094, 0x109 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x48 }, > + { 0x90098, 0x18 }, > + { 0x90099, 0x4 }, > + { 0x9009a, 0x58 }, > + { 0x9009b, 0xa }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x2 }, > + { 0x9009f, 0x10 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x5 }, > + { 0x900a2, 0x7c0 }, > + { 0x900a3, 0x109 }, > + { 0x900a4, 0x10 }, > + { 0x900a5, 0x10 }, > + { 0x900a6, 0x109 }, > + { 0x40000, 0x811 }, > + { 0x40020, 0x880 }, > + { 0x40040, 0x0 }, > + { 0x40060, 0x0 }, > + { 0x40001, 0x4008 }, > + { 0x40021, 0x83 }, > + { 0x40041, 0x4f }, > + { 0x40061, 0x0 }, > + { 0x40002, 0x4040 }, > + { 0x40022, 0x83 }, > + { 0x40042, 0x51 }, > + { 0x40062, 0x0 }, > + { 0x40003, 0x811 }, > + { 0x40023, 0x880 }, > + { 0x40043, 0x0 }, > + { 0x40063, 0x0 }, > + { 0x40004, 0x720 }, > + { 0x40024, 0xf }, > + { 0x40044, 0x1740 }, > + { 0x40064, 0x0 }, > + { 0x40005, 0x16 }, > + { 0x40025, 0x83 }, > + { 0x40045, 0x4b }, > + { 0x40065, 0x0 }, > + { 0x40006, 0x716 }, > + { 0x40026, 0xf }, > + { 0x40046, 0x2001 }, > + { 0x40066, 0x0 }, > + { 0x40007, 0x716 }, > + { 0x40027, 0xf }, > + { 0x40047, 0x2800 }, > + { 0x40067, 0x0 }, > + { 0x40008, 0x716 }, > + { 0x40028, 0xf }, > + { 0x40048, 0xf00 }, > + { 0x40068, 0x0 }, > + { 0x40009, 0x720 }, > + { 0x40029, 0xf }, > + { 0x40049, 0x1400 }, > + { 0x40069, 0x0 }, > + { 0x4000a, 0xe08 }, > + { 0x4002a, 0xc15 }, > + { 0x4004a, 0x0 }, > + { 0x4006a, 0x0 }, > + { 0x4000b, 0x623 }, > + { 0x4002b, 0x15 }, > + { 0x4004b, 0x0 }, > + { 0x4006b, 0x0 }, > + { 0x4000c, 0x4028 }, > + { 0x4002c, 0x80 }, > + { 0x4004c, 0x0 }, > + { 0x4006c, 0x0 }, > + { 0x4000d, 0xe08 }, > + { 0x4002d, 0xc1a }, > + { 0x4004d, 0x0 }, > + { 0x4006d, 0x0 }, > + { 0x4000e, 0x623 }, > + { 0x4002e, 0x1a }, > + { 0x4004e, 0x0 }, > + { 0x4006e, 0x0 }, > + { 0x4000f, 0x4040 }, > + { 0x4002f, 0x80 }, > + { 0x4004f, 0x0 }, > + { 0x4006f, 0x0 }, > + { 0x40010, 0x2604 }, > + { 0x40030, 0x15 }, > + { 0x40050, 0x0 }, > + { 0x40070, 0x0 }, > + { 0x40011, 0x708 }, > + { 0x40031, 0x5 }, > + { 0x40051, 0x0 }, > + { 0x40071, 0x2002 }, > + { 0x40012, 0x8 }, > + { 0x40032, 0x80 }, > + { 0x40052, 0x0 }, > + { 0x40072, 0x0 }, > + { 0x40013, 0x2604 }, > + { 0x40033, 0x1a }, > + { 0x40053, 0x0 }, > + { 0x40073, 0x0 }, > + { 0x40014, 0x708 }, > + { 0x40034, 0xa }, > + { 0x40054, 0x0 }, > + { 0x40074, 0x2002 }, > + { 0x40015, 0x4040 }, > + { 0x40035, 0x80 }, > + { 0x40055, 0x0 }, > + { 0x40075, 0x0 }, > + { 0x40016, 0x60a }, > + { 0x40036, 0x15 }, > + { 0x40056, 0x1200 }, > + { 0x40076, 0x0 }, > + { 0x40017, 0x61a }, > + { 0x40037, 0x15 }, > + { 0x40057, 0x1300 }, > + { 0x40077, 0x0 }, > + { 0x40018, 0x60a }, > + { 0x40038, 0x1a }, > + { 0x40058, 0x1200 }, > + { 0x40078, 0x0 }, > + { 0x40019, 0x642 }, > + { 0x40039, 0x1a }, > + { 0x40059, 0x1300 }, > + { 0x40079, 0x0 }, > + { 0x4001a, 0x4808 }, > + { 0x4003a, 0x880 }, > + { 0x4005a, 0x0 }, > + { 0x4007a, 0x0 }, > + { 0x900a7, 0x0 }, > + { 0x900a8, 0x790 }, > + { 0x900a9, 0x11a }, > + { 0x900aa, 0x8 }, > + { 0x900ab, 0x7aa }, > + { 0x900ac, 0x2a }, > + { 0x900ad, 0x10 }, > + { 0x900ae, 0x7b2 }, > + { 0x900af, 0x2a }, > + { 0x900b0, 0x0 }, > + { 0x900b1, 0x7c8 }, > + { 0x900b2, 0x109 }, > + { 0x900b3, 0x10 }, > + { 0x900b4, 0x2a8 }, > + { 0x900b5, 0x129 }, > + { 0x900b6, 0x8 }, > + { 0x900b7, 0x370 }, > + { 0x900b8, 0x129 }, > + { 0x900b9, 0xa }, > + { 0x900ba, 0x3c8 }, > + { 0x900bb, 0x1a9 }, > + { 0x900bc, 0xc }, > + { 0x900bd, 0x408 }, > + { 0x900be, 0x199 }, > + { 0x900bf, 0x14 }, > + { 0x900c0, 0x790 }, > + { 0x900c1, 0x11a }, > + { 0x900c2, 0x8 }, > + { 0x900c3, 0x4 }, > + { 0x900c4, 0x18 }, > + { 0x900c5, 0xe }, > + { 0x900c6, 0x408 }, > + { 0x900c7, 0x199 }, > + { 0x900c8, 0x8 }, > + { 0x900c9, 0x8568 }, > + { 0x900ca, 0x108 }, > + { 0x900cb, 0x18 }, > + { 0x900cc, 0x790 }, > + { 0x900cd, 0x16a }, > + { 0x900ce, 0x8 }, > + { 0x900cf, 0x1d8 }, > + { 0x900d0, 0x169 }, > + { 0x900d1, 0x10 }, > + { 0x900d2, 0x8558 }, > + { 0x900d3, 0x168 }, > + { 0x900d4, 0x70 }, > + { 0x900d5, 0x788 }, > + { 0x900d6, 0x16a }, > + { 0x900d7, 0x1ff8 }, > + { 0x900d8, 0x85a8 }, > + { 0x900d9, 0x1e8 }, > + { 0x900da, 0x50 }, > + { 0x900db, 0x798 }, > + { 0x900dc, 0x16a }, > + { 0x900dd, 0x60 }, > + { 0x900de, 0x7a0 }, > + { 0x900df, 0x16a }, > + { 0x900e0, 0x8 }, > + { 0x900e1, 0x8310 }, > + { 0x900e2, 0x168 }, > + { 0x900e3, 0x8 }, > + { 0x900e4, 0xa310 }, > + { 0x900e5, 0x168 }, > + { 0x900e6, 0xa }, > + { 0x900e7, 0x408 }, > + { 0x900e8, 0x169 }, > + { 0x900e9, 0x6e }, > + { 0x900ea, 0x0 }, > + { 0x900eb, 0x68 }, > + { 0x900ec, 0x0 }, > + { 0x900ed, 0x408 }, > + { 0x900ee, 0x169 }, > + { 0x900ef, 0x0 }, > + { 0x900f0, 0x8310 }, > + { 0x900f1, 0x168 }, > + { 0x900f2, 0x0 }, > + { 0x900f3, 0xa310 }, > + { 0x900f4, 0x168 }, > + { 0x900f5, 0x1ff8 }, > + { 0x900f6, 0x85a8 }, > + { 0x900f7, 0x1e8 }, > + { 0x900f8, 0x68 }, > + { 0x900f9, 0x798 }, > + { 0x900fa, 0x16a }, > + { 0x900fb, 0x78 }, > + { 0x900fc, 0x7a0 }, > + { 0x900fd, 0x16a }, > + { 0x900fe, 0x68 }, > + { 0x900ff, 0x790 }, > + { 0x90100, 0x16a }, > + { 0x90101, 0x8 }, > + { 0x90102, 0x8b10 }, > + { 0x90103, 0x168 }, > + { 0x90104, 0x8 }, > + { 0x90105, 0xab10 }, > + { 0x90106, 0x168 }, > + { 0x90107, 0xa }, > + { 0x90108, 0x408 }, > + { 0x90109, 0x169 }, > + { 0x9010a, 0x58 }, > + { 0x9010b, 0x0 }, > + { 0x9010c, 0x68 }, > + { 0x9010d, 0x0 }, > + { 0x9010e, 0x408 }, > + { 0x9010f, 0x169 }, > + { 0x90110, 0x0 }, > + { 0x90111, 0x8b10 }, > + { 0x90112, 0x168 }, > + { 0x90113, 0x0 }, > + { 0x90114, 0xab10 }, > + { 0x90115, 0x168 }, > + { 0x90116, 0x0 }, > + { 0x90117, 0x1d8 }, > + { 0x90118, 0x169 }, > + { 0x90119, 0x80 }, > + { 0x9011a, 0x790 }, > + { 0x9011b, 0x16a }, > + { 0x9011c, 0x18 }, > + { 0x9011d, 0x7aa }, > + { 0x9011e, 0x6a }, > + { 0x9011f, 0xa }, > + { 0x90120, 0x0 }, > + { 0x90121, 0x1e9 }, > + { 0x90122, 0x8 }, > + { 0x90123, 0x8080 }, > + { 0x90124, 0x108 }, > + { 0x90125, 0xf }, > + { 0x90126, 0x408 }, > + { 0x90127, 0x169 }, > + { 0x90128, 0xc }, > + { 0x90129, 0x0 }, > + { 0x9012a, 0x68 }, > + { 0x9012b, 0x9 }, > + { 0x9012c, 0x0 }, > + { 0x9012d, 0x1a9 }, > + { 0x9012e, 0x0 }, > + { 0x9012f, 0x408 }, > + { 0x90130, 0x169 }, > + { 0x90131, 0x0 }, > + { 0x90132, 0x8080 }, > + { 0x90133, 0x108 }, > + { 0x90134, 0x8 }, > + { 0x90135, 0x7aa }, > + { 0x90136, 0x6a }, > + { 0x90137, 0x0 }, > + { 0x90138, 0x8568 }, > + { 0x90139, 0x108 }, > + { 0x9013a, 0xb7 }, > + { 0x9013b, 0x790 }, > + { 0x9013c, 0x16a }, > + { 0x9013d, 0x1f }, > + { 0x9013e, 0x0 }, > + { 0x9013f, 0x68 }, > + { 0x90140, 0x8 }, > + { 0x90141, 0x8558 }, > + { 0x90142, 0x168 }, > + { 0x90143, 0xf }, > + { 0x90144, 0x408 }, > + { 0x90145, 0x169 }, > + { 0x90146, 0xc }, > + { 0x90147, 0x0 }, > + { 0x90148, 0x68 }, > + { 0x90149, 0x0 }, > + { 0x9014a, 0x408 }, > + { 0x9014b, 0x169 }, > + { 0x9014c, 0x0 }, > + { 0x9014d, 0x8558 }, > + { 0x9014e, 0x168 }, > + { 0x9014f, 0x8 }, > + { 0x90150, 0x3c8 }, > + { 0x90151, 0x1a9 }, > + { 0x90152, 0x3 }, > + { 0x90153, 0x370 }, > + { 0x90154, 0x129 }, > + { 0x90155, 0x20 }, > + { 0x90156, 0x2aa }, > + { 0x90157, 0x9 }, > + { 0x90158, 0x0 }, > + { 0x90159, 0x400 }, > + { 0x9015a, 0x10e }, > + { 0x9015b, 0x8 }, > + { 0x9015c, 0xe8 }, > + { 0x9015d, 0x109 }, > + { 0x9015e, 0x0 }, > + { 0x9015f, 0x8140 }, > + { 0x90160, 0x10c }, > + { 0x90161, 0x10 }, > + { 0x90162, 0x8138 }, > + { 0x90163, 0x10c }, > + { 0x90164, 0x8 }, > + { 0x90165, 0x7c8 }, > + { 0x90166, 0x101 }, > + { 0x90167, 0x8 }, > + { 0x90168, 0x0 }, > + { 0x90169, 0x8 }, > + { 0x9016a, 0x8 }, > + { 0x9016b, 0x448 }, > + { 0x9016c, 0x109 }, > + { 0x9016d, 0xf }, > + { 0x9016e, 0x7c0 }, > + { 0x9016f, 0x109 }, > + { 0x90170, 0x0 }, > + { 0x90171, 0xe8 }, > + { 0x90172, 0x109 }, > + { 0x90173, 0x47 }, > + { 0x90174, 0x630 }, > + { 0x90175, 0x109 }, > + { 0x90176, 0x8 }, > + { 0x90177, 0x618 }, > + { 0x90178, 0x109 }, > + { 0x90179, 0x8 }, > + { 0x9017a, 0xe0 }, > + { 0x9017b, 0x109 }, > + { 0x9017c, 0x0 }, > + { 0x9017d, 0x7c8 }, > + { 0x9017e, 0x109 }, > + { 0x9017f, 0x8 }, > + { 0x90180, 0x8140 }, > + { 0x90181, 0x10c }, > + { 0x90182, 0x0 }, > + { 0x90183, 0x1 }, > + { 0x90184, 0x8 }, > + { 0x90185, 0x8 }, > + { 0x90186, 0x4 }, > + { 0x90187, 0x8 }, > + { 0x90188, 0x8 }, > + { 0x90189, 0x7c8 }, > + { 0x9018a, 0x101 }, > + { 0x90006, 0x0 }, > + { 0x90007, 0x0 }, > + { 0x90008, 0x8 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x0 }, > + { 0x9000b, 0x0 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x9001f, 0x2a }, > + { 0x90026, 0x6a }, > + { 0x400d0, 0x0 }, > + { 0x400d1, 0x101 }, > + { 0x400d2, 0x105 }, > + { 0x400d3, 0x107 }, > + { 0x400d4, 0x10f }, > + { 0x400d5, 0x202 }, > + { 0x400d6, 0x20a }, > + { 0x400d7, 0x20b }, > + { 0x2003a, 0x2 }, > + { 0x2000b, 0x64 }, > + { 0x2000c, 0xc8 }, > + { 0x2000d, 0x7d0 }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0xc }, > + { 0x12000c, 0x19 }, > + { 0x12000d, 0xfa }, > + { 0x12000e, 0x10 }, > + { 0x22000b, 0x3 }, > + { 0x22000c, 0x6 }, > + { 0x22000d, 0x3e }, > + { 0x22000e, 0x10 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0x60 }, > + { 0x90013, 0x6152 }, > + { 0x20010, 0x5a }, > + { 0x20011, 0x3 }, > + { 0x40080, 0xe0 }, > + { 0x40081, 0x12 }, > + { 0x40082, 0xe0 }, > + { 0x40083, 0x12 }, > + { 0x40084, 0xe0 }, > + { 0x40085, 0x12 }, > + { 0x140080, 0xe0 }, > + { 0x140081, 0x12 }, > + { 0x140082, 0xe0 }, > + { 0x140083, 0x12 }, > + { 0x140084, 0xe0 }, > + { 0x140085, 0x12 }, > + { 0x240080, 0xe0 }, > + { 0x240081, 0x12 }, > + { 0x240082, 0xe0 }, > + { 0x240083, 0x12 }, > + { 0x240084, 0xe0 }, > + { 0x240085, 0x12 }, > + { 0x400fd, 0xf }, > + { 0x10011, 0x1 }, > + { 0x10012, 0x1 }, > + { 0x10013, 0x180 }, > + { 0x10018, 0x1 }, > + { 0x10002, 0x6209 }, > + { 0x100b2, 0x1 }, > + { 0x101b4, 0x1 }, > + { 0x102b4, 0x1 }, > + { 0x103b4, 0x1 }, > + { 0x104b4, 0x1 }, > + { 0x105b4, 0x1 }, > + { 0x106b4, 0x1 }, > + { 0x107b4, 0x1 }, > + { 0x108b4, 0x1 }, > + { 0x11011, 0x1 }, > + { 0x11012, 0x1 }, > + { 0x11013, 0x180 }, > + { 0x11018, 0x1 }, > + { 0x11002, 0x6209 }, > + { 0x110b2, 0x1 }, > + { 0x111b4, 0x1 }, > + { 0x112b4, 0x1 }, > + { 0x113b4, 0x1 }, > + { 0x114b4, 0x1 }, > + { 0x115b4, 0x1 }, > + { 0x116b4, 0x1 }, > + { 0x117b4, 0x1 }, > + { 0x118b4, 0x1 }, > + { 0x12011, 0x1 }, > + { 0x12012, 0x1 }, > + { 0x12013, 0x180 }, > + { 0x12018, 0x1 }, > + { 0x12002, 0x6209 }, > + { 0x120b2, 0x1 }, > + { 0x121b4, 0x1 }, > + { 0x122b4, 0x1 }, > + { 0x123b4, 0x1 }, > + { 0x124b4, 0x1 }, > + { 0x125b4, 0x1 }, > + { 0x126b4, 0x1 }, > + { 0x127b4, 0x1 }, > + { 0x128b4, 0x1 }, > + { 0x13011, 0x1 }, > + { 0x13012, 0x1 }, > + { 0x13013, 0x180 }, > + { 0x13018, 0x1 }, > + { 0x13002, 0x6209 }, > + { 0x130b2, 0x1 }, > + { 0x131b4, 0x1 }, > + { 0x132b4, 0x1 }, > + { 0x133b4, 0x1 }, > + { 0x134b4, 0x1 }, > + { 0x135b4, 0x1 }, > + { 0x136b4, 0x1 }, > + { 0x137b4, 0x1 }, > + { 0x138b4, 0x1 }, > + { 0x2003a, 0x2 }, > + { 0xc0080, 0x2 }, > + { 0xd0000, 0x1 }, > +}; > + > +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > + { > + /* P0 3200mts 1D */ > + .drate = 3200, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), > + }, > + { > + /* P1 400mts 1D */ > + .drate = 400, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = lpddr4_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), > + }, > + { > + /* P1 100mts 1D */ > + .drate = 100, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = lpddr4_fsp2_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), > + }, > + { > + /* P0 3200mts 2D */ > + .drate = 3200, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > + }, > +}; > + > +/* lpddr4 timing config params on EVK board */ > +struct dram_timing_info dram_timing = { > + .ddrc_cfg = lpddr4_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), > + .ddrphy_cfg = lpddr4_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), > + .fsp_msg = lpddr4_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), > + .ddrphy_pie = lpddr4_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), > + .fsp_table = { 3200, 400, 100, }, > +}; > diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c > b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c > new file mode 100644 > index 0000000000..ec68edaf69 > --- /dev/null > +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c > @@ -0,0 +1,1191 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + */ > + > +#include <linux/kernel.h> > +#include <common.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/lpddr4_define.h> > + > +#define WR_POST_EXT_3200 /* recommened to define */ > + > +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { > + /* Start to config, default 3200mbps */ > + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ > + { DDRC_DBG1(0), 0x00000001 }, > + /* selfref_en=1, SDRAM enter self-refresh state */ > + { DDRC_PWRCTL(0), 0x00000001 }, > + { DDRC_MSTR(0), 0xa3080020 }, > + { DDRC_MSTR2(0), 0x00000000 }, > + { DDRC_RFSHTMG(0), 0x006100E0 }, > + { DDRC_INIT0(0), 0xC003061B }, > + { DDRC_INIT1(0), 0x009D0000 }, > + { DDRC_INIT3(0), 0x00D4002D }, > +#ifdef WR_POST_EXT_3200 /* recommened to define */ > + { DDRC_INIT4(0), 0x00330008 }, > +#else > + { DDRC_INIT4(0), 0x00310008 }, > +#endif > + { DDRC_INIT6(0), 0x0066004a }, > + { DDRC_INIT7(0), 0x0006004a }, > + > + { DDRC_DRAMTMG0(0), 0x1A201B22 }, > + { DDRC_DRAMTMG1(0), 0x00060633 }, > + { DDRC_DRAMTMG3(0), 0x00C0C000 }, > + { DDRC_DRAMTMG4(0), 0x0F04080F }, > + { DDRC_DRAMTMG5(0), 0x02040C0C }, > + { DDRC_DRAMTMG6(0), 0x01010007 }, > + { DDRC_DRAMTMG7(0), 0x00000401 }, > + { DDRC_DRAMTMG12(0), 0x00020600 }, > + { DDRC_DRAMTMG13(0), 0x0C100002 }, > + { DDRC_DRAMTMG14(0), 0x000000E6 }, > + { DDRC_DRAMTMG17(0), 0x00A00050 }, > + > + { DDRC_ZQCTL0(0), 0x03200018 }, > + { DDRC_ZQCTL1(0), 0x028061A8 }, > + { DDRC_ZQCTL2(0), 0x00000000 }, > + > + { DDRC_DFITMG0(0), 0x0497820A }, > + { DDRC_DFITMG1(0), 0x00080303 }, > + { DDRC_DFIUPD0(0), 0xE0400018 }, > + { DDRC_DFIUPD1(0), 0x00DF00E4 }, > + { DDRC_DFIUPD2(0), 0x80000000 }, > + { DDRC_DFIMISC(0), 0x00000011 }, > + { DDRC_DFITMG2(0), 0x0000170A }, > + > + { DDRC_DBICTL(0), 0x00000001 }, > + { DDRC_DFIPHYMSTR(0), 0x00000001 }, > + > + /* need be refined by ddrphy trained value */ > + { DDRC_RANKCTL(0), 0x00000c99 }, > + { DDRC_DRAMTMG2(0), 0x070E171a }, > + > + /* address mapping */ > + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ > + { DDRC_ADDRMAP0(0), 0x00000015 }, > + { DDRC_ADDRMAP3(0), 0x00000000 }, > + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) > */ > + { DDRC_ADDRMAP4(0), 0x00001F1F }, > + /* bank interleave */ > + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ > + { DDRC_ADDRMAP1(0), 0x00080808 }, > + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 > addrmap_row_b0 */ > + { DDRC_ADDRMAP5(0), 0x07070707 }, > + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 > addrmap_row_b12 */ > + { DDRC_ADDRMAP6(0), 0x08080707 }, > + > + /* 667mts frequency setting */ > + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, > + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, > + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, > + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, > + { DDRC_FREQ1_INIT3(0), 0x0140009 }, > + { DDRC_FREQ1_INIT4(0), 0x00310008 }, > + { DDRC_FREQ1_INIT6(0), 0x0066004a }, > + { DDRC_FREQ1_INIT7(0), 0x0006004a }, > + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, > + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, > + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, > + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, > + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, > + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, > + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, > + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, > + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, > + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, > + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, > + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, > + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, > + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, > + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, > + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, > + > + /* performance setting */ > + { DDRC_ODTCFG(0), 0x0b060908 }, > + { DDRC_ODTMAP(0), 0x00000000 }, > + { DDRC_SCHED(0), 0x29511505 }, > + { DDRC_SCHED1(0), 0x0000002c }, > + { DDRC_PERFHPR1(0), 0x5900575b }, > + /* 150T starve and 0x90 max tran len */ > + { DDRC_PERFLPR1(0), 0x90000096 }, > + /* 300T starve and 0x10 max tran len */ > + { DDRC_PERFWR1(0), 0x1000012c }, > + { DDRC_DBG0(0), 0x00000016 }, > + { DDRC_DBG1(0), 0x00000000 }, > + { DDRC_DBGCMD(0), 0x00000000 }, > + { DDRC_SWCTL(0), 0x00000001 }, > + { DDRC_POISONCFG(0), 0x00000011 }, > + { DDRC_PCCFG(0), 0x00000111 }, > + { DDRC_PCFGR_0(0), 0x000010f3 }, > + { DDRC_PCFGW_0(0), 0x000072ff }, > + { DDRC_PCTRL_0(0), 0x00000001 }, > + /* disable Read Qos*/ > + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, > + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, > + /* disable Write Qos*/ > + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, > + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, > + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, > + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, > + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, > + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, > +}; > + > +/* PHY Initialize Configuration */ > +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { > + { 0x20110, 0x02 }, /* MapCAB0toDFI */ > + { 0x20111, 0x03 }, /* MapCAB1toDFI */ > + { 0x20112, 0x04 }, /* MapCAB2toDFI */ > + { 0x20113, 0x05 }, /* MapCAB3toDFI */ > + { 0x20114, 0x00 }, /* MapCAB4toDFI */ > + { 0x20115, 0x01 }, /* MapCAB5toDFI */ > + > + /* Initialize PHY Configuration */ > + { 0x1005f, 0x1ff }, > + { 0x1015f, 0x1ff }, > + { 0x1105f, 0x1ff }, > + { 0x1115f, 0x1ff }, > + { 0x1205f, 0x1ff }, > + { 0x1215f, 0x1ff }, > + { 0x1305f, 0x1ff }, > + { 0x1315f, 0x1ff }, > + > + { 0x11005f, 0x1ff }, > + { 0x11015f, 0x1ff }, > + { 0x11105f, 0x1ff }, > + { 0x11115f, 0x1ff }, > + { 0x11205f, 0x1ff }, > + { 0x11215f, 0x1ff }, > + { 0x11305f, 0x1ff }, > + { 0x11315f, 0x1ff }, > + > + { 0x21005f, 0x1ff }, > + { 0x21015f, 0x1ff }, > + { 0x21105f, 0x1ff }, > + { 0x21115f, 0x1ff }, > + { 0x21205f, 0x1ff }, > + { 0x21215f, 0x1ff }, > + { 0x21305f, 0x1ff }, > + { 0x21315f, 0x1ff }, > + > + { 0x55, 0x1ff }, > + { 0x1055, 0x1ff }, > + { 0x2055, 0x1ff }, > + { 0x3055, 0x1ff }, > + { 0x4055, 0x1ff }, > + { 0x5055, 0x1ff }, > + { 0x6055, 0x1ff }, > + { 0x7055, 0x1ff }, > + { 0x8055, 0x1ff }, > + { 0x9055, 0x1ff }, > + { 0x200c5, 0x19 }, > + { 0x1200c5, 0x7 }, > + { 0x2200c5, 0x7 }, > + { 0x2002e, 0x2 }, > + { 0x12002e, 0x1 }, > + { 0x22002e, 0x2 }, > + { 0x90204, 0x0 }, > + { 0x190204, 0x0 }, > + { 0x290204, 0x0 }, > + > + { 0x20024, 0xe3 }, > + { 0x2003a, 0x2 }, > + { 0x120024, 0xa3 }, > + { 0x2003a, 0x2 }, > + { 0x220024, 0xa3 }, > + { 0x2003a, 0x2 }, > + > + { 0x20056, 0x3 }, > + { 0x120056, 0xa }, > + { 0x220056, 0xa }, > + > + { 0x1004d, 0xe00 }, > + { 0x1014d, 0xe00 }, > + { 0x1104d, 0xe00 }, > + { 0x1114d, 0xe00 }, > + { 0x1204d, 0xe00 }, > + { 0x1214d, 0xe00 }, > + { 0x1304d, 0xe00 }, > + { 0x1314d, 0xe00 }, > + { 0x11004d, 0xe00 }, > + { 0x11014d, 0xe00 }, > + { 0x11104d, 0xe00 }, > + { 0x11114d, 0xe00 }, > + { 0x11204d, 0xe00 }, > + { 0x11214d, 0xe00 }, > + { 0x11304d, 0xe00 }, > + { 0x11314d, 0xe00 }, > + { 0x21004d, 0xe00 }, > + { 0x21014d, 0xe00 }, > + { 0x21104d, 0xe00 }, > + { 0x21114d, 0xe00 }, > + { 0x21204d, 0xe00 }, > + { 0x21214d, 0xe00 }, > + { 0x21304d, 0xe00 }, > + { 0x21314d, 0xe00 }, > + > + { 0x10049, 0xfbe }, > + { 0x10149, 0xfbe }, > + { 0x11049, 0xfbe }, > + { 0x11149, 0xfbe }, > + { 0x12049, 0xfbe }, > + { 0x12149, 0xfbe }, > + { 0x13049, 0xfbe }, > + { 0x13149, 0xfbe }, > + > + { 0x110049, 0xfbe }, > + { 0x110149, 0xfbe }, > + { 0x111049, 0xfbe }, > + { 0x111149, 0xfbe }, > + { 0x112049, 0xfbe }, > + { 0x112149, 0xfbe }, > + { 0x113049, 0xfbe }, > + { 0x113149, 0xfbe }, > + > + { 0x210049, 0xfbe }, > + { 0x210149, 0xfbe }, > + { 0x211049, 0xfbe }, > + { 0x211149, 0xfbe }, > + { 0x212049, 0xfbe }, > + { 0x212149, 0xfbe }, > + { 0x213049, 0xfbe }, > + { 0x213149, 0xfbe }, > + > + { 0x43, 0x63 }, > + { 0x1043, 0x63 }, > + { 0x2043, 0x63 }, > + { 0x3043, 0x63 }, > + { 0x4043, 0x63 }, > + { 0x5043, 0x63 }, > + { 0x6043, 0x63 }, > + { 0x7043, 0x63 }, > + { 0x8043, 0x63 }, > + { 0x9043, 0x63 }, > + > + { 0x20018, 0x3 }, > + { 0x20075, 0x4 }, > + { 0x20050, 0x0 }, > + { 0x20008, 0x320 }, > + { 0x120008, 0xa7 }, > + { 0x220008, 0x19 }, > + { 0x20088, 0x9 }, > + { 0x200b2, 0x104 }, > + { 0x10043, 0x5a1 }, > + { 0x10143, 0x5a1 }, > + { 0x11043, 0x5a1 }, > + { 0x11143, 0x5a1 }, > + { 0x12043, 0x5a1 }, > + { 0x12143, 0x5a1 }, > + { 0x13043, 0x5a1 }, > + { 0x13143, 0x5a1 }, > + { 0x1200b2, 0x104 }, > + { 0x110043, 0x5a1 }, > + { 0x110143, 0x5a1 }, > + { 0x111043, 0x5a1 }, > + { 0x111143, 0x5a1 }, > + { 0x112043, 0x5a1 }, > + { 0x112143, 0x5a1 }, > + { 0x113043, 0x5a1 }, > + { 0x113143, 0x5a1 }, > + { 0x2200b2, 0x104 }, > + { 0x210043, 0x5a1 }, > + { 0x210143, 0x5a1 }, > + { 0x211043, 0x5a1 }, > + { 0x211143, 0x5a1 }, > + { 0x212043, 0x5a1 }, > + { 0x212143, 0x5a1 }, > + { 0x213043, 0x5a1 }, > + { 0x213143, 0x5a1 }, > + { 0x200fa, 0x1 }, > + { 0x1200fa, 0x1 }, > + { 0x2200fa, 0x1 }, > + { 0x20019, 0x1 }, > + { 0x120019, 0x1 }, > + { 0x220019, 0x1 }, > + { 0x200f0, 0x600 }, > + { 0x200f1, 0x0 }, > + { 0x200f2, 0x4444 }, > + { 0x200f3, 0x8888 }, > + { 0x200f4, 0x5655 }, > + { 0x200f5, 0x0 }, > + { 0x200f6, 0x0 }, > + { 0x200f7, 0xf000 }, > + { 0x20025, 0x0 }, > + { 0x2002d, 0x0 }, > + { 0x12002d, 0x0 }, > + { 0x22002d, 0x0 }, > +}; > + > +/* P0 message block paremeter for training firmware */ > +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x0 }, > + { 0x54003, 0xc80 }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, 0x131f }, > + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, 0x0 }, > + { 0x54010, 0x0 }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54019, 0x2dd4 }, > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0 }, > + { 0x5401f, 0x2dd4 }, > + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0xd400 }, > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, > + { 0x54038, 0xd400 }, > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > +}; > + > +/* P1 message block paremeter for training firmware */ > +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x1 }, > + { 0x54003, 0x29c }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, 0x121f }, > + { 0x54009, 0xc8 }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, 0x0 }, > + { 0x5400e, 0x0 }, > + { 0x5400f, 0x0 }, > + { 0x54010, 0x0 }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54019, 0x914 }, > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401e, 0x6 }, > + { 0x5401f, 0x914 }, > + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0x1400 }, > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, > + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, 0x600 }, > + { 0x54038, 0x1400 }, > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, > + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0xd0000, 0x1 }, > + > +}; > + > +/* P0 2D message block paremeter for training firmware */ > +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { > + { 0xd0000, 0x0 }, > + { 0x54000, 0x0 }, > + { 0x54001, 0x0 }, > + { 0x54002, 0x0 }, > + { 0x54003, 0xc80 }, > + { 0x54004, 0x2 }, > + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, > + { 0x54006, LPDDR4_PHY_VREF_VALUE }, > + { 0x54007, 0x0 }, > + { 0x54008, 0x61 }, > + { 0x54009, LPDDR4_HDT_CTL_2D }, > + { 0x5400a, 0x0 }, > + { 0x5400b, 0x2 }, > + { 0x5400c, 0x0 }, > + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, > + { 0x5400e, 0x0 }, > + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, > + { 0x54010, LPDDR4_2D_WEIGHT }, > + { 0x54011, 0x0 }, > + { 0x54012, 0x310 }, > + { 0x54013, 0x0 }, > + { 0x54014, 0x0 }, > + { 0x54015, 0x0 }, > + { 0x54016, 0x0 }, > + { 0x54017, 0x0 }, > + { 0x54018, 0x0 }, > + { 0x54024, 0x5 }, > + { 0x54019, 0x2dd4 }, > + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, > + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, > + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, > + { 0x5401d, 0x0 }, > + { 0x5401e, LPDDR4_MR22_RANK0 }, > + { 0x5401f, 0x2dd4 }, > + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, > + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | > + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, > + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, > + { 0x54023, 0x0 }, > + { 0x54024, LPDDR4_MR22_RANK1 }, > + { 0x54025, 0x0 }, > + { 0x54026, 0x0 }, > + { 0x54027, 0x0 }, > + { 0x54028, 0x0 }, > + { 0x54029, 0x0 }, > + { 0x5402a, 0x0 }, > + { 0x5402b, 0x1000 }, > + { 0x5402c, 0x3 }, > + { 0x5402d, 0x0 }, > + { 0x5402e, 0x0 }, > + { 0x5402f, 0x0 }, > + { 0x54030, 0x0 }, > + { 0x54031, 0x0 }, > + { 0x54032, 0xd400 }, > + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, > + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, > + { 0x54038, 0xd400 }, > + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, > + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, > + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, > + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, > + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, > + { 0x5403e, 0x0 }, > + { 0x5403f, 0x0 }, > + { 0x54040, 0x0 }, > + { 0x54041, 0x0 }, > + { 0x54042, 0x0 }, > + { 0x54043, 0x0 }, > + { 0x54044, 0x0 }, > + { 0xd0000, 0x1 }, > + > +}; > + > +/* DRAM PHY init engine image */ > +static struct dram_cfg_param lpddr4_phy_pie[] = { > + { 0xd0000, 0x0 }, > + { 0x90000, 0x10 }, > + { 0x90001, 0x400 }, > + { 0x90002, 0x10e }, > + { 0x90003, 0x0 }, > + { 0x90004, 0x0 }, > + { 0x90005, 0x8 }, > + { 0x90029, 0xb }, > + { 0x9002a, 0x480 }, > + { 0x9002b, 0x109 }, > + { 0x9002c, 0x8 }, > + { 0x9002d, 0x448 }, > + { 0x9002e, 0x139 }, > + { 0x9002f, 0x8 }, > + { 0x90030, 0x478 }, > + { 0x90031, 0x109 }, > + { 0x90032, 0x0 }, > + { 0x90033, 0xe8 }, > + { 0x90034, 0x109 }, > + { 0x90035, 0x2 }, > + { 0x90036, 0x10 }, > + { 0x90037, 0x139 }, > + { 0x90038, 0xb }, > + { 0x90039, 0x7c0 }, > + { 0x9003a, 0x139 }, > + { 0x9003b, 0x44 }, > + { 0x9003c, 0x630 }, > + { 0x9003d, 0x159 }, > + { 0x9003e, 0x14f }, > + { 0x9003f, 0x630 }, > + { 0x90040, 0x159 }, > + { 0x90041, 0x47 }, > + { 0x90042, 0x630 }, > + { 0x90043, 0x149 }, > + { 0x90044, 0x4f }, > + { 0x90045, 0x630 }, > + { 0x90046, 0x179 }, > + { 0x90047, 0x8 }, > + { 0x90048, 0xe0 }, > + { 0x90049, 0x109 }, > + { 0x9004a, 0x0 }, > + { 0x9004b, 0x7c8 }, > + { 0x9004c, 0x109 }, > + { 0x9004d, 0x0 }, > + { 0x9004e, 0x1 }, > + { 0x9004f, 0x8 }, > + { 0x90050, 0x0 }, > + { 0x90051, 0x45a }, > + { 0x90052, 0x9 }, > + { 0x90053, 0x0 }, > + { 0x90054, 0x448 }, > + { 0x90055, 0x109 }, > + { 0x90056, 0x40 }, > + { 0x90057, 0x630 }, > + { 0x90058, 0x179 }, > + { 0x90059, 0x1 }, > + { 0x9005a, 0x618 }, > + { 0x9005b, 0x109 }, > + { 0x9005c, 0x40c0 }, > + { 0x9005d, 0x630 }, > + { 0x9005e, 0x149 }, > + { 0x9005f, 0x8 }, > + { 0x90060, 0x4 }, > + { 0x90061, 0x48 }, > + { 0x90062, 0x4040 }, > + { 0x90063, 0x630 }, > + { 0x90064, 0x149 }, > + { 0x90065, 0x0 }, > + { 0x90066, 0x4 }, > + { 0x90067, 0x48 }, > + { 0x90068, 0x40 }, > + { 0x90069, 0x630 }, > + { 0x9006a, 0x149 }, > + { 0x9006b, 0x10 }, > + { 0x9006c, 0x4 }, > + { 0x9006d, 0x18 }, > + { 0x9006e, 0x0 }, > + { 0x9006f, 0x4 }, > + { 0x90070, 0x78 }, > + { 0x90071, 0x549 }, > + { 0x90072, 0x630 }, > + { 0x90073, 0x159 }, > + { 0x90074, 0xd49 }, > + { 0x90075, 0x630 }, > + { 0x90076, 0x159 }, > + { 0x90077, 0x94a }, > + { 0x90078, 0x630 }, > + { 0x90079, 0x159 }, > + { 0x9007a, 0x441 }, > + { 0x9007b, 0x630 }, > + { 0x9007c, 0x149 }, > + { 0x9007d, 0x42 }, > + { 0x9007e, 0x630 }, > + { 0x9007f, 0x149 }, > + { 0x90080, 0x1 }, > + { 0x90081, 0x630 }, > + { 0x90082, 0x149 }, > + { 0x90083, 0x0 }, > + { 0x90084, 0xe0 }, > + { 0x90085, 0x109 }, > + { 0x90086, 0xa }, > + { 0x90087, 0x10 }, > + { 0x90088, 0x109 }, > + { 0x90089, 0x9 }, > + { 0x9008a, 0x3c0 }, > + { 0x9008b, 0x149 }, > + { 0x9008c, 0x9 }, > + { 0x9008d, 0x3c0 }, > + { 0x9008e, 0x159 }, > + { 0x9008f, 0x18 }, > + { 0x90090, 0x10 }, > + { 0x90091, 0x109 }, > + { 0x90092, 0x0 }, > + { 0x90093, 0x3c0 }, > + { 0x90094, 0x109 }, > + { 0x90095, 0x18 }, > + { 0x90096, 0x4 }, > + { 0x90097, 0x48 }, > + { 0x90098, 0x18 }, > + { 0x90099, 0x4 }, > + { 0x9009a, 0x58 }, > + { 0x9009b, 0xa }, > + { 0x9009c, 0x10 }, > + { 0x9009d, 0x109 }, > + { 0x9009e, 0x2 }, > + { 0x9009f, 0x10 }, > + { 0x900a0, 0x109 }, > + { 0x900a1, 0x5 }, > + { 0x900a2, 0x7c0 }, > + { 0x900a3, 0x109 }, > + { 0x900a4, 0xd }, > + { 0x900a5, 0x7c0 }, > + { 0x900a6, 0x109 }, > + { 0x900a7, 0x4 }, > + { 0x900a8, 0x7c0 }, > + { 0x900a9, 0x109 }, > + { 0x40000, 0x811 }, > + { 0x40020, 0x880 }, > + { 0x40040, 0x0 }, > + { 0x40060, 0x0 }, > + { 0x40001, 0x4008 }, > + { 0x40021, 0x83 }, > + { 0x40041, 0x4f }, > + { 0x40061, 0x0 }, > + { 0x40002, 0x4040 }, > + { 0x40022, 0x83 }, > + { 0x40042, 0x51 }, > + { 0x40062, 0x0 }, > + { 0x40003, 0x811 }, > + { 0x40023, 0x880 }, > + { 0x40043, 0x0 }, > + { 0x40063, 0x0 }, > + { 0x40004, 0x720 }, > + { 0x40024, 0xf }, > + { 0x40044, 0x1740 }, > + { 0x40064, 0x0 }, > + { 0x40005, 0x16 }, > + { 0x40025, 0x83 }, > + { 0x40045, 0x4b }, > + { 0x40065, 0x0 }, > + { 0x40006, 0x716 }, > + { 0x40026, 0xf }, > + { 0x40046, 0x2001 }, > + { 0x40066, 0x0 }, > + { 0x40007, 0x716 }, > + { 0x40027, 0xf }, > + { 0x40047, 0x2800 }, > + { 0x40067, 0x0 }, > + { 0x40008, 0x716 }, > + { 0x40028, 0xf }, > + { 0x40048, 0xf00 }, > + { 0x40068, 0x0 }, > + { 0x40009, 0x720 }, > + { 0x40029, 0xf }, > + { 0x40049, 0x1400 }, > + { 0x40069, 0x0 }, > + { 0x4000a, 0xe08 }, > + { 0x4002a, 0xc15 }, > + { 0x4004a, 0x0 }, > + { 0x4006a, 0x0 }, > + { 0x4000b, 0x623 }, > + { 0x4002b, 0x15 }, > + { 0x4004b, 0x0 }, > + { 0x4006b, 0x0 }, > + { 0x4000c, 0x4028 }, > + { 0x4002c, 0x80 }, > + { 0x4004c, 0x0 }, > + { 0x4006c, 0x0 }, > + { 0x4000d, 0xe08 }, > + { 0x4002d, 0xc1a }, > + { 0x4004d, 0x0 }, > + { 0x4006d, 0x0 }, > + { 0x4000e, 0x623 }, > + { 0x4002e, 0x1a }, > + { 0x4004e, 0x0 }, > + { 0x4006e, 0x0 }, > + { 0x4000f, 0x4040 }, > + { 0x4002f, 0x80 }, > + { 0x4004f, 0x0 }, > + { 0x4006f, 0x0 }, > + { 0x40010, 0x2604 }, > + { 0x40030, 0x15 }, > + { 0x40050, 0x0 }, > + { 0x40070, 0x0 }, > + { 0x40011, 0x708 }, > + { 0x40031, 0x5 }, > + { 0x40051, 0x0 }, > + { 0x40071, 0x2002 }, > + { 0x40012, 0x8 }, > + { 0x40032, 0x80 }, > + { 0x40052, 0x0 }, > + { 0x40072, 0x0 }, > + { 0x40013, 0x2604 }, > + { 0x40033, 0x1a }, > + { 0x40053, 0x0 }, > + { 0x40073, 0x0 }, > + { 0x40014, 0x708 }, > + { 0x40034, 0xa }, > + { 0x40054, 0x0 }, > + { 0x40074, 0x2002 }, > + { 0x40015, 0x4040 }, > + { 0x40035, 0x80 }, > + { 0x40055, 0x0 }, > + { 0x40075, 0x0 }, > + { 0x40016, 0x60a }, > + { 0x40036, 0x15 }, > + { 0x40056, 0x1200 }, > + { 0x40076, 0x0 }, > + { 0x40017, 0x61a }, > + { 0x40037, 0x15 }, > + { 0x40057, 0x1300 }, > + { 0x40077, 0x0 }, > + { 0x40018, 0x60a }, > + { 0x40038, 0x1a }, > + { 0x40058, 0x1200 }, > + { 0x40078, 0x0 }, > + { 0x40019, 0x642 }, > + { 0x40039, 0x1a }, > + { 0x40059, 0x1300 }, > + { 0x40079, 0x0 }, > + { 0x4001a, 0x4808 }, > + { 0x4003a, 0x880 }, > + { 0x4005a, 0x0 }, > + { 0x4007a, 0x0 }, > + { 0x900aa, 0x0 }, > + { 0x900ab, 0x790 }, > + { 0x900ac, 0x11a }, > + { 0x900ad, 0x8 }, > + { 0x900ae, 0x7aa }, > + { 0x900af, 0x2a }, > + { 0x900b0, 0x10 }, > + { 0x900b1, 0x7b2 }, > + { 0x900b2, 0x2a }, > + { 0x900b3, 0x0 }, > + { 0x900b4, 0x7c8 }, > + { 0x900b5, 0x109 }, > + { 0x900b6, 0x10 }, > + { 0x900b7, 0x10 }, > + { 0x900b8, 0x109 }, > + { 0x900b9, 0x10 }, > + { 0x900ba, 0x2a8 }, > + { 0x900bb, 0x129 }, > + { 0x900bc, 0x8 }, > + { 0x900bd, 0x370 }, > + { 0x900be, 0x129 }, > + { 0x900bf, 0xa }, > + { 0x900c0, 0x3c8 }, > + { 0x900c1, 0x1a9 }, > + { 0x900c2, 0xc }, > + { 0x900c3, 0x408 }, > + { 0x900c4, 0x199 }, > + { 0x900c5, 0x14 }, > + { 0x900c6, 0x790 }, > + { 0x900c7, 0x11a }, > + { 0x900c8, 0x8 }, > + { 0x900c9, 0x4 }, > + { 0x900ca, 0x18 }, > + { 0x900cb, 0xe }, > + { 0x900cc, 0x408 }, > + { 0x900cd, 0x199 }, > + { 0x900ce, 0x8 }, > + { 0x900cf, 0x8568 }, > + { 0x900d0, 0x108 }, > + { 0x900d1, 0x18 }, > + { 0x900d2, 0x790 }, > + { 0x900d3, 0x16a }, > + { 0x900d4, 0x8 }, > + { 0x900d5, 0x1d8 }, > + { 0x900d6, 0x169 }, > + { 0x900d7, 0x10 }, > + { 0x900d8, 0x8558 }, > + { 0x900d9, 0x168 }, > + { 0x900da, 0x70 }, > + { 0x900db, 0x788 }, > + { 0x900dc, 0x16a }, > + { 0x900dd, 0x1ff8 }, > + { 0x900de, 0x85a8 }, > + { 0x900df, 0x1e8 }, > + { 0x900e0, 0x50 }, > + { 0x900e1, 0x798 }, > + { 0x900e2, 0x16a }, > + { 0x900e3, 0x60 }, > + { 0x900e4, 0x7a0 }, > + { 0x900e5, 0x16a }, > + { 0x900e6, 0x8 }, > + { 0x900e7, 0x8310 }, > + { 0x900e8, 0x168 }, > + { 0x900e9, 0x8 }, > + { 0x900ea, 0xa310 }, > + { 0x900eb, 0x168 }, > + { 0x900ec, 0xa }, > + { 0x900ed, 0x408 }, > + { 0x900ee, 0x169 }, > + { 0x900ef, 0x6e }, > + { 0x900f0, 0x0 }, > + { 0x900f1, 0x68 }, > + { 0x900f2, 0x0 }, > + { 0x900f3, 0x408 }, > + { 0x900f4, 0x169 }, > + { 0x900f5, 0x0 }, > + { 0x900f6, 0x8310 }, > + { 0x900f7, 0x168 }, > + { 0x900f8, 0x0 }, > + { 0x900f9, 0xa310 }, > + { 0x900fa, 0x168 }, > + { 0x900fb, 0x1ff8 }, > + { 0x900fc, 0x85a8 }, > + { 0x900fd, 0x1e8 }, > + { 0x900fe, 0x68 }, > + { 0x900ff, 0x798 }, > + { 0x90100, 0x16a }, > + { 0x90101, 0x78 }, > + { 0x90102, 0x7a0 }, > + { 0x90103, 0x16a }, > + { 0x90104, 0x68 }, > + { 0x90105, 0x790 }, > + { 0x90106, 0x16a }, > + { 0x90107, 0x8 }, > + { 0x90108, 0x8b10 }, > + { 0x90109, 0x168 }, > + { 0x9010a, 0x8 }, > + { 0x9010b, 0xab10 }, > + { 0x9010c, 0x168 }, > + { 0x9010d, 0xa }, > + { 0x9010e, 0x408 }, > + { 0x9010f, 0x169 }, > + { 0x90110, 0x58 }, > + { 0x90111, 0x0 }, > + { 0x90112, 0x68 }, > + { 0x90113, 0x0 }, > + { 0x90114, 0x408 }, > + { 0x90115, 0x169 }, > + { 0x90116, 0x0 }, > + { 0x90117, 0x8b10 }, > + { 0x90118, 0x168 }, > + { 0x90119, 0x0 }, > + { 0x9011a, 0xab10 }, > + { 0x9011b, 0x168 }, > + { 0x9011c, 0x0 }, > + { 0x9011d, 0x1d8 }, > + { 0x9011e, 0x169 }, > + { 0x9011f, 0x80 }, > + { 0x90120, 0x790 }, > + { 0x90121, 0x16a }, > + { 0x90122, 0x18 }, > + { 0x90123, 0x7aa }, > + { 0x90124, 0x6a }, > + { 0x90125, 0xa }, > + { 0x90126, 0x0 }, > + { 0x90127, 0x1e9 }, > + { 0x90128, 0x8 }, > + { 0x90129, 0x8080 }, > + { 0x9012a, 0x108 }, > + { 0x9012b, 0xf }, > + { 0x9012c, 0x408 }, > + { 0x9012d, 0x169 }, > + { 0x9012e, 0xc }, > + { 0x9012f, 0x0 }, > + { 0x90130, 0x68 }, > + { 0x90131, 0x9 }, > + { 0x90132, 0x0 }, > + { 0x90133, 0x1a9 }, > + { 0x90134, 0x0 }, > + { 0x90135, 0x408 }, > + { 0x90136, 0x169 }, > + { 0x90137, 0x0 }, > + { 0x90138, 0x8080 }, > + { 0x90139, 0x108 }, > + { 0x9013a, 0x8 }, > + { 0x9013b, 0x7aa }, > + { 0x9013c, 0x6a }, > + { 0x9013d, 0x0 }, > + { 0x9013e, 0x8568 }, > + { 0x9013f, 0x108 }, > + { 0x90140, 0xb7 }, > + { 0x90141, 0x790 }, > + { 0x90142, 0x16a }, > + { 0x90143, 0x1f }, > + { 0x90144, 0x0 }, > + { 0x90145, 0x68 }, > + { 0x90146, 0x8 }, > + { 0x90147, 0x8558 }, > + { 0x90148, 0x168 }, > + { 0x90149, 0xf }, > + { 0x9014a, 0x408 }, > + { 0x9014b, 0x169 }, > + { 0x9014c, 0xc }, > + { 0x9014d, 0x0 }, > + { 0x9014e, 0x68 }, > + { 0x9014f, 0x0 }, > + { 0x90150, 0x408 }, > + { 0x90151, 0x169 }, > + { 0x90152, 0x0 }, > + { 0x90153, 0x8558 }, > + { 0x90154, 0x168 }, > + { 0x90155, 0x8 }, > + { 0x90156, 0x3c8 }, > + { 0x90157, 0x1a9 }, > + { 0x90158, 0x3 }, > + { 0x90159, 0x370 }, > + { 0x9015a, 0x129 }, > + { 0x9015b, 0x20 }, > + { 0x9015c, 0x2aa }, > + { 0x9015d, 0x9 }, > + { 0x9015e, 0x0 }, > + { 0x9015f, 0x400 }, > + { 0x90160, 0x10e }, > + { 0x90161, 0x8 }, > + { 0x90162, 0xe8 }, > + { 0x90163, 0x109 }, > + { 0x90164, 0x0 }, > + { 0x90165, 0x8140 }, > + { 0x90166, 0x10c }, > + { 0x90167, 0x10 }, > + { 0x90168, 0x8138 }, > + { 0x90169, 0x10c }, > + { 0x9016a, 0x8 }, > + { 0x9016b, 0x7c8 }, > + { 0x9016c, 0x101 }, > + { 0x9016d, 0x8 }, > + { 0x9016e, 0x0 }, > + { 0x9016f, 0x8 }, > + { 0x90170, 0x8 }, > + { 0x90171, 0x448 }, > + { 0x90172, 0x109 }, > + { 0x90173, 0xf }, > + { 0x90174, 0x7c0 }, > + { 0x90175, 0x109 }, > + { 0x90176, 0x0 }, > + { 0x90177, 0xe8 }, > + { 0x90178, 0x109 }, > + { 0x90179, 0x47 }, > + { 0x9017a, 0x630 }, > + { 0x9017b, 0x109 }, > + { 0x9017c, 0x8 }, > + { 0x9017d, 0x618 }, > + { 0x9017e, 0x109 }, > + { 0x9017f, 0x8 }, > + { 0x90180, 0xe0 }, > + { 0x90181, 0x109 }, > + { 0x90182, 0x0 }, > + { 0x90183, 0x7c8 }, > + { 0x90184, 0x109 }, > + { 0x90185, 0x8 }, > + { 0x90186, 0x8140 }, > + { 0x90187, 0x10c }, > + { 0x90188, 0x0 }, > + { 0x90189, 0x1 }, > + { 0x9018a, 0x8 }, > + { 0x9018b, 0x8 }, > + { 0x9018c, 0x4 }, > + { 0x9018d, 0x8 }, > + { 0x9018e, 0x8 }, > + { 0x9018f, 0x7c8 }, > + { 0x90190, 0x101 }, > + { 0x90006, 0x0 }, > + { 0x90007, 0x0 }, > + { 0x90008, 0x8 }, > + { 0x90009, 0x0 }, > + { 0x9000a, 0x0 }, > + { 0x9000b, 0x0 }, > + { 0xd00e7, 0x400 }, > + { 0x90017, 0x0 }, > + { 0x9001f, 0x2b }, > + { 0x90026, 0x6c }, > + { 0x400d0, 0x0 }, > + { 0x400d1, 0x101 }, > + { 0x400d2, 0x105 }, > + { 0x400d3, 0x107 }, > + { 0x400d4, 0x10f }, > + { 0x400d5, 0x202 }, > + { 0x400d6, 0x20a }, > + { 0x400d7, 0x20b }, > + { 0x2003a, 0x2 }, > + { 0x2000b, 0x64 }, > + { 0x2000c, 0xc8 }, > + { 0x2000d, 0x7d0 }, > + { 0x2000e, 0x2c }, > + { 0x12000b, 0x14 }, > + { 0x12000c, 0x29 }, > + { 0x12000d, 0x1a1 }, > + { 0x12000e, 0x10 }, > + { 0x22000b, 0x3 }, > + { 0x22000c, 0x6 }, > + { 0x22000d, 0x3e }, > + { 0x22000e, 0x10 }, > + { 0x9000c, 0x0 }, > + { 0x9000d, 0x173 }, > + { 0x9000e, 0x60 }, > + { 0x9000f, 0x6110 }, > + { 0x90010, 0x2152 }, > + { 0x90011, 0xdfbd }, > + { 0x90012, 0x60 }, > + { 0x90013, 0x6152 }, > + { 0x20010, 0x5a }, > + { 0x20011, 0x3 }, > + { 0x40080, 0xe0 }, > + { 0x40081, 0x12 }, > + { 0x40082, 0xe0 }, > + { 0x40083, 0x12 }, > + { 0x40084, 0xe0 }, > + { 0x40085, 0x12 }, > + { 0x140080, 0xe0 }, > + { 0x140081, 0x12 }, > + { 0x140082, 0xe0 }, > + { 0x140083, 0x12 }, > + { 0x140084, 0xe0 }, > + { 0x140085, 0x12 }, > + { 0x240080, 0xe0 }, > + { 0x240081, 0x12 }, > + { 0x240082, 0xe0 }, > + { 0x240083, 0x12 }, > + { 0x240084, 0xe0 }, > + { 0x240085, 0x12 }, > + { 0x400fd, 0xf }, > + { 0x10011, 0x1 }, > + { 0x10012, 0x1 }, > + { 0x10013, 0x180 }, > + { 0x10018, 0x1 }, > + { 0x10002, 0x6209 }, > + { 0x100b2, 0x1 }, > + { 0x101b4, 0x1 }, > + { 0x102b4, 0x1 }, > + { 0x103b4, 0x1 }, > + { 0x104b4, 0x1 }, > + { 0x105b4, 0x1 }, > + { 0x106b4, 0x1 }, > + { 0x107b4, 0x1 }, > + { 0x108b4, 0x1 }, > + { 0x11011, 0x1 }, > + { 0x11012, 0x1 }, > + { 0x11013, 0x180 }, > + { 0x11018, 0x1 }, > + { 0x11002, 0x6209 }, > + { 0x110b2, 0x1 }, > + { 0x111b4, 0x1 }, > + { 0x112b4, 0x1 }, > + { 0x113b4, 0x1 }, > + { 0x114b4, 0x1 }, > + { 0x115b4, 0x1 }, > + { 0x116b4, 0x1 }, > + { 0x117b4, 0x1 }, > + { 0x118b4, 0x1 }, > + { 0x12011, 0x1 }, > + { 0x12012, 0x1 }, > + { 0x12013, 0x180 }, > + { 0x12018, 0x1 }, > + { 0x12002, 0x6209 }, > + { 0x120b2, 0x1 }, > + { 0x121b4, 0x1 }, > + { 0x122b4, 0x1 }, > + { 0x123b4, 0x1 }, > + { 0x124b4, 0x1 }, > + { 0x125b4, 0x1 }, > + { 0x126b4, 0x1 }, > + { 0x127b4, 0x1 }, > + { 0x128b4, 0x1 }, > + { 0x13011, 0x1 }, > + { 0x13012, 0x1 }, > + { 0x13013, 0x180 }, > + { 0x13018, 0x1 }, > + { 0x13002, 0x6209 }, > + { 0x130b2, 0x1 }, > + { 0x131b4, 0x1 }, > + { 0x132b4, 0x1 }, > + { 0x133b4, 0x1 }, > + { 0x134b4, 0x1 }, > + { 0x135b4, 0x1 }, > + { 0x136b4, 0x1 }, > + { 0x137b4, 0x1 }, > + { 0x138b4, 0x1 }, > + { 0x20089, 0x1 }, > + { 0x20088, 0x19 }, > + { 0xc0080, 0x2 }, > + { 0xd0000, 0x1 }, > +}; > + > +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > + { > + /* P0 3200mts 1D */ > + .drate = 3200, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), > + }, > + { > + /* P1 667mts 1D */ > + .drate = 667, > + .fw_type = FW_1D_IMAGE, > + .fsp_cfg = lpddr4_fsp1_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), > + }, > + { > + /* P0 3200mts 2D */ > + .drate = 3200, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > + }, > +}; > + > +/* lpddr4 timing config params on EVK board */ > +struct dram_timing_info dram_timing_b0 = { > + .ddrc_cfg = lpddr4_ddrc_cfg, > + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), > + .ddrphy_cfg = lpddr4_ddrphy_cfg, > + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), > + .fsp_msg = lpddr4_dram_fsp_msg, > + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), > + .ddrphy_pie = lpddr4_phy_pie, > + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), > + /* > + * this table must be initialized if DDRPHY bypass mode is > + * not used: all fsp drate > 666MTS. > + */ > + .fsp_table = { 3200, 667, }, > +}; > diff --git a/board/freescale/imx8mq_evk/spl.c > b/board/freescale/imx8mq_evk/spl.c > new file mode 100644 > index 0000000000..e6cbc34b0d > --- /dev/null > +++ b/board/freescale/imx8mq_evk/spl.c > @@ -0,0 +1,246 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2018 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <errno.h> > +#include <asm/io.h> > +#include <asm/arch/ddr.h> > +#include <asm/arch/imx8mq_pins.h> > +#include <asm/arch/sys_proto.h> > +#include <asm/arch/clock.h> > +#include <asm/mach-imx/iomux-v3.h> > +#include <asm/mach-imx/gpio.h> > +#include <asm/mach-imx/mxc_i2c.h> > +#include <fsl_esdhc.h> > +#include <mmc.h> > +#include <power/pmic.h> > +#include <power/pfuze100_pmic.h> > +#include <spl.h> > +#include "../common/pfuze.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +extern struct dram_timing_info dram_timing_b0; > + > +void spl_dram_init(void) > +{ > + /* ddr init */ > + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) > + ddr_init(&dram_timing); > + else > + ddr_init(&dram_timing_b0); > +} > + > +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | > PAD_CTL_PUE) > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) > +struct i2c_pads_info i2c_pad_info1 = { > + .scl = { > + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, > + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, > + .gp = IMX_GPIO_NR(5, 14), > + }, > + .sda = { > + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, > + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, > + .gp = IMX_GPIO_NR(5, 15), > + }, > +}; > + > +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) > +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) > +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) > + > +int board_mmc_getcd(struct mmc *mmc) > +{ > + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; > + int ret = 0; > + > + switch (cfg->esdhc_base) { > + case USDHC1_BASE_ADDR: > + ret = 1; > + break; > + case USDHC2_BASE_ADDR: > + ret = !gpio_get_value(USDHC2_CD_GPIO); > + return ret; > + } > + > + return 1; > +} > + > +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | > PAD_CTL_PUE | \ > + PAD_CTL_FSEL2) > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) > + > +static iomux_v3_cfg_t const usdhc1_pads[] = { > + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), > + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | > MUX_PAD_CTRL(NO_PAD_CTRL), > +}; > + > +static iomux_v3_cfg_t const usdhc2_pads[] = { > + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ > + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ > + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ > + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ > + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ > + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | > MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ > + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | > MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), > +}; > + > +static struct fsl_esdhc_cfg usdhc_cfg[2] = { > + {USDHC1_BASE_ADDR, 0, 8}, > + {USDHC2_BASE_ADDR, 0, 4}, > +}; > + > +int board_mmc_init(bd_t *bis) > +{ > + int i, ret; > + /* > + * According to the board_mmc_init() the following map is done: > + * (U-Boot device node) (Physical Port) > + * mmc0 USDHC1 > + * mmc1 USDHC2 > + */ > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > + switch (i) { > + case 0: > + init_clk_usdhc(0); > + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); > + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, > + ARRAY_SIZE(usdhc1_pads)); > + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); > + gpio_direction_output(USDHC1_PWR_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC1_PWR_GPIO, 1); > + break; > + case 1: > + init_clk_usdhc(1); > + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); > + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, > + ARRAY_SIZE(usdhc2_pads)); > + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); > + gpio_direction_output(USDHC2_PWR_GPIO, 0); > + udelay(500); > + gpio_direction_output(USDHC2_PWR_GPIO, 1); > + break; > + default: > + printf("Warning: you configured more USDHC controllers(%d) > than supported by the board\n", i + 1); > + return -EINVAL; > + } > + > + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > +#ifdef CONFIG_POWER > +#define I2C_PMIC 0 > +int power_init_board(void) > +{ > + struct pmic *p; > + int ret; > + unsigned int reg; > + > + ret = power_pfuze100_init(I2C_PMIC); > + if (ret) > + return -ENODEV; > + > + p = pmic_get("PFUZE100"); > + ret = pmic_probe(p); > + if (ret) > + return -ENODEV; > + > + pmic_reg_read(p, PFUZE100_DEVICEID, ®); > + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); > + > + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); > + if ((reg & 0x3f) != 0x18) { > + reg &= ~0x3f; > + reg |= 0x18; > + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); > + } > + > + ret = pfuze_mode_init(p, APS_PFM); > + if (ret < 0) > + return ret; > + > + /* set SW3A standby mode to off */ > + pmic_reg_read(p, PFUZE100_SW3AMODE, ®); > + reg &= ~0xf; > + reg |= APS_OFF; > + pmic_reg_write(p, PFUZE100_SW3AMODE, reg); > + > + return 0; > +} > +#endif > + > +void spl_board_init(void) > +{ > + puts("Normal Boot\n"); > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + /* Just empty function now - can't decide what to choose */ > + debug("%s: %s\n", __func__, name); > + > + return 0; > +} > +#endif > + > +void board_init_f(ulong dummy) > +{ > + int ret; > + > + /* Clear global data */ > + memset((void *)gd, 0, sizeof(gd_t)); > + > + arch_cpu_init(); > + > + init_uart_clk(0); > + > + board_early_init_f(); > + > + timer_init(); > + > + preloader_console_init(); > + > + /* Clear the BSS. */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + ret = spl_init(); > + if (ret) { > + debug("spl_init() failed: %d\n", ret); > + hang(); > + } > + > + enable_tzc380(); > + > + /* Adjust pmic voltage to 1.0V for 800M */ > + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); > + > + power_init_board(); > + > + /* DDR initialization */ > + spl_dram_init(); > + > + board_init_r(NULL, 0); > +} > diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig > new file mode 100644 > index 0000000000..f216d46a8f > --- /dev/null > +++ b/configs/imx8mq_evk_defconfig > @@ -0,0 +1,37 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_IMX8M=y > +CONFIG_SYS_TEXT_BASE=0x40200000 > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SPL_SERIAL_SUPPORT=y > +CONFIG_TARGET_IMX8MQ_EVK=y > +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 > +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" > +CONFIG_OF_LIST="fsl-imx8mq-evk" > +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m > /imximage.cfg" > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" > +CONFIG_FIT=y > +CONFIG_SPL_LOAD_FIT=y > +#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd > .cfg" > +CONFIG_SPL=y > +CONFIG_SPL_BOARD_INIT=y > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_REGULATOR=y > +CONFIG_OF_CONTROL=y > +CONFIG_DM_GPIO=y > +CONFIG_DM_I2C=y > +CONFIG_DM_MMC=y > +CONFIG_DM_ETH=y > +CONFIG_PINCTRL=y > +CONFIG_PINCTRL_IMX8M=y > +CONFIG_SYS_I2C_MXC=y > +CONFIG_DM_PMIC_PFUZE100=y > +CONFIG_DM_REGULATOR=y > +CONFIG_DM_REGULATOR_PFUZE100=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_DM_THERMAL=y > +CONFIG_FS_FAT=y > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 > diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h > new file mode 100644 > index 0000000000..35f81152f2 > --- /dev/null > +++ b/include/configs/imx8mq_evk.h > @@ -0,0 +1,252 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright 2018 NXP > + */ > + > +#ifndef __IMX8M_EVK_H > +#define __IMX8M_EVK_H > + > +#include <linux/sizes.h> > +#include <asm/arch/imx-regs.h> > + > +#ifdef CONFIG_SECURE_BOOT > +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */ > +#endif > + > +#define CONFIG_SPL_TEXT_BASE 0x7E1000 > +#define CONFIG_SPL_MAX_SIZE (124 * 1024) > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 > + > +#ifdef CONFIG_SPL_BUILD > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ > +#define CONFIG_SPL_WATCHDOG_SUPPORT > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT > +#define CONFIG_SPL_POWER_SUPPORT > +#define CONFIG_SPL_I2C_SUPPORT > +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" > +#define CONFIG_SPL_STACK 0x187FF0 > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_GPIO_SUPPORT > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ > +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ > +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 > +#define CONFIG_SYS_ICACHE_OFF > +#define CONFIG_SYS_DCACHE_OFF > + > +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ > +#define CONFIG_MALLOC_F_ADDR 0x182000 > +/* For RAW image gives a error info not panic */ > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE > + > +#undef CONFIG_DM_MMC > +#undef CONFIG_DM_PMIC > +#undef CONFIG_DM_PMIC_PFUZE100 > + > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ > +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ > +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ > + > +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG > + > +#define CONFIG_POWER > +#define CONFIG_POWER_I2C > +#define CONFIG_POWER_PFUZE100 > +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 > +#endif > + > +#define CONFIG_REMAKE_ELF > + > +#define CONFIG_BOARD_EARLY_INIT_F > +#define CONFIG_BOARD_LATE_INIT > + > +#undef CONFIG_CMD_EXPORTENV > +#undef CONFIG_CMD_IMPORTENV > +#undef CONFIG_CMD_IMLS > + > +#undef CONFIG_CMD_CRC32 > +#undef CONFIG_BOOTM_NETBSD > + > +/* ENET Config */ > +/* ENET1 */ > +#if defined(CONFIG_CMD_NET) > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_MII > +#define CONFIG_MII > +#define CONFIG_ETHPRIME "FEC" > + > +#define CONFIG_FEC_MXC > +#define CONFIG_FEC_XCV_TYPE RGMII > +#define CONFIG_FEC_MXC_PHYADDR 0 > +#define FEC_QUIRK_ENET_MAC > + > +#define CONFIG_PHY_GIGE > +#define IMX_FEC_BASE 0x30BE0000 > + > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_ATHEROS > +#endif > + > +#define CONFIG_MFG_ENV_SETTINGS \ > + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ > + "rdinit=/linuxrc " \ > + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ > + "g_mass_storage.idVendor=0x066F > g_mass_storage.idProduct=0x37FF "\ > + "g_mass_storage.iSerialNumber=\"\" "\ > + "clk_ignore_unused "\ > + "\0" \ > + "initrd_addr=0x43800000\0" \ > + "initrd_high=0xffffffff\0" \ > + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} > ${fdt_addr};\0" \ > +/* Initial environment variables */ > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + CONFIG_MFG_ENV_SETTINGS \ > + "script=boot.scr\0" \ > + "image=Image\0" \ > + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ > + "fdt_addr=0x43000000\0" \ > + "fdt_high=0xffffffffffffffff\0" \ > + "boot_fdt=try\0" \ > + "fdt_file=fsl-imx8mq-evk.dtb\0" \ > + "initrd_addr=0x43800000\0" \ > + "initrd_high=0xffffffffffffffff\0" \ > + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ > + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ > + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ > + "mmcautodetect=yes\0" \ > + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ > + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${script};\0" \ > + "bootscript=echo Running bootscript from mmc ...; " \ > + "source\0" \ > + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} > ${image}\0" \ > + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" > \ > + "mmcboot=echo Booting from mmc ...; " \ > + "run mmcargs; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if run loadfdt; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "echo wait for boot; " \ > + "fi;\0" \ > + "netargs=setenv bootargs console=${console} " \ > + "root=/dev/nfs " \ > + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ > + "netboot=echo Booting from net ...; " \ > + "run netargs; " \ > + "if test ${ip_dyn} = yes; then " \ > + "setenv get_cmd dhcp; " \ > + "else " \ > + "setenv get_cmd tftp; " \ > + "fi; " \ > + "${get_cmd} ${loadaddr} ${image}; " \ > + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ > + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ > + "booti ${loadaddr} - ${fdt_addr}; " \ > + "else " \ > + "echo WARN: Cannot load the DT; " \ > + "fi; " \ > + "else " \ > + "booti; " \ > + "fi;\0" > + > +#define CONFIG_BOOTCOMMAND \ > + "mmc dev ${mmcdev}; if mmc rescan; then " \ > + "if run loadbootscript; then " \ > + "run bootscript; " \ > + "else " \ > + "if run loadimage; then " \ > + "run mmcboot; " \ > + "else run netboot; " \ > + "fi; " \ > + "fi; " \ > + "else booti ${loadaddr} - ${fdt_addr}; fi" > + > +/* Link Definitions */ > +#define CONFIG_LOADADDR 0x40480000 > + > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > + > +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 > +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 > +#define CONFIG_SYS_INIT_SP_OFFSET \ > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) > + > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_ENV_OFFSET (64 * SZ_64K) > +#define CONFIG_ENV_SIZE 0x1000 > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ > +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 > */ > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) > * 1024) > + > +#define CONFIG_SYS_SDRAM_BASE 0x40000000 > +#define PHYS_SDRAM 0x40000000 > +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ > + > +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM > +#define CONFIG_SYS_MEMTEST_END > (CONFIG_SYS_MEMTEST_START + \ > + (PHYS_SDRAM_SIZE >> 1)) > + > +#define CONFIG_BAUDRATE 115200 > + > +#define CONFIG_MXC_UART > +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR > + > +/* Monitor Command Prompt */ > +#undef CONFIG_SYS_PROMPT > +#define CONFIG_SYS_PROMPT "u-boot=> " > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_SYS_CBSIZE 1024 > +#define CONFIG_SYS_MAXARGS 64 > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +#define CONFIG_IMX_BOOTAUX > + > +#define CONFIG_CMD_MMC > +#define CONFIG_FSL_ESDHC > +#define CONFIG_FSL_USDHC > + > +#define CONFIG_SYS_FSL_USDHC_NUM 2 > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 > + > +#define CONFIG_DOS_PARTITION > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_EXT4 > +#define CONFIG_CMD_EXT4_WRITE > +#define CONFIG_CMD_FAT > + > +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ > +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 > + > +#define CONFIG_MXC_GPIO > + > +#define CONFIG_MXC_OCOTP > +#define CONFIG_CMD_FUSE > + > +/* I2C Configs */ > +#define CONFIG_SYS_I2C_SPEED 100000 > + > +#define CONFIG_OF_SYSTEM_SETUP > + > +#ifndef CONFIG_SPL_BUILD > +#define CONFIG_DM_PMIC > +#endif > + > +#endif > -- > 2.14.1 ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2018-12-15 3:09 UTC | newest] Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-20 10:19 [U-Boot] [PATCH V2 01/15] Introduce CONFIG_FIT_EXTERNAL_OFFSET Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 02/15] imx8m: Enable CONFIG_SPL_FIT_IMAGE_TINY for iMX8M Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 03/15] imx: cpu: add CHIP_REV_2_1 macro Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 04/15] imx: introduce is_imx8mq helper Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 05/15] imx: rename mx8m,MX8M to imx8m,IMX8M Peng Fan 2018-11-29 5:01 ` Jon Nettleton 2018-12-03 12:33 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 06/15] imx: spl: add MMC BOOT Device for i.MX8M Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 07/15] imx: imx8m: clock refactor dram pll part Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 08/15] tools: add i.MX8M image support Peng Fan 2018-12-14 13:25 ` Stefano Babic 2018-12-15 3:09 ` Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 09/15] imx: imx8m: introduce script to generate fit image Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 10/15] imx: imx8m: introduce imximage cfg file Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 11/15] imx: imx8mq: build flash.bin Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 12/15] imx: imx8m: not build bootaux when building SPL Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 13/15] imx: imx8m: add lpddr4 header file Peng Fan 2018-11-20 10:19 ` [U-Boot] [PATCH V2 14/15] drivers: ddr: introduce DDR driver for i.MX8M Peng Fan 2018-11-20 17:47 ` Troy Kisky 2018-11-21 2:54 ` Peng Fan 2018-11-21 12:39 ` Fabio Estevam 2018-11-28 14:45 ` Jon Nettleton 2018-11-28 14:57 ` Peng Fan 2018-11-28 16:02 ` Stefano Babic 2018-11-28 15:03 ` Jacky Bai 2018-11-28 15:32 ` Jon Nettleton 2018-11-20 10:20 ` [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support Peng Fan 2018-11-27 7:32 ` Peng Fan
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