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* [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
@ 2018-11-22  9:07 ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

This patchset will refactor the Amlogic Meson SoC support in order to
easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.

In order :
- Cleanup the mach-meson configs
- Move board support to reference design common boards
- Move board Kconfig into mach-meson
- Add AXG pinctrl & clock support
- Add AXG device tree and mach-meson support
- Add support for S400 reference design
- Do a final factorization of the code
- Add USB boot support in U-boot

At the end of the patches, the board code is lighter and we maintain
only the reference designs, where each board will differ in the defconfig.

It will be simpler to add custom board support for future boards with
more changes against the reference designs.

The complete AXG support depends on the :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson axg compatible
patches submitted to the U-Boot mailing list.

Changes since v1:
- Fixed AXG pinctrl request and AO pin count
- Fixed tabs/spaces issues on s400 README

Jerome Brunet (12):
  ARM: meson: clean-up platform selection
  configs: meson: remove unnecessary MESON_FDTFILE_SETTING
  board: amlogic: remove p212 derivatives
  board: amlogic: factorise gxbb boards
  ARM: rework amlogic configuration
  configs: meson: change default load addresses
  pinctrl: meson: rework gx pmx function
  pinctrl: meson: select generic pinctrl
  pinctrl: meson: add axg support
  clk: meson: silence debug print
  ARM: meson: rework soc arch file to prepare for new SoC
  ARM: meson: factorize common code out amlogic's boards

Neil Armstrong (7):
  board: amlogic: move khadas-vim2 as q200 ref board
  clk: meson: add static to meson_gates table
  ARM: meson: Add support for AXG family
  ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
  clk: Add clock driver for AXG
  board: amlogic: add support for S400 board
  ARM: meson: Add boot device discovery

 arch/arm/dts/Makefile                         |    3 +-
 arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
 arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
 arch/arm/include/asm/arch-meson/axg.h         |   52 +
 arch/arm/include/asm/arch-meson/boot.h        |   20 +
 arch/arm/include/asm/arch-meson/clock-axg.h   |  104 ++
 .../asm/arch-meson/{clock.h => clock-gx.h}    |    4 +-
 arch/arm/include/asm/arch-meson/eth.h         |    6 +-
 arch/arm/include/asm/arch-meson/gx.h          |    1 +
 arch/arm/include/asm/arch-meson/mem.h         |    3 +-
 arch/arm/mach-meson/Kconfig                   |  132 +-
 arch/arm/mach-meson/Makefile                  |    4 +-
 arch/arm/mach-meson/board-axg.c               |  118 ++
 arch/arm/mach-meson/board-common.c            |  117 ++
 arch/arm/mach-meson/{board.c => board-gx.c}   |  106 +-
 arch/arm/mach-meson/eth.c                     |   53 -
 arch/arm/mach-meson/sm.c                      |    1 -
 board/amlogic/khadas-vim/Kconfig              |   12 -
 board/amlogic/khadas-vim/MAINTAINERS          |    6 -
 board/amlogic/khadas-vim/khadas-vim.c         |   57 -
 board/amlogic/khadas-vim2/Kconfig             |   12 -
 board/amlogic/libretech-cc/Kconfig            |   12 -
 board/amlogic/libretech-cc/MAINTAINERS        |    6 -
 board/amlogic/libretech-cc/Makefile           |    6 -
 board/amlogic/libretech-cc/libretech-cc.c     |   57 -
 board/amlogic/nanopi-k2/Kconfig               |   12 -
 board/amlogic/nanopi-k2/MAINTAINERS           |    6 -
 board/amlogic/nanopi-k2/Makefile              |    7 -
 board/amlogic/nanopi-k2/nanopi-k2.c           |   55 -
 board/amlogic/odroid-c2/Kconfig               |   12 -
 board/amlogic/odroid-c2/MAINTAINERS           |    1 +
 .../README => odroid-c2/README.nanopi-k2}     |    0
 .../odroid-c2/{README => README.odroid-c2}    |    0
 board/amlogic/odroid-c2/odroid-c2.c           |   16 +-
 board/amlogic/p212/Kconfig                    |   12 -
 .../README => p212/README.khadas-vim}         |    0
 .../README => p212/README.libretech-cc}       |    0
 board/amlogic/p212/{README => README.p212}    |    0
 board/amlogic/p212/p212.c                     |   16 +-
 .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |    6 +-
 board/amlogic/{khadas-vim => q200}/Makefile   |    2 +-
 .../README => q200/README.khadas-vim2}        |    0
 board/amlogic/q200/README.q200                |  102 ++
 .../khadas-vim2.c => q200/q200.c}             |   14 +-
 board/amlogic/s400/MAINTAINERS                |    6 +
 board/amlogic/{khadas-vim2 => s400}/Makefile  |    2 +-
 board/amlogic/s400/README                     |  110 ++
 board/amlogic/s400/s400.c                     |   21 +
 configs/khadas-vim2_defconfig                 |    1 -
 configs/khadas-vim_defconfig                  |    1 -
 configs/libretech-cc_defconfig                |    1 -
 configs/nanopi-k2_defconfig                   |    2 -
 configs/odroid-c2_defconfig                   |    1 -
 configs/p212_defconfig                        |    1 -
 configs/s400_defconfig                        |   38 +
 drivers/clk/Makefile                          |    2 +-
 drivers/clk/clk_meson.c                       |    6 +-
 drivers/clk/clk_meson_axg.c                   |  316 ++++
 drivers/pinctrl/meson/Kconfig                 |   18 +-
 drivers/pinctrl/meson/Makefile                |    3 +
 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c |  125 ++
 drivers/pinctrl/meson/pinctrl-meson-axg.c     |  979 ++++++++++
 drivers/pinctrl/meson/pinctrl-meson-axg.h     |   66 +
 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c  |   97 +
 drivers/pinctrl/meson/pinctrl-meson-gx.h      |   48 +
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c    |    6 +-
 drivers/pinctrl/meson/pinctrl-meson-gxl.c     |    6 +-
 drivers/pinctrl/meson/pinctrl-meson.c         |  109 +-
 drivers/pinctrl/meson/pinctrl-meson.h         |   37 +-
 include/configs/khadas-vim.h                  |   16 -
 include/configs/khadas-vim2.h                 |   18 -
 include/configs/libretech-cc.h                |   16 -
 .../configs/{meson-gx-common.h => meson64.h}  |   49 +-
 include/configs/nanopi-k2.h                   |   16 -
 include/configs/odroid-c2.h                   |   16 -
 include/configs/p212.h                        |   18 -
 include/dt-bindings/clock/axg-aoclkc.h        |   26 +
 include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
 include/dt-bindings/clock/axg-clkc.h          |   76 +
 include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
 .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
 .../reset/amlogic,meson-axg-reset.h           |  124 ++
 include/dt-bindings/reset/axg-aoclkc.h        |   20 +
 83 files changed, 5166 insertions(+), 754 deletions(-)
 create mode 100644 arch/arm/dts/meson-axg-s400.dts
 create mode 100644 arch/arm/dts/meson-axg.dtsi
 create mode 100644 arch/arm/include/asm/arch-meson/axg.h
 create mode 100644 arch/arm/include/asm/arch-meson/boot.h
 create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
 rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
 create mode 100644 arch/arm/mach-meson/board-axg.c
 create mode 100644 arch/arm/mach-meson/board-common.c
 rename arch/arm/mach-meson/{board.c => board-gx.c} (59%)
 delete mode 100644 arch/arm/mach-meson/eth.c
 delete mode 100644 board/amlogic/khadas-vim/Kconfig
 delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
 delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
 delete mode 100644 board/amlogic/khadas-vim2/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
 delete mode 100644 board/amlogic/libretech-cc/Makefile
 delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
 delete mode 100644 board/amlogic/nanopi-k2/Kconfig
 delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
 delete mode 100644 board/amlogic/nanopi-k2/Makefile
 delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
 delete mode 100644 board/amlogic/odroid-c2/Kconfig
 rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
 rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)
 delete mode 100644 board/amlogic/p212/Kconfig
 rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
 rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
 rename board/amlogic/p212/{README => README.p212} (100%)
 rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
 rename board/amlogic/{khadas-vim => q200}/Makefile (85%)
 rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
 create mode 100644 board/amlogic/q200/README.q200
 rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (85%)
 create mode 100644 board/amlogic/s400/MAINTAINERS
 rename board/amlogic/{khadas-vim2 => s400}/Makefile (84%)
 create mode 100644 board/amlogic/s400/README
 create mode 100644 board/amlogic/s400/s400.c
 create mode 100644 configs/s400_defconfig
 create mode 100644 drivers/clk/clk_meson_axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h
 delete mode 100644 include/configs/khadas-vim.h
 delete mode 100644 include/configs/khadas-vim2.h
 delete mode 100644 include/configs/libretech-cc.h
 rename include/configs/{meson-gx-common.h => meson64.h} (51%)
 delete mode 100644 include/configs/nanopi-k2.h
 delete mode 100644 include/configs/odroid-c2.h
 delete mode 100644 include/configs/p212.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
 create mode 100644 include/dt-bindings/clock/axg-clkc.h
 create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.19.1

^ permalink raw reply	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
@ 2018-11-22  9:07 ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

This patchset will refactor the Amlogic Meson SoC support in order to
easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.

In order :
- Cleanup the mach-meson configs
- Move board support to reference design common boards
- Move board Kconfig into mach-meson
- Add AXG pinctrl & clock support
- Add AXG device tree and mach-meson support
- Add support for S400 reference design
- Do a final factorization of the code
- Add USB boot support in U-boot

At the end of the patches, the board code is lighter and we maintain
only the reference designs, where each board will differ in the defconfig.

It will be simpler to add custom board support for future boards with
more changes against the reference designs.

The complete AXG support depends on the :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson axg compatible
patches submitted to the U-Boot mailing list.

Changes since v1:
- Fixed AXG pinctrl request and AO pin count
- Fixed tabs/spaces issues on s400 README

Jerome Brunet (12):
  ARM: meson: clean-up platform selection
  configs: meson: remove unnecessary MESON_FDTFILE_SETTING
  board: amlogic: remove p212 derivatives
  board: amlogic: factorise gxbb boards
  ARM: rework amlogic configuration
  configs: meson: change default load addresses
  pinctrl: meson: rework gx pmx function
  pinctrl: meson: select generic pinctrl
  pinctrl: meson: add axg support
  clk: meson: silence debug print
  ARM: meson: rework soc arch file to prepare for new SoC
  ARM: meson: factorize common code out amlogic's boards

Neil Armstrong (7):
  board: amlogic: move khadas-vim2 as q200 ref board
  clk: meson: add static to meson_gates table
  ARM: meson: Add support for AXG family
  ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
  clk: Add clock driver for AXG
  board: amlogic: add support for S400 board
  ARM: meson: Add boot device discovery

 arch/arm/dts/Makefile                         |    3 +-
 arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
 arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
 arch/arm/include/asm/arch-meson/axg.h         |   52 +
 arch/arm/include/asm/arch-meson/boot.h        |   20 +
 arch/arm/include/asm/arch-meson/clock-axg.h   |  104 ++
 .../asm/arch-meson/{clock.h => clock-gx.h}    |    4 +-
 arch/arm/include/asm/arch-meson/eth.h         |    6 +-
 arch/arm/include/asm/arch-meson/gx.h          |    1 +
 arch/arm/include/asm/arch-meson/mem.h         |    3 +-
 arch/arm/mach-meson/Kconfig                   |  132 +-
 arch/arm/mach-meson/Makefile                  |    4 +-
 arch/arm/mach-meson/board-axg.c               |  118 ++
 arch/arm/mach-meson/board-common.c            |  117 ++
 arch/arm/mach-meson/{board.c => board-gx.c}   |  106 +-
 arch/arm/mach-meson/eth.c                     |   53 -
 arch/arm/mach-meson/sm.c                      |    1 -
 board/amlogic/khadas-vim/Kconfig              |   12 -
 board/amlogic/khadas-vim/MAINTAINERS          |    6 -
 board/amlogic/khadas-vim/khadas-vim.c         |   57 -
 board/amlogic/khadas-vim2/Kconfig             |   12 -
 board/amlogic/libretech-cc/Kconfig            |   12 -
 board/amlogic/libretech-cc/MAINTAINERS        |    6 -
 board/amlogic/libretech-cc/Makefile           |    6 -
 board/amlogic/libretech-cc/libretech-cc.c     |   57 -
 board/amlogic/nanopi-k2/Kconfig               |   12 -
 board/amlogic/nanopi-k2/MAINTAINERS           |    6 -
 board/amlogic/nanopi-k2/Makefile              |    7 -
 board/amlogic/nanopi-k2/nanopi-k2.c           |   55 -
 board/amlogic/odroid-c2/Kconfig               |   12 -
 board/amlogic/odroid-c2/MAINTAINERS           |    1 +
 .../README => odroid-c2/README.nanopi-k2}     |    0
 .../odroid-c2/{README => README.odroid-c2}    |    0
 board/amlogic/odroid-c2/odroid-c2.c           |   16 +-
 board/amlogic/p212/Kconfig                    |   12 -
 .../README => p212/README.khadas-vim}         |    0
 .../README => p212/README.libretech-cc}       |    0
 board/amlogic/p212/{README => README.p212}    |    0
 board/amlogic/p212/p212.c                     |   16 +-
 .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |    6 +-
 board/amlogic/{khadas-vim => q200}/Makefile   |    2 +-
 .../README => q200/README.khadas-vim2}        |    0
 board/amlogic/q200/README.q200                |  102 ++
 .../khadas-vim2.c => q200/q200.c}             |   14 +-
 board/amlogic/s400/MAINTAINERS                |    6 +
 board/amlogic/{khadas-vim2 => s400}/Makefile  |    2 +-
 board/amlogic/s400/README                     |  110 ++
 board/amlogic/s400/s400.c                     |   21 +
 configs/khadas-vim2_defconfig                 |    1 -
 configs/khadas-vim_defconfig                  |    1 -
 configs/libretech-cc_defconfig                |    1 -
 configs/nanopi-k2_defconfig                   |    2 -
 configs/odroid-c2_defconfig                   |    1 -
 configs/p212_defconfig                        |    1 -
 configs/s400_defconfig                        |   38 +
 drivers/clk/Makefile                          |    2 +-
 drivers/clk/clk_meson.c                       |    6 +-
 drivers/clk/clk_meson_axg.c                   |  316 ++++
 drivers/pinctrl/meson/Kconfig                 |   18 +-
 drivers/pinctrl/meson/Makefile                |    3 +
 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c |  125 ++
 drivers/pinctrl/meson/pinctrl-meson-axg.c     |  979 ++++++++++
 drivers/pinctrl/meson/pinctrl-meson-axg.h     |   66 +
 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c  |   97 +
 drivers/pinctrl/meson/pinctrl-meson-gx.h      |   48 +
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c    |    6 +-
 drivers/pinctrl/meson/pinctrl-meson-gxl.c     |    6 +-
 drivers/pinctrl/meson/pinctrl-meson.c         |  109 +-
 drivers/pinctrl/meson/pinctrl-meson.h         |   37 +-
 include/configs/khadas-vim.h                  |   16 -
 include/configs/khadas-vim2.h                 |   18 -
 include/configs/libretech-cc.h                |   16 -
 .../configs/{meson-gx-common.h => meson64.h}  |   49 +-
 include/configs/nanopi-k2.h                   |   16 -
 include/configs/odroid-c2.h                   |   16 -
 include/configs/p212.h                        |   18 -
 include/dt-bindings/clock/axg-aoclkc.h        |   26 +
 include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
 include/dt-bindings/clock/axg-clkc.h          |   76 +
 include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
 .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
 .../reset/amlogic,meson-axg-reset.h           |  124 ++
 include/dt-bindings/reset/axg-aoclkc.h        |   20 +
 83 files changed, 5166 insertions(+), 754 deletions(-)
 create mode 100644 arch/arm/dts/meson-axg-s400.dts
 create mode 100644 arch/arm/dts/meson-axg.dtsi
 create mode 100644 arch/arm/include/asm/arch-meson/axg.h
 create mode 100644 arch/arm/include/asm/arch-meson/boot.h
 create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
 rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
 create mode 100644 arch/arm/mach-meson/board-axg.c
 create mode 100644 arch/arm/mach-meson/board-common.c
 rename arch/arm/mach-meson/{board.c => board-gx.c} (59%)
 delete mode 100644 arch/arm/mach-meson/eth.c
 delete mode 100644 board/amlogic/khadas-vim/Kconfig
 delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
 delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
 delete mode 100644 board/amlogic/khadas-vim2/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
 delete mode 100644 board/amlogic/libretech-cc/Makefile
 delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
 delete mode 100644 board/amlogic/nanopi-k2/Kconfig
 delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
 delete mode 100644 board/amlogic/nanopi-k2/Makefile
 delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
 delete mode 100644 board/amlogic/odroid-c2/Kconfig
 rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
 rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)
 delete mode 100644 board/amlogic/p212/Kconfig
 rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
 rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
 rename board/amlogic/p212/{README => README.p212} (100%)
 rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
 rename board/amlogic/{khadas-vim => q200}/Makefile (85%)
 rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
 create mode 100644 board/amlogic/q200/README.q200
 rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (85%)
 create mode 100644 board/amlogic/s400/MAINTAINERS
 rename board/amlogic/{khadas-vim2 => s400}/Makefile (84%)
 create mode 100644 board/amlogic/s400/README
 create mode 100644 board/amlogic/s400/s400.c
 create mode 100644 configs/s400_defconfig
 create mode 100644 drivers/clk/clk_meson_axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h
 delete mode 100644 include/configs/khadas-vim.h
 delete mode 100644 include/configs/khadas-vim2.h
 delete mode 100644 include/configs/libretech-cc.h
 rename include/configs/{meson-gx-common.h => meson64.h} (51%)
 delete mode 100644 include/configs/nanopi-k2.h
 delete mode 100644 include/configs/odroid-c2.h
 delete mode 100644 include/configs/p212.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
 create mode 100644 include/dt-bindings/clock/axg-clkc.h
 create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.19.1

^ permalink raw reply	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 01/19] ARM: meson: clean-up platform selection
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

Even if multiple board are selected through Kconfig, u-boot will only
compile one. This makes sense since compiling these targets will export
global symbols, such as board_init()

The change rework amlogic Kconfig so only one board may be selected at
a time

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig | 51 +++++++++++++++----------------------
 1 file changed, 20 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index cc943443b3..bc0f6a169b 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -1,41 +1,32 @@
 if ARCH_MESON
 
-config MESON_GXBB
-	bool "Support Meson GXBaby"
+config MESON64_COMMON
+	bool
 	select ARM64
 	select CLK
 	select DM
 	select DM_SERIAL
 	imply CMD_DM
-	help
-	  The Amlogic Meson GXBaby (S905) is an ARM SoC with a
-	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+config MESON_GXBB
+	bool
+	select MESON64_COMMON
 
 config MESON_GXL
-	bool "Support Meson GXL"
-	select ARM64
-	select CLK
-	select DM
-	select DM_SERIAL
-	imply CMD_DM
-	help
-	  The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a
-	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+	bool
+	select MESON64_COMMON
 
 config MESON_GXM
-	bool "Support Meson GXM"
-	select ARM64
-	select CLK
-	select DM
-	select DM_SERIAL
-	help
-	  The Amlogic Meson GXM (S912) is an ARM SoC with an
-	  octo-core Cortex-A53 CPU and a Mali-T860 GPU.
+	bool
+	select MESON64_COMMON
 
-if MESON_GXBB
+choice
+	prompt "Platform select"
+	default TARGET_ODROID_C2
 
 config TARGET_ODROID_C2
 	bool "ODROID-C2"
+	select MESON_GXBB
 	help
 	  ODROID-C2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
@@ -43,16 +34,15 @@ config TARGET_ODROID_C2
 
 config TARGET_NANOPI_K2
 	bool "NANOPI_K2"
+	select MESON_GXBB
 	help
 	  NANOPI_K2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB,
 	  micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header.
-endif
-
-if MESON_GXL
 
 config TARGET_P212
 	bool "P212"
+	select MESON_GXL
 	help
 	  P212 is a reference dessign board based on Meson GXL S905X SoC
 	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
@@ -60,6 +50,7 @@ config TARGET_P212
 
 config TARGET_LIBRETECH_CC
 	bool "LIBRETECH-CC"
+	select MESON_GXL
 	help
 	  LibreTech CC is a single board computer based on Meson GXL
 	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
@@ -67,23 +58,21 @@ config TARGET_LIBRETECH_CC
 
 config TARGET_KHADAS_VIM
 	bool "KHADAS-VIM"
+	select MESON_GXL
 	help
 	  Khadas VIM is a single board computer based on Meson GXL
 	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
 	  eMMC, IR receiver and a 40-pin GPIO header.
 
-endif
-
-if MESON_GXM
-
 config TARGET_KHADAS_VIM2
 	bool "KHADAS-VIM2"
+	select MESON_GXM
 	help
 	  Khadas VIM2 is a single board computer based on Meson GXM
 	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
 	  eMMC, IR receiver and a 40-pin GPIO header.
 
-endif
+endchoice
 
 config SYS_SOC
 	default "meson"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 01/19] ARM: meson: clean-up platform selection
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

Even if multiple board are selected through Kconfig, u-boot will only
compile one. This makes sense since compiling these targets will export
global symbols, such as board_init()

The change rework amlogic Kconfig so only one board may be selected at
a time

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig | 51 +++++++++++++++----------------------
 1 file changed, 20 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index cc943443b3..bc0f6a169b 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -1,41 +1,32 @@
 if ARCH_MESON
 
-config MESON_GXBB
-	bool "Support Meson GXBaby"
+config MESON64_COMMON
+	bool
 	select ARM64
 	select CLK
 	select DM
 	select DM_SERIAL
 	imply CMD_DM
-	help
-	  The Amlogic Meson GXBaby (S905) is an ARM SoC with a
-	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+config MESON_GXBB
+	bool
+	select MESON64_COMMON
 
 config MESON_GXL
-	bool "Support Meson GXL"
-	select ARM64
-	select CLK
-	select DM
-	select DM_SERIAL
-	imply CMD_DM
-	help
-	  The Amlogic Meson GXL (S905X and S905D) is an ARM SoC with a
-	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+	bool
+	select MESON64_COMMON
 
 config MESON_GXM
-	bool "Support Meson GXM"
-	select ARM64
-	select CLK
-	select DM
-	select DM_SERIAL
-	help
-	  The Amlogic Meson GXM (S912) is an ARM SoC with an
-	  octo-core Cortex-A53 CPU and a Mali-T860 GPU.
+	bool
+	select MESON64_COMMON
 
-if MESON_GXBB
+choice
+	prompt "Platform select"
+	default TARGET_ODROID_C2
 
 config TARGET_ODROID_C2
 	bool "ODROID-C2"
+	select MESON_GXBB
 	help
 	  ODROID-C2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
@@ -43,16 +34,15 @@ config TARGET_ODROID_C2
 
 config TARGET_NANOPI_K2
 	bool "NANOPI_K2"
+	select MESON_GXBB
 	help
 	  NANOPI_K2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB,
 	  micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header.
-endif
-
-if MESON_GXL
 
 config TARGET_P212
 	bool "P212"
+	select MESON_GXL
 	help
 	  P212 is a reference dessign board based on Meson GXL S905X SoC
 	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
@@ -60,6 +50,7 @@ config TARGET_P212
 
 config TARGET_LIBRETECH_CC
 	bool "LIBRETECH-CC"
+	select MESON_GXL
 	help
 	  LibreTech CC is a single board computer based on Meson GXL
 	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
@@ -67,23 +58,21 @@ config TARGET_LIBRETECH_CC
 
 config TARGET_KHADAS_VIM
 	bool "KHADAS-VIM"
+	select MESON_GXL
 	help
 	  Khadas VIM is a single board computer based on Meson GXL
 	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
 	  eMMC, IR receiver and a 40-pin GPIO header.
 
-endif
-
-if MESON_GXM
-
 config TARGET_KHADAS_VIM2
 	bool "KHADAS-VIM2"
+	select MESON_GXM
 	help
 	  Khadas VIM2 is a single board computer based on Meson GXM
 	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
 	  eMMC, IR receiver and a 40-pin GPIO header.
 
-endif
+endchoice
 
 config SYS_SOC
 	default "meson"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 02/19] configs: meson: remove unnecessary MESON_FDTFILE_SETTING
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

MESON_FDTFILE_SETTING is used to define the default name of the fdt
file in u-boot environment. We can easily derive it from
CONFIG_DEFAULT_DEVICE_TREE instead. This will help factorize the code
a bit

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 include/configs/khadas-vim.h      | 2 --
 include/configs/libretech-cc.h    | 2 --
 include/configs/meson-gx-common.h | 2 +-
 include/configs/nanopi-k2.h       | 4 ----
 include/configs/odroid-c2.h       | 4 ----
 include/configs/p212.h            | 4 ----
 6 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
index 6615f7711d..ff87c02820 100644
--- a/include/configs/khadas-vim.h
+++ b/include/configs/khadas-vim.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
index a0856f98da..95e0f346fd 100644
--- a/include/configs/libretech-cc.h
+++ b/include/configs/libretech-cc.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h
index c46522ef7e..c43697665d 100644
--- a/include/configs/meson-gx-common.h
+++ b/include/configs/meson-gx-common.h
@@ -44,7 +44,7 @@
 	"kernel_addr_r=0x01080000\0" \
 	"pxefile_addr_r=0x01080000\0" \
 	"ramdisk_addr_r=0x13000000\0" \
-	MESON_FDTFILE_SETTING \
+	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	BOOTENV
 
 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h
index ef53f20c0f..3fd6e8fba4 100644
--- a/include/configs/nanopi-k2.h
+++ b/include/configs/nanopi-k2.h
@@ -7,10 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-nanopi-k2.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index d117b183aa..87e3ddb342 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -7,10 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/p212.h b/include/configs/p212.h
index 2aa9f5d143..4414293479 100644
--- a/include/configs/p212.h
+++ b/include/configs/p212.h
@@ -9,10 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 02/19] configs: meson: remove unnecessary MESON_FDTFILE_SETTING
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

MESON_FDTFILE_SETTING is used to define the default name of the fdt
file in u-boot environment. We can easily derive it from
CONFIG_DEFAULT_DEVICE_TREE instead. This will help factorize the code
a bit

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 include/configs/khadas-vim.h      | 2 --
 include/configs/libretech-cc.h    | 2 --
 include/configs/meson-gx-common.h | 2 +-
 include/configs/nanopi-k2.h       | 4 ----
 include/configs/odroid-c2.h       | 4 ----
 include/configs/p212.h            | 4 ----
 6 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
index 6615f7711d..ff87c02820 100644
--- a/include/configs/khadas-vim.h
+++ b/include/configs/khadas-vim.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
index a0856f98da..95e0f346fd 100644
--- a/include/configs/libretech-cc.h
+++ b/include/configs/libretech-cc.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/meson-gx-common.h b/include/configs/meson-gx-common.h
index c46522ef7e..c43697665d 100644
--- a/include/configs/meson-gx-common.h
+++ b/include/configs/meson-gx-common.h
@@ -44,7 +44,7 @@
 	"kernel_addr_r=0x01080000\0" \
 	"pxefile_addr_r=0x01080000\0" \
 	"ramdisk_addr_r=0x13000000\0" \
-	MESON_FDTFILE_SETTING \
+	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	BOOTENV
 
 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h
index ef53f20c0f..3fd6e8fba4 100644
--- a/include/configs/nanopi-k2.h
+++ b/include/configs/nanopi-k2.h
@@ -7,10 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-nanopi-k2.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
index d117b183aa..87e3ddb342 100644
--- a/include/configs/odroid-c2.h
+++ b/include/configs/odroid-c2.h
@@ -7,10 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxbb-odroidc2.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/p212.h b/include/configs/p212.h
index 2aa9f5d143..4414293479 100644
--- a/include/configs/p212.h
+++ b/include/configs/p212.h
@@ -9,10 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/* Serial setup */
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-p212.dtb\0"
-
 #include <configs/meson-gx-common.h>
 
 #endif /* __CONFIG_H */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 03/19] board: amlogic: remove p212 derivatives
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive
from amlogic s905x reference design (P212).

All the code in these board is a copy/paste from the p212, which is
tedious to maintain. This change use p212 u-boot board for all these
boards, while keeping a dedicated defconfig to customize the names
and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 22 +------
 board/amlogic/khadas-vim/Kconfig              | 12 ----
 board/amlogic/khadas-vim/MAINTAINERS          |  6 --
 board/amlogic/khadas-vim/Makefile             |  6 --
 board/amlogic/khadas-vim/khadas-vim.c         | 57 -------------------
 board/amlogic/libretech-cc/Kconfig            | 12 ----
 board/amlogic/libretech-cc/MAINTAINERS        |  6 --
 board/amlogic/libretech-cc/Makefile           |  6 --
 board/amlogic/libretech-cc/libretech-cc.c     | 57 -------------------
 .../README => p212/README.khadas-vim}         |  0
 .../README => p212/README.libretech-cc}       |  0
 board/amlogic/p212/{README => README.p212}    |  0
 configs/khadas-vim_defconfig                  |  2 +-
 configs/libretech-cc_defconfig                |  2 +-
 14 files changed, 4 insertions(+), 184 deletions(-)
 delete mode 100644 board/amlogic/khadas-vim/Kconfig
 delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
 delete mode 100644 board/amlogic/khadas-vim/Makefile
 delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
 delete mode 100644 board/amlogic/libretech-cc/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
 delete mode 100644 board/amlogic/libretech-cc/Makefile
 delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
 rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
 rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
 rename board/amlogic/p212/{README => README.p212} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index bc0f6a169b..e0b2812477 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -47,22 +47,8 @@ config TARGET_P212
 	  P212 is a reference dessign board based on Meson GXL S905X SoC
 	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
 	  eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
-
-config TARGET_LIBRETECH_CC
-	bool "LIBRETECH-CC"
-	select MESON_GXL
-	help
-	  LibreTech CC is a single board computer based on Meson GXL
-	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
-
-config TARGET_KHADAS_VIM
-	bool "KHADAS-VIM"
-	select MESON_GXL
-	help
-	  Khadas VIM is a single board computer based on Meson GXL
-	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
+	  You should also select this TARGET if you have Khadas Vim or
+	  a libretech aml-s905x-cc
 
 config TARGET_KHADAS_VIM2
 	bool "KHADAS-VIM2"
@@ -86,10 +72,6 @@ source "board/amlogic/nanopi-k2/Kconfig"
 
 source "board/amlogic/p212/Kconfig"
 
-source "board/amlogic/libretech-cc/Kconfig"
-
-source "board/amlogic/khadas-vim/Kconfig"
-
 source "board/amlogic/khadas-vim2/Kconfig"
 
 endif
diff --git a/board/amlogic/khadas-vim/Kconfig b/board/amlogic/khadas-vim/Kconfig
deleted file mode 100644
index 0fa8db97ea..0000000000
--- a/board/amlogic/khadas-vim/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KHADAS_VIM
-
-config SYS_BOARD
-	default "khadas-vim"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "khadas-vim"
-
-endif
diff --git a/board/amlogic/khadas-vim/MAINTAINERS b/board/amlogic/khadas-vim/MAINTAINERS
deleted file mode 100644
index 024220a526..0000000000
--- a/board/amlogic/khadas-vim/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KHADAS-VIM
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/khadas-vim/
-F:	include/configs/khadas-vim.h
-F:	configs/khadas-vim_defconfig
diff --git a/board/amlogic/khadas-vim/Makefile b/board/amlogic/khadas-vim/Makefile
deleted file mode 100644
index 558c0769b7..0000000000
--- a/board/amlogic/khadas-vim/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2016 BayLibre, SAS
-# Author: Neil Armstrong <narmstrong@baylibre.com>
-
-obj-y	:= khadas-vim.o
diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c
deleted file mode 100644
index 692bf2add3..0000000000
--- a/board/amlogic/khadas-vim/khadas-vim.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-					  EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/libretech-cc/Kconfig b/board/amlogic/libretech-cc/Kconfig
deleted file mode 100644
index 7a6f9169bd..0000000000
--- a/board/amlogic/libretech-cc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LIBRETECH_CC
-
-config SYS_BOARD
-	default "libretech-cc"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "libretech-cc"
-
-endif
diff --git a/board/amlogic/libretech-cc/MAINTAINERS b/board/amlogic/libretech-cc/MAINTAINERS
deleted file mode 100644
index 398ce57db2..0000000000
--- a/board/amlogic/libretech-cc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LIBRETECH-CC
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/libretech-cc/
-F:	include/configs/libretech-cc.h
-F:	configs/libretech-cc_defconfig
diff --git a/board/amlogic/libretech-cc/Makefile b/board/amlogic/libretech-cc/Makefile
deleted file mode 100644
index 3b0adf8bf5..0000000000
--- a/board/amlogic/libretech-cc/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2016 BayLibre, SAS
-# Author: Neil Armstrong <narmstrong@baylibre.com>
-
-obj-y	:= libretech-cc.o
diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c
deleted file mode 100644
index ccab1272c5..0000000000
--- a/board/amlogic/libretech-cc/libretech-cc.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-#include <asm/arch/mem.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-					  EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/p212/README.khadas-vim
similarity index 100%
rename from board/amlogic/khadas-vim/README
rename to board/amlogic/p212/README.khadas-vim
diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/p212/README.libretech-cc
similarity index 100%
rename from board/amlogic/libretech-cc/README
rename to board/amlogic/p212/README.libretech-cc
diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README.p212
similarity index 100%
rename from board/amlogic/p212/README
rename to board/amlogic/p212/README.p212
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 0c89d9a22c..af30113760 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_KHADAS_VIM=y
+CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim"
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 36d117c4ab..7526516060 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_LIBRETECH_CC=y
+CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" libretech-cc"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 03/19] board: amlogic: remove p212 derivatives
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

The Khadas vim and the libretech aml-s905x-cc (aka Potato) derive
from amlogic s905x reference design (P212).

All the code in these board is a copy/paste from the p212, which is
tedious to maintain. This change use p212 u-boot board for all these
boards, while keeping a dedicated defconfig to customize the names
and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 22 +------
 board/amlogic/khadas-vim/Kconfig              | 12 ----
 board/amlogic/khadas-vim/MAINTAINERS          |  6 --
 board/amlogic/khadas-vim/Makefile             |  6 --
 board/amlogic/khadas-vim/khadas-vim.c         | 57 -------------------
 board/amlogic/libretech-cc/Kconfig            | 12 ----
 board/amlogic/libretech-cc/MAINTAINERS        |  6 --
 board/amlogic/libretech-cc/Makefile           |  6 --
 board/amlogic/libretech-cc/libretech-cc.c     | 57 -------------------
 .../README => p212/README.khadas-vim}         |  0
 .../README => p212/README.libretech-cc}       |  0
 board/amlogic/p212/{README => README.p212}    |  0
 configs/khadas-vim_defconfig                  |  2 +-
 configs/libretech-cc_defconfig                |  2 +-
 14 files changed, 4 insertions(+), 184 deletions(-)
 delete mode 100644 board/amlogic/khadas-vim/Kconfig
 delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
 delete mode 100644 board/amlogic/khadas-vim/Makefile
 delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
 delete mode 100644 board/amlogic/libretech-cc/Kconfig
 delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
 delete mode 100644 board/amlogic/libretech-cc/Makefile
 delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
 rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
 rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
 rename board/amlogic/p212/{README => README.p212} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index bc0f6a169b..e0b2812477 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -47,22 +47,8 @@ config TARGET_P212
 	  P212 is a reference dessign board based on Meson GXL S905X SoC
 	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
 	  eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
-
-config TARGET_LIBRETECH_CC
-	bool "LIBRETECH-CC"
-	select MESON_GXL
-	help
-	  LibreTech CC is a single board computer based on Meson GXL
-	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
-
-config TARGET_KHADAS_VIM
-	bool "KHADAS-VIM"
-	select MESON_GXL
-	help
-	  Khadas VIM is a single board computer based on Meson GXL
-	  with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
+	  You should also select this TARGET if you have Khadas Vim or
+	  a libretech aml-s905x-cc
 
 config TARGET_KHADAS_VIM2
 	bool "KHADAS-VIM2"
@@ -86,10 +72,6 @@ source "board/amlogic/nanopi-k2/Kconfig"
 
 source "board/amlogic/p212/Kconfig"
 
-source "board/amlogic/libretech-cc/Kconfig"
-
-source "board/amlogic/khadas-vim/Kconfig"
-
 source "board/amlogic/khadas-vim2/Kconfig"
 
 endif
diff --git a/board/amlogic/khadas-vim/Kconfig b/board/amlogic/khadas-vim/Kconfig
deleted file mode 100644
index 0fa8db97ea..0000000000
--- a/board/amlogic/khadas-vim/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KHADAS_VIM
-
-config SYS_BOARD
-	default "khadas-vim"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "khadas-vim"
-
-endif
diff --git a/board/amlogic/khadas-vim/MAINTAINERS b/board/amlogic/khadas-vim/MAINTAINERS
deleted file mode 100644
index 024220a526..0000000000
--- a/board/amlogic/khadas-vim/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KHADAS-VIM
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/khadas-vim/
-F:	include/configs/khadas-vim.h
-F:	configs/khadas-vim_defconfig
diff --git a/board/amlogic/khadas-vim/Makefile b/board/amlogic/khadas-vim/Makefile
deleted file mode 100644
index 558c0769b7..0000000000
--- a/board/amlogic/khadas-vim/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2016 BayLibre, SAS
-# Author: Neil Armstrong <narmstrong@baylibre.com>
-
-obj-y	:= khadas-vim.o
diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c
deleted file mode 100644
index 692bf2add3..0000000000
--- a/board/amlogic/khadas-vim/khadas-vim.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-					  EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/libretech-cc/Kconfig b/board/amlogic/libretech-cc/Kconfig
deleted file mode 100644
index 7a6f9169bd..0000000000
--- a/board/amlogic/libretech-cc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_LIBRETECH_CC
-
-config SYS_BOARD
-	default "libretech-cc"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "libretech-cc"
-
-endif
diff --git a/board/amlogic/libretech-cc/MAINTAINERS b/board/amlogic/libretech-cc/MAINTAINERS
deleted file mode 100644
index 398ce57db2..0000000000
--- a/board/amlogic/libretech-cc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LIBRETECH-CC
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/libretech-cc/
-F:	include/configs/libretech-cc.h
-F:	configs/libretech-cc_defconfig
diff --git a/board/amlogic/libretech-cc/Makefile b/board/amlogic/libretech-cc/Makefile
deleted file mode 100644
index 3b0adf8bf5..0000000000
--- a/board/amlogic/libretech-cc/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2016 BayLibre, SAS
-# Author: Neil Armstrong <narmstrong@baylibre.com>
-
-obj-y	:= libretech-cc.o
diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c
deleted file mode 100644
index ccab1272c5..0000000000
--- a/board/amlogic/libretech-cc/libretech-cc.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-#include <asm/arch/mem.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-					  EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/khadas-vim/README b/board/amlogic/p212/README.khadas-vim
similarity index 100%
rename from board/amlogic/khadas-vim/README
rename to board/amlogic/p212/README.khadas-vim
diff --git a/board/amlogic/libretech-cc/README b/board/amlogic/p212/README.libretech-cc
similarity index 100%
rename from board/amlogic/libretech-cc/README
rename to board/amlogic/p212/README.libretech-cc
diff --git a/board/amlogic/p212/README b/board/amlogic/p212/README.p212
similarity index 100%
rename from board/amlogic/p212/README
rename to board/amlogic/p212/README.p212
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 0c89d9a22c..af30113760 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_KHADAS_VIM=y
+CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim"
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 36d117c4ab..7526516060 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_LIBRETECH_CC=y
+CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" libretech-cc"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 04/19] board: amlogic: move khadas-vim2 as q200 ref board
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

The Khadas vim2 derive from amlogic s912 reference design (Q200).

This patch moves the khadas-vim2 board support to a generic Q200 board,
while keeping a dedicated defconfig to customize the names and device tree.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   |   9 +-
 board/amlogic/{khadas-vim2 => q200}/Kconfig   |   6 +-
 .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |   6 +-
 board/amlogic/{khadas-vim2 => q200}/Makefile  |   2 +-
 .../README => q200/README.khadas-vim2}        |   0
 board/amlogic/q200/README.q200                | 102 ++++++++++++++++++
 .../khadas-vim2.c => q200/q200.c}             |   0
 configs/khadas-vim2_defconfig                 |   2 +-
 include/configs/{khadas-vim2.h => q200.h}     |   0
 9 files changed, 115 insertions(+), 12 deletions(-)
 rename board/amlogic/{khadas-vim2 => q200}/Kconfig (56%)
 rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
 rename board/amlogic/{khadas-vim2 => q200}/Makefile (84%)
 rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
 create mode 100644 board/amlogic/q200/README.q200
 rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (100%)
 rename include/configs/{khadas-vim2.h => q200.h} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index e0b2812477..98303dbda1 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -50,13 +50,14 @@ config TARGET_P212
 	  You should also select this TARGET if you have Khadas Vim or
 	  a libretech aml-s905x-cc
 
-config TARGET_KHADAS_VIM2
+config TARGET_Q200
 	bool "KHADAS-VIM2"
 	select MESON_GXM
 	help
-	  Khadas VIM2 is a single board computer based on Meson GXM
+	  Q200 is a reference dessign board based on Meson GXM
 	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
+	  eMMC, IR receiver.
+	  You should also select this TARGET if you have Khadas Vim2.
 
 endchoice
 
@@ -72,6 +73,6 @@ source "board/amlogic/nanopi-k2/Kconfig"
 
 source "board/amlogic/p212/Kconfig"
 
-source "board/amlogic/khadas-vim2/Kconfig"
+source "board/amlogic/q200/Kconfig"
 
 endif
diff --git a/board/amlogic/khadas-vim2/Kconfig b/board/amlogic/q200/Kconfig
similarity index 56%
rename from board/amlogic/khadas-vim2/Kconfig
rename to board/amlogic/q200/Kconfig
index d0af36264d..cfaf3797ac 100644
--- a/board/amlogic/khadas-vim2/Kconfig
+++ b/board/amlogic/q200/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_KHADAS_VIM2
+if TARGET_Q200
 
 config SYS_BOARD
-	default "khadas-vim2"
+	default "q200"
 
 config SYS_VENDOR
 	default "amlogic"
 
 config SYS_CONFIG_NAME
-	default "khadas-vim2"
+	default "q200"
 
 endif
diff --git a/board/amlogic/khadas-vim2/MAINTAINERS b/board/amlogic/q200/MAINTAINERS
similarity index 54%
rename from board/amlogic/khadas-vim2/MAINTAINERS
rename to board/amlogic/q200/MAINTAINERS
index ca63e311c6..be86386619 100644
--- a/board/amlogic/khadas-vim2/MAINTAINERS
+++ b/board/amlogic/q200/MAINTAINERS
@@ -1,6 +1,6 @@
-KHADAS-VIM2
+Q200
 M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
-F:	board/amlogic/khadas-vim2/
-F:	include/configs/khadas-vim2.h
+F:	board/amlogic/q200/
+F:	include/configs/q200.h
 F:	configs/khadas-vim2_defconfig
diff --git a/board/amlogic/khadas-vim2/Makefile b/board/amlogic/q200/Makefile
similarity index 84%
rename from board/amlogic/khadas-vim2/Makefile
rename to board/amlogic/q200/Makefile
index 4e7c9a0592..fd78fd068a 100644
--- a/board/amlogic/khadas-vim2/Makefile
+++ b/board/amlogic/q200/Makefile
@@ -3,4 +3,4 @@
 # (C) Copyright 2016 BayLibre, SAS
 # Author: Neil Armstrong <narmstrong@baylibre.com>
 
-obj-y	:= khadas-vim2.o
+obj-y	:= q200.o
diff --git a/board/amlogic/khadas-vim2/README b/board/amlogic/q200/README.khadas-vim2
similarity index 100%
rename from board/amlogic/khadas-vim2/README
rename to board/amlogic/q200/README.khadas-vim2
diff --git a/board/amlogic/q200/README.q200 b/board/amlogic/q200/README.q200
new file mode 100644
index 0000000000..55d730a0d2
--- /dev/null
+++ b/board/amlogic/q200/README.q200
@@ -0,0 +1,102 @@
+U-Boot for Amlogic Q200
+=======================
+
+Q200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T860 GPU
+ - 2/3GB DDR4 SDRAM
+ - 10/100/1000 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 16GB/32GB/64GB eMMC
+ - 2MB SPI Flash
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - IR receiver
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+U-Boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make khadas-vim2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make gxm_q200_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl30.bin \
+	fip/zero_tmp \
+	fip/bl30_zero.bin \
+	fip/bl301.bin \
+	fip/bl301_zero.bin \
+	fip/bl30_new.bin \
+	bl30
+
+ > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl2_acs.bin \
+	fip/zero_tmp \
+	fip/bl2_zero.bin \
+	fip/bl21.bin \
+	fip/bl21_zero.bin \
+	fip/bl2_new.bin \
+	bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+		--output fip/u-boot.bin \
+		--bl2 fip/bl2.n.bin.sig \
+		--bl30 fip/bl30_new.bin.enc \
+		--bl31 fip/bl31.img.enc \
+		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/khadas-vim2/khadas-vim2.c b/board/amlogic/q200/q200.c
similarity index 100%
rename from board/amlogic/khadas-vim2/khadas-vim2.c
rename to board/amlogic/q200/q200.c
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 4bbccc2f34..49b8104960 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXM=y
-CONFIG_TARGET_KHADAS_VIM2=y
+CONFIG_TARGET_Q200=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim2"
diff --git a/include/configs/khadas-vim2.h b/include/configs/q200.h
similarity index 100%
rename from include/configs/khadas-vim2.h
rename to include/configs/q200.h
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 04/19] board: amlogic: move khadas-vim2 as q200 ref board
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

The Khadas vim2 derive from amlogic s912 reference design (Q200).

This patch moves the khadas-vim2 board support to a generic Q200 board,
while keeping a dedicated defconfig to customize the names and device tree.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   |   9 +-
 board/amlogic/{khadas-vim2 => q200}/Kconfig   |   6 +-
 .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |   6 +-
 board/amlogic/{khadas-vim2 => q200}/Makefile  |   2 +-
 .../README => q200/README.khadas-vim2}        |   0
 board/amlogic/q200/README.q200                | 102 ++++++++++++++++++
 .../khadas-vim2.c => q200/q200.c}             |   0
 configs/khadas-vim2_defconfig                 |   2 +-
 include/configs/{khadas-vim2.h => q200.h}     |   0
 9 files changed, 115 insertions(+), 12 deletions(-)
 rename board/amlogic/{khadas-vim2 => q200}/Kconfig (56%)
 rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
 rename board/amlogic/{khadas-vim2 => q200}/Makefile (84%)
 rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
 create mode 100644 board/amlogic/q200/README.q200
 rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (100%)
 rename include/configs/{khadas-vim2.h => q200.h} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index e0b2812477..98303dbda1 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -50,13 +50,14 @@ config TARGET_P212
 	  You should also select this TARGET if you have Khadas Vim or
 	  a libretech aml-s905x-cc
 
-config TARGET_KHADAS_VIM2
+config TARGET_Q200
 	bool "KHADAS-VIM2"
 	select MESON_GXM
 	help
-	  Khadas VIM2 is a single board computer based on Meson GXM
+	  Q200 is a reference dessign board based on Meson GXM
 	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver and a 40-pin GPIO header.
+	  eMMC, IR receiver.
+	  You should also select this TARGET if you have Khadas Vim2.
 
 endchoice
 
@@ -72,6 +73,6 @@ source "board/amlogic/nanopi-k2/Kconfig"
 
 source "board/amlogic/p212/Kconfig"
 
-source "board/amlogic/khadas-vim2/Kconfig"
+source "board/amlogic/q200/Kconfig"
 
 endif
diff --git a/board/amlogic/khadas-vim2/Kconfig b/board/amlogic/q200/Kconfig
similarity index 56%
rename from board/amlogic/khadas-vim2/Kconfig
rename to board/amlogic/q200/Kconfig
index d0af36264d..cfaf3797ac 100644
--- a/board/amlogic/khadas-vim2/Kconfig
+++ b/board/amlogic/q200/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_KHADAS_VIM2
+if TARGET_Q200
 
 config SYS_BOARD
-	default "khadas-vim2"
+	default "q200"
 
 config SYS_VENDOR
 	default "amlogic"
 
 config SYS_CONFIG_NAME
-	default "khadas-vim2"
+	default "q200"
 
 endif
diff --git a/board/amlogic/khadas-vim2/MAINTAINERS b/board/amlogic/q200/MAINTAINERS
similarity index 54%
rename from board/amlogic/khadas-vim2/MAINTAINERS
rename to board/amlogic/q200/MAINTAINERS
index ca63e311c6..be86386619 100644
--- a/board/amlogic/khadas-vim2/MAINTAINERS
+++ b/board/amlogic/q200/MAINTAINERS
@@ -1,6 +1,6 @@
-KHADAS-VIM2
+Q200
 M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
-F:	board/amlogic/khadas-vim2/
-F:	include/configs/khadas-vim2.h
+F:	board/amlogic/q200/
+F:	include/configs/q200.h
 F:	configs/khadas-vim2_defconfig
diff --git a/board/amlogic/khadas-vim2/Makefile b/board/amlogic/q200/Makefile
similarity index 84%
rename from board/amlogic/khadas-vim2/Makefile
rename to board/amlogic/q200/Makefile
index 4e7c9a0592..fd78fd068a 100644
--- a/board/amlogic/khadas-vim2/Makefile
+++ b/board/amlogic/q200/Makefile
@@ -3,4 +3,4 @@
 # (C) Copyright 2016 BayLibre, SAS
 # Author: Neil Armstrong <narmstrong@baylibre.com>
 
-obj-y	:= khadas-vim2.o
+obj-y	:= q200.o
diff --git a/board/amlogic/khadas-vim2/README b/board/amlogic/q200/README.khadas-vim2
similarity index 100%
rename from board/amlogic/khadas-vim2/README
rename to board/amlogic/q200/README.khadas-vim2
diff --git a/board/amlogic/q200/README.q200 b/board/amlogic/q200/README.q200
new file mode 100644
index 0000000000..55d730a0d2
--- /dev/null
+++ b/board/amlogic/q200/README.q200
@@ -0,0 +1,102 @@
+U-Boot for Amlogic Q200
+=======================
+
+Q200 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T860 GPU
+ - 2/3GB DDR4 SDRAM
+ - 10/100/1000 Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 16GB/32GB/64GB eMMC
+ - 2MB SPI Flash
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - IR receiver
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC, microSD
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+U-Boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make khadas-vim2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make gxm_q200_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/gxl/bl2.bin fip/
+ > cp $FIPDIR/gxl/acs.bin fip/
+ > cp $FIPDIR/gxl/bl21.bin fip/
+ > cp $FIPDIR/gxl/bl30.bin fip/
+ > cp $FIPDIR/gxl/bl301.bin fip/
+ > cp $FIPDIR/gxl/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl30.bin \
+	fip/zero_tmp \
+	fip/bl30_zero.bin \
+	fip/bl301.bin \
+	fip/bl301_zero.bin \
+	fip/bl30_new.bin \
+	bl30
+
+ > python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl2_acs.bin \
+	fip/zero_tmp \
+	fip/bl2_zero.bin \
+	fip/bl21.bin \
+	fip/bl21_zero.bin \
+	fip/bl2_new.bin \
+	bl2
+
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+		--output fip/u-boot.bin \
+		--bl2 fip/bl2.n.bin.sig \
+		--bl30 fip/bl30_new.bin.enc \
+		--bl31 fip/bl31.img.enc \
+		--bl33 fip/bl33.bin.enc
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/khadas-vim2/khadas-vim2.c b/board/amlogic/q200/q200.c
similarity index 100%
rename from board/amlogic/khadas-vim2/khadas-vim2.c
rename to board/amlogic/q200/q200.c
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 4bbccc2f34..49b8104960 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXM=y
-CONFIG_TARGET_KHADAS_VIM2=y
+CONFIG_TARGET_Q200=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim2"
diff --git a/include/configs/khadas-vim2.h b/include/configs/q200.h
similarity index 100%
rename from include/configs/khadas-vim2.h
rename to include/configs/q200.h
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 05/19] board: amlogic: factorise gxbb boards
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

The nanopi-k2 and the odroid-c2 are similar enough to be supported
by the same u-boot board. This change use odroid-c2 u-boot board
for the nanopi-k2 as well. Dedicated defconfig are kept to customize
the names and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 11 +---
 board/amlogic/nanopi-k2/Kconfig               | 12 ----
 board/amlogic/nanopi-k2/MAINTAINERS           |  6 --
 board/amlogic/nanopi-k2/Makefile              |  7 ---
 board/amlogic/nanopi-k2/nanopi-k2.c           | 55 -------------------
 board/amlogic/odroid-c2/MAINTAINERS           |  1 +
 .../README => odroid-c2/README.nanopi-k2}     |  0
 .../odroid-c2/{README => README.odroid-c2}    |  0
 configs/nanopi-k2_defconfig                   |  2 +-
 9 files changed, 3 insertions(+), 91 deletions(-)
 delete mode 100644 board/amlogic/nanopi-k2/Kconfig
 delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
 delete mode 100644 board/amlogic/nanopi-k2/Makefile
 delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
 rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
 rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 98303dbda1..d86b1bed78 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -31,14 +31,7 @@ config TARGET_ODROID_C2
 	  ODROID-C2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
 	  slot, eMMC, IR receiver and a 40-pin GPIO header.
-
-config TARGET_NANOPI_K2
-	bool "NANOPI_K2"
-	select MESON_GXBB
-	help
-	  NANOPI_K2 is a single board computer based on Meson GXBaby
-	  with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB,
-	  micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header.
+	  You should also select this TARGET if you have an nanopi-k2
 
 config TARGET_P212
 	bool "P212"
@@ -69,8 +62,6 @@ config SYS_MALLOC_F_LEN
 
 source "board/amlogic/odroid-c2/Kconfig"
 
-source "board/amlogic/nanopi-k2/Kconfig"
-
 source "board/amlogic/p212/Kconfig"
 
 source "board/amlogic/q200/Kconfig"
diff --git a/board/amlogic/nanopi-k2/Kconfig b/board/amlogic/nanopi-k2/Kconfig
deleted file mode 100644
index 374bda200c..0000000000
--- a/board/amlogic/nanopi-k2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_NANOPI_K2
-
-config SYS_BOARD
-	default "nanopi-k2"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "nanopi-k2"
-
-endif
diff --git a/board/amlogic/nanopi-k2/MAINTAINERS b/board/amlogic/nanopi-k2/MAINTAINERS
deleted file mode 100644
index 0452bd1fa1..0000000000
--- a/board/amlogic/nanopi-k2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-NANOPI-K2
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/nanopi-k2/
-F:	include/configs/nanopi-k2.h
-F:	configs/nanopi-k2_defconfig
diff --git a/board/amlogic/nanopi-k2/Makefile b/board/amlogic/nanopi-k2/Makefile
deleted file mode 100644
index 7d9b666e76..0000000000
--- a/board/amlogic/nanopi-k2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2018 Thomas McKahan
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= nanopi-k2.o
diff --git a/board/amlogic/nanopi-k2/nanopi-k2.c b/board/amlogic/nanopi-k2/nanopi-k2.c
deleted file mode 100644
index ae29dd6fa4..0000000000
--- a/board/amlogic/nanopi-k2/nanopi-k2.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2018 Thomas McKahan
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-#include <asm/arch/mem.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-			EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS
index 699850fd0c..fd74d53bfe 100644
--- a/board/amlogic/odroid-c2/MAINTAINERS
+++ b/board/amlogic/odroid-c2/MAINTAINERS
@@ -1,5 +1,6 @@
 ODROID-C2
 M:	Beniamino Galvani <b.galvani@gmail.com>
+M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
 F:	board/amlogic/odroid-c2/
 F:	include/configs/odroid-c2.h
diff --git a/board/amlogic/nanopi-k2/README b/board/amlogic/odroid-c2/README.nanopi-k2
similarity index 100%
rename from board/amlogic/nanopi-k2/README
rename to board/amlogic/odroid-c2/README.nanopi-k2
diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README.odroid-c2
similarity index 100%
rename from board/amlogic/odroid-c2/README
rename to board/amlogic/odroid-c2/README.odroid-c2
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 5c8c747bf3..01196d6655 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXBB=y
-CONFIG_TARGET_NANOPI_K2=y
+CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" nanopi-k2"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 05/19] board: amlogic: factorise gxbb boards
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

The nanopi-k2 and the odroid-c2 are similar enough to be supported
by the same u-boot board. This change use odroid-c2 u-boot board
for the nanopi-k2 as well. Dedicated defconfig are kept to customize
the names and device tree.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 11 +---
 board/amlogic/nanopi-k2/Kconfig               | 12 ----
 board/amlogic/nanopi-k2/MAINTAINERS           |  6 --
 board/amlogic/nanopi-k2/Makefile              |  7 ---
 board/amlogic/nanopi-k2/nanopi-k2.c           | 55 -------------------
 board/amlogic/odroid-c2/MAINTAINERS           |  1 +
 .../README => odroid-c2/README.nanopi-k2}     |  0
 .../odroid-c2/{README => README.odroid-c2}    |  0
 configs/nanopi-k2_defconfig                   |  2 +-
 9 files changed, 3 insertions(+), 91 deletions(-)
 delete mode 100644 board/amlogic/nanopi-k2/Kconfig
 delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
 delete mode 100644 board/amlogic/nanopi-k2/Makefile
 delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
 rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
 rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 98303dbda1..d86b1bed78 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -31,14 +31,7 @@ config TARGET_ODROID_C2
 	  ODROID-C2 is a single board computer based on Meson GXBaby
 	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
 	  slot, eMMC, IR receiver and a 40-pin GPIO header.
-
-config TARGET_NANOPI_K2
-	bool "NANOPI_K2"
-	select MESON_GXBB
-	help
-	  NANOPI_K2 is a single board computer based on Meson GXBaby
-	  with 2 GiB of RAM, Gigabit Ethernet,AP6212 Wifi, HDMI, 4 USB,
-	  micro-SD slot, eMMC, IR receiver and a 40-pin GPIO header.
+	  You should also select this TARGET if you have an nanopi-k2
 
 config TARGET_P212
 	bool "P212"
@@ -69,8 +62,6 @@ config SYS_MALLOC_F_LEN
 
 source "board/amlogic/odroid-c2/Kconfig"
 
-source "board/amlogic/nanopi-k2/Kconfig"
-
 source "board/amlogic/p212/Kconfig"
 
 source "board/amlogic/q200/Kconfig"
diff --git a/board/amlogic/nanopi-k2/Kconfig b/board/amlogic/nanopi-k2/Kconfig
deleted file mode 100644
index 374bda200c..0000000000
--- a/board/amlogic/nanopi-k2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_NANOPI_K2
-
-config SYS_BOARD
-	default "nanopi-k2"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "nanopi-k2"
-
-endif
diff --git a/board/amlogic/nanopi-k2/MAINTAINERS b/board/amlogic/nanopi-k2/MAINTAINERS
deleted file mode 100644
index 0452bd1fa1..0000000000
--- a/board/amlogic/nanopi-k2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-NANOPI-K2
-M:	Neil Armstrong <narmstrong@baylibre.com>
-S:	Maintained
-F:	board/amlogic/nanopi-k2/
-F:	include/configs/nanopi-k2.h
-F:	configs/nanopi-k2_defconfig
diff --git a/board/amlogic/nanopi-k2/Makefile b/board/amlogic/nanopi-k2/Makefile
deleted file mode 100644
index 7d9b666e76..0000000000
--- a/board/amlogic/nanopi-k2/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2018 Thomas McKahan
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= nanopi-k2.o
diff --git a/board/amlogic/nanopi-k2/nanopi-k2.c b/board/amlogic/nanopi-k2/nanopi-k2.c
deleted file mode 100644
index ae29dd6fa4..0000000000
--- a/board/amlogic/nanopi-k2/nanopi-k2.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2018 Thomas McKahan
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
-#include <asm/arch/eth.h>
-#include <asm/arch/mem.h>
-
-#define EFUSE_SN_OFFSET		20
-#define EFUSE_SN_SIZE		16
-#define EFUSE_MAC_OFFSET	52
-#define EFUSE_MAC_SIZE		6
-
-int board_init(void)
-{
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u8 mac_addr[EFUSE_MAC_SIZE];
-	char serial[EFUSE_SN_SIZE];
-	ssize_t len;
-
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
-		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
-					  mac_addr, EFUSE_MAC_SIZE);
-		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
-			eth_env_set_enetaddr("ethaddr", mac_addr);
-	}
-
-	if (!env_get("serial#")) {
-		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
-			EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE)
-			env_set("serial#", serial);
-	}
-
-	return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_gx_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/odroid-c2/MAINTAINERS
index 699850fd0c..fd74d53bfe 100644
--- a/board/amlogic/odroid-c2/MAINTAINERS
+++ b/board/amlogic/odroid-c2/MAINTAINERS
@@ -1,5 +1,6 @@
 ODROID-C2
 M:	Beniamino Galvani <b.galvani@gmail.com>
+M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
 F:	board/amlogic/odroid-c2/
 F:	include/configs/odroid-c2.h
diff --git a/board/amlogic/nanopi-k2/README b/board/amlogic/odroid-c2/README.nanopi-k2
similarity index 100%
rename from board/amlogic/nanopi-k2/README
rename to board/amlogic/odroid-c2/README.nanopi-k2
diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README.odroid-c2
similarity index 100%
rename from board/amlogic/odroid-c2/README
rename to board/amlogic/odroid-c2/README.odroid-c2
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 5c8c747bf3..01196d6655 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXBB=y
-CONFIG_TARGET_NANOPI_K2=y
+CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" nanopi-k2"
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 06/19] ARM: rework amlogic configuration
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving
the board Kconfig into the mach-meson Kconfig to make it easier to add
new boards for a SoC architecture and add a custom config header or custom
board handler for a platform.

This drops the board CONFIGs and the duplicate boards configs headers in
favor of a single meson64.h config header.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 73 +++++++++----------
 board/amlogic/odroid-c2/Kconfig               | 12 ---
 board/amlogic/p212/Kconfig                    | 12 ---
 board/amlogic/q200/Kconfig                    | 12 ---
 configs/khadas-vim2_defconfig                 |  1 -
 configs/khadas-vim_defconfig                  |  1 -
 configs/libretech-cc_defconfig                |  1 -
 configs/nanopi-k2_defconfig                   |  2 -
 configs/odroid-c2_defconfig                   |  1 -
 configs/p212_defconfig                        |  1 -
 include/configs/khadas-vim.h                  | 14 ----
 include/configs/libretech-cc.h                | 14 ----
 .../configs/{meson-gx-common.h => meson64.h}  | 25 ++++---
 include/configs/nanopi-k2.h                   | 12 ---
 include/configs/odroid-c2.h                   | 12 ---
 include/configs/p212.h                        | 14 ----
 include/configs/q200.h                        | 18 -----
 17 files changed, 50 insertions(+), 175 deletions(-)
 delete mode 100644 board/amlogic/odroid-c2/Kconfig
 delete mode 100644 board/amlogic/p212/Kconfig
 delete mode 100644 board/amlogic/q200/Kconfig
 delete mode 100644 include/configs/khadas-vim.h
 delete mode 100644 include/configs/libretech-cc.h
 rename include/configs/{meson-gx-common.h => meson64.h} (81%)
 delete mode 100644 include/configs/nanopi-k2.h
 delete mode 100644 include/configs/odroid-c2.h
 delete mode 100644 include/configs/p212.h
 delete mode 100644 include/configs/q200.h

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index d86b1bed78..6f60167c8c 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,49 +8,27 @@ config MESON64_COMMON
 	select DM_SERIAL
 	imply CMD_DM
 
+choice
+	prompt "Platform select"
+	default MESON_GXBB
+
 config MESON_GXBB
-	bool
+	bool "GXBB"
 	select MESON64_COMMON
+	help
+	  Select this if your SoC is an S905
 
 config MESON_GXL
-	bool
+	bool "GXL"
 	select MESON64_COMMON
+	help
+	  Select this if your SoC is an S905X/D or S805X
 
 config MESON_GXM
-	bool
+	bool "GXM"
 	select MESON64_COMMON
-
-choice
-	prompt "Platform select"
-	default TARGET_ODROID_C2
-
-config TARGET_ODROID_C2
-	bool "ODROID-C2"
-	select MESON_GXBB
 	help
-	  ODROID-C2 is a single board computer based on Meson GXBaby
-	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
-	  slot, eMMC, IR receiver and a 40-pin GPIO header.
-	  You should also select this TARGET if you have an nanopi-k2
-
-config TARGET_P212
-	bool "P212"
-	select MESON_GXL
-	help
-	  P212 is a reference dessign board based on Meson GXL S905X SoC
-	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
-	  eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
-	  You should also select this TARGET if you have Khadas Vim or
-	  a libretech aml-s905x-cc
-
-config TARGET_Q200
-	bool "KHADAS-VIM2"
-	select MESON_GXM
-	help
-	  Q200 is a reference dessign board based on Meson GXM
-	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver.
-	  You should also select this TARGET if you have Khadas Vim2.
+	  Select this if your SoC is an S912
 
 endchoice
 
@@ -60,10 +38,31 @@ config SYS_SOC
 config SYS_MALLOC_F_LEN
 	default 0x1000
 
-source "board/amlogic/odroid-c2/Kconfig"
+config SYS_VENDOR
+	string "Vendor name"
+	default "amlogic"
+	help
+	  This option contains information about board name.
+	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+	  be used.
 
-source "board/amlogic/p212/Kconfig"
+config SYS_BOARD
+	string "Board name"
+	default "odroid-c2" if MESON_GXBB
+	default "p212" if MESON_GXL
+	default "q200" if MESON_GXM
+	default ""
+	help
+	  This option contains information about board name.
+	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+	  be used.
 
-source "board/amlogic/q200/Kconfig"
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default "meson64"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig
deleted file mode 100644
index 2b16889b07..0000000000
--- a/board/amlogic/odroid-c2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ODROID_C2
-
-config SYS_BOARD
-	default "odroid-c2"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "odroid-c2"
-
-endif
diff --git a/board/amlogic/p212/Kconfig b/board/amlogic/p212/Kconfig
deleted file mode 100644
index 720c92b1ee..0000000000
--- a/board/amlogic/p212/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P212
-
-config SYS_BOARD
-	default "p212"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "p212"
-
-endif
diff --git a/board/amlogic/q200/Kconfig b/board/amlogic/q200/Kconfig
deleted file mode 100644
index cfaf3797ac..0000000000
--- a/board/amlogic/q200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_Q200
-
-config SYS_BOARD
-	default "q200"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "q200"
-
-endif
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 49b8104960..6fe861c0e5 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXM=y
-CONFIG_TARGET_Q200=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim2"
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index af30113760..6e855dd6eb 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim"
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 7526516060..c2f985fcfb 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" libretech-cc"
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 01196d6655..8bbf48f41f 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -1,8 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_GXBB=y
-CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" nanopi-k2"
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 19196b3585..68554ba745 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXBB=y
-CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" odroid-c2"
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index 9e3b1d6bfb..a15064da81 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" p212"
diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
deleted file mode 100644
index ff87c02820..0000000000
--- a/include/configs/khadas-vim.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Khadas VIM
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
deleted file mode 100644
index 95e0f346fd..0000000000
--- a/include/configs/libretech-cc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for LibreTech CC
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/meson-gx-common.h b/include/configs/meson64.h
similarity index 81%
rename from include/configs/meson-gx-common.h
rename to include/configs/meson64.h
index c43697665d..1929a3e406 100644
--- a/include/configs/meson-gx-common.h
+++ b/include/configs/meson64.h
@@ -1,11 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Configuration for Amlogic Meson GX SoCs
+ * Configuration for Amlogic Meson 64bits SoCs
  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  */
 
-#ifndef __MESON_GX_COMMON_CONFIG_H
-#define __MESON_GX_COMMON_CONFIG_H
+#ifndef __MESON64_CONFIG_H
+#define __MESON64_CONFIG_H
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
@@ -17,10 +21,7 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_SYS_INIT_SP_ADDR		0x20000000
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE			0xc4301000
-#define GICC_BASE			0xc4302000
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64 MiB */
 
 #ifdef CONFIG_CMD_USB
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
@@ -28,6 +29,7 @@
 #define BOOT_TARGET_DEVICES_USB(func)
 #endif
 
+#ifndef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
@@ -35,9 +37,9 @@
 	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
+#endif
 
-#include <config_distro_bootcmd.h>
-
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"fdt_addr_r=0x01000000\0" \
 	"scriptaddr=0x1f000000\0" \
@@ -46,7 +48,8 @@
 	"ramdisk_addr_r=0x13000000\0" \
 	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	BOOTENV
+#endif
 
-#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
+#include <config_distro_bootcmd.h>
 
-#endif /* __MESON_GX_COMMON_CONFIG_H */
+#endif /* __MESON64_CONFIG_H */
diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h
deleted file mode 100644
index 3fd6e8fba4..0000000000
--- a/include/configs/nanopi-k2.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for NANOPI-K2
- * (C) Copyright 2018 Thomas McKahan
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
deleted file mode 100644
index 87e3ddb342..0000000000
--- a/include/configs/odroid-c2.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for ODROID-C2
- * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/p212.h b/include/configs/p212.h
deleted file mode 100644
index 4414293479..0000000000
--- a/include/configs/p212.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Amlogic P212
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/q200.h b/include/configs/q200.h
deleted file mode 100644
index 7ef8f42bd2..0000000000
--- a/include/configs/q200.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Khadas VIM2
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MISC_INIT_R
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxm-khadas-vim2.dtb\0"
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 06/19] ARM: rework amlogic configuration
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

Rework the board SYS_BOARD, SYS_VENDOR and SYS_CONFIG_NAME setup by moving
the board Kconfig into the mach-meson Kconfig to make it easier to add
new boards for a SoC architecture and add a custom config header or custom
board handler for a platform.

This drops the board CONFIGs and the duplicate boards configs headers in
favor of a single meson64.h config header.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig                   | 73 +++++++++----------
 board/amlogic/odroid-c2/Kconfig               | 12 ---
 board/amlogic/p212/Kconfig                    | 12 ---
 board/amlogic/q200/Kconfig                    | 12 ---
 configs/khadas-vim2_defconfig                 |  1 -
 configs/khadas-vim_defconfig                  |  1 -
 configs/libretech-cc_defconfig                |  1 -
 configs/nanopi-k2_defconfig                   |  2 -
 configs/odroid-c2_defconfig                   |  1 -
 configs/p212_defconfig                        |  1 -
 include/configs/khadas-vim.h                  | 14 ----
 include/configs/libretech-cc.h                | 14 ----
 .../configs/{meson-gx-common.h => meson64.h}  | 25 ++++---
 include/configs/nanopi-k2.h                   | 12 ---
 include/configs/odroid-c2.h                   | 12 ---
 include/configs/p212.h                        | 14 ----
 include/configs/q200.h                        | 18 -----
 17 files changed, 50 insertions(+), 175 deletions(-)
 delete mode 100644 board/amlogic/odroid-c2/Kconfig
 delete mode 100644 board/amlogic/p212/Kconfig
 delete mode 100644 board/amlogic/q200/Kconfig
 delete mode 100644 include/configs/khadas-vim.h
 delete mode 100644 include/configs/libretech-cc.h
 rename include/configs/{meson-gx-common.h => meson64.h} (81%)
 delete mode 100644 include/configs/nanopi-k2.h
 delete mode 100644 include/configs/odroid-c2.h
 delete mode 100644 include/configs/p212.h
 delete mode 100644 include/configs/q200.h

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index d86b1bed78..6f60167c8c 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,49 +8,27 @@ config MESON64_COMMON
 	select DM_SERIAL
 	imply CMD_DM
 
+choice
+	prompt "Platform select"
+	default MESON_GXBB
+
 config MESON_GXBB
-	bool
+	bool "GXBB"
 	select MESON64_COMMON
+	help
+	  Select this if your SoC is an S905
 
 config MESON_GXL
-	bool
+	bool "GXL"
 	select MESON64_COMMON
+	help
+	  Select this if your SoC is an S905X/D or S805X
 
 config MESON_GXM
-	bool
+	bool "GXM"
 	select MESON64_COMMON
-
-choice
-	prompt "Platform select"
-	default TARGET_ODROID_C2
-
-config TARGET_ODROID_C2
-	bool "ODROID-C2"
-	select MESON_GXBB
 	help
-	  ODROID-C2 is a single board computer based on Meson GXBaby
-	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
-	  slot, eMMC, IR receiver and a 40-pin GPIO header.
-	  You should also select this TARGET if you have an nanopi-k2
-
-config TARGET_P212
-	bool "P212"
-	select MESON_GXL
-	help
-	  P212 is a reference dessign board based on Meson GXL S905X SoC
-	  with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
-	  eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
-	  You should also select this TARGET if you have Khadas Vim or
-	  a libretech aml-s905x-cc
-
-config TARGET_Q200
-	bool "KHADAS-VIM2"
-	select MESON_GXM
-	help
-	  Q200 is a reference dessign board based on Meson GXM
-	  with 2/3 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
-	  eMMC, IR receiver.
-	  You should also select this TARGET if you have Khadas Vim2.
+	  Select this if your SoC is an S912
 
 endchoice
 
@@ -60,10 +38,31 @@ config SYS_SOC
 config SYS_MALLOC_F_LEN
 	default 0x1000
 
-source "board/amlogic/odroid-c2/Kconfig"
+config SYS_VENDOR
+	string "Vendor name"
+	default "amlogic"
+	help
+	  This option contains information about board name.
+	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+	  be used.
 
-source "board/amlogic/p212/Kconfig"
+config SYS_BOARD
+	string "Board name"
+	default "odroid-c2" if MESON_GXBB
+	default "p212" if MESON_GXL
+	default "q200" if MESON_GXM
+	default ""
+	help
+	  This option contains information about board name.
+	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will
+	  be used.
 
-source "board/amlogic/q200/Kconfig"
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default "meson64"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/board/amlogic/odroid-c2/Kconfig b/board/amlogic/odroid-c2/Kconfig
deleted file mode 100644
index 2b16889b07..0000000000
--- a/board/amlogic/odroid-c2/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ODROID_C2
-
-config SYS_BOARD
-	default "odroid-c2"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "odroid-c2"
-
-endif
diff --git a/board/amlogic/p212/Kconfig b/board/amlogic/p212/Kconfig
deleted file mode 100644
index 720c92b1ee..0000000000
--- a/board/amlogic/p212/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P212
-
-config SYS_BOARD
-	default "p212"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "p212"
-
-endif
diff --git a/board/amlogic/q200/Kconfig b/board/amlogic/q200/Kconfig
deleted file mode 100644
index cfaf3797ac..0000000000
--- a/board/amlogic/q200/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_Q200
-
-config SYS_BOARD
-	default "q200"
-
-config SYS_VENDOR
-	default "amlogic"
-
-config SYS_CONFIG_NAME
-	default "q200"
-
-endif
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 49b8104960..6fe861c0e5 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXM=y
-CONFIG_TARGET_Q200=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim2"
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index af30113760..6e855dd6eb 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" khadas-vim"
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index 7526516060..c2f985fcfb 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" libretech-cc"
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 01196d6655..8bbf48f41f 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -1,8 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_GXBB=y
-CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" nanopi-k2"
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 19196b3585..68554ba745 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXBB=y
-CONFIG_TARGET_ODROID_C2=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" odroid-c2"
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index 9e3b1d6bfb..a15064da81 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_MESON=y
 CONFIG_SYS_TEXT_BASE=0x01000000
 CONFIG_MESON_GXL=y
-CONFIG_TARGET_P212=y
 CONFIG_DEBUG_UART_BASE=0xc81004c0
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_IDENT_STRING=" p212"
diff --git a/include/configs/khadas-vim.h b/include/configs/khadas-vim.h
deleted file mode 100644
index ff87c02820..0000000000
--- a/include/configs/khadas-vim.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Khadas VIM
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/libretech-cc.h b/include/configs/libretech-cc.h
deleted file mode 100644
index 95e0f346fd..0000000000
--- a/include/configs/libretech-cc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for LibreTech CC
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/meson-gx-common.h b/include/configs/meson64.h
similarity index 81%
rename from include/configs/meson-gx-common.h
rename to include/configs/meson64.h
index c43697665d..1929a3e406 100644
--- a/include/configs/meson-gx-common.h
+++ b/include/configs/meson64.h
@@ -1,11 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Configuration for Amlogic Meson GX SoCs
+ * Configuration for Amlogic Meson 64bits SoCs
  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  */
 
-#ifndef __MESON_GX_COMMON_CONFIG_H
-#define __MESON_GX_COMMON_CONFIG_H
+#ifndef __MESON64_CONFIG_H
+#define __MESON64_CONFIG_H
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
@@ -17,10 +21,7 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define CONFIG_SYS_INIT_SP_ADDR		0x20000000
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE			0xc4301000
-#define GICC_BASE			0xc4302000
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64 MiB */
 
 #ifdef CONFIG_CMD_USB
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
@@ -28,6 +29,7 @@
 #define BOOT_TARGET_DEVICES_USB(func)
 #endif
 
+#ifndef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
@@ -35,9 +37,9 @@
 	BOOT_TARGET_DEVICES_USB(func) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
+#endif
 
-#include <config_distro_bootcmd.h>
-
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"fdt_addr_r=0x01000000\0" \
 	"scriptaddr=0x1f000000\0" \
@@ -46,7 +48,8 @@
 	"ramdisk_addr_r=0x13000000\0" \
 	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
 	BOOTENV
+#endif
 
-#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64 MiB */
+#include <config_distro_bootcmd.h>
 
-#endif /* __MESON_GX_COMMON_CONFIG_H */
+#endif /* __MESON64_CONFIG_H */
diff --git a/include/configs/nanopi-k2.h b/include/configs/nanopi-k2.h
deleted file mode 100644
index 3fd6e8fba4..0000000000
--- a/include/configs/nanopi-k2.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for NANOPI-K2
- * (C) Copyright 2018 Thomas McKahan
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
deleted file mode 100644
index 87e3ddb342..0000000000
--- a/include/configs/odroid-c2.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for ODROID-C2
- * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/p212.h b/include/configs/p212.h
deleted file mode 100644
index 4414293479..0000000000
--- a/include/configs/p212.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Amlogic P212
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/q200.h b/include/configs/q200.h
deleted file mode 100644
index 7ef8f42bd2..0000000000
--- a/include/configs/q200.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration for Khadas VIM2
- *
- * Copyright (C) 2017 Baylibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MISC_INIT_R
-
-#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxm-khadas-vim2.dtb\0"
-
-#include <configs/meson-gx-common.h>
-
-#endif /* __CONFIG_H */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 07/19] configs: meson: change default load addresses
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

The original chosen addresses conflict with the BL2 initialisation.
So far there was no issue with them but if we preload binaries in
RAM (ROMUSB boot) before running the BL2 they get corrupted by the
execution of BL2 init.

If we load them around 0x08000000, there is no such issue.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 include/configs/meson64.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 1929a3e406..80c883e3f4 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -41,9 +41,9 @@
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"fdt_addr_r=0x01000000\0" \
-	"scriptaddr=0x1f000000\0" \
-	"kernel_addr_r=0x01080000\0" \
+	"fdt_addr_r=0x08008000\0" \
+	"scriptaddr=0x08000000\0" \
+	"kernel_addr_r=0x08080000\0" \
 	"pxefile_addr_r=0x01080000\0" \
 	"ramdisk_addr_r=0x13000000\0" \
 	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 07/19] configs: meson: change default load addresses
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

The original chosen addresses conflict with the BL2 initialisation.
So far there was no issue with them but if we preload binaries in
RAM (ROMUSB boot) before running the BL2 they get corrupted by the
execution of BL2 init.

If we load them around 0x08000000, there is no such issue.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 include/configs/meson64.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 1929a3e406..80c883e3f4 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -41,9 +41,9 @@
 
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"fdt_addr_r=0x01000000\0" \
-	"scriptaddr=0x1f000000\0" \
-	"kernel_addr_r=0x01080000\0" \
+	"fdt_addr_r=0x08008000\0" \
+	"scriptaddr=0x08000000\0" \
+	"kernel_addr_r=0x08080000\0" \
 	"pxefile_addr_r=0x01080000\0" \
 	"ramdisk_addr_r=0x13000000\0" \
 	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 08/19] pinctrl: meson: rework gx pmx function
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig                |   8 +-
 drivers/pinctrl/meson/Makefile               |   1 +
 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c |  97 +++++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-gx.h     |  48 ++++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c   |   6 +-
 drivers/pinctrl/meson/pinctrl-meson-gxl.c    |   6 +-
 drivers/pinctrl/meson/pinctrl-meson.c        | 109 +++----------------
 drivers/pinctrl/meson/pinctrl-meson.h        |  37 +++----
 8 files changed, 191 insertions(+), 121 deletions(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 27ba8909d7..15a8d9c704 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -4,12 +4,16 @@ config PINCTRL_MESON
 	depends on PINCTRL_GENERIC
 	bool
 
+config PINCTRL_MESON_GX_PMX
+	select PINCTRL_MESON
+	bool
+
 config PINCTRL_MESON_GXBB
 	bool "Amlogic Meson GXBB SoC pinctrl driver"
-	select PINCTRL_MESON
+	select PINCTRL_MESON_GX_PMX
 
 config PINCTRL_MESON_GXL
 	bool "Amlogic Meson GXL SoC pinctrl driver"
-	select PINCTRL_MESON
+	select PINCTRL_MESON_GX_PMX
 
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 965092cd81..30b6875b88 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y					+= pinctrl-meson.o
+obj-$(CONFIG_PINCTRL_MESON_GX_PMX)	+= pinctrl-meson-gx-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_GXBB)	+= pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL)		+= pinctrl-meson-gxl.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
new file mode 100644
index 0000000000..fc1538ea71
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <asm/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include "pinctrl-meson-gx.h"
+
+static void meson_gx_pinmux_disable_other_groups(struct meson_pinctrl *priv,
+						 unsigned int pin,
+						 int sel_group)
+{
+	struct meson_pmx_group *group;
+	struct meson_gx_pmx_data *pmx_data;
+	void __iomem *addr;
+	int i, j;
+
+	for (i = 0; i < priv->data->num_groups; i++) {
+		group = &priv->data->groups[i];
+		pmx_data = (struct meson_gx_pmx_data *)group->data;
+		if (pmx_data->is_gpio || i == sel_group)
+			continue;
+
+		for (j = 0; j < group->num_pins; j++) {
+			if (group->pins[j] == pin) {
+				/* We have found a group using the pin */
+				debug("pinmux: disabling %s\n", group->name);
+				addr = priv->reg_mux + pmx_data->reg * 4;
+				writel(readl(addr) & ~BIT(pmx_data->bit), addr);
+			}
+		}
+	}
+}
+
+static int meson_gx_pinmux_group_set(struct udevice *dev,
+				     unsigned int group_selector,
+				     unsigned int func_selector)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	const struct meson_pmx_group *group;
+	const struct meson_pmx_func *func;
+	struct meson_gx_pmx_data *pmx_data;
+	void __iomem *addr;
+	int i;
+
+	group = &priv->data->groups[group_selector];
+	pmx_data = (struct meson_gx_pmx_data *)group->data;
+	func = &priv->data->funcs[func_selector];
+
+	debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+	/*
+	 * Disable groups using the same pins.
+	 * The selected group is not disabled to avoid glitches.
+	 */
+	for (i = 0; i < group->num_pins; i++) {
+		meson_gx_pinmux_disable_other_groups(priv,
+						     group->pins[i],
+						     group_selector);
+	}
+
+	/* Function 0 (GPIO) doesn't need any additional setting */
+	if (func_selector) {
+		addr = priv->reg_mux + pmx_data->reg * 4;
+		writel(readl(addr) | BIT(pmx_data->bit), addr);
+	}
+
+	return 0;
+}
+
+const struct pinctrl_ops meson_gx_pinctrl_ops = {
+	.get_groups_count = meson_pinctrl_get_groups_count,
+	.get_group_name = meson_pinctrl_get_group_name,
+	.get_functions_count = meson_pinmux_get_functions_count,
+	.get_function_name = meson_pinmux_get_function_name,
+	.pinmux_group_set = meson_gx_pinmux_group_set,
+	.set_state = pinctrl_generic_set_state,
+};
+
+static const struct dm_gpio_ops meson_gx_gpio_ops = {
+	.set_value = meson_gpio_set,
+	.get_value = meson_gpio_get,
+	.get_function = meson_gpio_get_direction,
+	.direction_input = meson_gpio_direction_input,
+	.direction_output = meson_gpio_direction_output,
+};
+
+const struct driver meson_gx_gpio_driver = {
+	.name	= "meson-gx-gpio",
+	.id	= UCLASS_GPIO,
+	.probe	= meson_gpio_probe,
+	.ops	= &meson_gx_gpio_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx.h b/drivers/pinctrl/meson/pinctrl-meson-gx.h
new file mode 100644
index 0000000000..4c1aa1a300
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gx.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright (C) 2017 Jerome Brunet  <jbrunet@baylibre.com>
+ */
+
+#ifndef __PINCTRL_MESON_GX_H__
+#define __PINCTRL_MESON_GX_H__
+
+#include "pinctrl-meson.h"
+
+struct meson_gx_pmx_data {
+	bool is_gpio;
+	unsigned int reg;
+	unsigned int bit;
+};
+
+#define PMX_DATA(r, b, g)						\
+	{								\
+		.reg = r,						\
+		.bit = b,						\
+		.is_gpio = g,						\
+	}
+
+#define GROUP(grp, r, b)						\
+	{								\
+		.name = #grp,						\
+		.pins = grp ## _pins,					\
+		.num_pins = ARRAY_SIZE(grp ## _pins),			\
+			.data = (const struct meson_gx_pmx_data[]){	\
+			PMX_DATA(r, b, false),				\
+		},							\
+	}
+
+#define GPIO_GROUP(gpio, b)						\
+	{								\
+		.name = #gpio,						\
+		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
+		.num_pins = 1,						\
+		.data = (const struct meson_gx_pmx_data[]){		\
+			PMX_DATA(0, 0, true),				\
+		},							\
+	}
+
+extern const struct pinctrl_ops meson_gx_pinctrl_ops;
+extern const struct driver meson_gx_gpio_driver;
+
+#endif /* __PINCTRL_MESON_GX_H__ */
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index a8e47e3c4e..22e8b055d7 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -11,7 +11,7 @@
 #include <dm/pinctrl.h>
 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
 
-#include "pinctrl-meson.h"
+#include "pinctrl-meson-gx.h"
 
 #define EE_OFF	15
 
@@ -417,6 +417,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxbb_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_periphs_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
@@ -429,6 +430,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxbb_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_aobus_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 static const struct udevice_id meson_gxbb_pinctrl_match[] = {
@@ -449,5 +451,5 @@ U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
 	.of_match = of_match_ptr(meson_gxbb_pinctrl_match),
 	.probe = meson_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
-	.ops = &meson_pinctrl_ops,
+	.ops = &meson_gx_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index ba6e3531d9..1819eee4d0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -11,7 +11,7 @@
 #include <dm/pinctrl.h>
 #include <dt-bindings/gpio/meson-gxl-gpio.h>
 
-#include "pinctrl-meson.h"
+#include "pinctrl-meson-gx.h"
 
 #define EE_OFF	11
 
@@ -699,6 +699,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxl_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_periphs_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
@@ -711,6 +712,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxl_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_aobus_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 static const struct udevice_id meson_gxl_pinctrl_match[] = {
@@ -731,5 +733,5 @@ U_BOOT_DRIVER(meson_gxl_pinctrl) = {
 	.of_match = of_match_ptr(meson_gxl_pinctrl_match),
 	.probe = meson_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
-	.ops = &meson_pinctrl_ops,
+	.ops = &meson_gx_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 387c241d12..0bd6152803 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static const char *meson_pinctrl_dummy_name = "_dummy";
 
-static int meson_pinctrl_get_groups_count(struct udevice *dev)
+int meson_pinctrl_get_groups_count(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->num_groups;
 }
 
-static const char *meson_pinctrl_get_group_name(struct udevice *dev,
-						unsigned selector)
+const char *meson_pinctrl_get_group_name(struct udevice *dev,
+					 unsigned int selector)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
@@ -38,87 +38,21 @@ static const char *meson_pinctrl_get_group_name(struct udevice *dev,
 	return priv->data->groups[selector].name;
 }
 
-static int meson_pinmux_get_functions_count(struct udevice *dev)
+int meson_pinmux_get_functions_count(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->num_funcs;
 }
 
-static const char *meson_pinmux_get_function_name(struct udevice *dev,
-						  unsigned selector)
+const char *meson_pinmux_get_function_name(struct udevice *dev,
+					   unsigned int selector)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->funcs[selector].name;
 }
 
-static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
-					      unsigned int pin, int sel_group)
-{
-	struct meson_pmx_group *group;
-	void __iomem *addr;
-	int i, j;
-
-	for (i = 0; i < priv->data->num_groups; i++) {
-		group = &priv->data->groups[i];
-		if (group->is_gpio || i == sel_group)
-			continue;
-
-		for (j = 0; j < group->num_pins; j++) {
-			if (group->pins[j] == pin) {
-				/* We have found a group using the pin */
-				debug("pinmux: disabling %s\n", group->name);
-				addr = priv->reg_mux + group->reg * 4;
-				writel(readl(addr) & ~BIT(group->bit), addr);
-			}
-		}
-	}
-}
-
-static int meson_pinmux_group_set(struct udevice *dev,
-				  unsigned group_selector,
-				  unsigned func_selector)
-{
-	struct meson_pinctrl *priv = dev_get_priv(dev);
-	const struct meson_pmx_group *group;
-	const struct meson_pmx_func *func;
-	void __iomem *addr;
-	int i;
-
-	group = &priv->data->groups[group_selector];
-	func = &priv->data->funcs[func_selector];
-
-	debug("pinmux: set group %s func %s\n", group->name, func->name);
-
-	/*
-	 * Disable groups using the same pins.
-	 * The selected group is not disabled to avoid glitches.
-	 */
-	for (i = 0; i < group->num_pins; i++) {
-		meson_pinmux_disable_other_groups(priv,
-						  group->pins[i],
-						  group_selector);
-	}
-
-	/* Function 0 (GPIO) doesn't need any additional setting */
-	if (func_selector) {
-		addr = priv->reg_mux + group->reg * 4;
-		writel(readl(addr) | BIT(group->bit), addr);
-	}
-
-	return 0;
-}
-
-const struct pinctrl_ops meson_pinctrl_ops = {
-	.get_groups_count = meson_pinctrl_get_groups_count,
-	.get_group_name = meson_pinctrl_get_group_name,
-	.get_functions_count = meson_pinmux_get_functions_count,
-	.get_function_name = meson_pinmux_get_function_name,
-	.pinmux_group_set = meson_pinmux_group_set,
-	.set_state = pinctrl_generic_set_state,
-};
-
 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
 				       enum meson_reg_type reg_type,
 				       unsigned int *reg, unsigned int *bit)
@@ -149,7 +83,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
 	return 0;
 }
 
-static int meson_gpio_get(struct udevice *dev, unsigned int offset)
+int meson_gpio_get(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -162,7 +96,7 @@ static int meson_gpio_get(struct udevice *dev, unsigned int offset)
 	return !!(readl(priv->reg_gpio + reg) & BIT(bit));
 }
 
-static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
+int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -177,7 +111,7 @@ static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
 	return 0;
 }
 
-static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
+int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit, val;
@@ -192,7 +126,7 @@ static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
 	return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
 }
 
-static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
+int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -207,8 +141,8 @@ static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
 	return 0;
 }
 
-static int meson_gpio_direction_output(struct udevice *dev,
-				       unsigned int offset, int value)
+int meson_gpio_direction_output(struct udevice *dev,
+				unsigned int offset, int value)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -229,7 +163,7 @@ static int meson_gpio_direction_output(struct udevice *dev,
 	return 0;
 }
 
-static int meson_gpio_probe(struct udevice *dev)
+int meson_gpio_probe(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	struct gpio_dev_priv *uc_priv;
@@ -241,21 +175,6 @@ static int meson_gpio_probe(struct udevice *dev)
 	return 0;
 }
 
-static const struct dm_gpio_ops meson_gpio_ops = {
-	.set_value = meson_gpio_set,
-	.get_value = meson_gpio_get,
-	.get_function = meson_gpio_get_direction,
-	.direction_input = meson_gpio_direction_input,
-	.direction_output = meson_gpio_direction_output,
-};
-
-static struct driver meson_gpio_driver = {
-	.name	= "meson-gpio",
-	.id	= UCLASS_GPIO,
-	.probe	= meson_gpio_probe,
-	.ops	= &meson_gpio_ops,
-};
-
 static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
 {
 	int index, len = 0;
@@ -334,7 +253,7 @@ int meson_pinctrl_probe(struct udevice *dev)
 	sprintf(name, "meson-gpio");
 
 	/* Create child device UCLASS_GPIO and bind it */
-	device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
+	device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
 	dev_set_of_offset(gpio_dev, gpio);
 
 	return 0;
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 6ec89ba117..bdee721fc0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -12,9 +12,7 @@ struct meson_pmx_group {
 	const char *name;
 	const unsigned int *pins;
 	unsigned int num_pins;
-	bool is_gpio;
-	unsigned int reg;
-	unsigned int bit;
+	const void *data;
 };
 
 struct meson_pmx_func {
@@ -33,6 +31,8 @@ struct meson_pinctrl_data {
 	unsigned int num_groups;
 	unsigned int num_funcs;
 	unsigned int num_banks;
+	const struct driver *gpio_driver;
+	void *pmx_data;
 };
 
 struct meson_pinctrl {
@@ -89,23 +89,6 @@ struct meson_bank {
 
 #define PIN(x, b)	(b + x)
 
-#define GROUP(grp, r, b)						\
-	{								\
-		.name = #grp,						\
-		.pins = grp ## _pins,					\
-		.num_pins = ARRAY_SIZE(grp ## _pins),			\
-		.reg = r,						\
-		.bit = b,						\
-	 }
-
-#define GPIO_GROUP(gpio, b)						\
-	{								\
-		.name = #gpio,						\
-		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
-		.num_pins = 1,						\
-		.is_gpio = true,					\
-	 }
-
 #define FUNCTION(fn)							\
 	{								\
 		.name = #fn,						\
@@ -131,6 +114,20 @@ struct meson_bank {
 
 extern const struct pinctrl_ops meson_pinctrl_ops;
 
+int meson_pinctrl_get_groups_count(struct udevice *dev);
+const char *meson_pinctrl_get_group_name(struct udevice *dev,
+					 unsigned int selector);
+int meson_pinmux_get_functions_count(struct udevice *dev);
+const char *meson_pinmux_get_function_name(struct udevice *dev,
+					   unsigned int selector);
 int meson_pinctrl_probe(struct udevice *dev);
 
+int meson_gpio_get(struct udevice *dev, unsigned int offset);
+int meson_gpio_set(struct udevice *dev, unsigned int offset, int value);
+int meson_gpio_get_direction(struct udevice *dev, unsigned int offset);
+int meson_gpio_direction_input(struct udevice *dev, unsigned int offset);
+int meson_gpio_direction_output(struct udevice *dev, unsigned int offset,
+				int value);
+int meson_gpio_probe(struct udevice *dev);
+
 #endif /* __PINCTRL_MESON_H__ */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 08/19] pinctrl: meson: rework gx pmx function
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

In preparation of supporting the new Amlogix AGX SoCs, we need to move
the Amlogic GX pinmux functions out of the common code to be able to
add a different set of SoC specific pinmux functions for AXG.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig                |   8 +-
 drivers/pinctrl/meson/Makefile               |   1 +
 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c |  97 +++++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-gx.h     |  48 ++++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c   |   6 +-
 drivers/pinctrl/meson/pinctrl-meson-gxl.c    |   6 +-
 drivers/pinctrl/meson/pinctrl-meson.c        | 109 +++----------------
 drivers/pinctrl/meson/pinctrl-meson.h        |  37 +++----
 8 files changed, 191 insertions(+), 121 deletions(-)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 27ba8909d7..15a8d9c704 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -4,12 +4,16 @@ config PINCTRL_MESON
 	depends on PINCTRL_GENERIC
 	bool
 
+config PINCTRL_MESON_GX_PMX
+	select PINCTRL_MESON
+	bool
+
 config PINCTRL_MESON_GXBB
 	bool "Amlogic Meson GXBB SoC pinctrl driver"
-	select PINCTRL_MESON
+	select PINCTRL_MESON_GX_PMX
 
 config PINCTRL_MESON_GXL
 	bool "Amlogic Meson GXL SoC pinctrl driver"
-	select PINCTRL_MESON
+	select PINCTRL_MESON_GX_PMX
 
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 965092cd81..30b6875b88 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y					+= pinctrl-meson.o
+obj-$(CONFIG_PINCTRL_MESON_GX_PMX)	+= pinctrl-meson-gx-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_GXBB)	+= pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL)		+= pinctrl-meson-gxl.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
new file mode 100644
index 0000000000..fc1538ea71
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <asm/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include "pinctrl-meson-gx.h"
+
+static void meson_gx_pinmux_disable_other_groups(struct meson_pinctrl *priv,
+						 unsigned int pin,
+						 int sel_group)
+{
+	struct meson_pmx_group *group;
+	struct meson_gx_pmx_data *pmx_data;
+	void __iomem *addr;
+	int i, j;
+
+	for (i = 0; i < priv->data->num_groups; i++) {
+		group = &priv->data->groups[i];
+		pmx_data = (struct meson_gx_pmx_data *)group->data;
+		if (pmx_data->is_gpio || i == sel_group)
+			continue;
+
+		for (j = 0; j < group->num_pins; j++) {
+			if (group->pins[j] == pin) {
+				/* We have found a group using the pin */
+				debug("pinmux: disabling %s\n", group->name);
+				addr = priv->reg_mux + pmx_data->reg * 4;
+				writel(readl(addr) & ~BIT(pmx_data->bit), addr);
+			}
+		}
+	}
+}
+
+static int meson_gx_pinmux_group_set(struct udevice *dev,
+				     unsigned int group_selector,
+				     unsigned int func_selector)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	const struct meson_pmx_group *group;
+	const struct meson_pmx_func *func;
+	struct meson_gx_pmx_data *pmx_data;
+	void __iomem *addr;
+	int i;
+
+	group = &priv->data->groups[group_selector];
+	pmx_data = (struct meson_gx_pmx_data *)group->data;
+	func = &priv->data->funcs[func_selector];
+
+	debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+	/*
+	 * Disable groups using the same pins.
+	 * The selected group is not disabled to avoid glitches.
+	 */
+	for (i = 0; i < group->num_pins; i++) {
+		meson_gx_pinmux_disable_other_groups(priv,
+						     group->pins[i],
+						     group_selector);
+	}
+
+	/* Function 0 (GPIO) doesn't need any additional setting */
+	if (func_selector) {
+		addr = priv->reg_mux + pmx_data->reg * 4;
+		writel(readl(addr) | BIT(pmx_data->bit), addr);
+	}
+
+	return 0;
+}
+
+const struct pinctrl_ops meson_gx_pinctrl_ops = {
+	.get_groups_count = meson_pinctrl_get_groups_count,
+	.get_group_name = meson_pinctrl_get_group_name,
+	.get_functions_count = meson_pinmux_get_functions_count,
+	.get_function_name = meson_pinmux_get_function_name,
+	.pinmux_group_set = meson_gx_pinmux_group_set,
+	.set_state = pinctrl_generic_set_state,
+};
+
+static const struct dm_gpio_ops meson_gx_gpio_ops = {
+	.set_value = meson_gpio_set,
+	.get_value = meson_gpio_get,
+	.get_function = meson_gpio_get_direction,
+	.direction_input = meson_gpio_direction_input,
+	.direction_output = meson_gpio_direction_output,
+};
+
+const struct driver meson_gx_gpio_driver = {
+	.name	= "meson-gx-gpio",
+	.id	= UCLASS_GPIO,
+	.probe	= meson_gpio_probe,
+	.ops	= &meson_gx_gpio_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx.h b/drivers/pinctrl/meson/pinctrl-meson-gx.h
new file mode 100644
index 0000000000..4c1aa1a300
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-gx.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright (C) 2017 Jerome Brunet  <jbrunet@baylibre.com>
+ */
+
+#ifndef __PINCTRL_MESON_GX_H__
+#define __PINCTRL_MESON_GX_H__
+
+#include "pinctrl-meson.h"
+
+struct meson_gx_pmx_data {
+	bool is_gpio;
+	unsigned int reg;
+	unsigned int bit;
+};
+
+#define PMX_DATA(r, b, g)						\
+	{								\
+		.reg = r,						\
+		.bit = b,						\
+		.is_gpio = g,						\
+	}
+
+#define GROUP(grp, r, b)						\
+	{								\
+		.name = #grp,						\
+		.pins = grp ## _pins,					\
+		.num_pins = ARRAY_SIZE(grp ## _pins),			\
+			.data = (const struct meson_gx_pmx_data[]){	\
+			PMX_DATA(r, b, false),				\
+		},							\
+	}
+
+#define GPIO_GROUP(gpio, b)						\
+	{								\
+		.name = #gpio,						\
+		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
+		.num_pins = 1,						\
+		.data = (const struct meson_gx_pmx_data[]){		\
+			PMX_DATA(0, 0, true),				\
+		},							\
+	}
+
+extern const struct pinctrl_ops meson_gx_pinctrl_ops;
+extern const struct driver meson_gx_gpio_driver;
+
+#endif /* __PINCTRL_MESON_GX_H__ */
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index a8e47e3c4e..22e8b055d7 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -11,7 +11,7 @@
 #include <dm/pinctrl.h>
 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
 
-#include "pinctrl-meson.h"
+#include "pinctrl-meson-gx.h"
 
 #define EE_OFF	15
 
@@ -417,6 +417,7 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxbb_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_periphs_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
@@ -429,6 +430,7 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxbb_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxbb_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxbb_aobus_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 static const struct udevice_id meson_gxbb_pinctrl_match[] = {
@@ -449,5 +451,5 @@ U_BOOT_DRIVER(meson_gxbb_pinctrl) = {
 	.of_match = of_match_ptr(meson_gxbb_pinctrl_match),
 	.probe = meson_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
-	.ops = &meson_pinctrl_ops,
+	.ops = &meson_gx_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index ba6e3531d9..1819eee4d0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -11,7 +11,7 @@
 #include <dm/pinctrl.h>
 #include <dt-bindings/gpio/meson-gxl-gpio.h>
 
-#include "pinctrl-meson.h"
+#include "pinctrl-meson-gx.h"
 
 #define EE_OFF	11
 
@@ -699,6 +699,7 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxl_periphs_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_periphs_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_periphs_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
@@ -711,6 +712,7 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
 	.num_groups	= ARRAY_SIZE(meson_gxl_aobus_groups),
 	.num_funcs	= ARRAY_SIZE(meson_gxl_aobus_functions),
 	.num_banks	= ARRAY_SIZE(meson_gxl_aobus_banks),
+	.gpio_driver	= &meson_gx_gpio_driver,
 };
 
 static const struct udevice_id meson_gxl_pinctrl_match[] = {
@@ -731,5 +733,5 @@ U_BOOT_DRIVER(meson_gxl_pinctrl) = {
 	.of_match = of_match_ptr(meson_gxl_pinctrl_match),
 	.probe = meson_pinctrl_probe,
 	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
-	.ops = &meson_pinctrl_ops,
+	.ops = &meson_gx_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 387c241d12..0bd6152803 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -20,15 +20,15 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static const char *meson_pinctrl_dummy_name = "_dummy";
 
-static int meson_pinctrl_get_groups_count(struct udevice *dev)
+int meson_pinctrl_get_groups_count(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->num_groups;
 }
 
-static const char *meson_pinctrl_get_group_name(struct udevice *dev,
-						unsigned selector)
+const char *meson_pinctrl_get_group_name(struct udevice *dev,
+					 unsigned int selector)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
@@ -38,87 +38,21 @@ static const char *meson_pinctrl_get_group_name(struct udevice *dev,
 	return priv->data->groups[selector].name;
 }
 
-static int meson_pinmux_get_functions_count(struct udevice *dev)
+int meson_pinmux_get_functions_count(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->num_funcs;
 }
 
-static const char *meson_pinmux_get_function_name(struct udevice *dev,
-						  unsigned selector)
+const char *meson_pinmux_get_function_name(struct udevice *dev,
+					   unsigned int selector)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev);
 
 	return priv->data->funcs[selector].name;
 }
 
-static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
-					      unsigned int pin, int sel_group)
-{
-	struct meson_pmx_group *group;
-	void __iomem *addr;
-	int i, j;
-
-	for (i = 0; i < priv->data->num_groups; i++) {
-		group = &priv->data->groups[i];
-		if (group->is_gpio || i == sel_group)
-			continue;
-
-		for (j = 0; j < group->num_pins; j++) {
-			if (group->pins[j] == pin) {
-				/* We have found a group using the pin */
-				debug("pinmux: disabling %s\n", group->name);
-				addr = priv->reg_mux + group->reg * 4;
-				writel(readl(addr) & ~BIT(group->bit), addr);
-			}
-		}
-	}
-}
-
-static int meson_pinmux_group_set(struct udevice *dev,
-				  unsigned group_selector,
-				  unsigned func_selector)
-{
-	struct meson_pinctrl *priv = dev_get_priv(dev);
-	const struct meson_pmx_group *group;
-	const struct meson_pmx_func *func;
-	void __iomem *addr;
-	int i;
-
-	group = &priv->data->groups[group_selector];
-	func = &priv->data->funcs[func_selector];
-
-	debug("pinmux: set group %s func %s\n", group->name, func->name);
-
-	/*
-	 * Disable groups using the same pins.
-	 * The selected group is not disabled to avoid glitches.
-	 */
-	for (i = 0; i < group->num_pins; i++) {
-		meson_pinmux_disable_other_groups(priv,
-						  group->pins[i],
-						  group_selector);
-	}
-
-	/* Function 0 (GPIO) doesn't need any additional setting */
-	if (func_selector) {
-		addr = priv->reg_mux + group->reg * 4;
-		writel(readl(addr) | BIT(group->bit), addr);
-	}
-
-	return 0;
-}
-
-const struct pinctrl_ops meson_pinctrl_ops = {
-	.get_groups_count = meson_pinctrl_get_groups_count,
-	.get_group_name = meson_pinctrl_get_group_name,
-	.get_functions_count = meson_pinmux_get_functions_count,
-	.get_function_name = meson_pinmux_get_function_name,
-	.pinmux_group_set = meson_pinmux_group_set,
-	.set_state = pinctrl_generic_set_state,
-};
-
 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
 				       enum meson_reg_type reg_type,
 				       unsigned int *reg, unsigned int *bit)
@@ -149,7 +83,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
 	return 0;
 }
 
-static int meson_gpio_get(struct udevice *dev, unsigned int offset)
+int meson_gpio_get(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -162,7 +96,7 @@ static int meson_gpio_get(struct udevice *dev, unsigned int offset)
 	return !!(readl(priv->reg_gpio + reg) & BIT(bit));
 }
 
-static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
+int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -177,7 +111,7 @@ static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
 	return 0;
 }
 
-static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
+int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit, val;
@@ -192,7 +126,7 @@ static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
 	return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
 }
 
-static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
+int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -207,8 +141,8 @@ static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
 	return 0;
 }
 
-static int meson_gpio_direction_output(struct udevice *dev,
-				       unsigned int offset, int value)
+int meson_gpio_direction_output(struct udevice *dev,
+				unsigned int offset, int value)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	unsigned int reg, bit;
@@ -229,7 +163,7 @@ static int meson_gpio_direction_output(struct udevice *dev,
 	return 0;
 }
 
-static int meson_gpio_probe(struct udevice *dev)
+int meson_gpio_probe(struct udevice *dev)
 {
 	struct meson_pinctrl *priv = dev_get_priv(dev->parent);
 	struct gpio_dev_priv *uc_priv;
@@ -241,21 +175,6 @@ static int meson_gpio_probe(struct udevice *dev)
 	return 0;
 }
 
-static const struct dm_gpio_ops meson_gpio_ops = {
-	.set_value = meson_gpio_set,
-	.get_value = meson_gpio_get,
-	.get_function = meson_gpio_get_direction,
-	.direction_input = meson_gpio_direction_input,
-	.direction_output = meson_gpio_direction_output,
-};
-
-static struct driver meson_gpio_driver = {
-	.name	= "meson-gpio",
-	.id	= UCLASS_GPIO,
-	.probe	= meson_gpio_probe,
-	.ops	= &meson_gpio_ops,
-};
-
 static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
 {
 	int index, len = 0;
@@ -334,7 +253,7 @@ int meson_pinctrl_probe(struct udevice *dev)
 	sprintf(name, "meson-gpio");
 
 	/* Create child device UCLASS_GPIO and bind it */
-	device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
+	device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
 	dev_set_of_offset(gpio_dev, gpio);
 
 	return 0;
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 6ec89ba117..bdee721fc0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -12,9 +12,7 @@ struct meson_pmx_group {
 	const char *name;
 	const unsigned int *pins;
 	unsigned int num_pins;
-	bool is_gpio;
-	unsigned int reg;
-	unsigned int bit;
+	const void *data;
 };
 
 struct meson_pmx_func {
@@ -33,6 +31,8 @@ struct meson_pinctrl_data {
 	unsigned int num_groups;
 	unsigned int num_funcs;
 	unsigned int num_banks;
+	const struct driver *gpio_driver;
+	void *pmx_data;
 };
 
 struct meson_pinctrl {
@@ -89,23 +89,6 @@ struct meson_bank {
 
 #define PIN(x, b)	(b + x)
 
-#define GROUP(grp, r, b)						\
-	{								\
-		.name = #grp,						\
-		.pins = grp ## _pins,					\
-		.num_pins = ARRAY_SIZE(grp ## _pins),			\
-		.reg = r,						\
-		.bit = b,						\
-	 }
-
-#define GPIO_GROUP(gpio, b)						\
-	{								\
-		.name = #gpio,						\
-		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
-		.num_pins = 1,						\
-		.is_gpio = true,					\
-	 }
-
 #define FUNCTION(fn)							\
 	{								\
 		.name = #fn,						\
@@ -131,6 +114,20 @@ struct meson_bank {
 
 extern const struct pinctrl_ops meson_pinctrl_ops;
 
+int meson_pinctrl_get_groups_count(struct udevice *dev);
+const char *meson_pinctrl_get_group_name(struct udevice *dev,
+					 unsigned int selector);
+int meson_pinmux_get_functions_count(struct udevice *dev);
+const char *meson_pinmux_get_function_name(struct udevice *dev,
+					   unsigned int selector);
 int meson_pinctrl_probe(struct udevice *dev);
 
+int meson_gpio_get(struct udevice *dev, unsigned int offset);
+int meson_gpio_set(struct udevice *dev, unsigned int offset, int value);
+int meson_gpio_get_direction(struct udevice *dev, unsigned int offset);
+int meson_gpio_direction_input(struct udevice *dev, unsigned int offset);
+int meson_gpio_direction_output(struct udevice *dev, unsigned int offset,
+				int value);
+int meson_gpio_probe(struct udevice *dev);
+
 #endif /* __PINCTRL_MESON_H__ */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 09/19] pinctrl: meson: select generic pinctrl
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

Meson pinctrl needs generic pinctrl, rather than depending on it
select it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 15a8d9c704..fc51b4361a 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -1,7 +1,7 @@
 if ARCH_MESON
 
 config PINCTRL_MESON
-	depends on PINCTRL_GENERIC
+	select PINCTRL_GENERIC
 	bool
 
 config PINCTRL_MESON_GX_PMX
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 09/19] pinctrl: meson: select generic pinctrl
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

Meson pinctrl needs generic pinctrl, rather than depending on it
select it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index 15a8d9c704..fc51b4361a 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -1,7 +1,7 @@
 if ARCH_MESON
 
 config PINCTRL_MESON
-	depends on PINCTRL_GENERIC
+	select PINCTRL_GENERIC
 	bool
 
 config PINCTRL_MESON_GX_PMX
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 10/19] pinctrl: meson: add axg support
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig                 |   8 +
 drivers/pinctrl/meson/Makefile                |   2 +
 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 125 +++
 drivers/pinctrl/meson/pinctrl-meson-axg.c     | 979 ++++++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-axg.h     |  66 ++
 5 files changed, 1180 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index fc51b4361a..ee820a57a0 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -8,6 +8,10 @@ config PINCTRL_MESON_GX_PMX
 	select PINCTRL_MESON
 	bool
 
+config PINCTRL_MESON_AXG_PMX
+	select PINCTRL_MESON
+	bool
+
 config PINCTRL_MESON_GXBB
 	bool "Amlogic Meson GXBB SoC pinctrl driver"
 	select PINCTRL_MESON_GX_PMX
@@ -16,4 +20,8 @@ config PINCTRL_MESON_GXL
 	bool "Amlogic Meson GXL SoC pinctrl driver"
 	select PINCTRL_MESON_GX_PMX
 
+config PINCTRL_MESON_AXG
+	bool "Amlogic Meson AXG SoC pinctrl driver"
+	select PINCTRL_MESON_AXG_PMX
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 30b6875b88..707287cd1d 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -2,5 +2,7 @@
 
 obj-y					+= pinctrl-meson.o
 obj-$(CONFIG_PINCTRL_MESON_GX_PMX)	+= pinctrl-meson-gx-pmx.o
+obj-$(CONFIG_PINCTRL_MESON_AXG_PMX)	+= pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_GXBB)	+= pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL)		+= pinctrl-meson-gxl.o
+obj-$(CONFIG_PINCTRL_MESON_AXG)		+= pinctrl-meson-axg.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
new file mode 100644
index 0000000000..c82413d08f
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jerome Brunet  <jbrunet@baylibre.com>
+ * Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#include <asm/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include "pinctrl-meson-axg.h"
+
+static int meson_axg_pmx_get_bank(struct udevice *dev, unsigned int pin,
+				  struct meson_pmx_bank **bank)
+{
+	int i;
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	struct meson_axg_pmx_data *pmx = priv->data->pmx_data;
+
+	for (i = 0; i < pmx->num_pmx_banks; i++)
+		if (pin >= pmx->pmx_banks[i].first &&
+		    pin <= pmx->pmx_banks[i].last) {
+			*bank = &pmx->pmx_banks[i];
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
+static int meson_axg_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
+					     unsigned int pin,
+					     unsigned int *reg,
+					     unsigned int *offset)
+{
+	int shift;
+
+	shift = pin - bank->first;
+
+	*reg = bank->reg + (bank->offset + (shift << 2)) / 32;
+	*offset = (bank->offset + (shift << 2)) % 32;
+
+	return 0;
+}
+
+static int meson_axg_pmx_update_function(struct udevice *dev,
+					 unsigned int pin, unsigned int func)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	struct meson_pmx_bank *bank;
+	unsigned int offset;
+	unsigned int reg;
+	unsigned int tmp;
+	int ret;
+
+	ret = meson_axg_pmx_get_bank(dev, pin, &bank);
+	if (ret)
+		return ret;
+
+	meson_axg_pmx_calc_reg_and_offset(bank, pin, &reg, &offset);
+
+	tmp = readl(priv->reg_mux + (reg << 2));
+	tmp &= ~(0xf << offset);
+	tmp |= (func & 0xf) << offset;
+	writel(tmp, priv->reg_mux + (reg << 2));
+
+	return ret;
+}
+
+static int meson_axg_pinmux_group_set(struct udevice *dev,
+				      unsigned int group_selector,
+				      unsigned int func_selector)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	const struct meson_pmx_group *group;
+	const struct meson_pmx_func *func;
+	struct meson_pmx_axg_data *pmx_data;
+	int i, ret;
+
+	group = &priv->data->groups[group_selector];
+	pmx_data = (struct meson_pmx_axg_data *)group->data;
+	func = &priv->data->funcs[func_selector];
+
+	debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+	for (i = 0; i < group->num_pins; i++) {
+		ret = meson_axg_pmx_update_function(dev, group->pins[i],
+						    pmx_data->func);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+const struct pinctrl_ops meson_axg_pinctrl_ops = {
+	.get_groups_count = meson_pinctrl_get_groups_count,
+	.get_group_name = meson_pinctrl_get_group_name,
+	.get_functions_count = meson_pinmux_get_functions_count,
+	.get_function_name = meson_pinmux_get_function_name,
+	.pinmux_group_set = meson_axg_pinmux_group_set,
+	.set_state = pinctrl_generic_set_state,
+};
+
+static int meson_axg_gpio_request(struct udevice *dev,
+				  unsigned int offset, const char *label)
+{
+	return meson_axg_pmx_update_function(dev->parent, offset, 0);
+}
+
+static const struct dm_gpio_ops meson_axg_gpio_ops = {
+	.request = meson_axg_gpio_request,
+	.set_value = meson_gpio_set,
+	.get_value = meson_gpio_get,
+	.get_function = meson_gpio_get_direction,
+	.direction_input = meson_gpio_direction_input,
+	.direction_output = meson_gpio_direction_output,
+};
+
+const struct driver meson_axg_gpio_driver = {
+	.name	= "meson-axg-gpio",
+	.id	= UCLASS_GPIO,
+	.probe	= meson_gpio_probe,
+	.ops	= &meson_axg_gpio_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
new file mode 100644
index 0000000000..a54fbce910
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -0,0 +1,979 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright (C) 2018 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Based on code from Linux kernel:
+ *  Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ *  Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
+
+#include "pinctrl-meson-axg.h"
+
+#define EE_OFF	14
+
+/* emmc */
+static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
+static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
+static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
+static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
+static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
+static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
+static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
+static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
+
+static const unsigned int emmc_clk_pins[] = {BOOT_8};
+static const unsigned int emmc_cmd_pins[] = {BOOT_10};
+static const unsigned int emmc_ds_pins[]  = {BOOT_13};
+
+/* nand */
+static const unsigned int nand_ce0_pins[] = {BOOT_8};
+static const unsigned int nand_ale_pins[] = {BOOT_9};
+static const unsigned int nand_cle_pins[] = {BOOT_10};
+static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
+static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
+static const unsigned int nand_rb0_pins[] = {BOOT_13};
+
+/* nor */
+static const unsigned int nor_hold_pins[] = {BOOT_3};
+static const unsigned int nor_d_pins[] = {BOOT_4};
+static const unsigned int nor_q_pins[] = {BOOT_5};
+static const unsigned int nor_c_pins[] = {BOOT_6};
+static const unsigned int nor_wp_pins[] = {BOOT_9};
+static const unsigned int nor_cs_pins[] = {BOOT_14};
+
+/* sdio */
+static const unsigned int sdio_d0_pins[] = {GPIOX_0};
+static const unsigned int sdio_d1_pins[] = {GPIOX_1};
+static const unsigned int sdio_d2_pins[] = {GPIOX_2};
+static const unsigned int sdio_d3_pins[] = {GPIOX_3};
+static const unsigned int sdio_clk_pins[] = {GPIOX_4};
+static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
+
+/* spi0 */
+static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
+static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
+static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
+static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
+static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
+static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
+
+/* spi1 */
+static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
+static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
+static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
+static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
+
+static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
+static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
+static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
+static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
+static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
+
+/* i2c0 */
+static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
+static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
+
+/* i2c1 */
+static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
+static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
+
+static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
+static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
+
+/* i2c2 */
+static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
+static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
+
+static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
+static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
+
+/* i2c3 */
+static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
+static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
+
+static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
+static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
+
+static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
+static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
+
+/* uart_a */
+static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
+static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
+static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
+static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
+
+/* uart_b */
+static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
+static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
+static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
+static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
+
+static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
+static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
+static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
+static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
+
+/* uart_ao_b */
+static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
+static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
+static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
+static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
+
+/* pwm_a */
+static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
+
+static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
+static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
+
+static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
+
+/* pwm_b */
+static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
+
+static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
+
+static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
+
+/* pwm_c */
+static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
+static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
+
+static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
+
+/* pwm_d */
+static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
+static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
+
+/* pwm_vs */
+static const unsigned int pwm_vs_pins[] = {GPIOA_0};
+
+/* spdif_in */
+static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
+
+static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
+static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
+static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
+static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
+
+/* spdif_out */
+static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
+
+static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
+static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
+static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
+static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
+
+/* jtag_ee */
+static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
+static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
+static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
+static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
+
+/* eth */
+static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
+static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
+static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
+static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
+static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
+static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
+static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
+static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
+static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
+
+static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
+static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
+static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
+static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
+static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
+static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
+static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
+static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
+static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
+
+static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
+static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
+static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
+static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
+static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
+
+/* pdm */
+static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
+static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
+static const unsigned int pdm_din0_pins[] = {GPIOA_15};
+static const unsigned int pdm_din1_pins[] = {GPIOA_16};
+static const unsigned int pdm_din2_pins[] = {GPIOA_17};
+static const unsigned int pdm_din3_pins[] = {GPIOA_18};
+
+/* mclk */
+static const unsigned int mclk_c_pins[] = {GPIOA_0};
+static const unsigned int mclk_b_pins[] = {GPIOA_1};
+
+/* tdm */
+static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
+static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
+static const unsigned int tdma_fs_pins[] = {GPIOX_13};
+static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
+static const unsigned int tdma_din0_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
+static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
+static const unsigned int tdma_din1_pins[] = {GPIOX_15};
+
+static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
+static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
+static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
+static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
+static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
+static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
+
+static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
+static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
+static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
+static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
+static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
+static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
+
+static struct meson_pmx_group meson_axg_periphs_groups[] = {
+	GPIO_GROUP(GPIOZ_0, EE_OFF),
+	GPIO_GROUP(GPIOZ_1, EE_OFF),
+	GPIO_GROUP(GPIOZ_2, EE_OFF),
+	GPIO_GROUP(GPIOZ_3, EE_OFF),
+	GPIO_GROUP(GPIOZ_4, EE_OFF),
+	GPIO_GROUP(GPIOZ_5, EE_OFF),
+	GPIO_GROUP(GPIOZ_6, EE_OFF),
+	GPIO_GROUP(GPIOZ_7, EE_OFF),
+	GPIO_GROUP(GPIOZ_8, EE_OFF),
+	GPIO_GROUP(GPIOZ_9, EE_OFF),
+	GPIO_GROUP(GPIOZ_10, EE_OFF),
+
+	GPIO_GROUP(BOOT_0, EE_OFF),
+	GPIO_GROUP(BOOT_1, EE_OFF),
+	GPIO_GROUP(BOOT_2, EE_OFF),
+	GPIO_GROUP(BOOT_3, EE_OFF),
+	GPIO_GROUP(BOOT_4, EE_OFF),
+	GPIO_GROUP(BOOT_5, EE_OFF),
+	GPIO_GROUP(BOOT_6, EE_OFF),
+	GPIO_GROUP(BOOT_7, EE_OFF),
+	GPIO_GROUP(BOOT_8, EE_OFF),
+	GPIO_GROUP(BOOT_9, EE_OFF),
+	GPIO_GROUP(BOOT_10, EE_OFF),
+	GPIO_GROUP(BOOT_11, EE_OFF),
+	GPIO_GROUP(BOOT_12, EE_OFF),
+	GPIO_GROUP(BOOT_13, EE_OFF),
+	GPIO_GROUP(BOOT_14, EE_OFF),
+
+	GPIO_GROUP(GPIOA_0, EE_OFF),
+	GPIO_GROUP(GPIOA_1, EE_OFF),
+	GPIO_GROUP(GPIOA_2, EE_OFF),
+	GPIO_GROUP(GPIOA_3, EE_OFF),
+	GPIO_GROUP(GPIOA_4, EE_OFF),
+	GPIO_GROUP(GPIOA_5, EE_OFF),
+	GPIO_GROUP(GPIOA_6, EE_OFF),
+	GPIO_GROUP(GPIOA_7, EE_OFF),
+	GPIO_GROUP(GPIOA_8, EE_OFF),
+	GPIO_GROUP(GPIOA_9, EE_OFF),
+	GPIO_GROUP(GPIOA_10, EE_OFF),
+	GPIO_GROUP(GPIOA_11, EE_OFF),
+	GPIO_GROUP(GPIOA_12, EE_OFF),
+	GPIO_GROUP(GPIOA_13, EE_OFF),
+	GPIO_GROUP(GPIOA_14, EE_OFF),
+	GPIO_GROUP(GPIOA_15, EE_OFF),
+	GPIO_GROUP(GPIOA_16, EE_OFF),
+	GPIO_GROUP(GPIOA_17, EE_OFF),
+	GPIO_GROUP(GPIOA_19, EE_OFF),
+	GPIO_GROUP(GPIOA_20, EE_OFF),
+
+	GPIO_GROUP(GPIOX_0, EE_OFF),
+	GPIO_GROUP(GPIOX_1, EE_OFF),
+	GPIO_GROUP(GPIOX_2, EE_OFF),
+	GPIO_GROUP(GPIOX_3, EE_OFF),
+	GPIO_GROUP(GPIOX_4, EE_OFF),
+	GPIO_GROUP(GPIOX_5, EE_OFF),
+	GPIO_GROUP(GPIOX_6, EE_OFF),
+	GPIO_GROUP(GPIOX_7, EE_OFF),
+	GPIO_GROUP(GPIOX_8, EE_OFF),
+	GPIO_GROUP(GPIOX_9, EE_OFF),
+	GPIO_GROUP(GPIOX_10, EE_OFF),
+	GPIO_GROUP(GPIOX_11, EE_OFF),
+	GPIO_GROUP(GPIOX_12, EE_OFF),
+	GPIO_GROUP(GPIOX_13, EE_OFF),
+	GPIO_GROUP(GPIOX_14, EE_OFF),
+	GPIO_GROUP(GPIOX_15, EE_OFF),
+	GPIO_GROUP(GPIOX_16, EE_OFF),
+	GPIO_GROUP(GPIOX_17, EE_OFF),
+	GPIO_GROUP(GPIOX_18, EE_OFF),
+	GPIO_GROUP(GPIOX_19, EE_OFF),
+	GPIO_GROUP(GPIOX_20, EE_OFF),
+	GPIO_GROUP(GPIOX_21, EE_OFF),
+	GPIO_GROUP(GPIOX_22, EE_OFF),
+
+	GPIO_GROUP(GPIOY_0, EE_OFF),
+	GPIO_GROUP(GPIOY_1, EE_OFF),
+	GPIO_GROUP(GPIOY_2, EE_OFF),
+	GPIO_GROUP(GPIOY_3, EE_OFF),
+	GPIO_GROUP(GPIOY_4, EE_OFF),
+	GPIO_GROUP(GPIOY_5, EE_OFF),
+	GPIO_GROUP(GPIOY_6, EE_OFF),
+	GPIO_GROUP(GPIOY_7, EE_OFF),
+	GPIO_GROUP(GPIOY_8, EE_OFF),
+	GPIO_GROUP(GPIOY_9, EE_OFF),
+	GPIO_GROUP(GPIOY_10, EE_OFF),
+	GPIO_GROUP(GPIOY_11, EE_OFF),
+	GPIO_GROUP(GPIOY_12, EE_OFF),
+	GPIO_GROUP(GPIOY_13, EE_OFF),
+	GPIO_GROUP(GPIOY_14, EE_OFF),
+	GPIO_GROUP(GPIOY_15, EE_OFF),
+
+	/* bank BOOT */
+	GROUP(emmc_nand_d0, 1),
+	GROUP(emmc_nand_d1, 1),
+	GROUP(emmc_nand_d2, 1),
+	GROUP(emmc_nand_d3, 1),
+	GROUP(emmc_nand_d4, 1),
+	GROUP(emmc_nand_d5, 1),
+	GROUP(emmc_nand_d6, 1),
+	GROUP(emmc_nand_d7, 1),
+	GROUP(emmc_clk, 1),
+	GROUP(emmc_cmd, 1),
+	GROUP(emmc_ds, 1),
+	GROUP(nand_ce0, 2),
+	GROUP(nand_ale, 2),
+	GROUP(nand_cle, 2),
+	GROUP(nand_wen_clk, 2),
+	GROUP(nand_ren_wr, 2),
+	GROUP(nand_rb0, 2),
+	GROUP(nor_hold, 3),
+	GROUP(nor_d, 3),
+	GROUP(nor_q, 3),
+	GROUP(nor_c, 3),
+	GROUP(nor_wp, 3),
+	GROUP(nor_cs, 3),
+
+	/* bank GPIOZ */
+	GROUP(spi0_clk, 1),
+	GROUP(spi0_mosi, 1),
+	GROUP(spi0_miso, 1),
+	GROUP(spi0_ss0, 1),
+	GROUP(spi0_ss1, 1),
+	GROUP(spi0_ss2, 1),
+	GROUP(i2c0_sck, 1),
+	GROUP(i2c0_sda, 1),
+	GROUP(i2c1_sck_z, 1),
+	GROUP(i2c1_sda_z, 1),
+	GROUP(uart_rts_b_z, 2),
+	GROUP(uart_cts_b_z, 2),
+	GROUP(uart_tx_b_z, 2),
+	GROUP(uart_rx_b_z, 2),
+	GROUP(pwm_a_z, 2),
+	GROUP(pwm_b_z, 2),
+	GROUP(spdif_in_z, 3),
+	GROUP(spdif_out_z, 3),
+	GROUP(uart_ao_tx_b_z, 2),
+	GROUP(uart_ao_rx_b_z, 2),
+	GROUP(uart_ao_cts_b_z, 2),
+	GROUP(uart_ao_rts_b_z, 2),
+
+	/* bank GPIOX */
+	GROUP(sdio_d0, 1),
+	GROUP(sdio_d1, 1),
+	GROUP(sdio_d2, 1),
+	GROUP(sdio_d3, 1),
+	GROUP(sdio_clk, 1),
+	GROUP(sdio_cmd, 1),
+	GROUP(i2c1_sck_x, 1),
+	GROUP(i2c1_sda_x, 1),
+	GROUP(i2c2_sck_x, 1),
+	GROUP(i2c2_sda_x, 1),
+	GROUP(uart_rts_a, 1),
+	GROUP(uart_cts_a, 1),
+	GROUP(uart_tx_a, 1),
+	GROUP(uart_rx_a, 1),
+	GROUP(uart_rts_b_x, 2),
+	GROUP(uart_cts_b_x, 2),
+	GROUP(uart_tx_b_x, 2),
+	GROUP(uart_rx_b_x, 2),
+	GROUP(jtag_tdo_x, 2),
+	GROUP(jtag_tdi_x, 2),
+	GROUP(jtag_clk_x, 2),
+	GROUP(jtag_tms_x, 2),
+	GROUP(spi1_clk_x, 4),
+	GROUP(spi1_mosi_x, 4),
+	GROUP(spi1_miso_x, 4),
+	GROUP(spi1_ss0_x, 4),
+	GROUP(pwm_a_x18, 3),
+	GROUP(pwm_a_x20, 1),
+	GROUP(pwm_b_x, 3),
+	GROUP(pwm_c_x10, 3),
+	GROUP(pwm_c_x17, 3),
+	GROUP(pwm_d_x11, 3),
+	GROUP(pwm_d_x16, 3),
+	GROUP(eth_txd0_x, 4),
+	GROUP(eth_txd1_x, 4),
+	GROUP(eth_txen_x, 4),
+	GROUP(eth_rgmii_rx_clk_x, 4),
+	GROUP(eth_rxd0_x, 4),
+	GROUP(eth_rxd1_x, 4),
+	GROUP(eth_rx_dv_x, 4),
+	GROUP(eth_mdio_x, 4),
+	GROUP(eth_mdc_x, 4),
+	GROUP(tdma_sclk, 1),
+	GROUP(tdma_sclk_slv, 2),
+	GROUP(tdma_fs, 1),
+	GROUP(tdma_fs_slv, 2),
+	GROUP(tdma_din0, 1),
+	GROUP(tdma_dout0_x14, 2),
+	GROUP(tdma_dout0_x15, 1),
+	GROUP(tdma_dout1, 2),
+	GROUP(tdma_din1, 3),
+
+	/* bank GPIOY */
+	GROUP(eth_txd0_y, 1),
+	GROUP(eth_txd1_y, 1),
+	GROUP(eth_txen_y, 1),
+	GROUP(eth_rgmii_rx_clk_y, 1),
+	GROUP(eth_rxd0_y, 1),
+	GROUP(eth_rxd1_y, 1),
+	GROUP(eth_rx_dv_y, 1),
+	GROUP(eth_mdio_y, 1),
+	GROUP(eth_mdc_y, 1),
+	GROUP(eth_rxd2_rgmii, 1),
+	GROUP(eth_rxd3_rgmii, 1),
+	GROUP(eth_rgmii_tx_clk, 1),
+	GROUP(eth_txd2_rgmii, 1),
+	GROUP(eth_txd3_rgmii, 1),
+
+	/* bank GPIOA */
+	GROUP(spdif_out_a1, 4),
+	GROUP(spdif_out_a11, 3),
+	GROUP(spdif_out_a19, 2),
+	GROUP(spdif_out_a20, 1),
+	GROUP(spdif_in_a1, 3),
+	GROUP(spdif_in_a7, 3),
+	GROUP(spdif_in_a19, 1),
+	GROUP(spdif_in_a20, 2),
+	GROUP(spi1_clk_a, 3),
+	GROUP(spi1_mosi_a, 3),
+	GROUP(spi1_miso_a, 3),
+	GROUP(spi1_ss0_a, 3),
+	GROUP(spi1_ss1, 3),
+	GROUP(pwm_a_a, 3),
+	GROUP(pwm_b_a, 3),
+	GROUP(pwm_c_a, 3),
+	GROUP(pwm_vs, 2),
+	GROUP(i2c2_sda_a, 3),
+	GROUP(i2c2_sck_a, 3),
+	GROUP(i2c3_sda_a6, 4),
+	GROUP(i2c3_sck_a7, 4),
+	GROUP(i2c3_sda_a12, 4),
+	GROUP(i2c3_sck_a13, 4),
+	GROUP(i2c3_sda_a19, 4),
+	GROUP(i2c3_sck_a20, 4),
+	GROUP(pdm_dclk_a14, 1),
+	GROUP(pdm_dclk_a19, 3),
+	GROUP(pdm_din0, 1),
+	GROUP(pdm_din1, 1),
+	GROUP(pdm_din2, 1),
+	GROUP(pdm_din3, 1),
+	GROUP(mclk_c, 1),
+	GROUP(mclk_b, 1),
+	GROUP(tdmc_sclk, 1),
+	GROUP(tdmc_sclk_slv, 2),
+	GROUP(tdmc_fs, 1),
+	GROUP(tdmc_fs_slv, 2),
+	GROUP(tdmc_din0, 2),
+	GROUP(tdmc_dout0, 1),
+	GROUP(tdmc_din1, 2),
+	GROUP(tdmc_dout1, 1),
+	GROUP(tdmc_din2, 2),
+	GROUP(tdmc_dout2, 1),
+	GROUP(tdmc_din3, 2),
+	GROUP(tdmc_dout3, 1),
+	GROUP(tdmb_sclk, 1),
+	GROUP(tdmb_sclk_slv, 2),
+	GROUP(tdmb_fs, 1),
+	GROUP(tdmb_fs_slv, 2),
+	GROUP(tdmb_din0, 2),
+	GROUP(tdmb_dout0, 1),
+	GROUP(tdmb_din1, 2),
+	GROUP(tdmb_dout1, 1),
+	GROUP(tdmb_din2, 2),
+	GROUP(tdmb_dout2, 1),
+	GROUP(tdmb_din3, 2),
+	GROUP(tdmb_dout3, 1),
+};
+
+/* uart_ao_a */
+static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
+static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
+static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
+static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
+
+/* uart_ao_b */
+static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
+static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
+static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
+static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
+
+/* i2c_ao */
+static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
+static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
+static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
+static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
+static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
+static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
+
+/* i2c_ao_slave */
+static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
+static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
+
+/* ir_in */
+static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
+
+/* ir_out */
+static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
+
+/* pwm_ao_a */
+static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
+
+/* pwm_ao_b */
+static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
+static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
+
+/* pwm_ao_c */
+static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
+static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
+
+/* pwm_ao_d */
+static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
+
+/* jtag_ao */
+static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
+static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
+static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
+static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
+
+static struct meson_pmx_group meson_axg_aobus_groups[] = {
+	GPIO_GROUP(GPIOAO_0, 0),
+	GPIO_GROUP(GPIOAO_1, 0),
+	GPIO_GROUP(GPIOAO_2, 0),
+	GPIO_GROUP(GPIOAO_3, 0),
+	GPIO_GROUP(GPIOAO_4, 0),
+	GPIO_GROUP(GPIOAO_5, 0),
+	GPIO_GROUP(GPIOAO_6, 0),
+	GPIO_GROUP(GPIOAO_7, 0),
+	GPIO_GROUP(GPIOAO_8, 0),
+	GPIO_GROUP(GPIOAO_9, 0),
+	GPIO_GROUP(GPIOAO_10, 0),
+	GPIO_GROUP(GPIOAO_11, 0),
+	GPIO_GROUP(GPIOAO_12, 0),
+	GPIO_GROUP(GPIOAO_13, 0),
+	GPIO_GROUP(GPIO_TEST_N, 0),
+
+	/* bank AO */
+	GROUP(uart_ao_tx_a, 1),
+	GROUP(uart_ao_rx_a, 1),
+	GROUP(uart_ao_cts_a, 2),
+	GROUP(uart_ao_rts_a, 2),
+	GROUP(uart_ao_tx_b, 1),
+	GROUP(uart_ao_rx_b, 1),
+	GROUP(uart_ao_cts_b, 1),
+	GROUP(uart_ao_rts_b, 1),
+	GROUP(i2c_ao_sck_4, 2),
+	GROUP(i2c_ao_sda_5, 2),
+	GROUP(i2c_ao_sck_8, 2),
+	GROUP(i2c_ao_sda_9, 2),
+	GROUP(i2c_ao_sck_10, 2),
+	GROUP(i2c_ao_sda_11, 2),
+	GROUP(i2c_ao_slave_sck, 1),
+	GROUP(i2c_ao_slave_sda, 1),
+	GROUP(remote_input_ao, 1),
+	GROUP(remote_out_ao, 1),
+	GROUP(pwm_ao_a, 3),
+	GROUP(pwm_ao_b_ao2, 3),
+	GROUP(pwm_ao_b_ao12, 3),
+	GROUP(pwm_ao_c_ao8, 3),
+	GROUP(pwm_ao_c_ao13, 3),
+	GROUP(pwm_ao_d, 3),
+	GROUP(jtag_ao_tdi, 4),
+	GROUP(jtag_ao_tdo, 4),
+	GROUP(jtag_ao_clk, 4),
+	GROUP(jtag_ao_tms, 4),
+};
+
+static const char * const gpio_periphs_groups[] = {
+	"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+	"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+	"GPIOZ_10",
+
+	"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+	"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+	"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+
+	"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+	"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+	"GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
+	"GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
+	"GPIOA_20",
+
+	"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+	"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+	"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+	"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+	"GPIOX_20", "GPIOX_21", "GPIOX_22",
+
+	"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
+	"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
+	"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
+	"GPIOY_15",
+};
+
+static const char * const emmc_groups[] = {
+	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+	"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+	"emmc_nand_d6", "emmc_nand_d7",
+	"emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const nand_groups[] = {
+	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+	"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+	"emmc_nand_d6", "emmc_nand_d7",
+	"nand_ce0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_rb0",
+};
+
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+	"nor_hold", "nor_wp",
+};
+
+static const char * const sdio_groups[] = {
+	"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
+	"sdio_cmd", "sdio_clk",
+};
+
+static const char * const spi0_groups[] = {
+	"spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
+	"spi0_ss1", "spi0_ss2"
+};
+
+static const char * const spi1_groups[] = {
+	"spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
+	"spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
+	"spi1_ss1"
+};
+
+static const char * const uart_a_groups[] = {
+	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+	"uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
+	"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
+};
+
+static const char * const uart_ao_b_z_groups[] = {
+	"uart_ao_tx_b_z", "uart_ao_rx_b_z",
+	"uart_ao_cts_b_z", "uart_ao_rts_b_z",
+};
+
+static const char * const i2c0_groups[] = {
+	"i2c0_sck", "i2c0_sda",
+};
+
+static const char * const i2c1_groups[] = {
+	"i2c1_sck_z", "i2c1_sda_z",
+	"i2c1_sck_x", "i2c1_sda_x",
+};
+
+static const char * const i2c2_groups[] = {
+	"i2c2_sck_x", "i2c2_sda_x",
+	"i2c2_sda_a", "i2c2_sck_a",
+};
+
+static const char * const i2c3_groups[] = {
+	"i2c3_sda_a6", "i2c3_sck_a7",
+	"i2c3_sda_a12", "i2c3_sck_a13",
+	"i2c3_sda_a19", "i2c3_sck_a20",
+};
+
+static const char * const eth_groups[] = {
+	"eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
+	"eth_txd2_rgmii", "eth_txd3_rgmii",
+	"eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
+	"eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
+	"eth_mdc_x",
+	"eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
+	"eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
+	"eth_mdc_y",
+};
+
+static const char * const pwm_a_groups[] = {
+	"pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
+};
+
+static const char * const pwm_b_groups[] = {
+	"pwm_b_z", "pwm_b_x", "pwm_b_a",
+};
+
+static const char * const pwm_c_groups[] = {
+	"pwm_c_x10", "pwm_c_x17", "pwm_c_a",
+};
+
+static const char * const pwm_d_groups[] = {
+	"pwm_d_x11", "pwm_d_x16",
+};
+
+static const char * const pwm_vs_groups[] = {
+	"pwm_vs",
+};
+
+static const char * const spdif_out_groups[] = {
+	"spdif_out_z", "spdif_out_a1", "spdif_out_a11",
+	"spdif_out_a19", "spdif_out_a20",
+};
+
+static const char * const spdif_in_groups[] = {
+	"spdif_in_z", "spdif_in_a1", "spdif_in_a7",
+	"spdif_in_a19", "spdif_in_a20",
+};
+
+static const char * const jtag_ee_groups[] = {
+	"jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
+	"jtag_tms_x",
+};
+
+static const char * const pdm_groups[] = {
+	"pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
+	"pdm_dclk_a14", "pdm_dclk_a19",
+};
+
+static const char * const gpio_aobus_groups[] = {
+	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+	"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
+	"GPIO_TEST_N",
+};
+
+static const char * const uart_ao_a_groups[] = {
+	"uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+	"uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+	"i2c_ao_sck_4", "i2c_ao_sda_5",
+	"i2c_ao_sck_8", "i2c_ao_sda_9",
+	"i2c_ao_sck_10", "i2c_ao_sda_11",
+};
+
+static const char * const i2c_ao_slave_groups[] = {
+	"i2c_ao_slave_sck", "i2c_ao_slave_sda",
+};
+
+static const char * const remote_input_ao_groups[] = {
+	"remote_input_ao",
+};
+
+static const char * const remote_out_ao_groups[] = {
+	"remote_out_ao",
+};
+
+static const char * const pwm_ao_a_groups[] = {
+	"pwm_ao_a",
+};
+
+static const char * const pwm_ao_b_groups[] = {
+	"pwm_ao_b_ao2", "pwm_ao_b_ao12",
+};
+
+static const char * const pwm_ao_c_groups[] = {
+	"pwm_ao_c_ao8", "pwm_ao_c_ao13",
+};
+
+static const char * const pwm_ao_d_groups[] = {
+	"pwm_ao_d",
+};
+
+static const char * const jtag_ao_groups[] = {
+	"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
+};
+
+static const char * const mclk_c_groups[] = {
+	"mclk_c",
+};
+
+static const char * const mclk_b_groups[] = {
+	"mclk_b",
+};
+
+static const char * const tdma_groups[] = {
+	"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
+	"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
+	"tdma_din1",
+};
+
+static const char * const tdmc_groups[] = {
+	"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
+	"tdmc_din0", "tdmc_dout0", "tdmc_din1",	"tdmc_dout1",
+	"tdmc_din2", "tdmc_dout2", "tdmc_din3",	"tdmc_dout3",
+};
+
+static const char * const tdmb_groups[] = {
+	"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
+	"tdmb_din0", "tdmb_dout0", "tdmb_din1",	"tdmb_dout1",
+	"tdmb_din2", "tdmb_dout2", "tdmb_din3",	"tdmb_dout3",
+};
+
+static struct meson_pmx_func meson_axg_periphs_functions[] = {
+	FUNCTION(gpio_periphs),
+	FUNCTION(emmc),
+	FUNCTION(nor),
+	FUNCTION(spi0),
+	FUNCTION(spi1),
+	FUNCTION(sdio),
+	FUNCTION(nand),
+	FUNCTION(uart_a),
+	FUNCTION(uart_b),
+	FUNCTION(uart_ao_b_z),
+	FUNCTION(i2c0),
+	FUNCTION(i2c1),
+	FUNCTION(i2c2),
+	FUNCTION(i2c3),
+	FUNCTION(eth),
+	FUNCTION(pwm_a),
+	FUNCTION(pwm_b),
+	FUNCTION(pwm_c),
+	FUNCTION(pwm_d),
+	FUNCTION(pwm_vs),
+	FUNCTION(spdif_out),
+	FUNCTION(spdif_in),
+	FUNCTION(jtag_ee),
+	FUNCTION(pdm),
+	FUNCTION(mclk_b),
+	FUNCTION(mclk_c),
+	FUNCTION(tdma),
+	FUNCTION(tdmb),
+	FUNCTION(tdmc),
+};
+
+static struct meson_pmx_func meson_axg_aobus_functions[] = {
+	FUNCTION(gpio_aobus),
+	FUNCTION(uart_ao_a),
+	FUNCTION(uart_ao_b),
+	FUNCTION(i2c_ao),
+	FUNCTION(i2c_ao_slave),
+	FUNCTION(remote_input_ao),
+	FUNCTION(remote_out_ao),
+	FUNCTION(pwm_ao_a),
+	FUNCTION(pwm_ao_b),
+	FUNCTION(pwm_ao_c),
+	FUNCTION(pwm_ao_d),
+	FUNCTION(jtag_ao),
+};
+
+static struct meson_bank meson_axg_periphs_banks[] = {
+	/*   name    first      last      pullen  pull    dir     out     in  */
+	BANK("Z",    GPIOZ_0,	GPIOZ_10, 3,  0,  3,  0,  9,  0,  10, 0,  11, 0),
+	BANK("BOOT", BOOT_0,	BOOT_14,  4,  0,  4,  0,  12, 0,  13, 0,  14, 0),
+	BANK("A",    GPIOA_0,	GPIOA_20, 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),
+	BANK("X",    GPIOX_0,	GPIOX_22, 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),
+	BANK("Y",    GPIOY_0,	GPIOY_15, 1,  0,  1,  0,  3,  0,  4,  0,  5,  0),
+};
+
+static struct meson_bank meson_axg_aobus_banks[] = {
+	/*   name    first      last       pullen  pull    dir     out     in  */
+	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
+};
+
+static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
+	/*	 name	 first		lask	   reg	offset  */
+	BANK_PMX("Z",	 GPIOZ_0, GPIOZ_10, 0x2, 0),
+	BANK_PMX("BOOT", BOOT_0,  BOOT_14,  0x0, 0),
+	BANK_PMX("A",	 GPIOA_0, GPIOA_20, 0xb, 0),
+	BANK_PMX("X",	 GPIOX_0, GPIOX_22, 0x4, 0),
+	BANK_PMX("Y",	 GPIOY_0, GPIOY_15, 0x8, 0),
+};
+
+static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
+	.pmx_banks	= meson_axg_periphs_pmx_banks,
+	.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
+};
+
+static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
+	BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
+};
+
+static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
+	.pmx_banks	= meson_axg_aobus_pmx_banks,
+	.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
+};
+
+struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
+	.name		= "periphs-banks",
+	.pin_base	= 11,
+	.groups		= meson_axg_periphs_groups,
+	.funcs		= meson_axg_periphs_functions,
+	.banks		= meson_axg_periphs_banks,
+	.num_pins	= 100,
+	.num_groups	= ARRAY_SIZE(meson_axg_periphs_groups),
+	.num_funcs	= ARRAY_SIZE(meson_axg_periphs_functions),
+	.num_banks	= ARRAY_SIZE(meson_axg_periphs_banks),
+	.gpio_driver	= &meson_axg_gpio_driver,
+	.pmx_data	= &meson_axg_periphs_pmx_banks_data,
+};
+
+struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
+	.name		= "aobus-banks",
+	.pin_base	= 0,
+	.groups		= meson_axg_aobus_groups,
+	.funcs		= meson_axg_aobus_functions,
+	.banks		= meson_axg_aobus_banks,
+	.num_pins	= 14,
+	.num_groups	= ARRAY_SIZE(meson_axg_aobus_groups),
+	.num_funcs	= ARRAY_SIZE(meson_axg_aobus_functions),
+	.num_banks	= ARRAY_SIZE(meson_axg_aobus_banks),
+	.gpio_driver	= &meson_axg_gpio_driver,
+	.pmx_data	= &meson_axg_aobus_pmx_banks_data,
+};
+
+static const struct udevice_id meson_axg_pinctrl_match[] = {
+	{
+		.compatible = "amlogic,meson-axg-periphs-pinctrl",
+		.data = (ulong)&meson_axg_periphs_pinctrl_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-aobus-pinctrl",
+		.data = (ulong)&meson_axg_aobus_pinctrl_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(meson_axg_pinctrl) = {
+	.name = "meson-axg-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(meson_axg_pinctrl_match),
+	.probe = meson_pinctrl_probe,
+	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+	.ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h
new file mode 100644
index 0000000000..c8d2b3af03
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Jerome Brunet  <jbrunet@baylibre.com>
+ * Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#ifndef __PINCTRL_MESON_AXG_H__
+#define __PINCTRL_MESON_AXG_H__
+
+#include "pinctrl-meson.h"
+
+struct meson_pmx_bank {
+	const char *name;
+	unsigned int first;
+	unsigned int last;
+	unsigned int reg;
+	unsigned int offset;
+};
+
+struct meson_axg_pmx_data {
+	struct meson_pmx_bank *pmx_banks;
+	unsigned int num_pmx_banks;
+};
+
+#define BANK_PMX(n, f, l, r, o)				\
+	{							\
+		.name   = n,					\
+		.first	= f,					\
+		.last	= l,					\
+		.reg	= r,					\
+		.offset = o,					\
+	}
+
+struct meson_pmx_axg_data {
+	unsigned int func;
+};
+
+#define PMX_DATA(f)							\
+	{								\
+		.func = f,						\
+	}
+
+#define GROUP(grp, f)							\
+	{								\
+		.name = #grp,						\
+		.pins = grp ## _pins,                                   \
+		.num_pins = ARRAY_SIZE(grp ## _pins),			\
+		.data = (const struct meson_pmx_axg_data[]){		\
+			PMX_DATA(f),					\
+		},							\
+	}
+
+#define GPIO_GROUP(gpio, b)						\
+	{								\
+		.name = #gpio,						\
+		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
+		.num_pins = 1,						\
+		.data = (const struct meson_pmx_axg_data[]){		\
+			PMX_DATA(0),					\
+		},							\
+	}
+
+extern const struct pinctrl_ops meson_axg_pinctrl_ops;
+extern const struct driver meson_axg_gpio_driver;
+
+#endif /* __PINCTRL_MESON_AXG_H__ */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 10/19] pinctrl: meson: add axg support
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

This adds support for the Amlogic AXG SoC pinctrl and GPIO controller
using a specific set of pinctrl functions which differs from the GX SoCs.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/pinctrl/meson/Kconfig                 |   8 +
 drivers/pinctrl/meson/Makefile                |   2 +
 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 125 +++
 drivers/pinctrl/meson/pinctrl-meson-axg.c     | 979 ++++++++++++++++++
 drivers/pinctrl/meson/pinctrl-meson-axg.h     |  66 ++
 5 files changed, 1180 insertions(+)
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
 create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index fc51b4361a..ee820a57a0 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -8,6 +8,10 @@ config PINCTRL_MESON_GX_PMX
 	select PINCTRL_MESON
 	bool
 
+config PINCTRL_MESON_AXG_PMX
+	select PINCTRL_MESON
+	bool
+
 config PINCTRL_MESON_GXBB
 	bool "Amlogic Meson GXBB SoC pinctrl driver"
 	select PINCTRL_MESON_GX_PMX
@@ -16,4 +20,8 @@ config PINCTRL_MESON_GXL
 	bool "Amlogic Meson GXL SoC pinctrl driver"
 	select PINCTRL_MESON_GX_PMX
 
+config PINCTRL_MESON_AXG
+	bool "Amlogic Meson AXG SoC pinctrl driver"
+	select PINCTRL_MESON_AXG_PMX
+
 endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 30b6875b88..707287cd1d 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -2,5 +2,7 @@
 
 obj-y					+= pinctrl-meson.o
 obj-$(CONFIG_PINCTRL_MESON_GX_PMX)	+= pinctrl-meson-gx-pmx.o
+obj-$(CONFIG_PINCTRL_MESON_AXG_PMX)	+= pinctrl-meson-axg-pmx.o
 obj-$(CONFIG_PINCTRL_MESON_GXBB)	+= pinctrl-meson-gxbb.o
 obj-$(CONFIG_PINCTRL_MESON_GXL)		+= pinctrl-meson-gxl.o
+obj-$(CONFIG_PINCTRL_MESON_AXG)		+= pinctrl-meson-axg.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
new file mode 100644
index 0000000000..c82413d08f
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jerome Brunet  <jbrunet@baylibre.com>
+ * Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#include <asm/gpio.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/io.h>
+#include "pinctrl-meson-axg.h"
+
+static int meson_axg_pmx_get_bank(struct udevice *dev, unsigned int pin,
+				  struct meson_pmx_bank **bank)
+{
+	int i;
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	struct meson_axg_pmx_data *pmx = priv->data->pmx_data;
+
+	for (i = 0; i < pmx->num_pmx_banks; i++)
+		if (pin >= pmx->pmx_banks[i].first &&
+		    pin <= pmx->pmx_banks[i].last) {
+			*bank = &pmx->pmx_banks[i];
+			return 0;
+		}
+
+	return -EINVAL;
+}
+
+static int meson_axg_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
+					     unsigned int pin,
+					     unsigned int *reg,
+					     unsigned int *offset)
+{
+	int shift;
+
+	shift = pin - bank->first;
+
+	*reg = bank->reg + (bank->offset + (shift << 2)) / 32;
+	*offset = (bank->offset + (shift << 2)) % 32;
+
+	return 0;
+}
+
+static int meson_axg_pmx_update_function(struct udevice *dev,
+					 unsigned int pin, unsigned int func)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	struct meson_pmx_bank *bank;
+	unsigned int offset;
+	unsigned int reg;
+	unsigned int tmp;
+	int ret;
+
+	ret = meson_axg_pmx_get_bank(dev, pin, &bank);
+	if (ret)
+		return ret;
+
+	meson_axg_pmx_calc_reg_and_offset(bank, pin, &reg, &offset);
+
+	tmp = readl(priv->reg_mux + (reg << 2));
+	tmp &= ~(0xf << offset);
+	tmp |= (func & 0xf) << offset;
+	writel(tmp, priv->reg_mux + (reg << 2));
+
+	return ret;
+}
+
+static int meson_axg_pinmux_group_set(struct udevice *dev,
+				      unsigned int group_selector,
+				      unsigned int func_selector)
+{
+	struct meson_pinctrl *priv = dev_get_priv(dev);
+	const struct meson_pmx_group *group;
+	const struct meson_pmx_func *func;
+	struct meson_pmx_axg_data *pmx_data;
+	int i, ret;
+
+	group = &priv->data->groups[group_selector];
+	pmx_data = (struct meson_pmx_axg_data *)group->data;
+	func = &priv->data->funcs[func_selector];
+
+	debug("pinmux: set group %s func %s\n", group->name, func->name);
+
+	for (i = 0; i < group->num_pins; i++) {
+		ret = meson_axg_pmx_update_function(dev, group->pins[i],
+						    pmx_data->func);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+const struct pinctrl_ops meson_axg_pinctrl_ops = {
+	.get_groups_count = meson_pinctrl_get_groups_count,
+	.get_group_name = meson_pinctrl_get_group_name,
+	.get_functions_count = meson_pinmux_get_functions_count,
+	.get_function_name = meson_pinmux_get_function_name,
+	.pinmux_group_set = meson_axg_pinmux_group_set,
+	.set_state = pinctrl_generic_set_state,
+};
+
+static int meson_axg_gpio_request(struct udevice *dev,
+				  unsigned int offset, const char *label)
+{
+	return meson_axg_pmx_update_function(dev->parent, offset, 0);
+}
+
+static const struct dm_gpio_ops meson_axg_gpio_ops = {
+	.request = meson_axg_gpio_request,
+	.set_value = meson_gpio_set,
+	.get_value = meson_gpio_get,
+	.get_function = meson_gpio_get_direction,
+	.direction_input = meson_gpio_direction_input,
+	.direction_output = meson_gpio_direction_output,
+};
+
+const struct driver meson_axg_gpio_driver = {
+	.name	= "meson-axg-gpio",
+	.id	= UCLASS_GPIO,
+	.probe	= meson_gpio_probe,
+	.ops	= &meson_axg_gpio_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
new file mode 100644
index 0000000000..a54fbce910
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -0,0 +1,979 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright (C) 2018 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Based on code from Linux kernel:
+ *  Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ *  Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
+
+#include "pinctrl-meson-axg.h"
+
+#define EE_OFF	14
+
+/* emmc */
+static const unsigned int emmc_nand_d0_pins[] = {BOOT_0};
+static const unsigned int emmc_nand_d1_pins[] = {BOOT_1};
+static const unsigned int emmc_nand_d2_pins[] = {BOOT_2};
+static const unsigned int emmc_nand_d3_pins[] = {BOOT_3};
+static const unsigned int emmc_nand_d4_pins[] = {BOOT_4};
+static const unsigned int emmc_nand_d5_pins[] = {BOOT_5};
+static const unsigned int emmc_nand_d6_pins[] = {BOOT_6};
+static const unsigned int emmc_nand_d7_pins[] = {BOOT_7};
+
+static const unsigned int emmc_clk_pins[] = {BOOT_8};
+static const unsigned int emmc_cmd_pins[] = {BOOT_10};
+static const unsigned int emmc_ds_pins[]  = {BOOT_13};
+
+/* nand */
+static const unsigned int nand_ce0_pins[] = {BOOT_8};
+static const unsigned int nand_ale_pins[] = {BOOT_9};
+static const unsigned int nand_cle_pins[] = {BOOT_10};
+static const unsigned int nand_wen_clk_pins[] = {BOOT_11};
+static const unsigned int nand_ren_wr_pins[] = {BOOT_12};
+static const unsigned int nand_rb0_pins[] = {BOOT_13};
+
+/* nor */
+static const unsigned int nor_hold_pins[] = {BOOT_3};
+static const unsigned int nor_d_pins[] = {BOOT_4};
+static const unsigned int nor_q_pins[] = {BOOT_5};
+static const unsigned int nor_c_pins[] = {BOOT_6};
+static const unsigned int nor_wp_pins[] = {BOOT_9};
+static const unsigned int nor_cs_pins[] = {BOOT_14};
+
+/* sdio */
+static const unsigned int sdio_d0_pins[] = {GPIOX_0};
+static const unsigned int sdio_d1_pins[] = {GPIOX_1};
+static const unsigned int sdio_d2_pins[] = {GPIOX_2};
+static const unsigned int sdio_d3_pins[] = {GPIOX_3};
+static const unsigned int sdio_clk_pins[] = {GPIOX_4};
+static const unsigned int sdio_cmd_pins[] = {GPIOX_5};
+
+/* spi0 */
+static const unsigned int spi0_clk_pins[] = {GPIOZ_0};
+static const unsigned int spi0_mosi_pins[] = {GPIOZ_1};
+static const unsigned int spi0_miso_pins[] = {GPIOZ_2};
+static const unsigned int spi0_ss0_pins[] = {GPIOZ_3};
+static const unsigned int spi0_ss1_pins[] = {GPIOZ_4};
+static const unsigned int spi0_ss2_pins[] = {GPIOZ_5};
+
+/* spi1 */
+static const unsigned int spi1_clk_x_pins[] = {GPIOX_19};
+static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17};
+static const unsigned int spi1_miso_x_pins[] = {GPIOX_18};
+static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16};
+
+static const unsigned int spi1_clk_a_pins[] = {GPIOA_4};
+static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2};
+static const unsigned int spi1_miso_a_pins[] = {GPIOA_3};
+static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5};
+static const unsigned int spi1_ss1_pins[] = {GPIOA_6};
+
+/* i2c0 */
+static const unsigned int i2c0_sck_pins[] = {GPIOZ_6};
+static const unsigned int i2c0_sda_pins[] = {GPIOZ_7};
+
+/* i2c1 */
+static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8};
+static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9};
+
+static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16};
+static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17};
+
+/* i2c2 */
+static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18};
+static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19};
+
+static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17};
+static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18};
+
+/* i2c3 */
+static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6};
+static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7};
+
+static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12};
+static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13};
+
+static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19};
+static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20};
+
+/* uart_a */
+static const unsigned int uart_rts_a_pins[] = {GPIOX_11};
+static const unsigned int uart_cts_a_pins[] = {GPIOX_10};
+static const unsigned int uart_tx_a_pins[] = {GPIOX_8};
+static const unsigned int uart_rx_a_pins[] = {GPIOX_9};
+
+/* uart_b */
+static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0};
+static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1};
+static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2};
+static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3};
+
+static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18};
+static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19};
+static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16};
+static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17};
+
+/* uart_ao_b */
+static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8};
+static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9};
+static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6};
+static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7};
+
+/* pwm_a */
+static const unsigned int pwm_a_z_pins[] = {GPIOZ_5};
+
+static const unsigned int pwm_a_x18_pins[] = {GPIOX_18};
+static const unsigned int pwm_a_x20_pins[] = {GPIOX_20};
+
+static const unsigned int pwm_a_a_pins[] = {GPIOA_14};
+
+/* pwm_b */
+static const unsigned int pwm_b_z_pins[] = {GPIOZ_4};
+
+static const unsigned int pwm_b_x_pins[] = {GPIOX_19};
+
+static const unsigned int pwm_b_a_pins[] = {GPIOA_15};
+
+/* pwm_c */
+static const unsigned int pwm_c_x10_pins[] = {GPIOX_10};
+static const unsigned int pwm_c_x17_pins[] = {GPIOX_17};
+
+static const unsigned int pwm_c_a_pins[] = {GPIOA_16};
+
+/* pwm_d */
+static const unsigned int pwm_d_x11_pins[] = {GPIOX_11};
+static const unsigned int pwm_d_x16_pins[] = {GPIOX_16};
+
+/* pwm_vs */
+static const unsigned int pwm_vs_pins[] = {GPIOA_0};
+
+/* spdif_in */
+static const unsigned int spdif_in_z_pins[] = {GPIOZ_4};
+
+static const unsigned int spdif_in_a1_pins[] = {GPIOA_1};
+static const unsigned int spdif_in_a7_pins[] = {GPIOA_7};
+static const unsigned int spdif_in_a19_pins[] = {GPIOA_19};
+static const unsigned int spdif_in_a20_pins[] = {GPIOA_20};
+
+/* spdif_out */
+static const unsigned int spdif_out_z_pins[] = {GPIOZ_5};
+
+static const unsigned int spdif_out_a1_pins[] = {GPIOA_1};
+static const unsigned int spdif_out_a11_pins[] = {GPIOA_11};
+static const unsigned int spdif_out_a19_pins[] = {GPIOA_19};
+static const unsigned int spdif_out_a20_pins[] = {GPIOA_20};
+
+/* jtag_ee */
+static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0};
+static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1};
+static const unsigned int jtag_clk_x_pins[] = {GPIOX_4};
+static const unsigned int jtag_tms_x_pins[] = {GPIOX_5};
+
+/* eth */
+static const unsigned int eth_txd0_x_pins[] = {GPIOX_8};
+static const unsigned int eth_txd1_x_pins[] = {GPIOX_9};
+static const unsigned int eth_txen_x_pins[] = {GPIOX_10};
+static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12};
+static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13};
+static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14};
+static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15};
+static const unsigned int eth_mdio_x_pins[] = {GPIOX_21};
+static const unsigned int eth_mdc_x_pins[] = {GPIOX_22};
+
+static const unsigned int eth_txd0_y_pins[] = {GPIOY_10};
+static const unsigned int eth_txd1_y_pins[] = {GPIOY_11};
+static const unsigned int eth_txen_y_pins[] = {GPIOY_9};
+static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2};
+static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4};
+static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5};
+static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3};
+static const unsigned int eth_mdio_y_pins[] = {GPIOY_0};
+static const unsigned int eth_mdc_y_pins[] = {GPIOY_1};
+
+static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6};
+static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7};
+static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8};
+static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12};
+static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13};
+
+/* pdm */
+static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14};
+static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19};
+static const unsigned int pdm_din0_pins[] = {GPIOA_15};
+static const unsigned int pdm_din1_pins[] = {GPIOA_16};
+static const unsigned int pdm_din2_pins[] = {GPIOA_17};
+static const unsigned int pdm_din3_pins[] = {GPIOA_18};
+
+/* mclk */
+static const unsigned int mclk_c_pins[] = {GPIOA_0};
+static const unsigned int mclk_b_pins[] = {GPIOA_1};
+
+/* tdm */
+static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
+static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
+static const unsigned int tdma_fs_pins[] = {GPIOX_13};
+static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
+static const unsigned int tdma_din0_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
+static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
+static const unsigned int tdma_din1_pins[] = {GPIOX_15};
+
+static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
+static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
+static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
+static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
+static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
+static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
+
+static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
+static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
+static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
+static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
+static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
+static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
+
+static struct meson_pmx_group meson_axg_periphs_groups[] = {
+	GPIO_GROUP(GPIOZ_0, EE_OFF),
+	GPIO_GROUP(GPIOZ_1, EE_OFF),
+	GPIO_GROUP(GPIOZ_2, EE_OFF),
+	GPIO_GROUP(GPIOZ_3, EE_OFF),
+	GPIO_GROUP(GPIOZ_4, EE_OFF),
+	GPIO_GROUP(GPIOZ_5, EE_OFF),
+	GPIO_GROUP(GPIOZ_6, EE_OFF),
+	GPIO_GROUP(GPIOZ_7, EE_OFF),
+	GPIO_GROUP(GPIOZ_8, EE_OFF),
+	GPIO_GROUP(GPIOZ_9, EE_OFF),
+	GPIO_GROUP(GPIOZ_10, EE_OFF),
+
+	GPIO_GROUP(BOOT_0, EE_OFF),
+	GPIO_GROUP(BOOT_1, EE_OFF),
+	GPIO_GROUP(BOOT_2, EE_OFF),
+	GPIO_GROUP(BOOT_3, EE_OFF),
+	GPIO_GROUP(BOOT_4, EE_OFF),
+	GPIO_GROUP(BOOT_5, EE_OFF),
+	GPIO_GROUP(BOOT_6, EE_OFF),
+	GPIO_GROUP(BOOT_7, EE_OFF),
+	GPIO_GROUP(BOOT_8, EE_OFF),
+	GPIO_GROUP(BOOT_9, EE_OFF),
+	GPIO_GROUP(BOOT_10, EE_OFF),
+	GPIO_GROUP(BOOT_11, EE_OFF),
+	GPIO_GROUP(BOOT_12, EE_OFF),
+	GPIO_GROUP(BOOT_13, EE_OFF),
+	GPIO_GROUP(BOOT_14, EE_OFF),
+
+	GPIO_GROUP(GPIOA_0, EE_OFF),
+	GPIO_GROUP(GPIOA_1, EE_OFF),
+	GPIO_GROUP(GPIOA_2, EE_OFF),
+	GPIO_GROUP(GPIOA_3, EE_OFF),
+	GPIO_GROUP(GPIOA_4, EE_OFF),
+	GPIO_GROUP(GPIOA_5, EE_OFF),
+	GPIO_GROUP(GPIOA_6, EE_OFF),
+	GPIO_GROUP(GPIOA_7, EE_OFF),
+	GPIO_GROUP(GPIOA_8, EE_OFF),
+	GPIO_GROUP(GPIOA_9, EE_OFF),
+	GPIO_GROUP(GPIOA_10, EE_OFF),
+	GPIO_GROUP(GPIOA_11, EE_OFF),
+	GPIO_GROUP(GPIOA_12, EE_OFF),
+	GPIO_GROUP(GPIOA_13, EE_OFF),
+	GPIO_GROUP(GPIOA_14, EE_OFF),
+	GPIO_GROUP(GPIOA_15, EE_OFF),
+	GPIO_GROUP(GPIOA_16, EE_OFF),
+	GPIO_GROUP(GPIOA_17, EE_OFF),
+	GPIO_GROUP(GPIOA_19, EE_OFF),
+	GPIO_GROUP(GPIOA_20, EE_OFF),
+
+	GPIO_GROUP(GPIOX_0, EE_OFF),
+	GPIO_GROUP(GPIOX_1, EE_OFF),
+	GPIO_GROUP(GPIOX_2, EE_OFF),
+	GPIO_GROUP(GPIOX_3, EE_OFF),
+	GPIO_GROUP(GPIOX_4, EE_OFF),
+	GPIO_GROUP(GPIOX_5, EE_OFF),
+	GPIO_GROUP(GPIOX_6, EE_OFF),
+	GPIO_GROUP(GPIOX_7, EE_OFF),
+	GPIO_GROUP(GPIOX_8, EE_OFF),
+	GPIO_GROUP(GPIOX_9, EE_OFF),
+	GPIO_GROUP(GPIOX_10, EE_OFF),
+	GPIO_GROUP(GPIOX_11, EE_OFF),
+	GPIO_GROUP(GPIOX_12, EE_OFF),
+	GPIO_GROUP(GPIOX_13, EE_OFF),
+	GPIO_GROUP(GPIOX_14, EE_OFF),
+	GPIO_GROUP(GPIOX_15, EE_OFF),
+	GPIO_GROUP(GPIOX_16, EE_OFF),
+	GPIO_GROUP(GPIOX_17, EE_OFF),
+	GPIO_GROUP(GPIOX_18, EE_OFF),
+	GPIO_GROUP(GPIOX_19, EE_OFF),
+	GPIO_GROUP(GPIOX_20, EE_OFF),
+	GPIO_GROUP(GPIOX_21, EE_OFF),
+	GPIO_GROUP(GPIOX_22, EE_OFF),
+
+	GPIO_GROUP(GPIOY_0, EE_OFF),
+	GPIO_GROUP(GPIOY_1, EE_OFF),
+	GPIO_GROUP(GPIOY_2, EE_OFF),
+	GPIO_GROUP(GPIOY_3, EE_OFF),
+	GPIO_GROUP(GPIOY_4, EE_OFF),
+	GPIO_GROUP(GPIOY_5, EE_OFF),
+	GPIO_GROUP(GPIOY_6, EE_OFF),
+	GPIO_GROUP(GPIOY_7, EE_OFF),
+	GPIO_GROUP(GPIOY_8, EE_OFF),
+	GPIO_GROUP(GPIOY_9, EE_OFF),
+	GPIO_GROUP(GPIOY_10, EE_OFF),
+	GPIO_GROUP(GPIOY_11, EE_OFF),
+	GPIO_GROUP(GPIOY_12, EE_OFF),
+	GPIO_GROUP(GPIOY_13, EE_OFF),
+	GPIO_GROUP(GPIOY_14, EE_OFF),
+	GPIO_GROUP(GPIOY_15, EE_OFF),
+
+	/* bank BOOT */
+	GROUP(emmc_nand_d0, 1),
+	GROUP(emmc_nand_d1, 1),
+	GROUP(emmc_nand_d2, 1),
+	GROUP(emmc_nand_d3, 1),
+	GROUP(emmc_nand_d4, 1),
+	GROUP(emmc_nand_d5, 1),
+	GROUP(emmc_nand_d6, 1),
+	GROUP(emmc_nand_d7, 1),
+	GROUP(emmc_clk, 1),
+	GROUP(emmc_cmd, 1),
+	GROUP(emmc_ds, 1),
+	GROUP(nand_ce0, 2),
+	GROUP(nand_ale, 2),
+	GROUP(nand_cle, 2),
+	GROUP(nand_wen_clk, 2),
+	GROUP(nand_ren_wr, 2),
+	GROUP(nand_rb0, 2),
+	GROUP(nor_hold, 3),
+	GROUP(nor_d, 3),
+	GROUP(nor_q, 3),
+	GROUP(nor_c, 3),
+	GROUP(nor_wp, 3),
+	GROUP(nor_cs, 3),
+
+	/* bank GPIOZ */
+	GROUP(spi0_clk, 1),
+	GROUP(spi0_mosi, 1),
+	GROUP(spi0_miso, 1),
+	GROUP(spi0_ss0, 1),
+	GROUP(spi0_ss1, 1),
+	GROUP(spi0_ss2, 1),
+	GROUP(i2c0_sck, 1),
+	GROUP(i2c0_sda, 1),
+	GROUP(i2c1_sck_z, 1),
+	GROUP(i2c1_sda_z, 1),
+	GROUP(uart_rts_b_z, 2),
+	GROUP(uart_cts_b_z, 2),
+	GROUP(uart_tx_b_z, 2),
+	GROUP(uart_rx_b_z, 2),
+	GROUP(pwm_a_z, 2),
+	GROUP(pwm_b_z, 2),
+	GROUP(spdif_in_z, 3),
+	GROUP(spdif_out_z, 3),
+	GROUP(uart_ao_tx_b_z, 2),
+	GROUP(uart_ao_rx_b_z, 2),
+	GROUP(uart_ao_cts_b_z, 2),
+	GROUP(uart_ao_rts_b_z, 2),
+
+	/* bank GPIOX */
+	GROUP(sdio_d0, 1),
+	GROUP(sdio_d1, 1),
+	GROUP(sdio_d2, 1),
+	GROUP(sdio_d3, 1),
+	GROUP(sdio_clk, 1),
+	GROUP(sdio_cmd, 1),
+	GROUP(i2c1_sck_x, 1),
+	GROUP(i2c1_sda_x, 1),
+	GROUP(i2c2_sck_x, 1),
+	GROUP(i2c2_sda_x, 1),
+	GROUP(uart_rts_a, 1),
+	GROUP(uart_cts_a, 1),
+	GROUP(uart_tx_a, 1),
+	GROUP(uart_rx_a, 1),
+	GROUP(uart_rts_b_x, 2),
+	GROUP(uart_cts_b_x, 2),
+	GROUP(uart_tx_b_x, 2),
+	GROUP(uart_rx_b_x, 2),
+	GROUP(jtag_tdo_x, 2),
+	GROUP(jtag_tdi_x, 2),
+	GROUP(jtag_clk_x, 2),
+	GROUP(jtag_tms_x, 2),
+	GROUP(spi1_clk_x, 4),
+	GROUP(spi1_mosi_x, 4),
+	GROUP(spi1_miso_x, 4),
+	GROUP(spi1_ss0_x, 4),
+	GROUP(pwm_a_x18, 3),
+	GROUP(pwm_a_x20, 1),
+	GROUP(pwm_b_x, 3),
+	GROUP(pwm_c_x10, 3),
+	GROUP(pwm_c_x17, 3),
+	GROUP(pwm_d_x11, 3),
+	GROUP(pwm_d_x16, 3),
+	GROUP(eth_txd0_x, 4),
+	GROUP(eth_txd1_x, 4),
+	GROUP(eth_txen_x, 4),
+	GROUP(eth_rgmii_rx_clk_x, 4),
+	GROUP(eth_rxd0_x, 4),
+	GROUP(eth_rxd1_x, 4),
+	GROUP(eth_rx_dv_x, 4),
+	GROUP(eth_mdio_x, 4),
+	GROUP(eth_mdc_x, 4),
+	GROUP(tdma_sclk, 1),
+	GROUP(tdma_sclk_slv, 2),
+	GROUP(tdma_fs, 1),
+	GROUP(tdma_fs_slv, 2),
+	GROUP(tdma_din0, 1),
+	GROUP(tdma_dout0_x14, 2),
+	GROUP(tdma_dout0_x15, 1),
+	GROUP(tdma_dout1, 2),
+	GROUP(tdma_din1, 3),
+
+	/* bank GPIOY */
+	GROUP(eth_txd0_y, 1),
+	GROUP(eth_txd1_y, 1),
+	GROUP(eth_txen_y, 1),
+	GROUP(eth_rgmii_rx_clk_y, 1),
+	GROUP(eth_rxd0_y, 1),
+	GROUP(eth_rxd1_y, 1),
+	GROUP(eth_rx_dv_y, 1),
+	GROUP(eth_mdio_y, 1),
+	GROUP(eth_mdc_y, 1),
+	GROUP(eth_rxd2_rgmii, 1),
+	GROUP(eth_rxd3_rgmii, 1),
+	GROUP(eth_rgmii_tx_clk, 1),
+	GROUP(eth_txd2_rgmii, 1),
+	GROUP(eth_txd3_rgmii, 1),
+
+	/* bank GPIOA */
+	GROUP(spdif_out_a1, 4),
+	GROUP(spdif_out_a11, 3),
+	GROUP(spdif_out_a19, 2),
+	GROUP(spdif_out_a20, 1),
+	GROUP(spdif_in_a1, 3),
+	GROUP(spdif_in_a7, 3),
+	GROUP(spdif_in_a19, 1),
+	GROUP(spdif_in_a20, 2),
+	GROUP(spi1_clk_a, 3),
+	GROUP(spi1_mosi_a, 3),
+	GROUP(spi1_miso_a, 3),
+	GROUP(spi1_ss0_a, 3),
+	GROUP(spi1_ss1, 3),
+	GROUP(pwm_a_a, 3),
+	GROUP(pwm_b_a, 3),
+	GROUP(pwm_c_a, 3),
+	GROUP(pwm_vs, 2),
+	GROUP(i2c2_sda_a, 3),
+	GROUP(i2c2_sck_a, 3),
+	GROUP(i2c3_sda_a6, 4),
+	GROUP(i2c3_sck_a7, 4),
+	GROUP(i2c3_sda_a12, 4),
+	GROUP(i2c3_sck_a13, 4),
+	GROUP(i2c3_sda_a19, 4),
+	GROUP(i2c3_sck_a20, 4),
+	GROUP(pdm_dclk_a14, 1),
+	GROUP(pdm_dclk_a19, 3),
+	GROUP(pdm_din0, 1),
+	GROUP(pdm_din1, 1),
+	GROUP(pdm_din2, 1),
+	GROUP(pdm_din3, 1),
+	GROUP(mclk_c, 1),
+	GROUP(mclk_b, 1),
+	GROUP(tdmc_sclk, 1),
+	GROUP(tdmc_sclk_slv, 2),
+	GROUP(tdmc_fs, 1),
+	GROUP(tdmc_fs_slv, 2),
+	GROUP(tdmc_din0, 2),
+	GROUP(tdmc_dout0, 1),
+	GROUP(tdmc_din1, 2),
+	GROUP(tdmc_dout1, 1),
+	GROUP(tdmc_din2, 2),
+	GROUP(tdmc_dout2, 1),
+	GROUP(tdmc_din3, 2),
+	GROUP(tdmc_dout3, 1),
+	GROUP(tdmb_sclk, 1),
+	GROUP(tdmb_sclk_slv, 2),
+	GROUP(tdmb_fs, 1),
+	GROUP(tdmb_fs_slv, 2),
+	GROUP(tdmb_din0, 2),
+	GROUP(tdmb_dout0, 1),
+	GROUP(tdmb_din1, 2),
+	GROUP(tdmb_dout1, 1),
+	GROUP(tdmb_din2, 2),
+	GROUP(tdmb_dout2, 1),
+	GROUP(tdmb_din3, 2),
+	GROUP(tdmb_dout3, 1),
+};
+
+/* uart_ao_a */
+static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0};
+static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1};
+static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2};
+static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3};
+
+/* uart_ao_b */
+static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4};
+static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5};
+static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2};
+static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3};
+
+/* i2c_ao */
+static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4};
+static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5};
+static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8};
+static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9};
+static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10};
+static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11};
+
+/* i2c_ao_slave */
+static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10};
+static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11};
+
+/* ir_in */
+static const unsigned int remote_input_ao_pins[] = {GPIOAO_6};
+
+/* ir_out */
+static const unsigned int remote_out_ao_pins[] = {GPIOAO_7};
+
+/* pwm_ao_a */
+static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3};
+
+/* pwm_ao_b */
+static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2};
+static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12};
+
+/* pwm_ao_c */
+static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8};
+static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13};
+
+/* pwm_ao_d */
+static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9};
+
+/* jtag_ao */
+static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3};
+static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
+static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
+static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
+
+static struct meson_pmx_group meson_axg_aobus_groups[] = {
+	GPIO_GROUP(GPIOAO_0, 0),
+	GPIO_GROUP(GPIOAO_1, 0),
+	GPIO_GROUP(GPIOAO_2, 0),
+	GPIO_GROUP(GPIOAO_3, 0),
+	GPIO_GROUP(GPIOAO_4, 0),
+	GPIO_GROUP(GPIOAO_5, 0),
+	GPIO_GROUP(GPIOAO_6, 0),
+	GPIO_GROUP(GPIOAO_7, 0),
+	GPIO_GROUP(GPIOAO_8, 0),
+	GPIO_GROUP(GPIOAO_9, 0),
+	GPIO_GROUP(GPIOAO_10, 0),
+	GPIO_GROUP(GPIOAO_11, 0),
+	GPIO_GROUP(GPIOAO_12, 0),
+	GPIO_GROUP(GPIOAO_13, 0),
+	GPIO_GROUP(GPIO_TEST_N, 0),
+
+	/* bank AO */
+	GROUP(uart_ao_tx_a, 1),
+	GROUP(uart_ao_rx_a, 1),
+	GROUP(uart_ao_cts_a, 2),
+	GROUP(uart_ao_rts_a, 2),
+	GROUP(uart_ao_tx_b, 1),
+	GROUP(uart_ao_rx_b, 1),
+	GROUP(uart_ao_cts_b, 1),
+	GROUP(uart_ao_rts_b, 1),
+	GROUP(i2c_ao_sck_4, 2),
+	GROUP(i2c_ao_sda_5, 2),
+	GROUP(i2c_ao_sck_8, 2),
+	GROUP(i2c_ao_sda_9, 2),
+	GROUP(i2c_ao_sck_10, 2),
+	GROUP(i2c_ao_sda_11, 2),
+	GROUP(i2c_ao_slave_sck, 1),
+	GROUP(i2c_ao_slave_sda, 1),
+	GROUP(remote_input_ao, 1),
+	GROUP(remote_out_ao, 1),
+	GROUP(pwm_ao_a, 3),
+	GROUP(pwm_ao_b_ao2, 3),
+	GROUP(pwm_ao_b_ao12, 3),
+	GROUP(pwm_ao_c_ao8, 3),
+	GROUP(pwm_ao_c_ao13, 3),
+	GROUP(pwm_ao_d, 3),
+	GROUP(jtag_ao_tdi, 4),
+	GROUP(jtag_ao_tdo, 4),
+	GROUP(jtag_ao_clk, 4),
+	GROUP(jtag_ao_tms, 4),
+};
+
+static const char * const gpio_periphs_groups[] = {
+	"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+	"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+	"GPIOZ_10",
+
+	"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+	"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+	"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+
+	"GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+	"GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+	"GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
+	"GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19",
+	"GPIOA_20",
+
+	"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+	"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+	"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+	"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+	"GPIOX_20", "GPIOX_21", "GPIOX_22",
+
+	"GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
+	"GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
+	"GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
+	"GPIOY_15",
+};
+
+static const char * const emmc_groups[] = {
+	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+	"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+	"emmc_nand_d6", "emmc_nand_d7",
+	"emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const nand_groups[] = {
+	"emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2",
+	"emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5",
+	"emmc_nand_d6", "emmc_nand_d7",
+	"nand_ce0", "nand_ale", "nand_cle",
+	"nand_wen_clk", "nand_ren_wr", "nand_rb0",
+};
+
+static const char * const nor_groups[] = {
+	"nor_d", "nor_q", "nor_c", "nor_cs",
+	"nor_hold", "nor_wp",
+};
+
+static const char * const sdio_groups[] = {
+	"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3",
+	"sdio_cmd", "sdio_clk",
+};
+
+static const char * const spi0_groups[] = {
+	"spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0",
+	"spi0_ss1", "spi0_ss2"
+};
+
+static const char * const spi1_groups[] = {
+	"spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x",
+	"spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a",
+	"spi1_ss1"
+};
+
+static const char * const uart_a_groups[] = {
+	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+	"uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z",
+	"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
+};
+
+static const char * const uart_ao_b_z_groups[] = {
+	"uart_ao_tx_b_z", "uart_ao_rx_b_z",
+	"uart_ao_cts_b_z", "uart_ao_rts_b_z",
+};
+
+static const char * const i2c0_groups[] = {
+	"i2c0_sck", "i2c0_sda",
+};
+
+static const char * const i2c1_groups[] = {
+	"i2c1_sck_z", "i2c1_sda_z",
+	"i2c1_sck_x", "i2c1_sda_x",
+};
+
+static const char * const i2c2_groups[] = {
+	"i2c2_sck_x", "i2c2_sda_x",
+	"i2c2_sda_a", "i2c2_sck_a",
+};
+
+static const char * const i2c3_groups[] = {
+	"i2c3_sda_a6", "i2c3_sck_a7",
+	"i2c3_sda_a12", "i2c3_sck_a13",
+	"i2c3_sda_a19", "i2c3_sck_a20",
+};
+
+static const char * const eth_groups[] = {
+	"eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
+	"eth_txd2_rgmii", "eth_txd3_rgmii",
+	"eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x",
+	"eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x",
+	"eth_mdc_x",
+	"eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y",
+	"eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y",
+	"eth_mdc_y",
+};
+
+static const char * const pwm_a_groups[] = {
+	"pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a",
+};
+
+static const char * const pwm_b_groups[] = {
+	"pwm_b_z", "pwm_b_x", "pwm_b_a",
+};
+
+static const char * const pwm_c_groups[] = {
+	"pwm_c_x10", "pwm_c_x17", "pwm_c_a",
+};
+
+static const char * const pwm_d_groups[] = {
+	"pwm_d_x11", "pwm_d_x16",
+};
+
+static const char * const pwm_vs_groups[] = {
+	"pwm_vs",
+};
+
+static const char * const spdif_out_groups[] = {
+	"spdif_out_z", "spdif_out_a1", "spdif_out_a11",
+	"spdif_out_a19", "spdif_out_a20",
+};
+
+static const char * const spdif_in_groups[] = {
+	"spdif_in_z", "spdif_in_a1", "spdif_in_a7",
+	"spdif_in_a19", "spdif_in_a20",
+};
+
+static const char * const jtag_ee_groups[] = {
+	"jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x",
+	"jtag_tms_x",
+};
+
+static const char * const pdm_groups[] = {
+	"pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3",
+	"pdm_dclk_a14", "pdm_dclk_a19",
+};
+
+static const char * const gpio_aobus_groups[] = {
+	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
+	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
+	"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
+	"GPIO_TEST_N",
+};
+
+static const char * const uart_ao_a_groups[] = {
+	"uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+	"uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+	"i2c_ao_sck_4", "i2c_ao_sda_5",
+	"i2c_ao_sck_8", "i2c_ao_sda_9",
+	"i2c_ao_sck_10", "i2c_ao_sda_11",
+};
+
+static const char * const i2c_ao_slave_groups[] = {
+	"i2c_ao_slave_sck", "i2c_ao_slave_sda",
+};
+
+static const char * const remote_input_ao_groups[] = {
+	"remote_input_ao",
+};
+
+static const char * const remote_out_ao_groups[] = {
+	"remote_out_ao",
+};
+
+static const char * const pwm_ao_a_groups[] = {
+	"pwm_ao_a",
+};
+
+static const char * const pwm_ao_b_groups[] = {
+	"pwm_ao_b_ao2", "pwm_ao_b_ao12",
+};
+
+static const char * const pwm_ao_c_groups[] = {
+	"pwm_ao_c_ao8", "pwm_ao_c_ao13",
+};
+
+static const char * const pwm_ao_d_groups[] = {
+	"pwm_ao_d",
+};
+
+static const char * const jtag_ao_groups[] = {
+	"jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
+};
+
+static const char * const mclk_c_groups[] = {
+	"mclk_c",
+};
+
+static const char * const mclk_b_groups[] = {
+	"mclk_b",
+};
+
+static const char * const tdma_groups[] = {
+	"tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
+	"tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
+	"tdma_din1",
+};
+
+static const char * const tdmc_groups[] = {
+	"tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
+	"tdmc_din0", "tdmc_dout0", "tdmc_din1",	"tdmc_dout1",
+	"tdmc_din2", "tdmc_dout2", "tdmc_din3",	"tdmc_dout3",
+};
+
+static const char * const tdmb_groups[] = {
+	"tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
+	"tdmb_din0", "tdmb_dout0", "tdmb_din1",	"tdmb_dout1",
+	"tdmb_din2", "tdmb_dout2", "tdmb_din3",	"tdmb_dout3",
+};
+
+static struct meson_pmx_func meson_axg_periphs_functions[] = {
+	FUNCTION(gpio_periphs),
+	FUNCTION(emmc),
+	FUNCTION(nor),
+	FUNCTION(spi0),
+	FUNCTION(spi1),
+	FUNCTION(sdio),
+	FUNCTION(nand),
+	FUNCTION(uart_a),
+	FUNCTION(uart_b),
+	FUNCTION(uart_ao_b_z),
+	FUNCTION(i2c0),
+	FUNCTION(i2c1),
+	FUNCTION(i2c2),
+	FUNCTION(i2c3),
+	FUNCTION(eth),
+	FUNCTION(pwm_a),
+	FUNCTION(pwm_b),
+	FUNCTION(pwm_c),
+	FUNCTION(pwm_d),
+	FUNCTION(pwm_vs),
+	FUNCTION(spdif_out),
+	FUNCTION(spdif_in),
+	FUNCTION(jtag_ee),
+	FUNCTION(pdm),
+	FUNCTION(mclk_b),
+	FUNCTION(mclk_c),
+	FUNCTION(tdma),
+	FUNCTION(tdmb),
+	FUNCTION(tdmc),
+};
+
+static struct meson_pmx_func meson_axg_aobus_functions[] = {
+	FUNCTION(gpio_aobus),
+	FUNCTION(uart_ao_a),
+	FUNCTION(uart_ao_b),
+	FUNCTION(i2c_ao),
+	FUNCTION(i2c_ao_slave),
+	FUNCTION(remote_input_ao),
+	FUNCTION(remote_out_ao),
+	FUNCTION(pwm_ao_a),
+	FUNCTION(pwm_ao_b),
+	FUNCTION(pwm_ao_c),
+	FUNCTION(pwm_ao_d),
+	FUNCTION(jtag_ao),
+};
+
+static struct meson_bank meson_axg_periphs_banks[] = {
+	/*   name    first      last      pullen  pull    dir     out     in  */
+	BANK("Z",    GPIOZ_0,	GPIOZ_10, 3,  0,  3,  0,  9,  0,  10, 0,  11, 0),
+	BANK("BOOT", BOOT_0,	BOOT_14,  4,  0,  4,  0,  12, 0,  13, 0,  14, 0),
+	BANK("A",    GPIOA_0,	GPIOA_20, 0,  0,  0,  0,  0,  0,  1,  0,  2,  0),
+	BANK("X",    GPIOX_0,	GPIOX_22, 2,  0,  2,  0,  6,  0,  7,  0,  8,  0),
+	BANK("Y",    GPIOY_0,	GPIOY_15, 1,  0,  1,  0,  3,  0,  4,  0,  5,  0),
+};
+
+static struct meson_bank meson_axg_aobus_banks[] = {
+	/*   name    first      last       pullen  pull    dir     out     in  */
+	BANK("AO",   GPIOAO_0,  GPIOAO_13, 0,  16,  0, 0,  0,  0,  0, 16,  1,  0),
+};
+
+static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
+	/*	 name	 first		lask	   reg	offset  */
+	BANK_PMX("Z",	 GPIOZ_0, GPIOZ_10, 0x2, 0),
+	BANK_PMX("BOOT", BOOT_0,  BOOT_14,  0x0, 0),
+	BANK_PMX("A",	 GPIOA_0, GPIOA_20, 0xb, 0),
+	BANK_PMX("X",	 GPIOX_0, GPIOX_22, 0x4, 0),
+	BANK_PMX("Y",	 GPIOY_0, GPIOY_15, 0x8, 0),
+};
+
+static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
+	.pmx_banks	= meson_axg_periphs_pmx_banks,
+	.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
+};
+
+static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
+	BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
+};
+
+static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
+	.pmx_banks	= meson_axg_aobus_pmx_banks,
+	.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
+};
+
+struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
+	.name		= "periphs-banks",
+	.pin_base	= 11,
+	.groups		= meson_axg_periphs_groups,
+	.funcs		= meson_axg_periphs_functions,
+	.banks		= meson_axg_periphs_banks,
+	.num_pins	= 100,
+	.num_groups	= ARRAY_SIZE(meson_axg_periphs_groups),
+	.num_funcs	= ARRAY_SIZE(meson_axg_periphs_functions),
+	.num_banks	= ARRAY_SIZE(meson_axg_periphs_banks),
+	.gpio_driver	= &meson_axg_gpio_driver,
+	.pmx_data	= &meson_axg_periphs_pmx_banks_data,
+};
+
+struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
+	.name		= "aobus-banks",
+	.pin_base	= 0,
+	.groups		= meson_axg_aobus_groups,
+	.funcs		= meson_axg_aobus_functions,
+	.banks		= meson_axg_aobus_banks,
+	.num_pins	= 14,
+	.num_groups	= ARRAY_SIZE(meson_axg_aobus_groups),
+	.num_funcs	= ARRAY_SIZE(meson_axg_aobus_functions),
+	.num_banks	= ARRAY_SIZE(meson_axg_aobus_banks),
+	.gpio_driver	= &meson_axg_gpio_driver,
+	.pmx_data	= &meson_axg_aobus_pmx_banks_data,
+};
+
+static const struct udevice_id meson_axg_pinctrl_match[] = {
+	{
+		.compatible = "amlogic,meson-axg-periphs-pinctrl",
+		.data = (ulong)&meson_axg_periphs_pinctrl_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-aobus-pinctrl",
+		.data = (ulong)&meson_axg_aobus_pinctrl_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(meson_axg_pinctrl) = {
+	.name = "meson-axg-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(meson_axg_pinctrl_match),
+	.probe = meson_pinctrl_probe,
+	.priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+	.ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.h b/drivers/pinctrl/meson/pinctrl-meson-axg.h
new file mode 100644
index 0000000000..c8d2b3af03
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Jerome Brunet  <jbrunet@baylibre.com>
+ * Copyright (C) 2017 Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#ifndef __PINCTRL_MESON_AXG_H__
+#define __PINCTRL_MESON_AXG_H__
+
+#include "pinctrl-meson.h"
+
+struct meson_pmx_bank {
+	const char *name;
+	unsigned int first;
+	unsigned int last;
+	unsigned int reg;
+	unsigned int offset;
+};
+
+struct meson_axg_pmx_data {
+	struct meson_pmx_bank *pmx_banks;
+	unsigned int num_pmx_banks;
+};
+
+#define BANK_PMX(n, f, l, r, o)				\
+	{							\
+		.name   = n,					\
+		.first	= f,					\
+		.last	= l,					\
+		.reg	= r,					\
+		.offset = o,					\
+	}
+
+struct meson_pmx_axg_data {
+	unsigned int func;
+};
+
+#define PMX_DATA(f)							\
+	{								\
+		.func = f,						\
+	}
+
+#define GROUP(grp, f)							\
+	{								\
+		.name = #grp,						\
+		.pins = grp ## _pins,                                   \
+		.num_pins = ARRAY_SIZE(grp ## _pins),			\
+		.data = (const struct meson_pmx_axg_data[]){		\
+			PMX_DATA(f),					\
+		},							\
+	}
+
+#define GPIO_GROUP(gpio, b)						\
+	{								\
+		.name = #gpio,						\
+		.pins = (const unsigned int[]){ PIN(gpio, b) },		\
+		.num_pins = 1,						\
+		.data = (const struct meson_pmx_axg_data[]){		\
+			PMX_DATA(0),					\
+		},							\
+	}
+
+extern const struct pinctrl_ops meson_axg_pinctrl_ops;
+extern const struct driver meson_axg_gpio_driver;
+
+#endif /* __PINCTRL_MESON_AXG_H__ */
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 11/19] clk: meson: add static to meson_gates table
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

The meson_gates table should be set static in the clk_meson driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/clk_meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index c44858822d..a096a3582c 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -79,7 +79,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
 
-struct meson_gate gates[] = {
+static struct meson_gate gates[] = {
 	/* Everything Else (EE) domain gates */
 	MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
 	MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 11/19] clk: meson: add static to meson_gates table
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

The meson_gates table should be set static in the clk_meson driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/clk_meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index c44858822d..a096a3582c 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -79,7 +79,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
 static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
 static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
 
-struct meson_gate gates[] = {
+static struct meson_gate gates[] = {
 	/* Everything Else (EE) domain gates */
 	MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
 	MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 12/19] clk: meson: silence debug print
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

This debug print was not designed to be active in non-debug mode.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/clk_meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index a096a3582c..f34f376057 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -791,7 +791,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 		return -ENOENT;
 	}
 
-	printf("clock %lu has rate %lu\n", id, rate);
+	debug("clock %lu has rate %lu\n", id, rate);
 	return rate;
 }
 
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 12/19] clk: meson: silence debug print
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

This debug print was not designed to be active in non-debug mode.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/clk_meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index a096a3582c..f34f376057 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -791,7 +791,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
 		return -ENOENT;
 	}
 
-	printf("clock %lu has rate %lu\n", id, rate);
+	debug("clock %lu has rate %lu\n", id, rate);
 	return rate;
 }
 
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 13/19] ARM: meson: rework soc arch file to prepare for new SoC
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../asm/arch-meson/{clock.h => clock-gx.h}    |   4 +-
 arch/arm/include/asm/arch-meson/eth.h         |   6 +-
 arch/arm/include/asm/arch-meson/mem.h         |   3 +-
 arch/arm/mach-meson/Kconfig                   |  10 +-
 arch/arm/mach-meson/Makefile                  |   3 +-
 arch/arm/mach-meson/board-common.c            |  55 +++++++++
 arch/arm/mach-meson/{board.c => board-gx.c}   | 106 +++++++++---------
 arch/arm/mach-meson/eth.c                     |  53 ---------
 arch/arm/mach-meson/sm.c                      |   1 -
 board/amlogic/odroid-c2/odroid-c2.c           |   6 +-
 board/amlogic/p212/p212.c                     |   6 +-
 board/amlogic/q200/q200.c                     |   4 +-
 drivers/clk/clk_meson.c                       |   2 +-
 13 files changed, 134 insertions(+), 125 deletions(-)
 rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
 create mode 100644 arch/arm/mach-meson/board-common.c
 rename arch/arm/mach-meson/{board.c => board-gx.c} (61%)
 delete mode 100644 arch/arm/mach-meson/eth.c

diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock-gx.h
similarity index 98%
rename from arch/arm/include/asm/arch-meson/clock.h
rename to arch/arm/include/asm/arch-meson/clock-gx.h
index c0ff00fc9a..13a2e7688f 100644
--- a/arch/arm/include/asm/arch-meson/clock.h
+++ b/arch/arm/include/asm/arch-meson/clock-gx.h
@@ -3,8 +3,8 @@
  * Copyright 2016 - AmLogic, Inc.
  * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  */
-#ifndef _ARCH_MESON_CLOCK_H_
-#define _ARCH_MESON_CLOCK_H_
+#ifndef _ARCH_MESON_CLOCK_GX_H_
+#define _ARCH_MESON_CLOCK_GX_H_
 
 /*
  * Clock controller register offsets
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index 1aa0872d53..08acc5cbf7 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -10,13 +10,13 @@
 #include <phy.h>
 
 enum {
-	/* Use GXL Internal RMII PHY */
-	MESON_GXL_USE_INTERNAL_RMII_PHY = 1,
+	/* Use Internal RMII PHY */
+	MESON_USE_INTERNAL_RMII_PHY = 1,
 };
 
 /* Configure the Ethernet MAC with the requested interface mode
  * with some optional flags.
  */
-void meson_gx_eth_init(phy_interface_t mode, unsigned int flags);
+void meson_eth_init(phy_interface_t mode, unsigned int flags);
 
 #endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h
index 62818335d9..a65100aeb7 100644
--- a/arch/arm/include/asm/arch-meson/mem.h
+++ b/arch/arm/include/asm/arch-meson/mem.h
@@ -10,6 +10,7 @@
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
-void meson_gx_init_reserved_memory(void *fdt);
+void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size);
+void meson_init_reserved_memory(void *fdt);
 
 #endif /* __MESON_MEM_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6f60167c8c..6225417a56 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,25 +8,29 @@ config MESON64_COMMON
 	select DM_SERIAL
 	imply CMD_DM
 
+config MESON_GX
+	bool
+	select MESON64_COMMON
+
 choice
 	prompt "Platform select"
 	default MESON_GXBB
 
 config MESON_GXBB
 	bool "GXBB"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S905
 
 config MESON_GXL
 	bool "GXL"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S905X/D or S805X
 
 config MESON_GXM
 	bool "GXM"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S912
 
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 8ad9b3e575..78345b47f2 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -2,4 +2,5 @@
 #
 # Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
 
-obj-y += board.o sm.o eth.o
+obj-y += board-common.o sm.o
+obj-$(CONFIG_MESON_GX) += board-gx.o
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
new file mode 100644
index 0000000000..6340445053
--- /dev/null
+++ b/arch/arm/mach-meson/board-common.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+#include <efi_loader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	const fdt64_t *val;
+	int offset;
+	int len;
+
+	offset = fdt_path_offset(gd->fdt_blob, "/memory");
+	if (offset < 0)
+		return -EINVAL;
+
+	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+	if (len < sizeof(*val) * 2)
+		return -EINVAL;
+
+	/* Use unaligned access since cache is still disabled */
+	gd->ram_size = get_unaligned_be64(&val[1]);
+
+	return 0;
+}
+
+void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
+{
+	int ret;
+
+	ret = fdt_add_mem_rsv(fdt, start, size);
+	if (ret)
+		printf("Could not reserve zone @ 0x%llx\n", start);
+
+	if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+		efi_add_memory_map(start,
+				   ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
+				   EFI_RESERVED_MEMORY_TYPE, false);
+	}
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board-gx.c
similarity index 61%
rename from arch/arm/mach-meson/board.c
rename to arch/arm/mach-meson/board-gx.c
index d6c6253152..f1397f87c5 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -1,64 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  */
 
 #include <common.h>
-#include <linux/libfdt.h>
-#include <linux/err.h>
+#include <asm/arch/eth.h>
 #include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
 #include <asm/armv8/mmu.h>
-#include <asm/unaligned.h>
 #include <linux/sizes.h>
-#include <efi_loader.h>
-#include <asm/io.h>
+#include <phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	const fdt64_t *val;
-	int offset;
-	int len;
-
-	offset = fdt_path_offset(gd->fdt_blob, "/memory");
-	if (offset < 0)
-		return -EINVAL;
-
-	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
-	if (len < sizeof(*val) * 2)
-		return -EINVAL;
-
-	/* Use unaligned access since cache is still disabled */
-	gd->ram_size = get_unaligned_be64(&val[1]);
-
-	return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
-	/* Size is reported in MiB, convert it in bytes */
-	return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
-			>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
-}
-
-static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
-{
-	int ret;
-
-	ret = fdt_add_mem_rsv(fdt, start, size);
-	if (ret)
-		printf("Could not reserve zone @ 0x%llx\n", start);
-
-	if (IS_ENABLED(CONFIG_EFI_LOADER)) {
-		efi_add_memory_map(start,
-				   ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
-				   EFI_RESERVED_MEMORY_TYPE, false);
-	}
-}
-
-void meson_gx_init_reserved_memory(void *fdt)
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_init_reserved_memory(void *fdt)
 {
 	u64 bl31_size, bl31_start;
 	u64 bl32_size, bl32_start;
@@ -70,7 +30,6 @@ void meson_gx_init_reserved_memory(void *fdt)
 	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
 	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
 	 */
-
 	reg = readl(GX_AO_SEC_GP_CFG3);
 
 	bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
@@ -102,9 +61,11 @@ void meson_gx_init_reserved_memory(void *fdt)
 		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
 }
 
-void reset_cpu(ulong addr)
+phys_size_t get_effective_memsize(void)
 {
-	psci_system_reset();
+	/* Size is reported in MiB, convert it in bytes */
+	return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
+			>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
 }
 
 static struct mm_region gx_mem_map[] = {
@@ -128,3 +89,44 @@ static struct mm_region gx_mem_map[] = {
 };
 
 struct mm_region *mem_map = gx_mem_map;
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags)
+{
+	switch (mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* Set RGMII mode */
+		setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+			     GX_ETH_REG_0_TX_PHASE(1) |
+			     GX_ETH_REG_0_TX_RATIO(4) |
+			     GX_ETH_REG_0_PHY_CLK_EN |
+			     GX_ETH_REG_0_CLK_EN);
+		break;
+
+	case PHY_INTERFACE_MODE_RMII:
+		/* Set RMII mode */
+		out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
+					 GX_ETH_REG_0_CLK_EN);
+
+		/* Use GXL RMII Internal PHY */
+		if (IS_ENABLED(CONFIG_MESON_GXL) &&
+		    (flags & MESON_USE_INTERNAL_RMII_PHY)) {
+			writel(0x10110181, GX_ETH_REG_2);
+			writel(0xe40908ff, GX_ETH_REG_3);
+		}
+
+		break;
+
+	default:
+		printf("Invalid Ethernet interface mode\n");
+		return;
+	}
+
+	/* Enable power gate */
+	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
+}
diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c
deleted file mode 100644
index 8b28bc8531..0000000000
--- a/arch/arm/mach-meson/eth.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/eth.h>
-#include <phy.h>
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
-{
-	switch (mode) {
-	case PHY_INTERFACE_MODE_RGMII:
-	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-		/* Set RGMII mode */
-		setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
-			     GX_ETH_REG_0_TX_PHASE(1) |
-			     GX_ETH_REG_0_TX_RATIO(4) |
-			     GX_ETH_REG_0_PHY_CLK_EN |
-			     GX_ETH_REG_0_CLK_EN);
-		break;
-
-	case PHY_INTERFACE_MODE_RMII:
-		/* Set RMII mode */
-		out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
-					 GX_ETH_REG_0_CLK_EN);
-
-		/* Use GXL RMII Internal PHY */
-		if (IS_ENABLED(CONFIG_MESON_GXL) &&
-		    (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
-			writel(0x10110181, GX_ETH_REG_2);
-			writel(0xe40908ff, GX_ETH_REG_3);
-		}
-
-		break;
-
-	default:
-		printf("Invalid Ethernet interface mode\n");
-		return;
-	}
-
-	/* Enable power gate */
-	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
-}
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 0bba5e4a07..a07b46895d 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,7 +6,6 @@
  */
 
 #include <common.h>
-#include <asm/arch/gx.h>
 #include <linux/kernel.h>
 
 #define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index 2a2755c387..d784d6bd09 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -28,7 +28,7 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@@ -40,7 +40,7 @@ int misc_init_r(void)
 	if (!env_get("serial#")) {
 		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
 			EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE) 
+		if (len == EFUSE_SN_SIZE)
 			env_set("serial#", serial);
 	}
 
@@ -49,7 +49,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 00e07d77ad..33992a2279 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -29,8 +29,8 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
+	meson_eth_init(PHY_INTERFACE_MODE_RMII,
+		       MESON_USE_INTERNAL_RMII_PHY);
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@@ -51,7 +51,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index ff56569f17..b59c11bd35 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -29,7 +29,7 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	/* Reset PHY on GPIOZ_14 */
 	clrbits_le32(GX_GPIO_EN(3), BIT(14));
@@ -56,7 +56,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index f34f376057..0df8b91d42 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/clock.h>
+#include <asm/arch/clock-gx.h>
 #include <asm/io.h>
 #include <clk-uclass.h>
 #include <div64.h>
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 13/19] ARM: meson: rework soc arch file to prepare for new SoC
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 .../asm/arch-meson/{clock.h => clock-gx.h}    |   4 +-
 arch/arm/include/asm/arch-meson/eth.h         |   6 +-
 arch/arm/include/asm/arch-meson/mem.h         |   3 +-
 arch/arm/mach-meson/Kconfig                   |  10 +-
 arch/arm/mach-meson/Makefile                  |   3 +-
 arch/arm/mach-meson/board-common.c            |  55 +++++++++
 arch/arm/mach-meson/{board.c => board-gx.c}   | 106 +++++++++---------
 arch/arm/mach-meson/eth.c                     |  53 ---------
 arch/arm/mach-meson/sm.c                      |   1 -
 board/amlogic/odroid-c2/odroid-c2.c           |   6 +-
 board/amlogic/p212/p212.c                     |   6 +-
 board/amlogic/q200/q200.c                     |   4 +-
 drivers/clk/clk_meson.c                       |   2 +-
 13 files changed, 134 insertions(+), 125 deletions(-)
 rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
 create mode 100644 arch/arm/mach-meson/board-common.c
 rename arch/arm/mach-meson/{board.c => board-gx.c} (61%)
 delete mode 100644 arch/arm/mach-meson/eth.c

diff --git a/arch/arm/include/asm/arch-meson/clock.h b/arch/arm/include/asm/arch-meson/clock-gx.h
similarity index 98%
rename from arch/arm/include/asm/arch-meson/clock.h
rename to arch/arm/include/asm/arch-meson/clock-gx.h
index c0ff00fc9a..13a2e7688f 100644
--- a/arch/arm/include/asm/arch-meson/clock.h
+++ b/arch/arm/include/asm/arch-meson/clock-gx.h
@@ -3,8 +3,8 @@
  * Copyright 2016 - AmLogic, Inc.
  * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
  */
-#ifndef _ARCH_MESON_CLOCK_H_
-#define _ARCH_MESON_CLOCK_H_
+#ifndef _ARCH_MESON_CLOCK_GX_H_
+#define _ARCH_MESON_CLOCK_GX_H_
 
 /*
  * Clock controller register offsets
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index 1aa0872d53..08acc5cbf7 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -10,13 +10,13 @@
 #include <phy.h>
 
 enum {
-	/* Use GXL Internal RMII PHY */
-	MESON_GXL_USE_INTERNAL_RMII_PHY = 1,
+	/* Use Internal RMII PHY */
+	MESON_USE_INTERNAL_RMII_PHY = 1,
 };
 
 /* Configure the Ethernet MAC with the requested interface mode
  * with some optional flags.
  */
-void meson_gx_eth_init(phy_interface_t mode, unsigned int flags);
+void meson_eth_init(phy_interface_t mode, unsigned int flags);
 
 #endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h
index 62818335d9..a65100aeb7 100644
--- a/arch/arm/include/asm/arch-meson/mem.h
+++ b/arch/arm/include/asm/arch-meson/mem.h
@@ -10,6 +10,7 @@
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
-void meson_gx_init_reserved_memory(void *fdt);
+void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size);
+void meson_init_reserved_memory(void *fdt);
 
 #endif /* __MESON_MEM_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6f60167c8c..6225417a56 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,25 +8,29 @@ config MESON64_COMMON
 	select DM_SERIAL
 	imply CMD_DM
 
+config MESON_GX
+	bool
+	select MESON64_COMMON
+
 choice
 	prompt "Platform select"
 	default MESON_GXBB
 
 config MESON_GXBB
 	bool "GXBB"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S905
 
 config MESON_GXL
 	bool "GXL"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S905X/D or S805X
 
 config MESON_GXM
 	bool "GXM"
-	select MESON64_COMMON
+	select MESON_GX
 	help
 	  Select this if your SoC is an S912
 
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 8ad9b3e575..78345b47f2 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -2,4 +2,5 @@
 #
 # Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
 
-obj-y += board.o sm.o eth.o
+obj-y += board-common.o sm.o
+obj-$(CONFIG_MESON_GX) += board-gx.o
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
new file mode 100644
index 0000000000..6340445053
--- /dev/null
+++ b/arch/arm/mach-meson/board-common.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+#include <efi_loader.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	const fdt64_t *val;
+	int offset;
+	int len;
+
+	offset = fdt_path_offset(gd->fdt_blob, "/memory");
+	if (offset < 0)
+		return -EINVAL;
+
+	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+	if (len < sizeof(*val) * 2)
+		return -EINVAL;
+
+	/* Use unaligned access since cache is still disabled */
+	gd->ram_size = get_unaligned_be64(&val[1]);
+
+	return 0;
+}
+
+void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
+{
+	int ret;
+
+	ret = fdt_add_mem_rsv(fdt, start, size);
+	if (ret)
+		printf("Could not reserve zone @ 0x%llx\n", start);
+
+	if (IS_ENABLED(CONFIG_EFI_LOADER)) {
+		efi_add_memory_map(start,
+				   ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
+				   EFI_RESERVED_MEMORY_TYPE, false);
+	}
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board-gx.c
similarity index 61%
rename from arch/arm/mach-meson/board.c
rename to arch/arm/mach-meson/board-gx.c
index d6c6253152..f1397f87c5 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -1,64 +1,24 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  */
 
 #include <common.h>
-#include <linux/libfdt.h>
-#include <linux/err.h>
+#include <asm/arch/eth.h>
 #include <asm/arch/gx.h>
-#include <asm/arch/sm.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
 #include <asm/armv8/mmu.h>
-#include <asm/unaligned.h>
 #include <linux/sizes.h>
-#include <efi_loader.h>
-#include <asm/io.h>
+#include <phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int dram_init(void)
-{
-	const fdt64_t *val;
-	int offset;
-	int len;
-
-	offset = fdt_path_offset(gd->fdt_blob, "/memory");
-	if (offset < 0)
-		return -EINVAL;
-
-	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
-	if (len < sizeof(*val) * 2)
-		return -EINVAL;
-
-	/* Use unaligned access since cache is still disabled */
-	gd->ram_size = get_unaligned_be64(&val[1]);
-
-	return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
-	/* Size is reported in MiB, convert it in bytes */
-	return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
-			>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
-}
-
-static void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
-{
-	int ret;
-
-	ret = fdt_add_mem_rsv(fdt, start, size);
-	if (ret)
-		printf("Could not reserve zone @ 0x%llx\n", start);
-
-	if (IS_ENABLED(CONFIG_EFI_LOADER)) {
-		efi_add_memory_map(start,
-				   ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
-				   EFI_RESERVED_MEMORY_TYPE, false);
-	}
-}
-
-void meson_gx_init_reserved_memory(void *fdt)
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_init_reserved_memory(void *fdt)
 {
 	u64 bl31_size, bl31_start;
 	u64 bl32_size, bl32_start;
@@ -70,7 +30,6 @@ void meson_gx_init_reserved_memory(void *fdt)
 	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
 	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
 	 */
-
 	reg = readl(GX_AO_SEC_GP_CFG3);
 
 	bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
@@ -102,9 +61,11 @@ void meson_gx_init_reserved_memory(void *fdt)
 		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
 }
 
-void reset_cpu(ulong addr)
+phys_size_t get_effective_memsize(void)
 {
-	psci_system_reset();
+	/* Size is reported in MiB, convert it in bytes */
+	return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
+			>> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
 }
 
 static struct mm_region gx_mem_map[] = {
@@ -128,3 +89,44 @@ static struct mm_region gx_mem_map[] = {
 };
 
 struct mm_region *mem_map = gx_mem_map;
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags)
+{
+	switch (mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* Set RGMII mode */
+		setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+			     GX_ETH_REG_0_TX_PHASE(1) |
+			     GX_ETH_REG_0_TX_RATIO(4) |
+			     GX_ETH_REG_0_PHY_CLK_EN |
+			     GX_ETH_REG_0_CLK_EN);
+		break;
+
+	case PHY_INTERFACE_MODE_RMII:
+		/* Set RMII mode */
+		out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
+					 GX_ETH_REG_0_CLK_EN);
+
+		/* Use GXL RMII Internal PHY */
+		if (IS_ENABLED(CONFIG_MESON_GXL) &&
+		    (flags & MESON_USE_INTERNAL_RMII_PHY)) {
+			writel(0x10110181, GX_ETH_REG_2);
+			writel(0xe40908ff, GX_ETH_REG_3);
+		}
+
+		break;
+
+	default:
+		printf("Invalid Ethernet interface mode\n");
+		return;
+	}
+
+	/* Enable power gate */
+	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
+}
diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c
deleted file mode 100644
index 8b28bc8531..0000000000
--- a/arch/arm/mach-meson/eth.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/gx.h>
-#include <asm/arch/eth.h>
-#include <phy.h>
-
-/* Configure the Ethernet MAC with the requested interface mode
- * with some optional flags.
- */
-void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
-{
-	switch (mode) {
-	case PHY_INTERFACE_MODE_RGMII:
-	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-		/* Set RGMII mode */
-		setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
-			     GX_ETH_REG_0_TX_PHASE(1) |
-			     GX_ETH_REG_0_TX_RATIO(4) |
-			     GX_ETH_REG_0_PHY_CLK_EN |
-			     GX_ETH_REG_0_CLK_EN);
-		break;
-
-	case PHY_INTERFACE_MODE_RMII:
-		/* Set RMII mode */
-		out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
-					 GX_ETH_REG_0_CLK_EN);
-
-		/* Use GXL RMII Internal PHY */
-		if (IS_ENABLED(CONFIG_MESON_GXL) &&
-		    (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) {
-			writel(0x10110181, GX_ETH_REG_2);
-			writel(0xe40908ff, GX_ETH_REG_3);
-		}
-
-		break;
-
-	default:
-		printf("Invalid Ethernet interface mode\n");
-		return;
-	}
-
-	/* Enable power gate */
-	clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
-}
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 0bba5e4a07..a07b46895d 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,7 +6,6 @@
  */
 
 #include <common.h>
-#include <asm/arch/gx.h>
 #include <linux/kernel.h>
 
 #define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index 2a2755c387..d784d6bd09 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -28,7 +28,7 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@@ -40,7 +40,7 @@ int misc_init_r(void)
 	if (!env_get("serial#")) {
 		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
 			EFUSE_SN_SIZE);
-		if (len == EFUSE_SN_SIZE) 
+		if (len == EFUSE_SN_SIZE)
 			env_set("serial#", serial);
 	}
 
@@ -49,7 +49,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 00e07d77ad..33992a2279 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -29,8 +29,8 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RMII,
-			  MESON_GXL_USE_INTERNAL_RMII_PHY);
+	meson_eth_init(PHY_INTERFACE_MODE_RMII,
+		       MESON_USE_INTERNAL_RMII_PHY);
 
 	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
@@ -51,7 +51,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index ff56569f17..b59c11bd35 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -29,7 +29,7 @@ int misc_init_r(void)
 	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
-	meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	/* Reset PHY on GPIOZ_14 */
 	clrbits_le32(GX_GPIO_EN(3), BIT(14));
@@ -56,7 +56,7 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	meson_gx_init_reserved_memory(blob);
+	meson_init_reserved_memory(blob);
 
 	return 0;
 }
diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c
index f34f376057..0df8b91d42 100644
--- a/drivers/clk/clk_meson.c
+++ b/drivers/clk/clk_meson.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/clock.h>
+#include <asm/arch/clock-gx.h>
 #include <asm/io.h>
 #include <clk-uclass.h>
 #include <div64.h>
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 14/19] ARM: meson: Add support for AXG family
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/axg.h |  51 ++++++++++++
 arch/arm/mach-meson/Kconfig           |   8 ++
 arch/arm/mach-meson/Makefile          |   1 +
 arch/arm/mach-meson/board-axg.c       | 112 ++++++++++++++++++++++++++
 include/configs/meson64.h             |   5 ++
 5 files changed, 177 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-meson/axg.h
 create mode 100644 arch/arm/mach-meson/board-axg.c

diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
new file mode 100644
index 0000000000..28a38b791d
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __AXG_H__
+#define __AXG_H__
+
+#define AXG_AOBUS_BASE		0xff800000
+#define AXG_PERIPHS_BASE	0xff634400
+#define AXG_HIU_BASE		0xff63c000
+#define AXG_ETH_BASE		0xff3f0000
+
+/* Always-On Peripherals registers */
+#define AXG_AO_ADDR(off)	(AXG_AOBUS_BASE + ((off) << 2))
+
+#define AXG_AO_SEC_GP_CFG0	AXG_AO_ADDR(0x90)
+#define AXG_AO_SEC_GP_CFG3	AXG_AO_ADDR(0x93)
+#define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
+#define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
+
+#define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_MEM_SIZE_SHIFT	16
+#define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define AXG_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define AXG_PERIPHS_ADDR(off)	(AXG_PERIPHS_BASE + ((off) << 2))
+
+#define AXG_ETH_REG_0		AXG_PERIPHS_ADDR(0x50)
+#define AXG_ETH_REG_1		AXG_PERIPHS_ADDR(0x51)
+
+#define AXG_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
+#define AXG_ETH_REG_0_PHY_INTF_RMII	BIT(2)
+#define AXG_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define AXG_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define AXG_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define AXG_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define AXG_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define AXG_HIU_ADDR(off)	(AXG_HIU_BASE + ((off) << 2))
+
+#define AXG_MEM_PD_REG_0	AXG_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define AXG_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+#endif /* __AXG_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6225417a56..7f217facd1 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -6,6 +6,8 @@ config MESON64_COMMON
 	select CLK
 	select DM
 	select DM_SERIAL
+	select SYSCON
+	select REGMAP
 	imply CMD_DM
 
 config MESON_GX
@@ -34,6 +36,12 @@ config MESON_GXM
 	help
 	  Select this if your SoC is an S912
 
+config MESON_AXG
+	bool "AXG"
+	select MESON64_COMMON
+	help
+		Select this if your SoC is an A113X/D
+
 endchoice
 
 config SYS_SOC
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 78345b47f2..b716e1a152 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += board-common.o sm.o
 obj-$(CONFIG_MESON_GX) += board-gx.o
+obj-$(CONFIG_MESON_AXG) += board-axg.o
diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c
new file mode 100644
index 0000000000..014b25d61a
--- /dev/null
+++ b/arch/arm/mach-meson/board-axg.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_init_reserved_memory(void *fdt)
+{
+	u64 bl31_size, bl31_start;
+	u64 bl32_size, bl32_start;
+	u32 reg;
+
+	/*
+	 * Get ARM Trusted Firmware reserved memory zones in :
+	 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+	 */
+	reg = readl(AXG_AO_SEC_GP_CFG3);
+
+	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
+			>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
+	bl32_start = readl(AXG_AO_SEC_GP_CFG4);
+
+	/* Add BL31 reserved zone */
+	if (bl31_start && bl31_size)
+		meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
+
+	/* Add BL32 reserved zone */
+	if (bl32_start && bl32_size)
+		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	/* Size is reported in MiB, convert it in bytes */
+	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
+			>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+static struct mm_region axg_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = axg_mem_map;
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags)
+{
+	switch (mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* Set RGMII mode */
+		setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+			     AXG_ETH_REG_0_TX_PHASE(1) |
+			     AXG_ETH_REG_0_TX_RATIO(4) |
+			     AXG_ETH_REG_0_PHY_CLK_EN |
+			     AXG_ETH_REG_0_CLK_EN);
+		break;
+
+	case PHY_INTERFACE_MODE_RMII:
+		/* Set RMII mode */
+		out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
+					AXG_ETH_REG_0_INVERT_RMII_CLK |
+					AXG_ETH_REG_0_CLK_EN);
+		break;
+
+	default:
+		printf("Invalid Ethernet interface mode\n");
+		return;
+	}
+
+	/* Enable power gate */
+	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
+}
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 80c883e3f4..f961f43871 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -8,8 +8,13 @@
 #define __MESON64_CONFIG_H
 
 /* Generic Interrupt Controller Definitions */
+#if defined(CONFIG_MESON_AXG)
+#define GICD_BASE			0xffc01000
+#define GICC_BASE			0xffc02000
+#else /* MESON GXL and GXBB */
 #define GICD_BASE			0xc4301000
 #define GICC_BASE			0xc4302000
+#endif
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 14/19] ARM: meson: Add support for AXG family
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/axg.h |  51 ++++++++++++
 arch/arm/mach-meson/Kconfig           |   8 ++
 arch/arm/mach-meson/Makefile          |   1 +
 arch/arm/mach-meson/board-axg.c       | 112 ++++++++++++++++++++++++++
 include/configs/meson64.h             |   5 ++
 5 files changed, 177 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-meson/axg.h
 create mode 100644 arch/arm/mach-meson/board-axg.c

diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
new file mode 100644
index 0000000000..28a38b791d
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __AXG_H__
+#define __AXG_H__
+
+#define AXG_AOBUS_BASE		0xff800000
+#define AXG_PERIPHS_BASE	0xff634400
+#define AXG_HIU_BASE		0xff63c000
+#define AXG_ETH_BASE		0xff3f0000
+
+/* Always-On Peripherals registers */
+#define AXG_AO_ADDR(off)	(AXG_AOBUS_BASE + ((off) << 2))
+
+#define AXG_AO_SEC_GP_CFG0	AXG_AO_ADDR(0x90)
+#define AXG_AO_SEC_GP_CFG3	AXG_AO_ADDR(0x93)
+#define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
+#define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
+
+#define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_MEM_SIZE_SHIFT	16
+#define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define AXG_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define AXG_PERIPHS_ADDR(off)	(AXG_PERIPHS_BASE + ((off) << 2))
+
+#define AXG_ETH_REG_0		AXG_PERIPHS_ADDR(0x50)
+#define AXG_ETH_REG_1		AXG_PERIPHS_ADDR(0x51)
+
+#define AXG_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
+#define AXG_ETH_REG_0_PHY_INTF_RMII	BIT(2)
+#define AXG_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define AXG_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define AXG_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define AXG_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define AXG_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define AXG_HIU_ADDR(off)	(AXG_HIU_BASE + ((off) << 2))
+
+#define AXG_MEM_PD_REG_0	AXG_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define AXG_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+#endif /* __AXG_H__ */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 6225417a56..7f217facd1 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -6,6 +6,8 @@ config MESON64_COMMON
 	select CLK
 	select DM
 	select DM_SERIAL
+	select SYSCON
+	select REGMAP
 	imply CMD_DM
 
 config MESON_GX
@@ -34,6 +36,12 @@ config MESON_GXM
 	help
 	  Select this if your SoC is an S912
 
+config MESON_AXG
+	bool "AXG"
+	select MESON64_COMMON
+	help
+		Select this if your SoC is an A113X/D
+
 endchoice
 
 config SYS_SOC
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index 78345b47f2..b716e1a152 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += board-common.o sm.o
 obj-$(CONFIG_MESON_GX) += board-gx.o
+obj-$(CONFIG_MESON_AXG) += board-axg.o
diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c
new file mode 100644
index 0000000000..014b25d61a
--- /dev/null
+++ b/arch/arm/mach-meson/board-axg.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_init_reserved_memory(void *fdt)
+{
+	u64 bl31_size, bl31_start;
+	u64 bl32_size, bl32_start;
+	u32 reg;
+
+	/*
+	 * Get ARM Trusted Firmware reserved memory zones in :
+	 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+	 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+	 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+	 */
+	reg = readl(AXG_AO_SEC_GP_CFG3);
+
+	bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
+			>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+	bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+	bl31_start = readl(AXG_AO_SEC_GP_CFG5);
+	bl32_start = readl(AXG_AO_SEC_GP_CFG4);
+
+	/* Add BL31 reserved zone */
+	if (bl31_start && bl31_size)
+		meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
+
+	/* Add BL32 reserved zone */
+	if (bl32_start && bl32_size)
+		meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	/* Size is reported in MiB, convert it in bytes */
+	return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
+			>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+static struct mm_region axg_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xf0000000UL,
+		.phys = 0xf0000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = axg_mem_map;
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags)
+{
+	switch (mode) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* Set RGMII mode */
+		setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+			     AXG_ETH_REG_0_TX_PHASE(1) |
+			     AXG_ETH_REG_0_TX_RATIO(4) |
+			     AXG_ETH_REG_0_PHY_CLK_EN |
+			     AXG_ETH_REG_0_CLK_EN);
+		break;
+
+	case PHY_INTERFACE_MODE_RMII:
+		/* Set RMII mode */
+		out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
+					AXG_ETH_REG_0_INVERT_RMII_CLK |
+					AXG_ETH_REG_0_CLK_EN);
+		break;
+
+	default:
+		printf("Invalid Ethernet interface mode\n");
+		return;
+	}
+
+	/* Enable power gate */
+	clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
+}
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 80c883e3f4..f961f43871 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -8,8 +8,13 @@
 #define __MESON64_CONFIG_H
 
 /* Generic Interrupt Controller Definitions */
+#if defined(CONFIG_MESON_AXG)
+#define GICD_BASE			0xffc01000
+#define GICC_BASE			0xffc02000
+#else /* MESON GXL and GXBB */
 #define GICD_BASE			0xc4301000
 #define GICC_BASE			0xc4302000
+#endif
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 15/19] ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

Synchronize the Amlogic AXG Device Tree files and bindings include from
the recent Linux 4.20-rc1, because it includes patches fixing support for
U-boot.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/dts/Makefile                         |    3 +-
 arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
 arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
 include/dt-bindings/clock/axg-aoclkc.h        |   26 +
 include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
 include/dt-bindings/clock/axg-clkc.h          |   76 +
 include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
 .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
 .../reset/amlogic,meson-axg-reset.h           |  124 ++
 include/dt-bindings/reset/axg-aoclkc.h        |   20 +
 10 files changed, 2618 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/meson-axg-s400.dts
 create mode 100644 arch/arm/dts/meson-axg.dtsi
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
 create mode 100644 include/dt-bindings/clock/axg-clkc.h
 create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 84b7e5335c..1fa2f2d8dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxl-s905x-p212.dtb \
 	meson-gxl-s905x-libretech-cc.dtb \
 	meson-gxl-s905x-khadas-vim.dtb \
-	meson-gxm-khadas-vim2.dtb
+	meson-gxm-khadas-vim2.dtb \
+	meson-axg-s400.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
new file mode 100644
index 0000000000..18778ada7b
--- /dev/null
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -0,0 +1,554 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-axg.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
+	model = "Amlogic Meson AXG S400 Development Board";
+
+	adc_keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+
+		button-next {
+			label = "Next";
+			linux,code = <KEY_NEXT>;
+			press-threshold-microvolt = <1116000>; /* 62% */
+		};
+
+		button-prev {
+			label = "Previous";
+			linux,code = <KEY_PREVIOUS>;
+			press-threshold-microvolt = <900000>; /* 50% */
+		};
+
+		button-wifi {
+			label = "Wifi";
+			linux,code = <KEY_WLAN>;
+			press-threshold-microvolt = <684000>; /* 38% */
+		};
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <468000>; /* 26% */
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <252000>; /* 14% */
+		};
+
+		button-voice {
+			label = "Voice";
+			linux,code = <KEY_VOICECOMMAND>;
+			press-threshold-microvolt = <0>; /* 0% */
+		};
+	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+	};
+
+	linein: audio-codec at 0 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es7241";
+		VDDA-supply = <&vcc_3v3>;
+		VDDP-supply = <&vcc_3v3>;
+		VDDD-supply = <&vcc_3v3>;
+		status = "okay";
+		sound-name-prefix = "Linein";
+	};
+
+	lineout: audio-codec at 1 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es7154";
+		VDD-supply = <&vcc_3v3>;
+		PVDD-supply = <&vcc_5v>;
+		status = "okay";
+		sound-name-prefix = "Lineout";
+	};
+
+	spdif_dit: audio-codec at 2 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	dmics: audio-codec at 3 {
+		#sound-dai-cells = <0>;
+		compatible = "dmic-codec";
+		num-channels = <7>;
+		wakeup-delay-ms = <50>;
+		status = "okay";
+		sound-name-prefix = "MIC";
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	main_12v: regulator-main_12v {
+		compatible = "regulator-fixed";
+		regulator-name = "12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vcc_5v: regulator-vcc_5v {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&main_12v>;
+
+		gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&main_12v>;
+		regulator-always-on;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	usb_pwr: regulator-usb_pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "USB_PWR";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v>;
+
+		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	speaker-leds {
+		compatible = "gpio-leds";
+
+		aled1 {
+			label = "speaker:aled1";
+			gpios = <&gpio_speaker 7 0>;
+		};
+
+		aled2 {
+			label = "speaker:aled2";
+			gpios = <&gpio_speaker 6 0>;
+		};
+
+		aled3 {
+			label = "speaker:aled3";
+			gpios = <&gpio_speaker 5 0>;
+		};
+
+		aled4 {
+			label = "speaker:aled4";
+			gpios = <&gpio_speaker 4 0>;
+		};
+
+		aled5 {
+			label = "speaker:aled5";
+			gpios = <&gpio_speaker 3 0>;
+		};
+
+		aled6 {
+			label = "speaker:aled6";
+			gpios = <&gpio_speaker 2 0>;
+		};
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "AXG-S400";
+		audio-aux-devs = <&tdmin_a>, <&tdmin_b>,  <&tdmin_c>,
+				 <&tdmin_lb>, <&tdmout_c>;
+		audio-widgets = "Line", "Lineout",
+				"Line", "Linein",
+				"Speaker", "Speaker1 Left",
+				"Speaker", "Speaker1 Right";
+		audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+				"SPDIFOUT IN 0", "FRDDR_A OUT 3",
+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
+				"SPDIFOUT IN 1", "FRDDR_B OUT 3",
+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
+				"SPDIFOUT IN 2", "FRDDR_C OUT 3",
+				"TDM_C Playback", "TDMOUT_C OUT",
+				"TDMIN_A IN 2", "TDM_C Capture",
+				"TDMIN_A IN 5", "TDM_C Loopback",
+				"TDMIN_B IN 2", "TDM_C Capture",
+				"TDMIN_B IN 5", "TDM_C Loopback",
+				"TDMIN_C IN 2", "TDM_C Capture",
+				"TDMIN_C IN 5", "TDM_C Loopback",
+				"TDMIN_LB IN 2", "TDM_C Loopback",
+				"TDMIN_LB IN 5", "TDM_C Capture",
+				"TODDR_A IN 0", "TDMIN_A OUT",
+				"TODDR_B IN 0", "TDMIN_A OUT",
+				"TODDR_C IN 0", "TDMIN_A OUT",
+				"TODDR_A IN 1", "TDMIN_B OUT",
+				"TODDR_B IN 1", "TDMIN_B OUT",
+				"TODDR_C IN 1", "TDMIN_B OUT",
+				"TODDR_A IN 2", "TDMIN_C OUT",
+				"TODDR_B IN 2", "TDMIN_C OUT",
+				"TODDR_C IN 2", "TDMIN_C OUT",
+				"TODDR_A IN 4", "PDM Capture",
+				"TODDR_B IN 4", "PDM Capture",
+				"TODDR_C IN 4", "PDM Capture",
+				"TODDR_A IN 6", "TDMIN_LB OUT",
+				"TODDR_B IN 6", "TDMIN_LB OUT",
+				"TODDR_C IN 6", "TDMIN_LB OUT",
+				"Lineout", "Lineout AOUTL",
+				"Lineout", "Lineout AOUTR",
+				"Speaker1 Left", "SPK1 OUT_A",
+				"Speaker1 Left", "SPK1 OUT_B",
+				"Speaker1 Right", "SPK1 OUT_C",
+				"Speaker1 Right", "SPK1 OUT_D",
+				"Linein AINL", "Linein",
+				"Linein AINR", "Linein";
+		assigned-clocks = <&clkc CLKID_HIFI_PLL>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <589824000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link at 0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link at 1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link at 2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		dai-link at 3 {
+			sound-dai = <&toddr_a>;
+		};
+
+		dai-link at 4 {
+			sound-dai = <&toddr_b>;
+		};
+
+		dai-link at 5 {
+			sound-dai = <&toddr_c>;
+		};
+
+		dai-link at 6 {
+			sound-dai = <&tdmif_c>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-rx-mask-1 = <1 1>;
+			mclk-fs = <256>;
+
+			codec at 0 {
+				sound-dai = <&lineout>;
+			};
+
+			codec at 1 {
+				sound-dai = <&speaker_amp1>;
+			};
+
+			codec at 2 {
+				sound-dai = <&linein>;
+			};
+
+		};
+
+		dai-link at 7 {
+			sound-dai = <&spdifout>;
+
+			codec {
+				sound-dai = <&spdif_dit>;
+			};
+		};
+
+		dai-link at 8 {
+			sound-dai = <&pdm>;
+
+			codec {
+				sound-dai = <&dmics>;
+			};
+		};
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+	};
+};
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_rgmii_y_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&eth_phy0>;
+	phy-mode = "rgmii";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy0: ethernet-phy at 0 {
+			/* Realtek RTL8211F (0x001cc916) */
+			reg = <0>;
+			eee-broken-1000t;
+		};
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	status = "okay";
+	pinctrl-0 = <&remote_input_ao_pins>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_z_pins>;
+	pinctrl-names = "default";
+
+	speaker_amp1: audio-codec at 1b {
+		compatible = "ti,tas5707";
+		reg = <0x1b>;
+		reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		AVDD-supply = <&vcc_3v3>;
+		DVDD-supply = <&vcc_3v3>;
+		PVDD_A-supply = <&main_12v>;
+		PVDD_B-supply = <&main_12v>;
+		PVDD_C-supply = <&main_12v>;
+		PVDD_D-supply = <&main_12v>;
+		sound-name-prefix = "SPK1";
+	};
+};
+
+&i2c_AO {
+	status = "okay";
+	pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
+	pinctrl-names = "default";
+
+	gpio_speaker: gpio-controller at 1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&vddao_3v3>;
+	};
+};
+
+&pdm {
+	pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
+		    <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_x20_pins>;
+	pinctrl-names = "default";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vddio_ao18>;
+};
+
+/* wifi module */
+&sd_emmc_b {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+	non-removable;
+	disable-wp;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+
+	brcmf: wifi at 1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* emmc storage */
+&sd_emmc_c {
+	status = "disabled";
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	max-frequency = <180000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+&spdifout {
+	pinctrl-0 = <&spdif_out_a20_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_a {
+	pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
+		    <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_b {
+	pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
+		    <&tdmb_din3_pins>, <&mclk_b_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_c {
+	pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
+		    <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
+		    <&mclk_c_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmin_a {
+	status = "okay";
+};
+
+&tdmin_b {
+	status = "okay";
+};
+
+&tdmin_c {
+	status = "okay";
+};
+
+&tdmin_lb {
+	status = "okay";
+};
+
+&tdmout_c {
+	status = "okay";
+};
+
+&toddr_a {
+	status = "okay";
+};
+
+&toddr_b {
+	status = "okay";
+};
+
+&toddr_c {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
new file mode 100644
index 0000000000..df017dbd2e
--- /dev/null
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -0,0 +1,1589 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/clock/axg-audio-clkc.h>
+#include <dt-bindings/clock/axg-clkc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
+#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+
+/ {
+	compatible = "amlogic,meson-axg";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	tdmif_a: audio-controller at 0 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_A";
+		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	tdmif_b: audio-controller at 1 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_B";
+		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	tdmif_c: audio-controller at 2 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_C";
+		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	ao_alt_xtal: ao_alt_xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <32000000>;
+		clock-output-names = "ao_alt_xtal";
+		#clock-cells = <0>;
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 16 MiB reserved for Hardware ROM Firmware */
+		hwrom_reserved: hwrom at 0 {
+			reg = <0x0 0x0 0x0 0x1000000>;
+			no-map;
+		};
+
+		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon at 5000000 {
+			reg = <0x0 0x05000000 0x0 0x300000>;
+			no-map;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ethmac: ethernet at ff3f0000 {
+			compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
+			reg = <0x0 0xff3f0000 0x0 0x10000
+			       0x0 0xff634540 0x0 0x8>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "macirq";
+			clocks = <&clkc CLKID_ETH>,
+				 <&clkc CLKID_FCLK_DIV2>,
+				 <&clkc CLKID_MPLL2>;
+			clock-names = "stmmaceth", "clkin0", "clkin1";
+			status = "disabled";
+		};
+
+		pdm: audio-controller at ff632000 {
+			compatible = "amlogic,axg-pdm";
+			reg = <0x0 0xff632000 0x0 0x34>;
+			#sound-dai-cells = <0>;
+			sound-name-prefix = "PDM";
+			clocks = <&clkc_audio AUD_CLKID_PDM>,
+				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
+				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+			clock-names = "pclk", "dclk", "sysclk";
+			status = "disabled";
+		};
+
+		periphs: bus at ff634000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff634000 0x0 0x2000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+			hwrng: rng at 18 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x0 0x18 0x0 0x4>;
+				clocks = <&clkc CLKID_RNG0>;
+				clock-names = "core";
+			};
+
+			pinctrl_periphs: pinctrl at 480 {
+				compatible = "amlogic,meson-axg-periphs-pinctrl";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges;
+
+				gpio: bank at 480 {
+					reg = <0x0 0x00480 0x0 0x40>,
+					      <0x0 0x004e8 0x0 0x14>,
+					      <0x0 0x00520 0x0 0x14>,
+					      <0x0 0x00430 0x0 0x3c>;
+					reg-names = "mux", "pull", "pull-enable", "gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&pinctrl_periphs 0 0 86>;
+				};
+
+				i2c0_pins: i2c0 {
+					mux {
+						groups = "i2c0_sck",
+							 "i2c0_sda";
+						function = "i2c0";
+					};
+				};
+
+				i2c1_x_pins: i2c1_x {
+					mux {
+						groups = "i2c1_sck_x",
+							 "i2c1_sda_x";
+						function = "i2c1";
+					};
+				};
+
+				i2c1_z_pins: i2c1_z {
+					mux {
+						groups = "i2c1_sck_z",
+							 "i2c1_sda_z";
+						function = "i2c1";
+					};
+				};
+
+				i2c2_a_pins: i2c2_a {
+					mux {
+						groups = "i2c2_sck_a",
+							 "i2c2_sda_a";
+						function = "i2c2";
+					};
+				};
+
+				i2c2_x_pins: i2c2_x {
+					mux {
+						groups = "i2c2_sck_x",
+							 "i2c2_sda_x";
+						function = "i2c2";
+					};
+				};
+
+				i2c3_a6_pins: i2c3_a6 {
+					mux {
+						groups = "i2c3_sda_a6",
+							 "i2c3_sck_a7";
+						function = "i2c3";
+					};
+				};
+
+				i2c3_a12_pins: i2c3_a12 {
+					mux {
+						groups = "i2c3_sda_a12",
+							 "i2c3_sck_a13";
+						function = "i2c3";
+					};
+				};
+
+				i2c3_a19_pins: i2c3_a19 {
+					mux {
+						groups = "i2c3_sda_a19",
+							 "i2c3_sck_a20";
+						function = "i2c3";
+					};
+				};
+
+				emmc_pins: emmc {
+					mux {
+						groups = "emmc_nand_d0",
+							 "emmc_nand_d1",
+							 "emmc_nand_d2",
+							 "emmc_nand_d3",
+							 "emmc_nand_d4",
+							 "emmc_nand_d5",
+							 "emmc_nand_d6",
+							 "emmc_nand_d7",
+							 "emmc_clk",
+							 "emmc_cmd",
+							 "emmc_ds";
+						function = "emmc";
+					};
+				};
+
+				emmc_clk_gate_pins: emmc_clk_gate {
+					mux {
+						groups = "BOOT_8";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "BOOT_8";
+						bias-pull-down;
+					};
+				};
+
+				eth_rgmii_x_pins: eth-x-rgmii {
+					mux {
+						groups = "eth_mdio_x",
+							 "eth_mdc_x",
+							 "eth_rgmii_rx_clk_x",
+							 "eth_rx_dv_x",
+							 "eth_rxd0_x",
+							 "eth_rxd1_x",
+							 "eth_rxd2_rgmii",
+							 "eth_rxd3_rgmii",
+							 "eth_rgmii_tx_clk",
+							 "eth_txen_x",
+							 "eth_txd0_x",
+							 "eth_txd1_x",
+							 "eth_txd2_rgmii",
+							 "eth_txd3_rgmii";
+						function = "eth";
+					};
+				};
+
+				eth_rgmii_y_pins: eth-y-rgmii {
+					mux {
+						groups = "eth_mdio_y",
+							 "eth_mdc_y",
+							 "eth_rgmii_rx_clk_y",
+							 "eth_rx_dv_y",
+							 "eth_rxd0_y",
+							 "eth_rxd1_y",
+							 "eth_rxd2_rgmii",
+							 "eth_rxd3_rgmii",
+							 "eth_rgmii_tx_clk",
+							 "eth_txen_y",
+							 "eth_txd0_y",
+							 "eth_txd1_y",
+							 "eth_txd2_rgmii",
+							 "eth_txd3_rgmii";
+						function = "eth";
+					};
+				};
+
+				eth_rmii_x_pins: eth-x-rmii {
+					mux {
+						groups = "eth_mdio_x",
+							 "eth_mdc_x",
+							 "eth_rgmii_rx_clk_x",
+							 "eth_rx_dv_x",
+							 "eth_rxd0_x",
+							 "eth_rxd1_x",
+							 "eth_txen_x",
+							 "eth_txd0_x",
+							 "eth_txd1_x";
+						function = "eth";
+					};
+				};
+
+				eth_rmii_y_pins: eth-y-rmii {
+					mux {
+						groups = "eth_mdio_y",
+							 "eth_mdc_y",
+							 "eth_rgmii_rx_clk_y",
+							 "eth_rx_dv_y",
+							 "eth_rxd0_y",
+							 "eth_rxd1_y",
+							 "eth_txen_y",
+							 "eth_txd0_y",
+							 "eth_txd1_y";
+						function = "eth";
+					};
+				};
+
+				mclk_b_pins: mclk_b {
+					mux {
+						groups = "mclk_b";
+						function = "mclk_b";
+					};
+				};
+
+				mclk_c_pins: mclk_c {
+					mux {
+						groups = "mclk_c";
+						function = "mclk_c";
+					};
+				};
+
+				pdm_dclk_a14_pins: pdm_dclk_a14 {
+					mux {
+						groups = "pdm_dclk_a14";
+						function = "pdm";
+					};
+				};
+
+				pdm_dclk_a19_pins: pdm_dclk_a19 {
+					mux {
+						groups = "pdm_dclk_a19";
+						function = "pdm";
+					};
+				};
+
+				pdm_din0_pins: pdm_din0 {
+					mux {
+						groups = "pdm_din0";
+						function = "pdm";
+					};
+				};
+
+				pdm_din1_pins: pdm_din1 {
+					mux {
+						groups = "pdm_din1";
+						function = "pdm";
+					};
+				};
+
+				pdm_din2_pins: pdm_din2 {
+					mux {
+						groups = "pdm_din2";
+						function = "pdm";
+					};
+				};
+
+				pdm_din3_pins: pdm_din3 {
+					mux {
+						groups = "pdm_din3";
+						function = "pdm";
+					};
+				};
+
+				pwm_a_a_pins: pwm_a_a {
+					mux {
+						groups = "pwm_a_a";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_x18_pins: pwm_a_x18 {
+					mux {
+						groups = "pwm_a_x18";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_x20_pins: pwm_a_x20 {
+					mux {
+						groups = "pwm_a_x20";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_z_pins: pwm_a_z {
+					mux {
+						groups = "pwm_a_z";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_b_a_pins: pwm_b_a {
+					mux {
+						groups = "pwm_b_a";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_b_x_pins: pwm_b_x {
+					mux {
+						groups = "pwm_b_x";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_b_z_pins: pwm_b_z {
+					mux {
+						groups = "pwm_b_z";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_c_a_pins: pwm_c_a {
+					mux {
+						groups = "pwm_c_a";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_c_x10_pins: pwm_c_x10 {
+					mux {
+						groups = "pwm_c_x10";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_c_x17_pins: pwm_c_x17 {
+					mux {
+						groups = "pwm_c_x17";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_d_x11_pins: pwm_d_x11 {
+					mux {
+						groups = "pwm_d_x11";
+						function = "pwm_d";
+					};
+				};
+
+				pwm_d_x16_pins: pwm_d_x16 {
+					mux {
+						groups = "pwm_d_x16";
+						function = "pwm_d";
+					};
+				};
+
+				sdio_pins: sdio {
+					mux {
+						groups = "sdio_d0",
+							 "sdio_d1",
+							 "sdio_d2",
+							 "sdio_d3",
+							 "sdio_cmd",
+							 "sdio_clk";
+						function = "sdio";
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "GPIOX_4";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "GPIOX_4";
+						bias-pull-down;
+					};
+				};
+
+				spdif_in_z_pins: spdif_in_z {
+					mux {
+						groups = "spdif_in_z";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a1_pins: spdif_in_a1 {
+					mux {
+						groups = "spdif_in_a1";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a7_pins: spdif_in_a7 {
+					mux {
+						groups = "spdif_in_a7";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a19_pins: spdif_in_a19 {
+					mux {
+						groups = "spdif_in_a19";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a20_pins: spdif_in_a20 {
+					mux {
+						groups = "spdif_in_a20";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_out_a1_pins: spdif_out_a1 {
+					mux {
+						groups = "spdif_out_a1";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a11_pins: spdif_out_a11 {
+					mux {
+						groups = "spdif_out_a11";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a19_pins: spdif_out_a19 {
+					mux {
+						groups = "spdif_out_a19";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a20_pins: spdif_out_a20 {
+					mux {
+						groups = "spdif_out_a20";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_z_pins: spdif_out_z {
+					mux {
+						groups = "spdif_out_z";
+						function = "spdif_out";
+					};
+				};
+
+				spi0_pins: spi0 {
+					mux {
+						groups = "spi0_miso",
+							 "spi0_mosi",
+							 "spi0_clk";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss0_pins: spi0_ss0 {
+					mux {
+						groups = "spi0_ss0";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss1_pins: spi0_ss1 {
+					mux {
+						groups = "spi0_ss1";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss2_pins: spi0_ss2 {
+					mux {
+						groups = "spi0_ss2";
+						function = "spi0";
+					};
+				};
+
+				spi1_a_pins: spi1_a {
+					mux {
+						groups = "spi1_miso_a",
+							 "spi1_mosi_a",
+							 "spi1_clk_a";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss0_a_pins: spi1_ss0_a {
+					mux {
+						groups = "spi1_ss0_a";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss1_pins: spi1_ss1 {
+					mux {
+						groups = "spi1_ss1";
+						function = "spi1";
+					};
+				};
+
+				spi1_x_pins: spi1_x {
+					mux {
+						groups = "spi1_miso_x",
+							 "spi1_mosi_x",
+							 "spi1_clk_x";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss0_x_pins: spi1_ss0_x {
+					mux {
+						groups = "spi1_ss0_x";
+						function = "spi1";
+					};
+				};
+
+				tdma_din0_pins: tdma_din0 {
+					mux {
+						groups = "tdma_din0";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x14_pins: tdma_dout0_x14 {
+					mux {
+						groups = "tdma_dout0_x14";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x15_pins: tdma_dout0_x15 {
+					mux {
+						groups = "tdma_dout0_x15";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout1_pins: tdma_dout1 {
+					mux {
+						groups = "tdma_dout1";
+						function = "tdma";
+					};
+				};
+
+				tdma_din1_pins: tdma_din1 {
+					mux {
+						groups = "tdma_din1";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_pins: tdma_fs {
+					mux {
+						groups = "tdma_fs";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_slv_pins: tdma_fs_slv {
+					mux {
+						groups = "tdma_fs_slv";
+						function = "tdma";
+					};
+				};
+
+				tdma_sclk_pins: tdma_sclk {
+					mux {
+						groups = "tdma_sclk";
+						function = "tdma";
+					};
+				};
+
+				tdma_sclk_slv_pins: tdma_sclk_slv {
+					mux {
+						groups = "tdma_sclk_slv";
+						function = "tdma";
+					};
+				};
+
+				tdmb_din0_pins: tdmb_din0 {
+					mux {
+						groups = "tdmb_din0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din1_pins: tdmb_din1 {
+					mux {
+						groups = "tdmb_din1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din2_pins: tdmb_din2 {
+					mux {
+						groups = "tdmb_din2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din3_pins: tdmb_din3 {
+					mux {
+						groups = "tdmb_din3";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout0_pins: tdmb_dout0 {
+					mux {
+						groups = "tdmb_dout0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout1_pins: tdmb_dout1 {
+					mux {
+						groups = "tdmb_dout1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout2_pins: tdmb_dout2 {
+					mux {
+						groups = "tdmb_dout2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout3_pins: tdmb_dout3 {
+					mux {
+						groups = "tdmb_dout3";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_pins: tdmb_fs {
+					mux {
+						groups = "tdmb_fs";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_slv_pins: tdmb_fs_slv {
+					mux {
+						groups = "tdmb_fs_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_sclk_pins: tdmb_sclk {
+					mux {
+						groups = "tdmb_sclk";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_sclk_slv_pins: tdmb_sclk_slv {
+					mux {
+						groups = "tdmb_sclk_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmc_fs_pins: tdmc_fs {
+					mux {
+						groups = "tdmc_fs";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_fs_slv_pins: tdmc_fs_slv {
+					mux {
+						groups = "tdmc_fs_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_sclk_pins: tdmc_sclk {
+					mux {
+						groups = "tdmc_sclk";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_sclk_slv_pins: tdmc_sclk_slv {
+					mux {
+						groups = "tdmc_sclk_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din0_pins: tdmc_din0 {
+					mux {
+						groups = "tdmc_din0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din1_pins: tdmc_din1 {
+					mux {
+						groups = "tdmc_din1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din2_pins: tdmc_din2 {
+					mux {
+						groups = "tdmc_din2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din3_pins: tdmc_din3 {
+					mux {
+						groups = "tdmc_din3";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout0_pins: tdmc_dout0 {
+					mux {
+						groups = "tdmc_dout0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout1_pins: tdmc_dout1 {
+					mux {
+						groups = "tdmc_dout1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout2_pins: tdmc_dout2 {
+					mux {
+						groups = "tdmc_dout2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout3_pins: tdmc_dout3 {
+					mux {
+						groups = "tdmc_dout3";
+						function = "tdmc";
+					};
+				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							 "uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_cts_a",
+							 "uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							 "uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							 "uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							 "uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							 "uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							 "uart_ao_rx_b_z";
+						function = "uart_ao_b_z";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							 "uart_ao_rts_b_z";
+						function = "uart_ao_b_z";
+					};
+				};
+			};
+		};
+
+		hiubus: bus at ff63c000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff63c000 0x0 0x1c00>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+
+			sysctrl: system-controller at 0 {
+				compatible = "amlogic,meson-axg-hhi-sysctrl",
+					     "simple-mfd", "syscon";
+				reg = <0 0 0 0x400>;
+
+				clkc: clock-controller {
+					compatible = "amlogic,axg-clkc";
+					#clock-cells = <1>;
+				};
+			};
+		};
+
+		mailbox: mailbox at ff63dc00 {
+			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+			reg = <0 0xff63dc00 0 0x400>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+			#mbox-cells = <1>;
+		};
+
+		audio: bus at ff642000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff642000 0x0 0x2000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
+
+			clkc_audio: clock-controller at 0 {
+				compatible = "amlogic,axg-audio-clkc";
+				reg = <0x0 0x0 0x0 0xb4>;
+				#clock-cells = <1>;
+
+				clocks = <&clkc CLKID_AUDIO>,
+					 <&clkc CLKID_MPLL0>,
+					 <&clkc CLKID_MPLL1>,
+					 <&clkc CLKID_MPLL2>,
+					 <&clkc CLKID_MPLL3>,
+					 <&clkc CLKID_HIFI_PLL>,
+					 <&clkc CLKID_FCLK_DIV3>,
+					 <&clkc CLKID_FCLK_DIV4>,
+					 <&clkc CLKID_GP0_PLL>;
+				clock-names = "pclk",
+					      "mst_in0",
+					      "mst_in1",
+					      "mst_in2",
+					      "mst_in3",
+					      "mst_in4",
+					      "mst_in5",
+					      "mst_in6",
+					      "mst_in7";
+
+				resets = <&reset RESET_AUDIO>;
+			};
+
+			toddr_a: audio-controller at 100 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x100 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_A";
+				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+				resets = <&arb AXG_ARB_TODDR_A>;
+				status = "disabled";
+			};
+
+			toddr_b: audio-controller at 140 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x140 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_B";
+				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+				resets = <&arb AXG_ARB_TODDR_B>;
+				status = "disabled";
+			};
+
+			toddr_c: audio-controller at 180 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x180 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_C";
+				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+				resets = <&arb AXG_ARB_TODDR_C>;
+				status = "disabled";
+			};
+
+			frddr_a: audio-controller at 1c0 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x1c0 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_A";
+				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+				resets = <&arb AXG_ARB_FRDDR_A>;
+				status = "disabled";
+			};
+
+			frddr_b: audio-controller at 200 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x200 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_B";
+				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+				resets = <&arb AXG_ARB_FRDDR_B>;
+				status = "disabled";
+			};
+
+			frddr_c: audio-controller at 240 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x240 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_C";
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+				resets = <&arb AXG_ARB_FRDDR_C>;
+				status = "disabled";
+			};
+
+			arb: reset-controller at 280 {
+				compatible = "amlogic,meson-axg-audio-arb";
+				reg = <0x0 0x280 0x0 0x4>;
+				#reset-cells = <1>;
+				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+			};
+
+			tdmin_a: audio-controller at 300 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x300 0x0 0x40>;
+				sound-name-prefix = "TDMIN_A";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_b: audio-controller at 340 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x340 0x0 0x40>;
+				sound-name-prefix = "TDMIN_B";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_c: audio-controller at 380 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x380 0x0 0x40>;
+				sound-name-prefix = "TDMIN_C";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_lb: audio-controller at 3c0 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x3c0 0x0 0x40>;
+				sound-name-prefix = "TDMIN_LB";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			spdifout: audio-controller at 480 {
+				compatible = "amlogic,axg-spdifout";
+				reg = <0x0 0x480 0x0 0x50>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "SPDIFOUT";
+				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+				clock-names = "pclk", "mclk";
+				status = "disabled";
+			};
+
+			tdmout_a: audio-controller at 500 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x500 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_A";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmout_b: audio-controller at 540 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x540 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_B";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmout_c: audio-controller at 580 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x580 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_C";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+		};
+
+		aobus: bus at ff800000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff800000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+
+			sysctrl_AO: sys-ctrl at 0 {
+				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
+				reg =  <0x0 0x0 0x0 0x100>;
+
+				clkc_AO: clock-controller {
+					compatible = "amlogic,meson-axg-aoclkc";
+					#clock-cells = <1>;
+					#reset-cells = <1>;
+				};
+			};
+
+			pinctrl_aobus: pinctrl at 14 {
+				compatible = "amlogic,meson-axg-aobus-pinctrl";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges;
+
+				gpio_ao: bank at 14 {
+					reg = <0x0 0x00014 0x0 0x8>,
+					      <0x0 0x0002c 0x0 0x4>,
+					      <0x0 0x00024 0x0 0x8>;
+					reg-names = "mux", "pull", "gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&pinctrl_aobus 0 0 15>;
+				};
+
+				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
+					mux {
+						groups = "i2c_ao_sck_4";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
+					mux {
+						groups = "i2c_ao_sck_8";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
+					mux {
+						groups = "i2c_ao_sck_10";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
+					mux {
+						groups = "i2c_ao_sda_5";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
+					mux {
+						groups = "i2c_ao_sda_9";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
+					mux {
+						groups = "i2c_ao_sda_11";
+						function = "i2c_ao";
+					};
+				};
+
+				remote_input_ao_pins: remote_input_ao {
+					mux {
+						groups = "remote_input_ao";
+						function = "remote_input_ao";
+					};
+				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							 "uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							 "uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							 "uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							 "uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
+			};
+
+			sec_AO: ao-secure at 140 {
+				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+				reg = <0x0 0x140 0x0 0x140>;
+				amlogic,has-chip-id;
+			};
+
+			pwm_AO_cd: pwm at 2000 {
+				compatible = "amlogic,meson-axg-ao-pwm";
+				reg = <0x0 0x02000  0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			uart_AO: serial at 3000 {
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x3000 0x0 0x18>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+
+			uart_AO_B: serial at 4000 {
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x4000 0x0 0x18>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+
+			i2c_AO: i2c at 5000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x05000 0x0 0x20>;
+				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_AO_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			pwm_AO_ab: pwm at 7000 {
+				compatible = "amlogic,meson-axg-ao-pwm";
+				reg = <0x0 0x07000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			ir: ir at 8000 {
+				compatible = "amlogic,meson-gxbb-ir";
+				reg = <0x0 0x8000 0x0 0x20>;
+				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
+
+			saradc: adc at 9000 {
+				compatible = "amlogic,meson-axg-saradc",
+					"amlogic,meson-saradc";
+				reg = <0x0 0x9000 0x0 0x38>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>,
+					 <&clkc_AO CLKID_AO_SAR_ADC>,
+					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+				clock-names = "clkin", "core", "adc_clk", "adc_sel";
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller at ffc01000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xffc01000 0 0x1000>,
+			      <0x0 0xffc02000 0 0x2000>,
+			      <0x0 0xffc04000 0 0x2000>,
+			      <0x0 0xffc06000 0 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+
+		cbus: bus at ffd00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffd00000 0x0 0x25000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
+
+			reset: reset-controller at 1004 {
+				compatible = "amlogic,meson-axg-reset";
+				reg = <0x0 0x01004 0x0 0x9c>;
+				#reset-cells = <1>;
+			};
+
+			gpio_intc: interrupt-controller at f080 {
+				compatible = "amlogic,meson-gpio-intc";
+				reg = <0x0 0xf080 0x0 0x10>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+				status = "disabled";
+			};
+
+			pwm_ab: pwm at 1b000 {
+				compatible = "amlogic,meson-axg-ee-pwm";
+				reg = <0x0 0x1b000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_cd: pwm at 1a000 {
+				compatible = "amlogic,meson-axg-ee-pwm";
+				reg = <0x0 0x1a000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			spicc0: spi at 13000 {
+				compatible = "amlogic,meson-axg-spicc";
+				reg = <0x0 0x13000 0x0 0x3c>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC0>;
+				clock-names = "core";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spicc1: spi at 15000 {
+				compatible = "amlogic,meson-axg-spicc";
+				reg = <0x0 0x15000 0x0 0x3c>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC1>;
+				clock-names = "core";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 1c000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1c000 0x0 0x20>;
+				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 1d000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1d000 0x0 0x20>;
+				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 1e000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1e000 0x0 0x20>;
+				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 1f000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1f000 0x0 0x20>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart_B: serial at 23000 {
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x23000 0x0 0x18>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+			};
+
+			uart_A: serial at 24000 {
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x24000 0x0 0x18>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+			};
+		};
+
+		apb: bus at ffe00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffe00000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+			sd_emmc_b: sd at 5000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x5000 0x0 0x800>;
+				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_B>,
+					<&clkc CLKID_SD_EMMC_B_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_B>;
+			};
+
+			sd_emmc_c: mmc at 7000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x7000 0x0 0x800>;
+				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_C>,
+					<&clkc CLKID_SD_EMMC_C_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_C>;
+			};
+		};
+
+		sram: sram at fffc0000 {
+			compatible = "amlogic,meson-axg-sram", "mmio-sram";
+			reg = <0x0 0xfffc0000 0x0 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x0 0xfffc0000 0x20000>;
+
+			cpu_scp_lpri: scp-shmem at 0 {
+				compatible = "amlogic,meson-axg-scp-shmem";
+				reg = <0x13000 0x400>;
+			};
+
+			cpu_scp_hpri: scp-shmem at 200 {
+				compatible = "amlogic,meson-axg-scp-shmem";
+				reg = <0x13400 0x400>;
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+};
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000000..61955016a5
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
new file mode 100644
index 0000000000..fd9c362099
--- /dev/null
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_SLV_SCLK0		9
+#define AUD_CLKID_SLV_SCLK1		10
+#define AUD_CLKID_SLV_SCLK2		11
+#define AUD_CLKID_SLV_SCLK3		12
+#define AUD_CLKID_SLV_SCLK4		13
+#define AUD_CLKID_SLV_SCLK5		14
+#define AUD_CLKID_SLV_SCLK6		15
+#define AUD_CLKID_SLV_SCLK7		16
+#define AUD_CLKID_SLV_SCLK8		17
+#define AUD_CLKID_SLV_SCLK9		18
+#define AUD_CLKID_SLV_LRCLK0		19
+#define AUD_CLKID_SLV_LRCLK1		20
+#define AUD_CLKID_SLV_LRCLK2		21
+#define AUD_CLKID_SLV_LRCLK3		22
+#define AUD_CLKID_SLV_LRCLK4		23
+#define AUD_CLKID_SLV_LRCLK5		24
+#define AUD_CLKID_SLV_LRCLK6		25
+#define AUD_CLKID_SLV_LRCLK7		26
+#define AUD_CLKID_SLV_LRCLK8		27
+#define AUD_CLKID_SLV_LRCLK9		28
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 0000000000..fd1f938c38
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_MIPI_ENABLE			81
+#define CLKID_GEN_CLK				84
+
+#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
new file mode 100644
index 0000000000..25bb1fffa9
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-axg-gpio.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
+#define _DT_BINDINGS_MESON_AXG_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0	0
+#define GPIOAO_1	1
+#define GPIOAO_2	2
+#define GPIOAO_3	3
+#define GPIOAO_4	4
+#define GPIOAO_5	5
+#define GPIOAO_6	6
+#define GPIOAO_7	7
+#define GPIOAO_8	8
+#define GPIOAO_9	9
+#define GPIOAO_10	10
+#define GPIOAO_11	11
+#define GPIOAO_12	12
+#define GPIOAO_13	13
+#define GPIO_TEST_N 14
+
+/* Second GPIO chip */
+#define GPIOZ_0		0
+#define GPIOZ_1		1
+#define GPIOZ_2		2
+#define GPIOZ_3		3
+#define GPIOZ_4		4
+#define GPIOZ_5		5
+#define GPIOZ_6		6
+#define GPIOZ_7		7
+#define GPIOZ_8		8
+#define GPIOZ_9		9
+#define GPIOZ_10	10
+#define BOOT_0		11
+#define BOOT_1		12
+#define BOOT_2		13
+#define BOOT_3		14
+#define BOOT_4		15
+#define BOOT_5		16
+#define BOOT_6		17
+#define BOOT_7		18
+#define BOOT_8		19
+#define BOOT_9		20
+#define BOOT_10		21
+#define BOOT_11		22
+#define BOOT_12		23
+#define BOOT_13		24
+#define BOOT_14		25
+#define GPIOA_0	    26
+#define GPIOA_1		27
+#define GPIOA_2		28
+#define GPIOA_3		29
+#define GPIOA_4		30
+#define GPIOA_5		31
+#define GPIOA_6		32
+#define GPIOA_7		33
+#define GPIOA_8		34
+#define GPIOA_9		35
+#define GPIOA_10	36
+#define GPIOA_11	37
+#define GPIOA_12	38
+#define GPIOA_13	39
+#define GPIOA_14	40
+#define GPIOA_15	41
+#define GPIOA_16	42
+#define GPIOA_17	43
+#define GPIOA_18	44
+#define GPIOA_19	45
+#define GPIOA_20	46
+#define GPIOX_0		47
+#define GPIOX_1		48
+#define GPIOX_2		49
+#define GPIOX_3		50
+#define GPIOX_4		51
+#define GPIOX_5		52
+#define GPIOX_6		53
+#define GPIOX_7		54
+#define GPIOX_8		55
+#define GPIOX_9		56
+#define GPIOX_10	57
+#define GPIOX_11	58
+#define GPIOX_12	59
+#define GPIOX_13	60
+#define GPIOX_14	61
+#define GPIOX_15	62
+#define GPIOX_16	63
+#define GPIOX_17	64
+#define GPIOX_18	65
+#define GPIOX_19	66
+#define GPIOX_20	67
+#define GPIOX_21	68
+#define GPIOX_22	69
+#define GPIOY_0		70
+#define GPIOY_1		71
+#define GPIOY_2		72
+#define GPIOY_3		73
+#define GPIOY_4		74
+#define GPIOY_5		75
+#define GPIOY_6		76
+#define GPIOY_7		77
+#define GPIOY_8		78
+#define GPIOY_9		79
+#define GPIOY_10	80
+#define GPIOY_11	81
+#define GPIOY_12	82
+#define GPIOY_13	83
+#define GPIOY_14	84
+#define GPIOY_15	85
+
+#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
new file mode 100644
index 0000000000..05c3636787
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ *
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+
+#define AXG_ARB_TODDR_A	0
+#define AXG_ARB_TODDR_B	1
+#define AXG_ARB_TODDR_C	2
+#define AXG_ARB_FRDDR_A	3
+#define AXG_ARB_FRDDR_B	4
+#define AXG_ARB_FRDDR_C	5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
new file mode 100644
index 0000000000..ad6f55dabd
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
@@ -0,0 +1,124 @@
+/*
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+
+/*	RESET0					*/
+#define RESET_HIU			0
+#define RESET_PCIE_A			1
+#define RESET_PCIE_B			2
+#define RESET_DDR_TOP			3
+/*					4	*/
+#define RESET_VIU			5
+#define RESET_PCIE_PHY			6
+#define RESET_PCIE_APB			7
+/*					8	*/
+/*					9	*/
+#define RESET_VENC			10
+#define RESET_ASSIST			11
+/*					12	*/
+#define RESET_VCBUS			13
+/*					14	*/
+/*					15	*/
+#define RESET_GIC			16
+#define RESET_CAPB3_DECODE		17
+/*					18-21	*/
+#define RESET_SYS_CPU_CAPB3		22
+#define RESET_CBUS_CAPB3		23
+#define RESET_AHB_CNTL			24
+#define RESET_AHB_DATA			25
+#define RESET_VCBUS_CLK81		26
+#define RESET_MMC			27
+/*					28-31	*/
+/*	RESET1					*/
+/*					32	*/
+/*					33	*/
+#define RESET_USB_OTG			34
+#define RESET_DDR			35
+#define RESET_AO_RESET			36
+/*					37	*/
+#define RESET_AHB_SRAM			38
+/*					39	*/
+/*					40	*/
+#define RESET_DMA			41
+#define RESET_ISA			42
+#define RESET_ETHERNET			43
+/*					44	*/
+#define RESET_SD_EMMC_B			45
+#define RESET_SD_EMMC_C			46
+#define RESET_ROM_BOOT			47
+#define RESET_SYS_CPU_0			48
+#define RESET_SYS_CPU_1			49
+#define RESET_SYS_CPU_2			50
+#define RESET_SYS_CPU_3			51
+#define RESET_SYS_CPU_CORE_0		52
+#define RESET_SYS_CPU_CORE_1		53
+#define RESET_SYS_CPU_CORE_2		54
+#define RESET_SYS_CPU_CORE_3		55
+#define RESET_SYS_PLL_DIV		56
+#define RESET_SYS_CPU_AXI		57
+#define RESET_SYS_CPU_L2		58
+#define RESET_SYS_CPU_P			59
+#define RESET_SYS_CPU_MBIST		60
+/*					61-63	*/
+/*	RESET2					*/
+/*					64	*/
+/*					65	*/
+#define RESET_AUDIO			66
+/*					67	*/
+#define RESET_MIPI_HOST			68
+#define RESET_AUDIO_LOCKER		69
+#define RESET_GE2D			70
+/*					71-76	*/
+#define RESET_AO_CPU_RESET		77
+/*					78-95	*/
+/*	RESET3					*/
+#define RESET_RING_OSCILLATOR		96
+/*					97-127	*/
+/*	RESET4					*/
+/*					128	*/
+/*					129	*/
+#define RESET_MIPI_PHY			130
+/*					131-140	*/
+#define RESET_VENCL			141
+#define RESET_I2C_MASTER_2		142
+#define RESET_I2C_MASTER_1		143
+/*					144-159	*/
+/*	RESET5					*/
+/*					160-191	*/
+/*	RESET6					*/
+#define RESET_PERIPHS_GENERAL		192
+#define RESET_PERIPHS_SPICC		193
+/*					194	*/
+/*					195	*/
+#define RESET_PERIPHS_I2C_MASTER_0	196
+/*					197-200	*/
+#define RESET_PERIPHS_UART_0		201
+#define RESET_PERIPHS_UART_1		202
+/*					203-204	*/
+#define RESET_PERIPHS_SPI_0		205
+#define RESET_PERIPHS_I2C_MASTER_3	206
+/*					207-223	*/
+/*	RESET7					*/
+#define RESET_USB_DDR_0			224
+#define RESET_USB_DDR_1			225
+#define RESET_USB_DDR_2			226
+#define RESET_USB_DDR_3			227
+/*					228	*/
+#define RESET_DEVICE_MMC_ARB		229
+/*					230	*/
+#define RESET_VID_LOCK			231
+#define RESET_A9_DMC_PIPEL		232
+#define RESET_DMC_VPU_PIPEL		233
+/*					234-255	*/
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 0000000000..d342c0b6b2
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 15/19] ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

Synchronize the Amlogic AXG Device Tree files and bindings include from
the recent Linux 4.20-rc1, because it includes patches fixing support for
U-boot.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/dts/Makefile                         |    3 +-
 arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
 arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
 include/dt-bindings/clock/axg-aoclkc.h        |   26 +
 include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
 include/dt-bindings/clock/axg-clkc.h          |   76 +
 include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
 .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
 .../reset/amlogic,meson-axg-reset.h           |  124 ++
 include/dt-bindings/reset/axg-aoclkc.h        |   20 +
 10 files changed, 2618 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/meson-axg-s400.dts
 create mode 100644 arch/arm/dts/meson-axg.dtsi
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
 create mode 100644 include/dt-bindings/clock/axg-clkc.h
 create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
 create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 84b7e5335c..1fa2f2d8dc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -59,7 +59,8 @@ dtb-$(CONFIG_ARCH_MESON) += \
 	meson-gxl-s905x-p212.dtb \
 	meson-gxl-s905x-libretech-cc.dtb \
 	meson-gxl-s905x-khadas-vim.dtb \
-	meson-gxm-khadas-vim2.dtb
+	meson-gxm-khadas-vim2.dtb \
+	meson-axg-s400.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
new file mode 100644
index 0000000000..18778ada7b
--- /dev/null
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -0,0 +1,554 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-axg.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
+	model = "Amlogic Meson AXG S400 Development Board";
+
+	adc_keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+
+		button-next {
+			label = "Next";
+			linux,code = <KEY_NEXT>;
+			press-threshold-microvolt = <1116000>; /* 62% */
+		};
+
+		button-prev {
+			label = "Previous";
+			linux,code = <KEY_PREVIOUS>;
+			press-threshold-microvolt = <900000>; /* 50% */
+		};
+
+		button-wifi {
+			label = "Wifi";
+			linux,code = <KEY_WLAN>;
+			press-threshold-microvolt = <684000>; /* 38% */
+		};
+
+		button-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <468000>; /* 26% */
+		};
+
+		button-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <252000>; /* 14% */
+		};
+
+		button-voice {
+			label = "Voice";
+			linux,code = <KEY_VOICECOMMAND>;
+			press-threshold-microvolt = <0>; /* 0% */
+		};
+	};
+
+	aliases {
+		serial0 = &uart_AO;
+		serial1 = &uart_A;
+	};
+
+	linein: audio-codec at 0 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es7241";
+		VDDA-supply = <&vcc_3v3>;
+		VDDP-supply = <&vcc_3v3>;
+		VDDD-supply = <&vcc_3v3>;
+		status = "okay";
+		sound-name-prefix = "Linein";
+	};
+
+	lineout: audio-codec at 1 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es7154";
+		VDD-supply = <&vcc_3v3>;
+		PVDD-supply = <&vcc_5v>;
+		status = "okay";
+		sound-name-prefix = "Lineout";
+	};
+
+	spdif_dit: audio-codec at 2 {
+		#sound-dai-cells = <0>;
+		compatible = "linux,spdif-dit";
+		status = "okay";
+		sound-name-prefix = "DIT";
+	};
+
+	dmics: audio-codec at 3 {
+		#sound-dai-cells = <0>;
+		compatible = "dmic-codec";
+		num-channels = <7>;
+		wakeup-delay-ms = <50>;
+		status = "okay";
+		sound-name-prefix = "MIC";
+	};
+
+	emmc_pwrseq: emmc-pwrseq {
+		compatible = "mmc-pwrseq-emmc";
+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	main_12v: regulator-main_12v {
+		compatible = "regulator-fixed";
+		regulator-name = "12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+	};
+
+	vcc_3v3: regulator-vcc_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vcc_5v: regulator-vcc_5v {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&main_12v>;
+
+		gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vddao_3v3: regulator-vddao_3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&main_12v>;
+		regulator-always-on;
+	};
+
+	vddio_ao18: regulator-vddio_ao18 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_AO18";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddio_boot: regulator-vddio_boot {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_BOOT";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	usb_pwr: regulator-usb_pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "USB_PWR";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_5v>;
+
+		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	speaker-leds {
+		compatible = "gpio-leds";
+
+		aled1 {
+			label = "speaker:aled1";
+			gpios = <&gpio_speaker 7 0>;
+		};
+
+		aled2 {
+			label = "speaker:aled2";
+			gpios = <&gpio_speaker 6 0>;
+		};
+
+		aled3 {
+			label = "speaker:aled3";
+			gpios = <&gpio_speaker 5 0>;
+		};
+
+		aled4 {
+			label = "speaker:aled4";
+			gpios = <&gpio_speaker 4 0>;
+		};
+
+		aled5 {
+			label = "speaker:aled5";
+			gpios = <&gpio_speaker 3 0>;
+		};
+
+		aled6 {
+			label = "speaker:aled6";
+			gpios = <&gpio_speaker 2 0>;
+		};
+	};
+
+	sound {
+		compatible = "amlogic,axg-sound-card";
+		model = "AXG-S400";
+		audio-aux-devs = <&tdmin_a>, <&tdmin_b>,  <&tdmin_c>,
+				 <&tdmin_lb>, <&tdmout_c>;
+		audio-widgets = "Line", "Lineout",
+				"Line", "Linein",
+				"Speaker", "Speaker1 Left",
+				"Speaker", "Speaker1 Right";
+		audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+				"SPDIFOUT IN 0", "FRDDR_A OUT 3",
+				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
+				"SPDIFOUT IN 1", "FRDDR_B OUT 3",
+				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
+				"SPDIFOUT IN 2", "FRDDR_C OUT 3",
+				"TDM_C Playback", "TDMOUT_C OUT",
+				"TDMIN_A IN 2", "TDM_C Capture",
+				"TDMIN_A IN 5", "TDM_C Loopback",
+				"TDMIN_B IN 2", "TDM_C Capture",
+				"TDMIN_B IN 5", "TDM_C Loopback",
+				"TDMIN_C IN 2", "TDM_C Capture",
+				"TDMIN_C IN 5", "TDM_C Loopback",
+				"TDMIN_LB IN 2", "TDM_C Loopback",
+				"TDMIN_LB IN 5", "TDM_C Capture",
+				"TODDR_A IN 0", "TDMIN_A OUT",
+				"TODDR_B IN 0", "TDMIN_A OUT",
+				"TODDR_C IN 0", "TDMIN_A OUT",
+				"TODDR_A IN 1", "TDMIN_B OUT",
+				"TODDR_B IN 1", "TDMIN_B OUT",
+				"TODDR_C IN 1", "TDMIN_B OUT",
+				"TODDR_A IN 2", "TDMIN_C OUT",
+				"TODDR_B IN 2", "TDMIN_C OUT",
+				"TODDR_C IN 2", "TDMIN_C OUT",
+				"TODDR_A IN 4", "PDM Capture",
+				"TODDR_B IN 4", "PDM Capture",
+				"TODDR_C IN 4", "PDM Capture",
+				"TODDR_A IN 6", "TDMIN_LB OUT",
+				"TODDR_B IN 6", "TDMIN_LB OUT",
+				"TODDR_C IN 6", "TDMIN_LB OUT",
+				"Lineout", "Lineout AOUTL",
+				"Lineout", "Lineout AOUTR",
+				"Speaker1 Left", "SPK1 OUT_A",
+				"Speaker1 Left", "SPK1 OUT_B",
+				"Speaker1 Right", "SPK1 OUT_C",
+				"Speaker1 Right", "SPK1 OUT_D",
+				"Linein AINL", "Linein",
+				"Linein AINR", "Linein";
+		assigned-clocks = <&clkc CLKID_HIFI_PLL>,
+				  <&clkc CLKID_MPLL0>,
+				  <&clkc CLKID_MPLL1>;
+		assigned-clock-parents = <0>, <0>, <0>;
+		assigned-clock-rates = <589824000>,
+				       <270950400>,
+				       <393216000>;
+		status = "okay";
+
+		dai-link at 0 {
+			sound-dai = <&frddr_a>;
+		};
+
+		dai-link at 1 {
+			sound-dai = <&frddr_b>;
+		};
+
+		dai-link at 2 {
+			sound-dai = <&frddr_c>;
+		};
+
+		dai-link at 3 {
+			sound-dai = <&toddr_a>;
+		};
+
+		dai-link at 4 {
+			sound-dai = <&toddr_b>;
+		};
+
+		dai-link at 5 {
+			sound-dai = <&toddr_c>;
+		};
+
+		dai-link at 6 {
+			sound-dai = <&tdmif_c>;
+			dai-format = "i2s";
+			dai-tdm-slot-tx-mask-2 = <1 1>;
+			dai-tdm-slot-rx-mask-1 = <1 1>;
+			mclk-fs = <256>;
+
+			codec at 0 {
+				sound-dai = <&lineout>;
+			};
+
+			codec at 1 {
+				sound-dai = <&speaker_amp1>;
+			};
+
+			codec at 2 {
+				sound-dai = <&linein>;
+			};
+
+		};
+
+		dai-link at 7 {
+			sound-dai = <&spdifout>;
+
+			codec {
+				sound-dai = <&spdif_dit>;
+			};
+		};
+
+		dai-link at 8 {
+			sound-dai = <&pdm>;
+
+			codec {
+				sound-dai = <&dmics>;
+			};
+		};
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+	};
+};
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_rgmii_y_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&eth_phy0>;
+	phy-mode = "rgmii";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy0: ethernet-phy at 0 {
+			/* Realtek RTL8211F (0x001cc916) */
+			reg = <0>;
+			eee-broken-1000t;
+		};
+	};
+};
+
+&frddr_a {
+	status = "okay";
+};
+
+&frddr_b {
+	status = "okay";
+};
+
+&frddr_c {
+	status = "okay";
+};
+
+&ir {
+	status = "okay";
+	pinctrl-0 = <&remote_input_ao_pins>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-0 = <&i2c1_z_pins>;
+	pinctrl-names = "default";
+
+	speaker_amp1: audio-codec at 1b {
+		compatible = "ti,tas5707";
+		reg = <0x1b>;
+		reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		AVDD-supply = <&vcc_3v3>;
+		DVDD-supply = <&vcc_3v3>;
+		PVDD_A-supply = <&main_12v>;
+		PVDD_B-supply = <&main_12v>;
+		PVDD_C-supply = <&main_12v>;
+		PVDD_D-supply = <&main_12v>;
+		sound-name-prefix = "SPK1";
+	};
+};
+
+&i2c_AO {
+	status = "okay";
+	pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
+	pinctrl-names = "default";
+
+	gpio_speaker: gpio-controller at 1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&vddao_3v3>;
+	};
+};
+
+&pdm {
+	pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
+		    <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_x20_pins>;
+	pinctrl-names = "default";
+};
+
+&saradc {
+	status = "okay";
+	vref-supply = <&vddio_ao18>;
+};
+
+/* wifi module */
+&sd_emmc_b {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	max-frequency = <100000000>;
+	non-removable;
+	disable-wp;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+
+	brcmf: wifi at 1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* emmc storage */
+&sd_emmc_c {
+	status = "disabled";
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	max-frequency = <180000000>;
+	non-removable;
+	disable-wp;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+
+	mmc-pwrseq = <&emmc_pwrseq>;
+
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vddio_boot>;
+};
+
+&spdifout {
+	pinctrl-0 = <&spdif_out_a20_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_a {
+	pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
+		    <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_b {
+	pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
+		    <&tdmb_din3_pins>, <&mclk_b_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmif_c {
+	pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
+		    <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
+		    <&mclk_c_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tdmin_a {
+	status = "okay";
+};
+
+&tdmin_b {
+	status = "okay";
+};
+
+&tdmin_c {
+	status = "okay";
+};
+
+&tdmin_lb {
+	status = "okay";
+};
+
+&tdmout_c {
+	status = "okay";
+};
+
+&toddr_a {
+	status = "okay";
+};
+
+&toddr_b {
+	status = "okay";
+};
+
+&toddr_c {
+	status = "okay";
+};
+
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>;
+	pinctrl-names = "default";
+};
+
+&uart_AO {
+	status = "okay";
+	pinctrl-0 = <&uart_ao_a_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
new file mode 100644
index 0000000000..df017dbd2e
--- /dev/null
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -0,0 +1,1589 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/clock/axg-audio-clkc.h>
+#include <dt-bindings/clock/axg-clkc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
+#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+
+/ {
+	compatible = "amlogic,meson-axg";
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	tdmif_a: audio-controller at 0 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_A";
+		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	tdmif_b: audio-controller at 1 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_B";
+		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	tdmif_c: audio-controller at 2 {
+		compatible = "amlogic,axg-tdm-iface";
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "TDM_C";
+		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
+			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
+		clock-names = "mclk", "sclk", "lrclk";
+		status = "disabled";
+	};
+
+	ao_alt_xtal: ao_alt_xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <32000000>;
+		clock-output-names = "ao_alt_xtal";
+		#clock-cells = <0>;
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 16 MiB reserved for Hardware ROM Firmware */
+		hwrom_reserved: hwrom at 0 {
+			reg = <0x0 0x0 0x0 0x1000000>;
+			no-map;
+		};
+
+		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon at 5000000 {
+			reg = <0x0 0x05000000 0x0 0x300000>;
+			no-map;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ethmac: ethernet at ff3f0000 {
+			compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
+			reg = <0x0 0xff3f0000 0x0 0x10000
+			       0x0 0xff634540 0x0 0x8>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "macirq";
+			clocks = <&clkc CLKID_ETH>,
+				 <&clkc CLKID_FCLK_DIV2>,
+				 <&clkc CLKID_MPLL2>;
+			clock-names = "stmmaceth", "clkin0", "clkin1";
+			status = "disabled";
+		};
+
+		pdm: audio-controller at ff632000 {
+			compatible = "amlogic,axg-pdm";
+			reg = <0x0 0xff632000 0x0 0x34>;
+			#sound-dai-cells = <0>;
+			sound-name-prefix = "PDM";
+			clocks = <&clkc_audio AUD_CLKID_PDM>,
+				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
+				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+			clock-names = "pclk", "dclk", "sysclk";
+			status = "disabled";
+		};
+
+		periphs: bus at ff634000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff634000 0x0 0x2000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+			hwrng: rng at 18 {
+				compatible = "amlogic,meson-rng";
+				reg = <0x0 0x18 0x0 0x4>;
+				clocks = <&clkc CLKID_RNG0>;
+				clock-names = "core";
+			};
+
+			pinctrl_periphs: pinctrl at 480 {
+				compatible = "amlogic,meson-axg-periphs-pinctrl";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges;
+
+				gpio: bank at 480 {
+					reg = <0x0 0x00480 0x0 0x40>,
+					      <0x0 0x004e8 0x0 0x14>,
+					      <0x0 0x00520 0x0 0x14>,
+					      <0x0 0x00430 0x0 0x3c>;
+					reg-names = "mux", "pull", "pull-enable", "gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&pinctrl_periphs 0 0 86>;
+				};
+
+				i2c0_pins: i2c0 {
+					mux {
+						groups = "i2c0_sck",
+							 "i2c0_sda";
+						function = "i2c0";
+					};
+				};
+
+				i2c1_x_pins: i2c1_x {
+					mux {
+						groups = "i2c1_sck_x",
+							 "i2c1_sda_x";
+						function = "i2c1";
+					};
+				};
+
+				i2c1_z_pins: i2c1_z {
+					mux {
+						groups = "i2c1_sck_z",
+							 "i2c1_sda_z";
+						function = "i2c1";
+					};
+				};
+
+				i2c2_a_pins: i2c2_a {
+					mux {
+						groups = "i2c2_sck_a",
+							 "i2c2_sda_a";
+						function = "i2c2";
+					};
+				};
+
+				i2c2_x_pins: i2c2_x {
+					mux {
+						groups = "i2c2_sck_x",
+							 "i2c2_sda_x";
+						function = "i2c2";
+					};
+				};
+
+				i2c3_a6_pins: i2c3_a6 {
+					mux {
+						groups = "i2c3_sda_a6",
+							 "i2c3_sck_a7";
+						function = "i2c3";
+					};
+				};
+
+				i2c3_a12_pins: i2c3_a12 {
+					mux {
+						groups = "i2c3_sda_a12",
+							 "i2c3_sck_a13";
+						function = "i2c3";
+					};
+				};
+
+				i2c3_a19_pins: i2c3_a19 {
+					mux {
+						groups = "i2c3_sda_a19",
+							 "i2c3_sck_a20";
+						function = "i2c3";
+					};
+				};
+
+				emmc_pins: emmc {
+					mux {
+						groups = "emmc_nand_d0",
+							 "emmc_nand_d1",
+							 "emmc_nand_d2",
+							 "emmc_nand_d3",
+							 "emmc_nand_d4",
+							 "emmc_nand_d5",
+							 "emmc_nand_d6",
+							 "emmc_nand_d7",
+							 "emmc_clk",
+							 "emmc_cmd",
+							 "emmc_ds";
+						function = "emmc";
+					};
+				};
+
+				emmc_clk_gate_pins: emmc_clk_gate {
+					mux {
+						groups = "BOOT_8";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "BOOT_8";
+						bias-pull-down;
+					};
+				};
+
+				eth_rgmii_x_pins: eth-x-rgmii {
+					mux {
+						groups = "eth_mdio_x",
+							 "eth_mdc_x",
+							 "eth_rgmii_rx_clk_x",
+							 "eth_rx_dv_x",
+							 "eth_rxd0_x",
+							 "eth_rxd1_x",
+							 "eth_rxd2_rgmii",
+							 "eth_rxd3_rgmii",
+							 "eth_rgmii_tx_clk",
+							 "eth_txen_x",
+							 "eth_txd0_x",
+							 "eth_txd1_x",
+							 "eth_txd2_rgmii",
+							 "eth_txd3_rgmii";
+						function = "eth";
+					};
+				};
+
+				eth_rgmii_y_pins: eth-y-rgmii {
+					mux {
+						groups = "eth_mdio_y",
+							 "eth_mdc_y",
+							 "eth_rgmii_rx_clk_y",
+							 "eth_rx_dv_y",
+							 "eth_rxd0_y",
+							 "eth_rxd1_y",
+							 "eth_rxd2_rgmii",
+							 "eth_rxd3_rgmii",
+							 "eth_rgmii_tx_clk",
+							 "eth_txen_y",
+							 "eth_txd0_y",
+							 "eth_txd1_y",
+							 "eth_txd2_rgmii",
+							 "eth_txd3_rgmii";
+						function = "eth";
+					};
+				};
+
+				eth_rmii_x_pins: eth-x-rmii {
+					mux {
+						groups = "eth_mdio_x",
+							 "eth_mdc_x",
+							 "eth_rgmii_rx_clk_x",
+							 "eth_rx_dv_x",
+							 "eth_rxd0_x",
+							 "eth_rxd1_x",
+							 "eth_txen_x",
+							 "eth_txd0_x",
+							 "eth_txd1_x";
+						function = "eth";
+					};
+				};
+
+				eth_rmii_y_pins: eth-y-rmii {
+					mux {
+						groups = "eth_mdio_y",
+							 "eth_mdc_y",
+							 "eth_rgmii_rx_clk_y",
+							 "eth_rx_dv_y",
+							 "eth_rxd0_y",
+							 "eth_rxd1_y",
+							 "eth_txen_y",
+							 "eth_txd0_y",
+							 "eth_txd1_y";
+						function = "eth";
+					};
+				};
+
+				mclk_b_pins: mclk_b {
+					mux {
+						groups = "mclk_b";
+						function = "mclk_b";
+					};
+				};
+
+				mclk_c_pins: mclk_c {
+					mux {
+						groups = "mclk_c";
+						function = "mclk_c";
+					};
+				};
+
+				pdm_dclk_a14_pins: pdm_dclk_a14 {
+					mux {
+						groups = "pdm_dclk_a14";
+						function = "pdm";
+					};
+				};
+
+				pdm_dclk_a19_pins: pdm_dclk_a19 {
+					mux {
+						groups = "pdm_dclk_a19";
+						function = "pdm";
+					};
+				};
+
+				pdm_din0_pins: pdm_din0 {
+					mux {
+						groups = "pdm_din0";
+						function = "pdm";
+					};
+				};
+
+				pdm_din1_pins: pdm_din1 {
+					mux {
+						groups = "pdm_din1";
+						function = "pdm";
+					};
+				};
+
+				pdm_din2_pins: pdm_din2 {
+					mux {
+						groups = "pdm_din2";
+						function = "pdm";
+					};
+				};
+
+				pdm_din3_pins: pdm_din3 {
+					mux {
+						groups = "pdm_din3";
+						function = "pdm";
+					};
+				};
+
+				pwm_a_a_pins: pwm_a_a {
+					mux {
+						groups = "pwm_a_a";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_x18_pins: pwm_a_x18 {
+					mux {
+						groups = "pwm_a_x18";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_x20_pins: pwm_a_x20 {
+					mux {
+						groups = "pwm_a_x20";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_a_z_pins: pwm_a_z {
+					mux {
+						groups = "pwm_a_z";
+						function = "pwm_a";
+					};
+				};
+
+				pwm_b_a_pins: pwm_b_a {
+					mux {
+						groups = "pwm_b_a";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_b_x_pins: pwm_b_x {
+					mux {
+						groups = "pwm_b_x";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_b_z_pins: pwm_b_z {
+					mux {
+						groups = "pwm_b_z";
+						function = "pwm_b";
+					};
+				};
+
+				pwm_c_a_pins: pwm_c_a {
+					mux {
+						groups = "pwm_c_a";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_c_x10_pins: pwm_c_x10 {
+					mux {
+						groups = "pwm_c_x10";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_c_x17_pins: pwm_c_x17 {
+					mux {
+						groups = "pwm_c_x17";
+						function = "pwm_c";
+					};
+				};
+
+				pwm_d_x11_pins: pwm_d_x11 {
+					mux {
+						groups = "pwm_d_x11";
+						function = "pwm_d";
+					};
+				};
+
+				pwm_d_x16_pins: pwm_d_x16 {
+					mux {
+						groups = "pwm_d_x16";
+						function = "pwm_d";
+					};
+				};
+
+				sdio_pins: sdio {
+					mux {
+						groups = "sdio_d0",
+							 "sdio_d1",
+							 "sdio_d2",
+							 "sdio_d3",
+							 "sdio_cmd",
+							 "sdio_clk";
+						function = "sdio";
+					};
+				};
+
+				sdio_clk_gate_pins: sdio_clk_gate {
+					mux {
+						groups = "GPIOX_4";
+						function = "gpio_periphs";
+					};
+					cfg-pull-down {
+						pins = "GPIOX_4";
+						bias-pull-down;
+					};
+				};
+
+				spdif_in_z_pins: spdif_in_z {
+					mux {
+						groups = "spdif_in_z";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a1_pins: spdif_in_a1 {
+					mux {
+						groups = "spdif_in_a1";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a7_pins: spdif_in_a7 {
+					mux {
+						groups = "spdif_in_a7";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a19_pins: spdif_in_a19 {
+					mux {
+						groups = "spdif_in_a19";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_in_a20_pins: spdif_in_a20 {
+					mux {
+						groups = "spdif_in_a20";
+						function = "spdif_in";
+					};
+				};
+
+				spdif_out_a1_pins: spdif_out_a1 {
+					mux {
+						groups = "spdif_out_a1";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a11_pins: spdif_out_a11 {
+					mux {
+						groups = "spdif_out_a11";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a19_pins: spdif_out_a19 {
+					mux {
+						groups = "spdif_out_a19";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_a20_pins: spdif_out_a20 {
+					mux {
+						groups = "spdif_out_a20";
+						function = "spdif_out";
+					};
+				};
+
+				spdif_out_z_pins: spdif_out_z {
+					mux {
+						groups = "spdif_out_z";
+						function = "spdif_out";
+					};
+				};
+
+				spi0_pins: spi0 {
+					mux {
+						groups = "spi0_miso",
+							 "spi0_mosi",
+							 "spi0_clk";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss0_pins: spi0_ss0 {
+					mux {
+						groups = "spi0_ss0";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss1_pins: spi0_ss1 {
+					mux {
+						groups = "spi0_ss1";
+						function = "spi0";
+					};
+				};
+
+				spi0_ss2_pins: spi0_ss2 {
+					mux {
+						groups = "spi0_ss2";
+						function = "spi0";
+					};
+				};
+
+				spi1_a_pins: spi1_a {
+					mux {
+						groups = "spi1_miso_a",
+							 "spi1_mosi_a",
+							 "spi1_clk_a";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss0_a_pins: spi1_ss0_a {
+					mux {
+						groups = "spi1_ss0_a";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss1_pins: spi1_ss1 {
+					mux {
+						groups = "spi1_ss1";
+						function = "spi1";
+					};
+				};
+
+				spi1_x_pins: spi1_x {
+					mux {
+						groups = "spi1_miso_x",
+							 "spi1_mosi_x",
+							 "spi1_clk_x";
+						function = "spi1";
+					};
+				};
+
+				spi1_ss0_x_pins: spi1_ss0_x {
+					mux {
+						groups = "spi1_ss0_x";
+						function = "spi1";
+					};
+				};
+
+				tdma_din0_pins: tdma_din0 {
+					mux {
+						groups = "tdma_din0";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x14_pins: tdma_dout0_x14 {
+					mux {
+						groups = "tdma_dout0_x14";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout0_x15_pins: tdma_dout0_x15 {
+					mux {
+						groups = "tdma_dout0_x15";
+						function = "tdma";
+					};
+				};
+
+				tdma_dout1_pins: tdma_dout1 {
+					mux {
+						groups = "tdma_dout1";
+						function = "tdma";
+					};
+				};
+
+				tdma_din1_pins: tdma_din1 {
+					mux {
+						groups = "tdma_din1";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_pins: tdma_fs {
+					mux {
+						groups = "tdma_fs";
+						function = "tdma";
+					};
+				};
+
+				tdma_fs_slv_pins: tdma_fs_slv {
+					mux {
+						groups = "tdma_fs_slv";
+						function = "tdma";
+					};
+				};
+
+				tdma_sclk_pins: tdma_sclk {
+					mux {
+						groups = "tdma_sclk";
+						function = "tdma";
+					};
+				};
+
+				tdma_sclk_slv_pins: tdma_sclk_slv {
+					mux {
+						groups = "tdma_sclk_slv";
+						function = "tdma";
+					};
+				};
+
+				tdmb_din0_pins: tdmb_din0 {
+					mux {
+						groups = "tdmb_din0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din1_pins: tdmb_din1 {
+					mux {
+						groups = "tdmb_din1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din2_pins: tdmb_din2 {
+					mux {
+						groups = "tdmb_din2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_din3_pins: tdmb_din3 {
+					mux {
+						groups = "tdmb_din3";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout0_pins: tdmb_dout0 {
+					mux {
+						groups = "tdmb_dout0";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout1_pins: tdmb_dout1 {
+					mux {
+						groups = "tdmb_dout1";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout2_pins: tdmb_dout2 {
+					mux {
+						groups = "tdmb_dout2";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_dout3_pins: tdmb_dout3 {
+					mux {
+						groups = "tdmb_dout3";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_pins: tdmb_fs {
+					mux {
+						groups = "tdmb_fs";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_fs_slv_pins: tdmb_fs_slv {
+					mux {
+						groups = "tdmb_fs_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_sclk_pins: tdmb_sclk {
+					mux {
+						groups = "tdmb_sclk";
+						function = "tdmb";
+					};
+				};
+
+				tdmb_sclk_slv_pins: tdmb_sclk_slv {
+					mux {
+						groups = "tdmb_sclk_slv";
+						function = "tdmb";
+					};
+				};
+
+				tdmc_fs_pins: tdmc_fs {
+					mux {
+						groups = "tdmc_fs";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_fs_slv_pins: tdmc_fs_slv {
+					mux {
+						groups = "tdmc_fs_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_sclk_pins: tdmc_sclk {
+					mux {
+						groups = "tdmc_sclk";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_sclk_slv_pins: tdmc_sclk_slv {
+					mux {
+						groups = "tdmc_sclk_slv";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din0_pins: tdmc_din0 {
+					mux {
+						groups = "tdmc_din0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din1_pins: tdmc_din1 {
+					mux {
+						groups = "tdmc_din1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din2_pins: tdmc_din2 {
+					mux {
+						groups = "tdmc_din2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_din3_pins: tdmc_din3 {
+					mux {
+						groups = "tdmc_din3";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout0_pins: tdmc_dout0 {
+					mux {
+						groups = "tdmc_dout0";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout1_pins: tdmc_dout1 {
+					mux {
+						groups = "tdmc_dout1";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout2_pins: tdmc_dout2 {
+					mux {
+						groups = "tdmc_dout2";
+						function = "tdmc";
+					};
+				};
+
+				tdmc_dout3_pins: tdmc_dout3 {
+					mux {
+						groups = "tdmc_dout3";
+						function = "tdmc";
+					};
+				};
+
+				uart_a_pins: uart_a {
+					mux {
+						groups = "uart_tx_a",
+							 "uart_rx_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart_a_cts_rts {
+					mux {
+						groups = "uart_cts_a",
+							 "uart_rts_a";
+						function = "uart_a";
+					};
+				};
+
+				uart_b_x_pins: uart_b_x {
+					mux {
+						groups = "uart_tx_b_x",
+							 "uart_rx_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+					mux {
+						groups = "uart_cts_b_x",
+							 "uart_rts_b_x";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_pins: uart_b_z {
+					mux {
+						groups = "uart_tx_b_z",
+							 "uart_rx_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+					mux {
+						groups = "uart_cts_b_z",
+							 "uart_rts_b_z";
+						function = "uart_b";
+					};
+				};
+
+				uart_ao_b_z_pins: uart_ao_b_z {
+					mux {
+						groups = "uart_ao_tx_b_z",
+							 "uart_ao_rx_b_z";
+						function = "uart_ao_b_z";
+					};
+				};
+
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b_z",
+							 "uart_ao_rts_b_z";
+						function = "uart_ao_b_z";
+					};
+				};
+			};
+		};
+
+		hiubus: bus at ff63c000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff63c000 0x0 0x1c00>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+
+			sysctrl: system-controller at 0 {
+				compatible = "amlogic,meson-axg-hhi-sysctrl",
+					     "simple-mfd", "syscon";
+				reg = <0 0 0 0x400>;
+
+				clkc: clock-controller {
+					compatible = "amlogic,axg-clkc";
+					#clock-cells = <1>;
+				};
+			};
+		};
+
+		mailbox: mailbox at ff63dc00 {
+			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+			reg = <0 0xff63dc00 0 0x400>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+			#mbox-cells = <1>;
+		};
+
+		audio: bus at ff642000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff642000 0x0 0x2000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
+
+			clkc_audio: clock-controller at 0 {
+				compatible = "amlogic,axg-audio-clkc";
+				reg = <0x0 0x0 0x0 0xb4>;
+				#clock-cells = <1>;
+
+				clocks = <&clkc CLKID_AUDIO>,
+					 <&clkc CLKID_MPLL0>,
+					 <&clkc CLKID_MPLL1>,
+					 <&clkc CLKID_MPLL2>,
+					 <&clkc CLKID_MPLL3>,
+					 <&clkc CLKID_HIFI_PLL>,
+					 <&clkc CLKID_FCLK_DIV3>,
+					 <&clkc CLKID_FCLK_DIV4>,
+					 <&clkc CLKID_GP0_PLL>;
+				clock-names = "pclk",
+					      "mst_in0",
+					      "mst_in1",
+					      "mst_in2",
+					      "mst_in3",
+					      "mst_in4",
+					      "mst_in5",
+					      "mst_in6",
+					      "mst_in7";
+
+				resets = <&reset RESET_AUDIO>;
+			};
+
+			toddr_a: audio-controller at 100 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x100 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_A";
+				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+				resets = <&arb AXG_ARB_TODDR_A>;
+				status = "disabled";
+			};
+
+			toddr_b: audio-controller at 140 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x140 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_B";
+				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+				resets = <&arb AXG_ARB_TODDR_B>;
+				status = "disabled";
+			};
+
+			toddr_c: audio-controller at 180 {
+				compatible = "amlogic,axg-toddr";
+				reg = <0x0 0x180 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "TODDR_C";
+				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+				resets = <&arb AXG_ARB_TODDR_C>;
+				status = "disabled";
+			};
+
+			frddr_a: audio-controller at 1c0 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x1c0 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_A";
+				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+				resets = <&arb AXG_ARB_FRDDR_A>;
+				status = "disabled";
+			};
+
+			frddr_b: audio-controller at 200 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x200 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_B";
+				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+				resets = <&arb AXG_ARB_FRDDR_B>;
+				status = "disabled";
+			};
+
+			frddr_c: audio-controller at 240 {
+				compatible = "amlogic,axg-frddr";
+				reg = <0x0 0x240 0x0 0x1c>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "FRDDR_C";
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+				resets = <&arb AXG_ARB_FRDDR_C>;
+				status = "disabled";
+			};
+
+			arb: reset-controller at 280 {
+				compatible = "amlogic,meson-axg-audio-arb";
+				reg = <0x0 0x280 0x0 0x4>;
+				#reset-cells = <1>;
+				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+			};
+
+			tdmin_a: audio-controller at 300 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x300 0x0 0x40>;
+				sound-name-prefix = "TDMIN_A";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_b: audio-controller at 340 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x340 0x0 0x40>;
+				sound-name-prefix = "TDMIN_B";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_c: audio-controller at 380 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x380 0x0 0x40>;
+				sound-name-prefix = "TDMIN_C";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmin_lb: audio-controller at 3c0 {
+				compatible = "amlogic,axg-tdmin";
+				reg = <0x0 0x3c0 0x0 0x40>;
+				sound-name-prefix = "TDMIN_LB";
+				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			spdifout: audio-controller at 480 {
+				compatible = "amlogic,axg-spdifout";
+				reg = <0x0 0x480 0x0 0x50>;
+				#sound-dai-cells = <0>;
+				sound-name-prefix = "SPDIFOUT";
+				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+				clock-names = "pclk", "mclk";
+				status = "disabled";
+			};
+
+			tdmout_a: audio-controller at 500 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x500 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_A";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmout_b: audio-controller at 540 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x540 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_B";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+
+			tdmout_c: audio-controller at 580 {
+				compatible = "amlogic,axg-tdmout";
+				reg = <0x0 0x580 0x0 0x40>;
+				sound-name-prefix = "TDMOUT_C";
+				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
+					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
+				clock-names = "pclk", "sclk", "sclk_sel",
+					      "lrclk", "lrclk_sel";
+				status = "disabled";
+			};
+		};
+
+		aobus: bus at ff800000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xff800000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+
+			sysctrl_AO: sys-ctrl at 0 {
+				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
+				reg =  <0x0 0x0 0x0 0x100>;
+
+				clkc_AO: clock-controller {
+					compatible = "amlogic,meson-axg-aoclkc";
+					#clock-cells = <1>;
+					#reset-cells = <1>;
+				};
+			};
+
+			pinctrl_aobus: pinctrl at 14 {
+				compatible = "amlogic,meson-axg-aobus-pinctrl";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges;
+
+				gpio_ao: bank at 14 {
+					reg = <0x0 0x00014 0x0 0x8>,
+					      <0x0 0x0002c 0x0 0x4>,
+					      <0x0 0x00024 0x0 0x8>;
+					reg-names = "mux", "pull", "gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					gpio-ranges = <&pinctrl_aobus 0 0 15>;
+				};
+
+				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
+					mux {
+						groups = "i2c_ao_sck_4";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
+					mux {
+						groups = "i2c_ao_sck_8";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
+					mux {
+						groups = "i2c_ao_sck_10";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
+					mux {
+						groups = "i2c_ao_sda_5";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
+					mux {
+						groups = "i2c_ao_sda_9";
+						function = "i2c_ao";
+					};
+				};
+
+				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
+					mux {
+						groups = "i2c_ao_sda_11";
+						function = "i2c_ao";
+					};
+				};
+
+				remote_input_ao_pins: remote_input_ao {
+					mux {
+						groups = "remote_input_ao";
+						function = "remote_input_ao";
+					};
+				};
+
+				uart_ao_a_pins: uart_ao_a {
+					mux {
+						groups = "uart_ao_tx_a",
+							 "uart_ao_rx_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+					mux {
+						groups = "uart_ao_cts_a",
+							 "uart_ao_rts_a";
+						function = "uart_ao_a";
+					};
+				};
+
+				uart_ao_b_pins: uart_ao_b {
+					mux {
+						groups = "uart_ao_tx_b",
+							 "uart_ao_rx_b";
+						function = "uart_ao_b";
+					};
+				};
+
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+					mux {
+						groups = "uart_ao_cts_b",
+							 "uart_ao_rts_b";
+						function = "uart_ao_b";
+					};
+				};
+			};
+
+			sec_AO: ao-secure at 140 {
+				compatible = "amlogic,meson-gx-ao-secure", "syscon";
+				reg = <0x0 0x140 0x0 0x140>;
+				amlogic,has-chip-id;
+			};
+
+			pwm_AO_cd: pwm at 2000 {
+				compatible = "amlogic,meson-axg-ao-pwm";
+				reg = <0x0 0x02000  0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			uart_AO: serial at 3000 {
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x3000 0x0 0x18>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+
+			uart_AO_B: serial at 4000 {
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+				reg = <0x0 0x4000 0x0 0x18>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+				status = "disabled";
+			};
+
+			i2c_AO: i2c at 5000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x05000 0x0 0x20>;
+				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_AO_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			pwm_AO_ab: pwm at 7000 {
+				compatible = "amlogic,meson-axg-ao-pwm";
+				reg = <0x0 0x07000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			ir: ir at 8000 {
+				compatible = "amlogic,meson-gxbb-ir";
+				reg = <0x0 0x8000 0x0 0x20>;
+				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
+
+			saradc: adc at 9000 {
+				compatible = "amlogic,meson-axg-saradc",
+					"amlogic,meson-saradc";
+				reg = <0x0 0x9000 0x0 0x38>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>,
+					 <&clkc_AO CLKID_AO_SAR_ADC>,
+					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+				clock-names = "clkin", "core", "adc_clk", "adc_sel";
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller at ffc01000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xffc01000 0 0x1000>,
+			      <0x0 0xffc02000 0 0x2000>,
+			      <0x0 0xffc04000 0 0x2000>,
+			      <0x0 0xffc06000 0 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+
+		cbus: bus at ffd00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffd00000 0x0 0x25000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
+
+			reset: reset-controller at 1004 {
+				compatible = "amlogic,meson-axg-reset";
+				reg = <0x0 0x01004 0x0 0x9c>;
+				#reset-cells = <1>;
+			};
+
+			gpio_intc: interrupt-controller at f080 {
+				compatible = "amlogic,meson-gpio-intc";
+				reg = <0x0 0xf080 0x0 0x10>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+				status = "disabled";
+			};
+
+			pwm_ab: pwm at 1b000 {
+				compatible = "amlogic,meson-axg-ee-pwm";
+				reg = <0x0 0x1b000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_cd: pwm at 1a000 {
+				compatible = "amlogic,meson-axg-ee-pwm";
+				reg = <0x0 0x1a000 0x0 0x20>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			spicc0: spi at 13000 {
+				compatible = "amlogic,meson-axg-spicc";
+				reg = <0x0 0x13000 0x0 0x3c>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC0>;
+				clock-names = "core";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spicc1: spi at 15000 {
+				compatible = "amlogic,meson-axg-spicc";
+				reg = <0x0 0x15000 0x0 0x3c>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_SPICC1>;
+				clock-names = "core";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 1c000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1c000 0x0 0x20>;
+				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 1d000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1d000 0x0 0x20>;
+				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 1e000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1e000 0x0 0x20>;
+				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 1f000 {
+				compatible = "amlogic,meson-axg-i2c";
+				reg = <0x0 0x1f000 0x0 0x20>;
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc CLKID_I2C>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart_B: serial at 23000 {
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x23000 0x0 0x18>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+			};
+
+			uart_A: serial at 24000 {
+				compatible = "amlogic,meson-gx-uart";
+				reg = <0x0 0x24000 0x0 0x18>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+				clock-names = "xtal", "pclk", "baud";
+			};
+		};
+
+		apb: bus at ffe00000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xffe00000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+			sd_emmc_b: sd at 5000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x5000 0x0 0x800>;
+				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_B>,
+					<&clkc CLKID_SD_EMMC_B_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_B>;
+			};
+
+			sd_emmc_c: mmc at 7000 {
+				compatible = "amlogic,meson-axg-mmc";
+				reg = <0x0 0x7000 0x0 0x800>;
+				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+				clocks = <&clkc CLKID_SD_EMMC_C>,
+					<&clkc CLKID_SD_EMMC_C_CLK0>,
+					<&clkc CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_C>;
+			};
+		};
+
+		sram: sram at fffc0000 {
+			compatible = "amlogic,meson-axg-sram", "mmio-sram";
+			reg = <0x0 0xfffc0000 0x0 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x0 0xfffc0000 0x20000>;
+
+			cpu_scp_lpri: scp-shmem at 0 {
+				compatible = "amlogic,meson-axg-scp-shmem";
+				reg = <0x13000 0x400>;
+			};
+
+			cpu_scp_hpri: scp-shmem at 200 {
+				compatible = "amlogic,meson-axg-scp-shmem";
+				reg = <0x13400 0x400>;
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+};
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000000..61955016a5
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
new file mode 100644
index 0000000000..fd9c362099
--- /dev/null
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_SLV_SCLK0		9
+#define AUD_CLKID_SLV_SCLK1		10
+#define AUD_CLKID_SLV_SCLK2		11
+#define AUD_CLKID_SLV_SCLK3		12
+#define AUD_CLKID_SLV_SCLK4		13
+#define AUD_CLKID_SLV_SCLK5		14
+#define AUD_CLKID_SLV_SCLK6		15
+#define AUD_CLKID_SLV_SCLK7		16
+#define AUD_CLKID_SLV_SCLK8		17
+#define AUD_CLKID_SLV_SCLK9		18
+#define AUD_CLKID_SLV_LRCLK0		19
+#define AUD_CLKID_SLV_LRCLK1		20
+#define AUD_CLKID_SLV_LRCLK2		21
+#define AUD_CLKID_SLV_LRCLK3		22
+#define AUD_CLKID_SLV_LRCLK4		23
+#define AUD_CLKID_SLV_LRCLK5		24
+#define AUD_CLKID_SLV_LRCLK6		25
+#define AUD_CLKID_SLV_LRCLK7		26
+#define AUD_CLKID_SLV_LRCLK8		27
+#define AUD_CLKID_SLV_LRCLK9		28
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 0000000000..fd1f938c38
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_MIPI_ENABLE			81
+#define CLKID_GEN_CLK				84
+
+#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
new file mode 100644
index 0000000000..25bb1fffa9
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-axg-gpio.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
+#define _DT_BINDINGS_MESON_AXG_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0	0
+#define GPIOAO_1	1
+#define GPIOAO_2	2
+#define GPIOAO_3	3
+#define GPIOAO_4	4
+#define GPIOAO_5	5
+#define GPIOAO_6	6
+#define GPIOAO_7	7
+#define GPIOAO_8	8
+#define GPIOAO_9	9
+#define GPIOAO_10	10
+#define GPIOAO_11	11
+#define GPIOAO_12	12
+#define GPIOAO_13	13
+#define GPIO_TEST_N 14
+
+/* Second GPIO chip */
+#define GPIOZ_0		0
+#define GPIOZ_1		1
+#define GPIOZ_2		2
+#define GPIOZ_3		3
+#define GPIOZ_4		4
+#define GPIOZ_5		5
+#define GPIOZ_6		6
+#define GPIOZ_7		7
+#define GPIOZ_8		8
+#define GPIOZ_9		9
+#define GPIOZ_10	10
+#define BOOT_0		11
+#define BOOT_1		12
+#define BOOT_2		13
+#define BOOT_3		14
+#define BOOT_4		15
+#define BOOT_5		16
+#define BOOT_6		17
+#define BOOT_7		18
+#define BOOT_8		19
+#define BOOT_9		20
+#define BOOT_10		21
+#define BOOT_11		22
+#define BOOT_12		23
+#define BOOT_13		24
+#define BOOT_14		25
+#define GPIOA_0	    26
+#define GPIOA_1		27
+#define GPIOA_2		28
+#define GPIOA_3		29
+#define GPIOA_4		30
+#define GPIOA_5		31
+#define GPIOA_6		32
+#define GPIOA_7		33
+#define GPIOA_8		34
+#define GPIOA_9		35
+#define GPIOA_10	36
+#define GPIOA_11	37
+#define GPIOA_12	38
+#define GPIOA_13	39
+#define GPIOA_14	40
+#define GPIOA_15	41
+#define GPIOA_16	42
+#define GPIOA_17	43
+#define GPIOA_18	44
+#define GPIOA_19	45
+#define GPIOA_20	46
+#define GPIOX_0		47
+#define GPIOX_1		48
+#define GPIOX_2		49
+#define GPIOX_3		50
+#define GPIOX_4		51
+#define GPIOX_5		52
+#define GPIOX_6		53
+#define GPIOX_7		54
+#define GPIOX_8		55
+#define GPIOX_9		56
+#define GPIOX_10	57
+#define GPIOX_11	58
+#define GPIOX_12	59
+#define GPIOX_13	60
+#define GPIOX_14	61
+#define GPIOX_15	62
+#define GPIOX_16	63
+#define GPIOX_17	64
+#define GPIOX_18	65
+#define GPIOX_19	66
+#define GPIOX_20	67
+#define GPIOX_21	68
+#define GPIOX_22	69
+#define GPIOY_0		70
+#define GPIOY_1		71
+#define GPIOY_2		72
+#define GPIOY_3		73
+#define GPIOY_4		74
+#define GPIOY_5		75
+#define GPIOY_6		76
+#define GPIOY_7		77
+#define GPIOY_8		78
+#define GPIOY_9		79
+#define GPIOY_10	80
+#define GPIOY_11	81
+#define GPIOY_12	82
+#define GPIOY_13	83
+#define GPIOY_14	84
+#define GPIOY_15	85
+
+#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
new file mode 100644
index 0000000000..05c3636787
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ *
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+
+#define AXG_ARB_TODDR_A	0
+#define AXG_ARB_TODDR_B	1
+#define AXG_ARB_TODDR_C	2
+#define AXG_ARB_FRDDR_A	3
+#define AXG_ARB_FRDDR_B	4
+#define AXG_ARB_FRDDR_C	5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
new file mode 100644
index 0000000000..ad6f55dabd
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
@@ -0,0 +1,124 @@
+/*
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+
+/*	RESET0					*/
+#define RESET_HIU			0
+#define RESET_PCIE_A			1
+#define RESET_PCIE_B			2
+#define RESET_DDR_TOP			3
+/*					4	*/
+#define RESET_VIU			5
+#define RESET_PCIE_PHY			6
+#define RESET_PCIE_APB			7
+/*					8	*/
+/*					9	*/
+#define RESET_VENC			10
+#define RESET_ASSIST			11
+/*					12	*/
+#define RESET_VCBUS			13
+/*					14	*/
+/*					15	*/
+#define RESET_GIC			16
+#define RESET_CAPB3_DECODE		17
+/*					18-21	*/
+#define RESET_SYS_CPU_CAPB3		22
+#define RESET_CBUS_CAPB3		23
+#define RESET_AHB_CNTL			24
+#define RESET_AHB_DATA			25
+#define RESET_VCBUS_CLK81		26
+#define RESET_MMC			27
+/*					28-31	*/
+/*	RESET1					*/
+/*					32	*/
+/*					33	*/
+#define RESET_USB_OTG			34
+#define RESET_DDR			35
+#define RESET_AO_RESET			36
+/*					37	*/
+#define RESET_AHB_SRAM			38
+/*					39	*/
+/*					40	*/
+#define RESET_DMA			41
+#define RESET_ISA			42
+#define RESET_ETHERNET			43
+/*					44	*/
+#define RESET_SD_EMMC_B			45
+#define RESET_SD_EMMC_C			46
+#define RESET_ROM_BOOT			47
+#define RESET_SYS_CPU_0			48
+#define RESET_SYS_CPU_1			49
+#define RESET_SYS_CPU_2			50
+#define RESET_SYS_CPU_3			51
+#define RESET_SYS_CPU_CORE_0		52
+#define RESET_SYS_CPU_CORE_1		53
+#define RESET_SYS_CPU_CORE_2		54
+#define RESET_SYS_CPU_CORE_3		55
+#define RESET_SYS_PLL_DIV		56
+#define RESET_SYS_CPU_AXI		57
+#define RESET_SYS_CPU_L2		58
+#define RESET_SYS_CPU_P			59
+#define RESET_SYS_CPU_MBIST		60
+/*					61-63	*/
+/*	RESET2					*/
+/*					64	*/
+/*					65	*/
+#define RESET_AUDIO			66
+/*					67	*/
+#define RESET_MIPI_HOST			68
+#define RESET_AUDIO_LOCKER		69
+#define RESET_GE2D			70
+/*					71-76	*/
+#define RESET_AO_CPU_RESET		77
+/*					78-95	*/
+/*	RESET3					*/
+#define RESET_RING_OSCILLATOR		96
+/*					97-127	*/
+/*	RESET4					*/
+/*					128	*/
+/*					129	*/
+#define RESET_MIPI_PHY			130
+/*					131-140	*/
+#define RESET_VENCL			141
+#define RESET_I2C_MASTER_2		142
+#define RESET_I2C_MASTER_1		143
+/*					144-159	*/
+/*	RESET5					*/
+/*					160-191	*/
+/*	RESET6					*/
+#define RESET_PERIPHS_GENERAL		192
+#define RESET_PERIPHS_SPICC		193
+/*					194	*/
+/*					195	*/
+#define RESET_PERIPHS_I2C_MASTER_0	196
+/*					197-200	*/
+#define RESET_PERIPHS_UART_0		201
+#define RESET_PERIPHS_UART_1		202
+/*					203-204	*/
+#define RESET_PERIPHS_SPI_0		205
+#define RESET_PERIPHS_I2C_MASTER_3	206
+/*					207-223	*/
+/*	RESET7					*/
+#define RESET_USB_DDR_0			224
+#define RESET_USB_DDR_1			225
+#define RESET_USB_DDR_2			226
+#define RESET_USB_DDR_3			227
+/*					228	*/
+#define RESET_DEVICE_MMC_ARB		229
+/*					230	*/
+#define RESET_VID_LOCK			231
+#define RESET_A9_DMC_PIPEL		232
+#define RESET_DMC_VPU_PIPEL		233
+/*					234-255	*/
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 0000000000..d342c0b6b2
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 16/19] clk: Add clock driver for AXG
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/clock-axg.h | 104 +++++++
 drivers/clk/Makefile                        |   2 +-
 drivers/clk/clk_meson_axg.c                 | 316 ++++++++++++++++++++
 3 files changed, 421 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
 create mode 100644 drivers/clk/clk_meson_axg.c

diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h
new file mode 100644
index 0000000000..1ef88e4fad
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-axg.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_AXG_H_
+#define _ARCH_MESON_CLOCK_AXG_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+#define HHI_GP0_PLL_CNTL		0x40
+#define HHI_GP0_PLL_CNTL2		0x44
+#define HHI_GP0_PLL_CNTL3		0x48
+#define HHI_GP0_PLL_CNTL4		0x4c
+#define HHI_GP0_PLL_CNTL5		0x50
+#define HHI_GP0_PLL_STS			0x54
+#define HHI_GP0_PLL_CNTL1		0x58
+#define HHI_HIFI_PLL_CNTL		0x80
+#define HHI_HIFI_PLL_CNTL2		0x84
+#define HHI_HIFI_PLL_CNTL3		0x88
+#define HHI_HIFI_PLL_CNTL4		0x8C
+#define HHI_HIFI_PLL_CNTL5		0x90
+#define HHI_HIFI_PLL_STS		0x94
+#define HHI_HIFI_PLL_CNTL1		0x98
+
+#define HHI_XTAL_DIVN_CNTL		0xbc
+#define HHI_GCLK2_MPEG0			0xc0
+#define HHI_GCLK2_MPEG1			0xc4
+#define HHI_GCLK2_MPEG2			0xc8
+#define HHI_GCLK2_OTHER			0xd0
+#define HHI_GCLK2_AO			0xd4
+#define HHI_PCIE_PLL_CNTL		0xd8
+#define HHI_PCIE_PLL_CNTL1		0xdC
+#define HHI_PCIE_PLL_CNTL2		0xe0
+#define HHI_PCIE_PLL_CNTL3		0xe4
+#define HHI_PCIE_PLL_CNTL4		0xe8
+#define HHI_PCIE_PLL_CNTL5		0xec
+#define HHI_PCIE_PLL_CNTL6		0xf0
+#define HHI_PCIE_PLL_STS		0xf4
+
+#define HHI_MEM_PD_REG0			0x100
+#define HHI_VPU_MEM_PD_REG0		0x104
+#define HHI_VIID_CLK_DIV		0x128
+#define HHI_VIID_CLK_CNTL		0x12c
+
+#define HHI_GCLK_MPEG0			0x140
+#define HHI_GCLK_MPEG1			0x144
+#define HHI_GCLK_MPEG2			0x148
+#define HHI_GCLK_OTHER			0x150
+#define HHI_GCLK_AO			0x154
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c
+#define HHI_SYS_CPU_RESET_CNTL		0x160
+#define HHI_VID_CLK_DIV			0x164
+#define HHI_SPICC_HCLK_CNTL		0x168
+
+#define HHI_MPEG_CLK_CNTL		0x174
+#define HHI_VID_CLK_CNTL		0x17c
+#define HHI_TS_CLK_CNTL			0x190
+#define HHI_VID_CLK_CNTL2		0x194
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c
+#define HHI_VID_PLL_CLK_DIV		0x1a0
+#define HHI_VPU_CLK_CNTL		0x1bC
+
+#define HHI_VAPBCLK_CNTL		0x1F4
+
+#define HHI_GEN_CLK_CNTL		0x228
+
+#define HHI_VDIN_MEAS_CLK_CNTL		0x250
+#define HHI_NAND_CLK_CNTL		0x25C
+#define HHI_SD_EMMC_CLK_CNTL		0x264
+
+#define HHI_MPLL_CNTL			0x280
+#define HHI_MPLL_CNTL2			0x284
+#define HHI_MPLL_CNTL3			0x288
+#define HHI_MPLL_CNTL4			0x28C
+#define HHI_MPLL_CNTL5			0x290
+#define HHI_MPLL_CNTL6			0x294
+#define HHI_MPLL_CNTL7			0x298
+#define HHI_MPLL_CNTL8			0x29C
+#define HHI_MPLL_CNTL9			0x2A0
+#define HHI_MPLL_CNTL10			0x2A4
+
+#define HHI_MPLL3_CNTL0			0x2E0
+#define HHI_MPLL3_CNTL1			0x2E4
+#define HHI_PLL_TOP_MISC		0x2E8
+
+#define HHI_SYS_PLL_CNTL1		0x2FC
+#define HHI_SYS_PLL_CNTL		0x300
+#define HHI_SYS_PLL_CNTL2		0x304
+#define HHI_SYS_PLL_CNTL3		0x308
+#define HHI_SYS_PLL_CNTL4		0x30c
+#define HHI_SYS_PLL_CNTL5		0x310
+#define HHI_SYS_PLL_STS			0x314
+#define HHI_DPLL_TOP_I			0x318
+#define HHI_DPLL_TOP2_I			0x31C
+
+#endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 821b5867e8..a6962453a1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
 obj-y += imx/
 obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_ARCH_SOCFPGA) += altera/
 obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/clk_meson_axg.c
new file mode 100644
index 0000000000..32cbf752ae
--- /dev/null
+++ b/drivers/clk/clk_meson_axg.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock-axg.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <div64.h>
+#include <dt-bindings/clock/axg-clkc.h>
+#include "clk_meson.h"
+
+#define XTAL_RATE 24000000
+
+struct meson_clk {
+	struct regmap *map;
+};
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
+
+static struct meson_gate gates[] = {
+	/* Everything Else (EE) domain gates */
+	MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
+	MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
+	MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
+	MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
+	MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
+	MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
+	MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
+	MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
+
+	/* Always On (AO) domain gates */
+	MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
+
+	/* PLL Gates */
+	/* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
+	MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
+	/* CLKID_CLK81 is critical for the system */
+
+	/* Peripheral Gates */
+	MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
+	MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
+};
+
+static int meson_set_gate(struct clk *clk, bool on)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct meson_gate *gate;
+
+	if (clk->id >= ARRAY_SIZE(gates))
+		return -ENOENT;
+
+	gate = &gates[clk->id];
+
+	if (gate->reg == 0)
+		return 0;
+
+	regmap_update_bits(priv->map, gate->reg,
+			   BIT(gate->bit), on ? BIT(gate->bit) : 0);
+
+	return 0;
+}
+
+static int meson_clk_enable(struct clk *clk)
+{
+	return meson_set_gate(clk, true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+	return meson_set_gate(clk, false);
+}
+
+static unsigned long meson_clk81_get_rate(struct clk *clk)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	unsigned long parent_rate;
+	uint reg;
+	int parents[] = {
+		-1,
+		-1,
+		CLKID_FCLK_DIV7,
+		CLKID_MPLL1,
+		CLKID_MPLL2,
+		CLKID_FCLK_DIV4,
+		CLKID_FCLK_DIV3,
+		CLKID_FCLK_DIV5
+	};
+
+	/* mux */
+	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
+	reg = (reg >> 12) & 7;
+
+	switch (reg) {
+	case 0:
+		parent_rate = XTAL_RATE;
+		break;
+	case 1:
+		return -ENOENT;
+	default:
+		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
+	}
+
+	/* divider */
+	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
+	reg = reg & ((1 << 7) - 1);
+
+	return parent_rate / reg;
+}
+
+static long mpll_rate_from_params(unsigned long parent_rate,
+				  unsigned long sdm,
+				  unsigned long n2)
+{
+	unsigned long divisor = (SDM_DEN * n2) + sdm;
+
+	if (n2 < N2_MIN)
+		return -EINVAL;
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
+}
+
+static struct parm meson_mpll0_parm[3] = {
+	{HHI_MPLL_CNTL7, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll1_parm[3] = {
+	{HHI_MPLL_CNTL8, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll2_parm[3] = {
+	{HHI_MPLL_CNTL9, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
+};
+
+/*
+ * MultiPhase Locked Loops are outputs from a PLL with additional frequency
+ * scaling capabilities. MPLL rates are calculated as:
+ *
+ * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
+ */
+static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct parm *psdm, *pn2;
+	unsigned long sdm, n2;
+	unsigned long parent_rate;
+	uint reg;
+
+	switch (id) {
+	case CLKID_MPLL0:
+		psdm = &meson_mpll0_parm[0];
+		pn2 = &meson_mpll0_parm[1];
+		break;
+	case CLKID_MPLL1:
+		psdm = &meson_mpll1_parm[0];
+		pn2 = &meson_mpll1_parm[1];
+		break;
+	case CLKID_MPLL2:
+		psdm = &meson_mpll2_parm[0];
+		pn2 = &meson_mpll2_parm[1];
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
+	if (IS_ERR_VALUE(parent_rate))
+		return parent_rate;
+
+	regmap_read(priv->map, psdm->reg_off, &reg);
+	sdm = PARM_GET(psdm->width, psdm->shift, reg);
+
+	regmap_read(priv->map, pn2->reg_off, &reg);
+	n2 = PARM_GET(pn2->width, pn2->shift, reg);
+
+	return mpll_rate_from_params(parent_rate, sdm, n2);
+}
+
+static struct parm meson_fixed_pll_parm[3] = {
+	{HHI_MPLL_CNTL, 0, 9}, /* pm */
+	{HHI_MPLL_CNTL, 9, 5}, /* pn */
+	{HHI_MPLL_CNTL, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+	{HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
+	{HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
+	{HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
+};
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct parm *pm, *pn, *pod;
+	unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
+	u16 n, m, od;
+	uint reg;
+
+	switch (id) {
+	case CLKID_FIXED_PLL:
+		pm = &meson_fixed_pll_parm[0];
+		pn = &meson_fixed_pll_parm[1];
+		pod = &meson_fixed_pll_parm[2];
+		break;
+	case CLKID_SYS_PLL:
+		pm = &meson_sys_pll_parm[0];
+		pn = &meson_sys_pll_parm[1];
+		pod = &meson_sys_pll_parm[2];
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	regmap_read(priv->map, pn->reg_off, &reg);
+	n = PARM_GET(pn->width, pn->shift, reg);
+
+	regmap_read(priv->map, pm->reg_off, &reg);
+	m = PARM_GET(pm->width, pm->shift, reg);
+
+	regmap_read(priv->map, pod->reg_off, &reg);
+	od = PARM_GET(pod->width, pod->shift, reg);
+
+	return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
+{
+	ulong rate;
+
+	switch (id) {
+	case CLKID_FIXED_PLL:
+	case CLKID_SYS_PLL:
+		rate = meson_pll_get_rate(clk, id);
+		break;
+	case CLKID_FCLK_DIV2:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+		break;
+	case CLKID_FCLK_DIV3:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+		break;
+	case CLKID_FCLK_DIV4:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+		break;
+	case CLKID_FCLK_DIV5:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+		break;
+	case CLKID_FCLK_DIV7:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+		break;
+	case CLKID_MPLL0:
+	case CLKID_MPLL1:
+	case CLKID_MPLL2:
+		rate = meson_mpll_get_rate(clk, id);
+		break;
+	case CLKID_CLK81:
+		rate = meson_clk81_get_rate(clk);
+		break;
+	default:
+		if (gates[id].reg != 0) {
+			/* a clock gate */
+			rate = meson_clk81_get_rate(clk);
+			break;
+		}
+		return -ENOENT;
+	}
+
+	debug("clock %lu has rate %lu\n", id, rate);
+	return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+	return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static int meson_clk_probe(struct udevice *dev)
+{
+	struct meson_clk *priv = dev_get_priv(dev);
+
+	priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+	if (IS_ERR(priv->map))
+		return PTR_ERR(priv->map);
+
+	debug("meson-clk-axg: probed\n");
+
+	return 0;
+}
+
+static struct clk_ops meson_clk_ops = {
+	.disable	= meson_clk_disable,
+	.enable		= meson_clk_enable,
+	.get_rate	= meson_clk_get_rate,
+};
+
+static const struct udevice_id meson_clk_ids[] = {
+	{ .compatible = "amlogic,axg-clkc" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_clk_axg) = {
+	.name		= "meson_clk_axg",
+	.id		= UCLASS_CLK,
+	.of_match	= meson_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct meson_clk),
+	.ops		= &meson_clk_ops,
+	.probe		= meson_clk_probe,
+};
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 16/19] clk: Add clock driver for AXG
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/clock-axg.h | 104 +++++++
 drivers/clk/Makefile                        |   2 +-
 drivers/clk/clk_meson_axg.c                 | 316 ++++++++++++++++++++
 3 files changed, 421 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
 create mode 100644 drivers/clk/clk_meson_axg.c

diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h
new file mode 100644
index 0000000000..1ef88e4fad
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-axg.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_AXG_H_
+#define _ARCH_MESON_CLOCK_AXG_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+#define HHI_GP0_PLL_CNTL		0x40
+#define HHI_GP0_PLL_CNTL2		0x44
+#define HHI_GP0_PLL_CNTL3		0x48
+#define HHI_GP0_PLL_CNTL4		0x4c
+#define HHI_GP0_PLL_CNTL5		0x50
+#define HHI_GP0_PLL_STS			0x54
+#define HHI_GP0_PLL_CNTL1		0x58
+#define HHI_HIFI_PLL_CNTL		0x80
+#define HHI_HIFI_PLL_CNTL2		0x84
+#define HHI_HIFI_PLL_CNTL3		0x88
+#define HHI_HIFI_PLL_CNTL4		0x8C
+#define HHI_HIFI_PLL_CNTL5		0x90
+#define HHI_HIFI_PLL_STS		0x94
+#define HHI_HIFI_PLL_CNTL1		0x98
+
+#define HHI_XTAL_DIVN_CNTL		0xbc
+#define HHI_GCLK2_MPEG0			0xc0
+#define HHI_GCLK2_MPEG1			0xc4
+#define HHI_GCLK2_MPEG2			0xc8
+#define HHI_GCLK2_OTHER			0xd0
+#define HHI_GCLK2_AO			0xd4
+#define HHI_PCIE_PLL_CNTL		0xd8
+#define HHI_PCIE_PLL_CNTL1		0xdC
+#define HHI_PCIE_PLL_CNTL2		0xe0
+#define HHI_PCIE_PLL_CNTL3		0xe4
+#define HHI_PCIE_PLL_CNTL4		0xe8
+#define HHI_PCIE_PLL_CNTL5		0xec
+#define HHI_PCIE_PLL_CNTL6		0xf0
+#define HHI_PCIE_PLL_STS		0xf4
+
+#define HHI_MEM_PD_REG0			0x100
+#define HHI_VPU_MEM_PD_REG0		0x104
+#define HHI_VIID_CLK_DIV		0x128
+#define HHI_VIID_CLK_CNTL		0x12c
+
+#define HHI_GCLK_MPEG0			0x140
+#define HHI_GCLK_MPEG1			0x144
+#define HHI_GCLK_MPEG2			0x148
+#define HHI_GCLK_OTHER			0x150
+#define HHI_GCLK_AO			0x154
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c
+#define HHI_SYS_CPU_RESET_CNTL		0x160
+#define HHI_VID_CLK_DIV			0x164
+#define HHI_SPICC_HCLK_CNTL		0x168
+
+#define HHI_MPEG_CLK_CNTL		0x174
+#define HHI_VID_CLK_CNTL		0x17c
+#define HHI_TS_CLK_CNTL			0x190
+#define HHI_VID_CLK_CNTL2		0x194
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c
+#define HHI_VID_PLL_CLK_DIV		0x1a0
+#define HHI_VPU_CLK_CNTL		0x1bC
+
+#define HHI_VAPBCLK_CNTL		0x1F4
+
+#define HHI_GEN_CLK_CNTL		0x228
+
+#define HHI_VDIN_MEAS_CLK_CNTL		0x250
+#define HHI_NAND_CLK_CNTL		0x25C
+#define HHI_SD_EMMC_CLK_CNTL		0x264
+
+#define HHI_MPLL_CNTL			0x280
+#define HHI_MPLL_CNTL2			0x284
+#define HHI_MPLL_CNTL3			0x288
+#define HHI_MPLL_CNTL4			0x28C
+#define HHI_MPLL_CNTL5			0x290
+#define HHI_MPLL_CNTL6			0x294
+#define HHI_MPLL_CNTL7			0x298
+#define HHI_MPLL_CNTL8			0x29C
+#define HHI_MPLL_CNTL9			0x2A0
+#define HHI_MPLL_CNTL10			0x2A4
+
+#define HHI_MPLL3_CNTL0			0x2E0
+#define HHI_MPLL3_CNTL1			0x2E4
+#define HHI_PLL_TOP_MISC		0x2E8
+
+#define HHI_SYS_PLL_CNTL1		0x2FC
+#define HHI_SYS_PLL_CNTL		0x300
+#define HHI_SYS_PLL_CNTL2		0x304
+#define HHI_SYS_PLL_CNTL3		0x308
+#define HHI_SYS_PLL_CNTL4		0x30c
+#define HHI_SYS_PLL_CNTL5		0x310
+#define HHI_SYS_PLL_STS			0x314
+#define HHI_DPLL_TOP_I			0x318
+#define HHI_DPLL_TOP2_I			0x31C
+
+#endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 821b5867e8..a6962453a1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
 obj-y += imx/
 obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_ARCH_SOCFPGA) += altera/
 obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/clk_meson_axg.c
new file mode 100644
index 0000000000..32cbf752ae
--- /dev/null
+++ b/drivers/clk/clk_meson_axg.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * (C) Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock-axg.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <div64.h>
+#include <dt-bindings/clock/axg-clkc.h>
+#include "clk_meson.h"
+
+#define XTAL_RATE 24000000
+
+struct meson_clk {
+	struct regmap *map;
+};
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
+
+static struct meson_gate gates[] = {
+	/* Everything Else (EE) domain gates */
+	MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
+	MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
+	MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
+	MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
+	MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
+	MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
+	MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
+	MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
+
+	/* Always On (AO) domain gates */
+	MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
+
+	/* PLL Gates */
+	/* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
+	MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
+	/* CLKID_CLK81 is critical for the system */
+
+	/* Peripheral Gates */
+	MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
+	MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
+};
+
+static int meson_set_gate(struct clk *clk, bool on)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct meson_gate *gate;
+
+	if (clk->id >= ARRAY_SIZE(gates))
+		return -ENOENT;
+
+	gate = &gates[clk->id];
+
+	if (gate->reg == 0)
+		return 0;
+
+	regmap_update_bits(priv->map, gate->reg,
+			   BIT(gate->bit), on ? BIT(gate->bit) : 0);
+
+	return 0;
+}
+
+static int meson_clk_enable(struct clk *clk)
+{
+	return meson_set_gate(clk, true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+	return meson_set_gate(clk, false);
+}
+
+static unsigned long meson_clk81_get_rate(struct clk *clk)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	unsigned long parent_rate;
+	uint reg;
+	int parents[] = {
+		-1,
+		-1,
+		CLKID_FCLK_DIV7,
+		CLKID_MPLL1,
+		CLKID_MPLL2,
+		CLKID_FCLK_DIV4,
+		CLKID_FCLK_DIV3,
+		CLKID_FCLK_DIV5
+	};
+
+	/* mux */
+	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
+	reg = (reg >> 12) & 7;
+
+	switch (reg) {
+	case 0:
+		parent_rate = XTAL_RATE;
+		break;
+	case 1:
+		return -ENOENT;
+	default:
+		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
+	}
+
+	/* divider */
+	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
+	reg = reg & ((1 << 7) - 1);
+
+	return parent_rate / reg;
+}
+
+static long mpll_rate_from_params(unsigned long parent_rate,
+				  unsigned long sdm,
+				  unsigned long n2)
+{
+	unsigned long divisor = (SDM_DEN * n2) + sdm;
+
+	if (n2 < N2_MIN)
+		return -EINVAL;
+
+	return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
+}
+
+static struct parm meson_mpll0_parm[3] = {
+	{HHI_MPLL_CNTL7, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll1_parm[3] = {
+	{HHI_MPLL_CNTL8, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
+};
+
+static struct parm meson_mpll2_parm[3] = {
+	{HHI_MPLL_CNTL9, 0, 14}, /* psdm */
+	{HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
+};
+
+/*
+ * MultiPhase Locked Loops are outputs from a PLL with additional frequency
+ * scaling capabilities. MPLL rates are calculated as:
+ *
+ * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
+ */
+static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct parm *psdm, *pn2;
+	unsigned long sdm, n2;
+	unsigned long parent_rate;
+	uint reg;
+
+	switch (id) {
+	case CLKID_MPLL0:
+		psdm = &meson_mpll0_parm[0];
+		pn2 = &meson_mpll0_parm[1];
+		break;
+	case CLKID_MPLL1:
+		psdm = &meson_mpll1_parm[0];
+		pn2 = &meson_mpll1_parm[1];
+		break;
+	case CLKID_MPLL2:
+		psdm = &meson_mpll2_parm[0];
+		pn2 = &meson_mpll2_parm[1];
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
+	if (IS_ERR_VALUE(parent_rate))
+		return parent_rate;
+
+	regmap_read(priv->map, psdm->reg_off, &reg);
+	sdm = PARM_GET(psdm->width, psdm->shift, reg);
+
+	regmap_read(priv->map, pn2->reg_off, &reg);
+	n2 = PARM_GET(pn2->width, pn2->shift, reg);
+
+	return mpll_rate_from_params(parent_rate, sdm, n2);
+}
+
+static struct parm meson_fixed_pll_parm[3] = {
+	{HHI_MPLL_CNTL, 0, 9}, /* pm */
+	{HHI_MPLL_CNTL, 9, 5}, /* pn */
+	{HHI_MPLL_CNTL, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+	{HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
+	{HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
+	{HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
+};
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+	struct meson_clk *priv = dev_get_priv(clk->dev);
+	struct parm *pm, *pn, *pod;
+	unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
+	u16 n, m, od;
+	uint reg;
+
+	switch (id) {
+	case CLKID_FIXED_PLL:
+		pm = &meson_fixed_pll_parm[0];
+		pn = &meson_fixed_pll_parm[1];
+		pod = &meson_fixed_pll_parm[2];
+		break;
+	case CLKID_SYS_PLL:
+		pm = &meson_sys_pll_parm[0];
+		pn = &meson_sys_pll_parm[1];
+		pod = &meson_sys_pll_parm[2];
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	regmap_read(priv->map, pn->reg_off, &reg);
+	n = PARM_GET(pn->width, pn->shift, reg);
+
+	regmap_read(priv->map, pm->reg_off, &reg);
+	m = PARM_GET(pm->width, pm->shift, reg);
+
+	regmap_read(priv->map, pod->reg_off, &reg);
+	od = PARM_GET(pod->width, pod->shift, reg);
+
+	return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
+{
+	ulong rate;
+
+	switch (id) {
+	case CLKID_FIXED_PLL:
+	case CLKID_SYS_PLL:
+		rate = meson_pll_get_rate(clk, id);
+		break;
+	case CLKID_FCLK_DIV2:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+		break;
+	case CLKID_FCLK_DIV3:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+		break;
+	case CLKID_FCLK_DIV4:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+		break;
+	case CLKID_FCLK_DIV5:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+		break;
+	case CLKID_FCLK_DIV7:
+		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+		break;
+	case CLKID_MPLL0:
+	case CLKID_MPLL1:
+	case CLKID_MPLL2:
+		rate = meson_mpll_get_rate(clk, id);
+		break;
+	case CLKID_CLK81:
+		rate = meson_clk81_get_rate(clk);
+		break;
+	default:
+		if (gates[id].reg != 0) {
+			/* a clock gate */
+			rate = meson_clk81_get_rate(clk);
+			break;
+		}
+		return -ENOENT;
+	}
+
+	debug("clock %lu has rate %lu\n", id, rate);
+	return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+	return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static int meson_clk_probe(struct udevice *dev)
+{
+	struct meson_clk *priv = dev_get_priv(dev);
+
+	priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
+	if (IS_ERR(priv->map))
+		return PTR_ERR(priv->map);
+
+	debug("meson-clk-axg: probed\n");
+
+	return 0;
+}
+
+static struct clk_ops meson_clk_ops = {
+	.disable	= meson_clk_disable,
+	.enable		= meson_clk_enable,
+	.get_rate	= meson_clk_get_rate,
+};
+
+static const struct udevice_id meson_clk_ids[] = {
+	{ .compatible = "amlogic,axg-clkc" },
+	{ }
+};
+
+U_BOOT_DRIVER(meson_clk_axg) = {
+	.name		= "meson_clk_axg",
+	.id		= UCLASS_CLK,
+	.of_match	= meson_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct meson_clk),
+	.ops		= &meson_clk_ops,
+	.probe		= meson_clk_probe,
+};
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 17/19] board: amlogic: add support for S400 board
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

The S400 board is the Amlogic AXG SoC reference board including :
 - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
 - 1GB DDR4 SDRAM
 - 10/100 Ethernet
 - 2 x USB 2.0 Host
 - eMMC
 - Infrared receiver
 - SDIO WiFi Module
 - MIPI DSI Connector
 - Audio HAT Connector
 - PCI-E M.2 Connectors

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig    |   1 +
 board/amlogic/s400/MAINTAINERS |   6 ++
 board/amlogic/s400/Makefile    |   6 ++
 board/amlogic/s400/README      | 110 +++++++++++++++++++++++++++++++++
 board/amlogic/s400/s400.c      |  33 ++++++++++
 configs/s400_defconfig         |  38 ++++++++++++
 6 files changed, 194 insertions(+)
 create mode 100644 board/amlogic/s400/MAINTAINERS
 create mode 100644 board/amlogic/s400/Makefile
 create mode 100644 board/amlogic/s400/README
 create mode 100644 board/amlogic/s400/s400.c
 create mode 100644 configs/s400_defconfig

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 7f217facd1..deddcc5ab0 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -63,6 +63,7 @@ config SYS_BOARD
 	default "odroid-c2" if MESON_GXBB
 	default "p212" if MESON_GXL
 	default "q200" if MESON_GXM
+	default "s400" if MESON_AXG
 	default ""
 	help
 	  This option contains information about board name.
diff --git a/board/amlogic/s400/MAINTAINERS b/board/amlogic/s400/MAINTAINERS
new file mode 100644
index 0000000000..9ca9836016
--- /dev/null
+++ b/board/amlogic/s400/MAINTAINERS
@@ -0,0 +1,6 @@
+S400
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+F:	board/amlogic/s400/
+F:	include/configs/s400.h
+F:	configs/s400_defconfig
diff --git a/board/amlogic/s400/Makefile b/board/amlogic/s400/Makefile
new file mode 100644
index 0000000000..bf03862b90
--- /dev/null
+++ b/board/amlogic/s400/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= s400.o
diff --git a/board/amlogic/s400/README b/board/amlogic/s400/README
new file mode 100644
index 0000000000..ab21998dc8
--- /dev/null
+++ b/board/amlogic/s400/README
@@ -0,0 +1,110 @@
+U-Boot for Amlogic S400
+=======================
+
+S400 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - 1GB DDR4 SDRAM
+ - 10/100 Ethernet
+ - 2 x USB 2.0 Host
+ - eMMC
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connectors
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make s400_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make axg_s400_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/axg/bl2.bin fip/
+ > cp $FIPDIR/axg/acs.bin fip/
+ > cp $FIPDIR/axg/bl21.bin fip/
+ > cp $FIPDIR/axg/bl30.bin fip/
+ > cp $FIPDIR/axg/bl301.bin fip/
+ > cp $FIPDIR/axg/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl30.bin \
+	fip/zero_tmp \
+	fip/bl30_zero.bin \
+	fip/bl301.bin \
+	fip/bl301_zero.bin \
+	fip/bl30_new.bin \
+	bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl2_acs.bin \
+	fip/zero_tmp \
+	fip/bl2_zero.bin \
+	fip/bl21.bin \
+	fip/bl21_zero.bin \
+	fip/bl2_new.bin \
+	bl2
+
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
+					--output fip/bl30_new.bin.enc \
+					--level v3 --type bl30
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
+					--output fip/bl31.img.enc \
+					--level v3 --type bl31
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
+					--output fip/bl33.bin.enc \
+					--level v3 --type bl33
+ > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
+					--output fip/bl2.n.bin.sig
+ > $FIPDIR/axg/aml_encrypt_axg --bootmk \
+		--output fip/u-boot.bin \
+		--bl2 fip/bl2.n.bin.sig \
+		--bl30 fip/bl30_new.bin.enc \
+		--bl31 fip/bl31.img.enc \
+		--bl33 fip/bl33.bin.enc --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
new file mode 100644
index 0000000000..c2b50f6c17
--- /dev/null
+++ b/board/amlogic/s400/s400.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	meson_init_reserved_memory(blob);
+
+	return 0;
+}
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
new file mode 100644
index 0000000000..1bd4b7127b
--- /dev/null
+++ b/configs/s400_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_AXG=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" s400"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_AXG=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 17/19] board: amlogic: add support for S400 board
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

The S400 board is the Amlogic AXG SoC reference board including :
 - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
 - 1GB DDR4 SDRAM
 - 10/100 Ethernet
 - 2 x USB 2.0 Host
 - eMMC
 - Infrared receiver
 - SDIO WiFi Module
 - MIPI DSI Connector
 - Audio HAT Connector
 - PCI-E M.2 Connectors

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/Kconfig    |   1 +
 board/amlogic/s400/MAINTAINERS |   6 ++
 board/amlogic/s400/Makefile    |   6 ++
 board/amlogic/s400/README      | 110 +++++++++++++++++++++++++++++++++
 board/amlogic/s400/s400.c      |  33 ++++++++++
 configs/s400_defconfig         |  38 ++++++++++++
 6 files changed, 194 insertions(+)
 create mode 100644 board/amlogic/s400/MAINTAINERS
 create mode 100644 board/amlogic/s400/Makefile
 create mode 100644 board/amlogic/s400/README
 create mode 100644 board/amlogic/s400/s400.c
 create mode 100644 configs/s400_defconfig

diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 7f217facd1..deddcc5ab0 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -63,6 +63,7 @@ config SYS_BOARD
 	default "odroid-c2" if MESON_GXBB
 	default "p212" if MESON_GXL
 	default "q200" if MESON_GXM
+	default "s400" if MESON_AXG
 	default ""
 	help
 	  This option contains information about board name.
diff --git a/board/amlogic/s400/MAINTAINERS b/board/amlogic/s400/MAINTAINERS
new file mode 100644
index 0000000000..9ca9836016
--- /dev/null
+++ b/board/amlogic/s400/MAINTAINERS
@@ -0,0 +1,6 @@
+S400
+M:	Neil Armstrong <narmstrong@baylibre.com>
+S:	Maintained
+F:	board/amlogic/s400/
+F:	include/configs/s400.h
+F:	configs/s400_defconfig
diff --git a/board/amlogic/s400/Makefile b/board/amlogic/s400/Makefile
new file mode 100644
index 0000000000..bf03862b90
--- /dev/null
+++ b/board/amlogic/s400/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y	:= s400.o
diff --git a/board/amlogic/s400/README b/board/amlogic/s400/README
new file mode 100644
index 0000000000..ab21998dc8
--- /dev/null
+++ b/board/amlogic/s400/README
@@ -0,0 +1,110 @@
+U-Boot for Amlogic S400
+=======================
+
+S400 is a reference board manufactured by Amlogic with the following
+specifications:
+
+ - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - 1GB DDR4 SDRAM
+ - 10/100 Ethernet
+ - 2 x USB 2.0 Host
+ - eMMC
+ - Infrared receiver
+ - SDIO WiFi Module
+ - MIPI DSI Connector
+ - Audio HAT Connector
+ - PCI-E M.2 Connectors
+
+Schematics are available from Amlogic on demand.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - eMMC
+ - Ethernet
+ - I2C
+ - Regulators
+ - Reset controller
+ - Clock controller
+ - USB Host
+ - ADC
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make s400_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot
+ > cd amlogic-u-boot
+ > make axg_s400_v1_defconfig
+ > make
+ > export FIPDIR=$PWD/fip
+
+Go back to mainline U-boot source tree then :
+ > mkdir fip
+
+ > cp $FIPDIR/axg/bl2.bin fip/
+ > cp $FIPDIR/axg/acs.bin fip/
+ > cp $FIPDIR/axg/bl21.bin fip/
+ > cp $FIPDIR/axg/bl30.bin fip/
+ > cp $FIPDIR/axg/bl301.bin fip/
+ > cp $FIPDIR/axg/bl31.img fip/
+ > cp u-boot.bin fip/bl33.bin
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl30.bin \
+	fip/zero_tmp \
+	fip/bl30_zero.bin \
+	fip/bl301.bin \
+	fip/bl301_zero.bin \
+	fip/bl30_new.bin \
+	bl30
+
+ > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ > $FIPDIR/blx_fix.sh \
+	fip/bl2_acs.bin \
+	fip/zero_tmp \
+	fip/bl2_zero.bin \
+	fip/bl21.bin \
+	fip/bl21_zero.bin \
+	fip/bl2_new.bin \
+	bl2
+
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
+					--output fip/bl30_new.bin.enc \
+					--level v3 --type bl30
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
+					--output fip/bl31.img.enc \
+					--level v3 --type bl31
+ > $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
+					--output fip/bl33.bin.enc \
+					--level v3 --type bl33
+ > $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
+					--output fip/bl2.n.bin.sig
+ > $FIPDIR/axg/aml_encrypt_axg --bootmk \
+		--output fip/u-boot.bin \
+		--bl2 fip/bl2.n.bin.sig \
+		--bl30 fip/bl30_new.bin.enc \
+		--bl31 fip/bl31.img.enc \
+		--bl33 fip/bl33.bin.enc --level v3
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
new file mode 100644
index 0000000000..c2b50f6c17
--- /dev/null
+++ b/board/amlogic/s400/s400.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <environment.h>
+#include <asm/io.h>
+#include <asm/arch/axg.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	meson_init_reserved_memory(blob);
+
+	return 0;
+}
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
new file mode 100644
index 0000000000..1bd4b7127b
--- /dev/null
+++ b/configs/s400_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_AXG=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" s400"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_AXG=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 18/19] ARM: meson: factorize common code out amlogic's boards
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

From: Jerome Brunet <jbrunet@baylibre.com>

Now we have moved all the Amlogic board support to common generic board code,
we can move the identical board_init() and ft_board_setup() functions to
weak functions into the board-common mach-meson file.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/board-common.c  | 17 +++++++++++++++++
 board/amlogic/odroid-c2/odroid-c2.c | 12 ------------
 board/amlogic/p212/p212.c           | 12 ------------
 board/amlogic/q200/q200.c           | 12 ------------
 board/amlogic/s400/s400.c           | 12 ------------
 5 files changed, 17 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 6340445053..8c4f3074fb 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -14,6 +14,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+__weak int board_init(void)
+{
+	return 0;
+}
+
 int dram_init(void)
 {
 	const fdt64_t *val;
@@ -34,6 +39,18 @@ int dram_init(void)
 	return 0;
 }
 
+__weak int meson_ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	meson_init_reserved_memory(blob);
+
+	return meson_ft_board_setup(blob, bd);
+}
+
 void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
 {
 	int ret;
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index d784d6bd09..62f0f4c871 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -17,11 +17,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -46,10 +41,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 33992a2279..546c4d9c86 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -18,11 +18,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -48,10 +43,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index b59c11bd35..6db1b26e08 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -18,11 +18,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -53,10 +48,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
index c2b50f6c17..02a0e9286c 100644
--- a/board/amlogic/s400/s400.c
+++ b/board/amlogic/s400/s400.c
@@ -13,21 +13,9 @@
 #include <asm/arch/eth.h>
 #include <asm/arch/mem.h>
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 18/19] ARM: meson: factorize common code out amlogic's boards
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

From: Jerome Brunet <jbrunet@baylibre.com>

Now we have moved all the Amlogic board support to common generic board code,
we can move the identical board_init() and ft_board_setup() functions to
weak functions into the board-common mach-meson file.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/mach-meson/board-common.c  | 17 +++++++++++++++++
 board/amlogic/odroid-c2/odroid-c2.c | 12 ------------
 board/amlogic/p212/p212.c           | 12 ------------
 board/amlogic/q200/q200.c           | 12 ------------
 board/amlogic/s400/s400.c           | 12 ------------
 5 files changed, 17 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 6340445053..8c4f3074fb 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -14,6 +14,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+__weak int board_init(void)
+{
+	return 0;
+}
+
 int dram_init(void)
 {
 	const fdt64_t *val;
@@ -34,6 +39,18 @@ int dram_init(void)
 	return 0;
 }
 
+__weak int meson_ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	meson_init_reserved_memory(blob);
+
+	return meson_ft_board_setup(blob, bd);
+}
+
 void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
 {
 	int ret;
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index d784d6bd09..62f0f4c871 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -17,11 +17,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -46,10 +41,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 33992a2279..546c4d9c86 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -18,11 +18,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -48,10 +43,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index b59c11bd35..6db1b26e08 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -18,11 +18,6 @@
 #define EFUSE_MAC_OFFSET	52
 #define EFUSE_MAC_SIZE		6
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
@@ -53,10 +48,3 @@ int misc_init_r(void)
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
diff --git a/board/amlogic/s400/s400.c b/board/amlogic/s400/s400.c
index c2b50f6c17..02a0e9286c 100644
--- a/board/amlogic/s400/s400.c
+++ b/board/amlogic/s400/s400.c
@@ -13,21 +13,9 @@
 #include <asm/arch/eth.h>
 #include <asm/arch/mem.h>
 
-int board_init(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
 
 	return 0;
 }
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	meson_init_reserved_memory(blob);
-
-	return 0;
-}
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 19/19] ARM: meson: Add boot device discovery
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-22  9:07   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: u-boot

The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.

When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.

When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.

In this mode, we can load different binaries that can be used by U-boot
like a script image file.

This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.

The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.

[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/axg.h  |  1 +
 arch/arm/include/asm/arch-meson/boot.h | 20 ++++++++++++
 arch/arm/include/asm/arch-meson/gx.h   |  1 +
 arch/arm/mach-meson/Kconfig            |  1 +
 arch/arm/mach-meson/board-axg.c        |  6 ++++
 arch/arm/mach-meson/board-common.c     | 45 ++++++++++++++++++++++++++
 arch/arm/mach-meson/board-gx.c         |  6 ++++
 include/configs/meson64.h              | 13 ++++++++
 8 files changed, 93 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-meson/boot.h

diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
index 28a38b791d..d293f2a839 100644
--- a/arch/arm/include/asm/arch-meson/axg.h
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -20,6 +20,7 @@
 #define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
 #define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
 
+#define AXG_AO_BOOT_DEVICE	0xF
 #define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
 #define AXG_AO_MEM_SIZE_SHIFT	16
 #define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
new file mode 100644
index 0000000000..a90fe55081
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_BOOT_H__
+#define __MESON_BOOT_H__
+
+/* Boot device */
+#define BOOT_DEVICE_RESERVED    0
+#define BOOT_DEVICE_EMMC        1
+#define BOOT_DEVICE_NAND        2
+#define BOOT_DEVICE_SPI         3
+#define BOOT_DEVICE_SD          4
+#define BOOT_DEVICE_USB         5
+
+int meson_get_boot_device(void);
+
+#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
index 4bc9475d35..b781ba9475 100644
--- a/arch/arm/include/asm/arch-meson/gx.h
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -21,6 +21,7 @@
 #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
 #define GX_AO_SEC_GP_CFG5	GX_AO_ADDR(0x95)
 
+#define GX_AO_BOOT_DEVICE	0xF
 #define GX_AO_MEM_SIZE_MASK	0xFFFF0000
 #define GX_AO_MEM_SIZE_SHIFT	16
 #define GX_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index deddcc5ab0..11077bc6cc 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,6 +8,7 @@ config MESON64_COMMON
 	select DM_SERIAL
 	select SYSCON
 	select REGMAP
+	select BOARD_LATE_INIT
 	imply CMD_DM
 
 config MESON_GX
diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c
index 014b25d61a..173905e762 100644
--- a/arch/arm/mach-meson/board-axg.c
+++ b/arch/arm/mach-meson/board-axg.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/axg.h>
 #include <asm/arch/mem.h>
@@ -15,6 +16,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int meson_get_boot_device(void)
+{
+	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
+}
+
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 8c4f3074fb..8c41301674 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <asm/arch/mem.h>
@@ -66,6 +67,50 @@ void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
 	}
 }
 
+static void meson_set_boot_source(void)
+{
+	const char *source;
+
+	switch (meson_get_boot_device()) {
+	case BOOT_DEVICE_EMMC:
+		source = "emmc";
+		break;
+
+	case BOOT_DEVICE_NAND:
+		source = "nand";
+		break;
+
+	case BOOT_DEVICE_SPI:
+		source = "spi";
+		break;
+
+	case BOOT_DEVICE_SD:
+		source = "sd";
+		break;
+
+	case BOOT_DEVICE_USB:
+		source = "usb";
+		break;
+
+	default:
+		source = "unknown";
+	}
+
+	env_set("boot_source", source);
+}
+
+__weak int meson_board_late_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	meson_set_boot_source();
+
+	return meson_board_late_init();
+}
+
 void reset_cpu(ulong addr)
 {
 	psci_system_reset();
diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c
index f1397f87c5..e41552db52 100644
--- a/arch/arm/mach-meson/board-gx.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/gx.h>
 #include <asm/arch/mem.h>
@@ -15,6 +16,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int meson_get_boot_device(void)
+{
+	return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
+}
+
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index f961f43871..40ac079dfc 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -28,6 +28,18 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64 MiB */
 
+/* ROM USB boot support, auto-execute boot.scr@scriptaddr */
+#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
+	"bootcmd_romusb=" \
+		"if test \"${boot_source}\" = \"usb\" && " \
+				"test -n \"${scriptaddr}\"; then " \
+			"echo '(ROM USB boot)'; " \
+			"source ${scriptaddr}; " \
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance)	\
+		"romusb "
+
 #ifdef CONFIG_CMD_USB
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
 #else
@@ -36,6 +48,7 @@
 
 #ifndef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
+	func(ROMUSB, romusb, na)  \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
 	func(MMC, mmc, 2) \
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 19/19] ARM: meson: Add boot device discovery
@ 2018-11-22  9:07   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-22  9:07 UTC (permalink / raw)
  To: linus-amlogic

The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.

When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.

When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.

In this mode, we can load different binaries that can be used by U-boot
like a script image file.

This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.

The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.

[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm/include/asm/arch-meson/axg.h  |  1 +
 arch/arm/include/asm/arch-meson/boot.h | 20 ++++++++++++
 arch/arm/include/asm/arch-meson/gx.h   |  1 +
 arch/arm/mach-meson/Kconfig            |  1 +
 arch/arm/mach-meson/board-axg.c        |  6 ++++
 arch/arm/mach-meson/board-common.c     | 45 ++++++++++++++++++++++++++
 arch/arm/mach-meson/board-gx.c         |  6 ++++
 include/configs/meson64.h              | 13 ++++++++
 8 files changed, 93 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-meson/boot.h

diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
index 28a38b791d..d293f2a839 100644
--- a/arch/arm/include/asm/arch-meson/axg.h
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -20,6 +20,7 @@
 #define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
 #define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
 
+#define AXG_AO_BOOT_DEVICE	0xF
 #define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
 #define AXG_AO_MEM_SIZE_SHIFT	16
 #define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
new file mode 100644
index 0000000000..a90fe55081
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_BOOT_H__
+#define __MESON_BOOT_H__
+
+/* Boot device */
+#define BOOT_DEVICE_RESERVED    0
+#define BOOT_DEVICE_EMMC        1
+#define BOOT_DEVICE_NAND        2
+#define BOOT_DEVICE_SPI         3
+#define BOOT_DEVICE_SD          4
+#define BOOT_DEVICE_USB         5
+
+int meson_get_boot_device(void);
+
+#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
index 4bc9475d35..b781ba9475 100644
--- a/arch/arm/include/asm/arch-meson/gx.h
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -21,6 +21,7 @@
 #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
 #define GX_AO_SEC_GP_CFG5	GX_AO_ADDR(0x95)
 
+#define GX_AO_BOOT_DEVICE	0xF
 #define GX_AO_MEM_SIZE_MASK	0xFFFF0000
 #define GX_AO_MEM_SIZE_SHIFT	16
 #define GX_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index deddcc5ab0..11077bc6cc 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -8,6 +8,7 @@ config MESON64_COMMON
 	select DM_SERIAL
 	select SYSCON
 	select REGMAP
+	select BOARD_LATE_INIT
 	imply CMD_DM
 
 config MESON_GX
diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c
index 014b25d61a..173905e762 100644
--- a/arch/arm/mach-meson/board-axg.c
+++ b/arch/arm/mach-meson/board-axg.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/axg.h>
 #include <asm/arch/mem.h>
@@ -15,6 +16,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int meson_get_boot_device(void)
+{
+	return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
+}
+
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 8c4f3074fb..8c41301674 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <asm/arch/mem.h>
@@ -66,6 +67,50 @@ void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size)
 	}
 }
 
+static void meson_set_boot_source(void)
+{
+	const char *source;
+
+	switch (meson_get_boot_device()) {
+	case BOOT_DEVICE_EMMC:
+		source = "emmc";
+		break;
+
+	case BOOT_DEVICE_NAND:
+		source = "nand";
+		break;
+
+	case BOOT_DEVICE_SPI:
+		source = "spi";
+		break;
+
+	case BOOT_DEVICE_SD:
+		source = "sd";
+		break;
+
+	case BOOT_DEVICE_USB:
+		source = "usb";
+		break;
+
+	default:
+		source = "unknown";
+	}
+
+	env_set("boot_source", source);
+}
+
+__weak int meson_board_late_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	meson_set_boot_source();
+
+	return meson_board_late_init();
+}
+
 void reset_cpu(ulong addr)
 {
 	psci_system_reset();
diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c
index f1397f87c5..e41552db52 100644
--- a/arch/arm/mach-meson/board-gx.c
+++ b/arch/arm/mach-meson/board-gx.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/boot.h>
 #include <asm/arch/eth.h>
 #include <asm/arch/gx.h>
 #include <asm/arch/mem.h>
@@ -15,6 +16,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int meson_get_boot_device(void)
+{
+	return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
+}
+
 /* Configure the reserved memory zones exported by the secure registers
  * into EFI and DTB reserved memory entries.
  */
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index f961f43871..40ac079dfc 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -28,6 +28,18 @@
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64 MiB */
 
+/* ROM USB boot support, auto-execute boot.scr@scriptaddr */
+#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
+	"bootcmd_romusb=" \
+		"if test \"${boot_source}\" = \"usb\" && " \
+				"test -n \"${scriptaddr}\"; then " \
+			"echo '(ROM USB boot)'; " \
+			"source ${scriptaddr}; " \
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance)	\
+		"romusb "
+
 #ifdef CONFIG_CMD_USB
 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
 #else
@@ -36,6 +48,7 @@
 
 #ifndef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
+	func(ROMUSB, romusb, na)  \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
 	func(MMC, mmc, 2) \
-- 
2.19.1

^ permalink raw reply related	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
  2018-11-22  9:07 ` Neil Armstrong
@ 2018-11-26  8:59   ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-26  8:59 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On 22/11/2018 10:07, Neil Armstrong wrote:
> This patchset will refactor the Amlogic Meson SoC support in order to
> easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
> 
> In order :
> - Cleanup the mach-meson configs
> - Move board support to reference design common boards
> - Move board Kconfig into mach-meson
> - Add AXG pinctrl & clock support
> - Add AXG device tree and mach-meson support
> - Add support for S400 reference design
> - Do a final factorization of the code
> - Add USB boot support in U-boot
> 
> At the end of the patches, the board code is lighter and we maintain
> only the reference designs, where each board will differ in the defconfig.
> 
> It will be simpler to add custom board support for future boards with
> more changes against the reference designs.
> 
> The complete AXG support depends on the :
> - mmc: meson-gx: Add AXG compatible
> - net: designware: add meson meson axg compatible
> patches submitted to the U-Boot mailing list.Hi 

Would it be simpler if I send you a pull-request with this patchset and all dependencies ?

Tell me if you have any comments on the patchset and the 2 dependencies !

Thanks,
Neil

> 
> Changes since v1:
> - Fixed AXG pinctrl request and AO pin count
> - Fixed tabs/spaces issues on s400 README
> 
> Jerome Brunet (12):
>   ARM: meson: clean-up platform selection
>   configs: meson: remove unnecessary MESON_FDTFILE_SETTING
>   board: amlogic: remove p212 derivatives
>   board: amlogic: factorise gxbb boards
>   ARM: rework amlogic configuration
>   configs: meson: change default load addresses
>   pinctrl: meson: rework gx pmx function
>   pinctrl: meson: select generic pinctrl
>   pinctrl: meson: add axg support
>   clk: meson: silence debug print
>   ARM: meson: rework soc arch file to prepare for new SoC
>   ARM: meson: factorize common code out amlogic's boards
> 
> Neil Armstrong (7):
>   board: amlogic: move khadas-vim2 as q200 ref board
>   clk: meson: add static to meson_gates table
>   ARM: meson: Add support for AXG family
>   ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
>   clk: Add clock driver for AXG
>   board: amlogic: add support for S400 board
>   ARM: meson: Add boot device discovery
> 
>  arch/arm/dts/Makefile                         |    3 +-
>  arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
>  arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
>  arch/arm/include/asm/arch-meson/axg.h         |   52 +
>  arch/arm/include/asm/arch-meson/boot.h        |   20 +
>  arch/arm/include/asm/arch-meson/clock-axg.h   |  104 ++
>  .../asm/arch-meson/{clock.h => clock-gx.h}    |    4 +-
>  arch/arm/include/asm/arch-meson/eth.h         |    6 +-
>  arch/arm/include/asm/arch-meson/gx.h          |    1 +
>  arch/arm/include/asm/arch-meson/mem.h         |    3 +-
>  arch/arm/mach-meson/Kconfig                   |  132 +-
>  arch/arm/mach-meson/Makefile                  |    4 +-
>  arch/arm/mach-meson/board-axg.c               |  118 ++
>  arch/arm/mach-meson/board-common.c            |  117 ++
>  arch/arm/mach-meson/{board.c => board-gx.c}   |  106 +-
>  arch/arm/mach-meson/eth.c                     |   53 -
>  arch/arm/mach-meson/sm.c                      |    1 -
>  board/amlogic/khadas-vim/Kconfig              |   12 -
>  board/amlogic/khadas-vim/MAINTAINERS          |    6 -
>  board/amlogic/khadas-vim/khadas-vim.c         |   57 -
>  board/amlogic/khadas-vim2/Kconfig             |   12 -
>  board/amlogic/libretech-cc/Kconfig            |   12 -
>  board/amlogic/libretech-cc/MAINTAINERS        |    6 -
>  board/amlogic/libretech-cc/Makefile           |    6 -
>  board/amlogic/libretech-cc/libretech-cc.c     |   57 -
>  board/amlogic/nanopi-k2/Kconfig               |   12 -
>  board/amlogic/nanopi-k2/MAINTAINERS           |    6 -
>  board/amlogic/nanopi-k2/Makefile              |    7 -
>  board/amlogic/nanopi-k2/nanopi-k2.c           |   55 -
>  board/amlogic/odroid-c2/Kconfig               |   12 -
>  board/amlogic/odroid-c2/MAINTAINERS           |    1 +
>  .../README => odroid-c2/README.nanopi-k2}     |    0
>  .../odroid-c2/{README => README.odroid-c2}    |    0
>  board/amlogic/odroid-c2/odroid-c2.c           |   16 +-
>  board/amlogic/p212/Kconfig                    |   12 -
>  .../README => p212/README.khadas-vim}         |    0
>  .../README => p212/README.libretech-cc}       |    0
>  board/amlogic/p212/{README => README.p212}    |    0
>  board/amlogic/p212/p212.c                     |   16 +-
>  .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |    6 +-
>  board/amlogic/{khadas-vim => q200}/Makefile   |    2 +-
>  .../README => q200/README.khadas-vim2}        |    0
>  board/amlogic/q200/README.q200                |  102 ++
>  .../khadas-vim2.c => q200/q200.c}             |   14 +-
>  board/amlogic/s400/MAINTAINERS                |    6 +
>  board/amlogic/{khadas-vim2 => s400}/Makefile  |    2 +-
>  board/amlogic/s400/README                     |  110 ++
>  board/amlogic/s400/s400.c                     |   21 +
>  configs/khadas-vim2_defconfig                 |    1 -
>  configs/khadas-vim_defconfig                  |    1 -
>  configs/libretech-cc_defconfig                |    1 -
>  configs/nanopi-k2_defconfig                   |    2 -
>  configs/odroid-c2_defconfig                   |    1 -
>  configs/p212_defconfig                        |    1 -
>  configs/s400_defconfig                        |   38 +
>  drivers/clk/Makefile                          |    2 +-
>  drivers/clk/clk_meson.c                       |    6 +-
>  drivers/clk/clk_meson_axg.c                   |  316 ++++
>  drivers/pinctrl/meson/Kconfig                 |   18 +-
>  drivers/pinctrl/meson/Makefile                |    3 +
>  drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c |  125 ++
>  drivers/pinctrl/meson/pinctrl-meson-axg.c     |  979 ++++++++++
>  drivers/pinctrl/meson/pinctrl-meson-axg.h     |   66 +
>  drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c  |   97 +
>  drivers/pinctrl/meson/pinctrl-meson-gx.h      |   48 +
>  drivers/pinctrl/meson/pinctrl-meson-gxbb.c    |    6 +-
>  drivers/pinctrl/meson/pinctrl-meson-gxl.c     |    6 +-
>  drivers/pinctrl/meson/pinctrl-meson.c         |  109 +-
>  drivers/pinctrl/meson/pinctrl-meson.h         |   37 +-
>  include/configs/khadas-vim.h                  |   16 -
>  include/configs/khadas-vim2.h                 |   18 -
>  include/configs/libretech-cc.h                |   16 -
>  .../configs/{meson-gx-common.h => meson64.h}  |   49 +-
>  include/configs/nanopi-k2.h                   |   16 -
>  include/configs/odroid-c2.h                   |   16 -
>  include/configs/p212.h                        |   18 -
>  include/dt-bindings/clock/axg-aoclkc.h        |   26 +
>  include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
>  include/dt-bindings/clock/axg-clkc.h          |   76 +
>  include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
>  .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
>  .../reset/amlogic,meson-axg-reset.h           |  124 ++
>  include/dt-bindings/reset/axg-aoclkc.h        |   20 +
>  83 files changed, 5166 insertions(+), 754 deletions(-)
>  create mode 100644 arch/arm/dts/meson-axg-s400.dts
>  create mode 100644 arch/arm/dts/meson-axg.dtsi
>  create mode 100644 arch/arm/include/asm/arch-meson/axg.h
>  create mode 100644 arch/arm/include/asm/arch-meson/boot.h
>  create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
>  rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
>  create mode 100644 arch/arm/mach-meson/board-axg.c
>  create mode 100644 arch/arm/mach-meson/board-common.c
>  rename arch/arm/mach-meson/{board.c => board-gx.c} (59%)
>  delete mode 100644 arch/arm/mach-meson/eth.c
>  delete mode 100644 board/amlogic/khadas-vim/Kconfig
>  delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
>  delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
>  delete mode 100644 board/amlogic/khadas-vim2/Kconfig
>  delete mode 100644 board/amlogic/libretech-cc/Kconfig
>  delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
>  delete mode 100644 board/amlogic/libretech-cc/Makefile
>  delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
>  delete mode 100644 board/amlogic/nanopi-k2/Kconfig
>  delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
>  delete mode 100644 board/amlogic/nanopi-k2/Makefile
>  delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
>  delete mode 100644 board/amlogic/odroid-c2/Kconfig
>  rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
>  rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)
>  delete mode 100644 board/amlogic/p212/Kconfig
>  rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
>  rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
>  rename board/amlogic/p212/{README => README.p212} (100%)
>  rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
>  rename board/amlogic/{khadas-vim => q200}/Makefile (85%)
>  rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
>  create mode 100644 board/amlogic/q200/README.q200
>  rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (85%)
>  create mode 100644 board/amlogic/s400/MAINTAINERS
>  rename board/amlogic/{khadas-vim2 => s400}/Makefile (84%)
>  create mode 100644 board/amlogic/s400/README
>  create mode 100644 board/amlogic/s400/s400.c
>  create mode 100644 configs/s400_defconfig
>  create mode 100644 drivers/clk/clk_meson_axg.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h
>  delete mode 100644 include/configs/khadas-vim.h
>  delete mode 100644 include/configs/khadas-vim2.h
>  delete mode 100644 include/configs/libretech-cc.h
>  rename include/configs/{meson-gx-common.h => meson64.h} (51%)
>  delete mode 100644 include/configs/nanopi-k2.h
>  delete mode 100644 include/configs/odroid-c2.h
>  delete mode 100644 include/configs/p212.h
>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>  create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
>  create mode 100644 include/dt-bindings/clock/axg-clkc.h
>  create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
>  create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
>  create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> 

^ permalink raw reply	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
@ 2018-11-26  8:59   ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-26  8:59 UTC (permalink / raw)
  To: linus-amlogic

Hi Tom,

On 22/11/2018 10:07, Neil Armstrong wrote:
> This patchset will refactor the Amlogic Meson SoC support in order to
> easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
> 
> In order :
> - Cleanup the mach-meson configs
> - Move board support to reference design common boards
> - Move board Kconfig into mach-meson
> - Add AXG pinctrl & clock support
> - Add AXG device tree and mach-meson support
> - Add support for S400 reference design
> - Do a final factorization of the code
> - Add USB boot support in U-boot
> 
> At the end of the patches, the board code is lighter and we maintain
> only the reference designs, where each board will differ in the defconfig.
> 
> It will be simpler to add custom board support for future boards with
> more changes against the reference designs.
> 
> The complete AXG support depends on the :
> - mmc: meson-gx: Add AXG compatible
> - net: designware: add meson meson axg compatible
> patches submitted to the U-Boot mailing list.Hi 

Would it be simpler if I send you a pull-request with this patchset and all dependencies ?

Tell me if you have any comments on the patchset and the 2 dependencies !

Thanks,
Neil

> 
> Changes since v1:
> - Fixed AXG pinctrl request and AO pin count
> - Fixed tabs/spaces issues on s400 README
> 
> Jerome Brunet (12):
>   ARM: meson: clean-up platform selection
>   configs: meson: remove unnecessary MESON_FDTFILE_SETTING
>   board: amlogic: remove p212 derivatives
>   board: amlogic: factorise gxbb boards
>   ARM: rework amlogic configuration
>   configs: meson: change default load addresses
>   pinctrl: meson: rework gx pmx function
>   pinctrl: meson: select generic pinctrl
>   pinctrl: meson: add axg support
>   clk: meson: silence debug print
>   ARM: meson: rework soc arch file to prepare for new SoC
>   ARM: meson: factorize common code out amlogic's boards
> 
> Neil Armstrong (7):
>   board: amlogic: move khadas-vim2 as q200 ref board
>   clk: meson: add static to meson_gates table
>   ARM: meson: Add support for AXG family
>   ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1
>   clk: Add clock driver for AXG
>   board: amlogic: add support for S400 board
>   ARM: meson: Add boot device discovery
> 
>  arch/arm/dts/Makefile                         |    3 +-
>  arch/arm/dts/meson-axg-s400.dts               |  554 ++++++
>  arch/arm/dts/meson-axg.dtsi                   | 1589 +++++++++++++++++
>  arch/arm/include/asm/arch-meson/axg.h         |   52 +
>  arch/arm/include/asm/arch-meson/boot.h        |   20 +
>  arch/arm/include/asm/arch-meson/clock-axg.h   |  104 ++
>  .../asm/arch-meson/{clock.h => clock-gx.h}    |    4 +-
>  arch/arm/include/asm/arch-meson/eth.h         |    6 +-
>  arch/arm/include/asm/arch-meson/gx.h          |    1 +
>  arch/arm/include/asm/arch-meson/mem.h         |    3 +-
>  arch/arm/mach-meson/Kconfig                   |  132 +-
>  arch/arm/mach-meson/Makefile                  |    4 +-
>  arch/arm/mach-meson/board-axg.c               |  118 ++
>  arch/arm/mach-meson/board-common.c            |  117 ++
>  arch/arm/mach-meson/{board.c => board-gx.c}   |  106 +-
>  arch/arm/mach-meson/eth.c                     |   53 -
>  arch/arm/mach-meson/sm.c                      |    1 -
>  board/amlogic/khadas-vim/Kconfig              |   12 -
>  board/amlogic/khadas-vim/MAINTAINERS          |    6 -
>  board/amlogic/khadas-vim/khadas-vim.c         |   57 -
>  board/amlogic/khadas-vim2/Kconfig             |   12 -
>  board/amlogic/libretech-cc/Kconfig            |   12 -
>  board/amlogic/libretech-cc/MAINTAINERS        |    6 -
>  board/amlogic/libretech-cc/Makefile           |    6 -
>  board/amlogic/libretech-cc/libretech-cc.c     |   57 -
>  board/amlogic/nanopi-k2/Kconfig               |   12 -
>  board/amlogic/nanopi-k2/MAINTAINERS           |    6 -
>  board/amlogic/nanopi-k2/Makefile              |    7 -
>  board/amlogic/nanopi-k2/nanopi-k2.c           |   55 -
>  board/amlogic/odroid-c2/Kconfig               |   12 -
>  board/amlogic/odroid-c2/MAINTAINERS           |    1 +
>  .../README => odroid-c2/README.nanopi-k2}     |    0
>  .../odroid-c2/{README => README.odroid-c2}    |    0
>  board/amlogic/odroid-c2/odroid-c2.c           |   16 +-
>  board/amlogic/p212/Kconfig                    |   12 -
>  .../README => p212/README.khadas-vim}         |    0
>  .../README => p212/README.libretech-cc}       |    0
>  board/amlogic/p212/{README => README.p212}    |    0
>  board/amlogic/p212/p212.c                     |   16 +-
>  .../amlogic/{khadas-vim2 => q200}/MAINTAINERS |    6 +-
>  board/amlogic/{khadas-vim => q200}/Makefile   |    2 +-
>  .../README => q200/README.khadas-vim2}        |    0
>  board/amlogic/q200/README.q200                |  102 ++
>  .../khadas-vim2.c => q200/q200.c}             |   14 +-
>  board/amlogic/s400/MAINTAINERS                |    6 +
>  board/amlogic/{khadas-vim2 => s400}/Makefile  |    2 +-
>  board/amlogic/s400/README                     |  110 ++
>  board/amlogic/s400/s400.c                     |   21 +
>  configs/khadas-vim2_defconfig                 |    1 -
>  configs/khadas-vim_defconfig                  |    1 -
>  configs/libretech-cc_defconfig                |    1 -
>  configs/nanopi-k2_defconfig                   |    2 -
>  configs/odroid-c2_defconfig                   |    1 -
>  configs/p212_defconfig                        |    1 -
>  configs/s400_defconfig                        |   38 +
>  drivers/clk/Makefile                          |    2 +-
>  drivers/clk/clk_meson.c                       |    6 +-
>  drivers/clk/clk_meson_axg.c                   |  316 ++++
>  drivers/pinctrl/meson/Kconfig                 |   18 +-
>  drivers/pinctrl/meson/Makefile                |    3 +
>  drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c |  125 ++
>  drivers/pinctrl/meson/pinctrl-meson-axg.c     |  979 ++++++++++
>  drivers/pinctrl/meson/pinctrl-meson-axg.h     |   66 +
>  drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c  |   97 +
>  drivers/pinctrl/meson/pinctrl-meson-gx.h      |   48 +
>  drivers/pinctrl/meson/pinctrl-meson-gxbb.c    |    6 +-
>  drivers/pinctrl/meson/pinctrl-meson-gxl.c     |    6 +-
>  drivers/pinctrl/meson/pinctrl-meson.c         |  109 +-
>  drivers/pinctrl/meson/pinctrl-meson.h         |   37 +-
>  include/configs/khadas-vim.h                  |   16 -
>  include/configs/khadas-vim2.h                 |   18 -
>  include/configs/libretech-cc.h                |   16 -
>  .../configs/{meson-gx-common.h => meson64.h}  |   49 +-
>  include/configs/nanopi-k2.h                   |   16 -
>  include/configs/odroid-c2.h                   |   16 -
>  include/configs/p212.h                        |   18 -
>  include/dt-bindings/clock/axg-aoclkc.h        |   26 +
>  include/dt-bindings/clock/axg-audio-clkc.h    |   94 +
>  include/dt-bindings/clock/axg-clkc.h          |   76 +
>  include/dt-bindings/gpio/meson-axg-gpio.h     |  116 ++
>  .../reset/amlogic,meson-axg-audio-arb.h       |   17 +
>  .../reset/amlogic,meson-axg-reset.h           |  124 ++
>  include/dt-bindings/reset/axg-aoclkc.h        |   20 +
>  83 files changed, 5166 insertions(+), 754 deletions(-)
>  create mode 100644 arch/arm/dts/meson-axg-s400.dts
>  create mode 100644 arch/arm/dts/meson-axg.dtsi
>  create mode 100644 arch/arm/include/asm/arch-meson/axg.h
>  create mode 100644 arch/arm/include/asm/arch-meson/boot.h
>  create mode 100644 arch/arm/include/asm/arch-meson/clock-axg.h
>  rename arch/arm/include/asm/arch-meson/{clock.h => clock-gx.h} (98%)
>  create mode 100644 arch/arm/mach-meson/board-axg.c
>  create mode 100644 arch/arm/mach-meson/board-common.c
>  rename arch/arm/mach-meson/{board.c => board-gx.c} (59%)
>  delete mode 100644 arch/arm/mach-meson/eth.c
>  delete mode 100644 board/amlogic/khadas-vim/Kconfig
>  delete mode 100644 board/amlogic/khadas-vim/MAINTAINERS
>  delete mode 100644 board/amlogic/khadas-vim/khadas-vim.c
>  delete mode 100644 board/amlogic/khadas-vim2/Kconfig
>  delete mode 100644 board/amlogic/libretech-cc/Kconfig
>  delete mode 100644 board/amlogic/libretech-cc/MAINTAINERS
>  delete mode 100644 board/amlogic/libretech-cc/Makefile
>  delete mode 100644 board/amlogic/libretech-cc/libretech-cc.c
>  delete mode 100644 board/amlogic/nanopi-k2/Kconfig
>  delete mode 100644 board/amlogic/nanopi-k2/MAINTAINERS
>  delete mode 100644 board/amlogic/nanopi-k2/Makefile
>  delete mode 100644 board/amlogic/nanopi-k2/nanopi-k2.c
>  delete mode 100644 board/amlogic/odroid-c2/Kconfig
>  rename board/amlogic/{nanopi-k2/README => odroid-c2/README.nanopi-k2} (100%)
>  rename board/amlogic/odroid-c2/{README => README.odroid-c2} (100%)
>  delete mode 100644 board/amlogic/p212/Kconfig
>  rename board/amlogic/{khadas-vim/README => p212/README.khadas-vim} (100%)
>  rename board/amlogic/{libretech-cc/README => p212/README.libretech-cc} (100%)
>  rename board/amlogic/p212/{README => README.p212} (100%)
>  rename board/amlogic/{khadas-vim2 => q200}/MAINTAINERS (54%)
>  rename board/amlogic/{khadas-vim => q200}/Makefile (85%)
>  rename board/amlogic/{khadas-vim2/README => q200/README.khadas-vim2} (100%)
>  create mode 100644 board/amlogic/q200/README.q200
>  rename board/amlogic/{khadas-vim2/khadas-vim2.c => q200/q200.c} (85%)
>  create mode 100644 board/amlogic/s400/MAINTAINERS
>  rename board/amlogic/{khadas-vim2 => s400}/Makefile (84%)
>  create mode 100644 board/amlogic/s400/README
>  create mode 100644 board/amlogic/s400/s400.c
>  create mode 100644 configs/s400_defconfig
>  create mode 100644 drivers/clk/clk_meson_axg.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-axg.h
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
>  create mode 100644 drivers/pinctrl/meson/pinctrl-meson-gx.h
>  delete mode 100644 include/configs/khadas-vim.h
>  delete mode 100644 include/configs/khadas-vim2.h
>  delete mode 100644 include/configs/libretech-cc.h
>  rename include/configs/{meson-gx-common.h => meson64.h} (51%)
>  delete mode 100644 include/configs/nanopi-k2.h
>  delete mode 100644 include/configs/odroid-c2.h
>  delete mode 100644 include/configs/p212.h
>  create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
>  create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h
>  create mode 100644 include/dt-bindings/clock/axg-clkc.h
>  create mode 100644 include/dt-bindings/gpio/meson-axg-gpio.h
>  create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
>  create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-reset.h
>  create mode 100644 include/dt-bindings/reset/axg-aoclkc.h
> 

^ permalink raw reply	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
  2018-11-26  8:59   ` Neil Armstrong
@ 2018-11-26 12:58     ` Tom Rini
  -1 siblings, 0 replies; 46+ messages in thread
From: Tom Rini @ 2018-11-26 12:58 UTC (permalink / raw)
  To: u-boot

On Mon, Nov 26, 2018 at 09:59:33AM +0100, Neil Armstrong wrote:
> Hi Tom,
> 
> On 22/11/2018 10:07, Neil Armstrong wrote:
> > This patchset will refactor the Amlogic Meson SoC support in order to
> > easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
> > 
> > In order :
> > - Cleanup the mach-meson configs
> > - Move board support to reference design common boards
> > - Move board Kconfig into mach-meson
> > - Add AXG pinctrl & clock support
> > - Add AXG device tree and mach-meson support
> > - Add support for S400 reference design
> > - Do a final factorization of the code
> > - Add USB boot support in U-boot
> > 
> > At the end of the patches, the board code is lighter and we maintain
> > only the reference designs, where each board will differ in the defconfig.
> > 
> > It will be simpler to add custom board support for future boards with
> > more changes against the reference designs.
> > 
> > The complete AXG support depends on the :
> > - mmc: meson-gx: Add AXG compatible
> > - net: designware: add meson meson axg compatible
> > patches submitted to the U-Boot mailing list.Hi 
> 
> Would it be simpler if I send you a pull-request with this patchset
> and all dependencies ?
> 
> Tell me if you have any comments on the patchset and the 2
> dependencies !

Sure, lets try that.  Do you want to get a tree setup on git.denx.de or
will you use github/etc?  Traditionally we host things on git.denx.de
but at least Alex has been doing the EFI and RPi stuff from his github
instead, and I'm fine taking a signed tag to pull from either.  Thanks!

-- 
Tom
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^ permalink raw reply	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
@ 2018-11-26 12:58     ` Tom Rini
  0 siblings, 0 replies; 46+ messages in thread
From: Tom Rini @ 2018-11-26 12:58 UTC (permalink / raw)
  To: linus-amlogic

On Mon, Nov 26, 2018 at 09:59:33AM +0100, Neil Armstrong wrote:
> Hi Tom,
> 
> On 22/11/2018 10:07, Neil Armstrong wrote:
> > This patchset will refactor the Amlogic Meson SoC support in order to
> > easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
> > 
> > In order :
> > - Cleanup the mach-meson configs
> > - Move board support to reference design common boards
> > - Move board Kconfig into mach-meson
> > - Add AXG pinctrl & clock support
> > - Add AXG device tree and mach-meson support
> > - Add support for S400 reference design
> > - Do a final factorization of the code
> > - Add USB boot support in U-boot
> > 
> > At the end of the patches, the board code is lighter and we maintain
> > only the reference designs, where each board will differ in the defconfig.
> > 
> > It will be simpler to add custom board support for future boards with
> > more changes against the reference designs.
> > 
> > The complete AXG support depends on the :
> > - mmc: meson-gx: Add AXG compatible
> > - net: designware: add meson meson axg compatible
> > patches submitted to the U-Boot mailing list.Hi 
> 
> Would it be simpler if I send you a pull-request with this patchset
> and all dependencies ?
> 
> Tell me if you have any comments on the patchset and the 2
> dependencies !

Sure, lets try that.  Do you want to get a tree setup on git.denx.de or
will you use github/etc?  Traditionally we host things on git.denx.de
but at least Alex has been doing the EFI and RPi stuff from his github
instead, and I'm fine taking a signed tag to pull from either.  Thanks!

-- 
Tom
-------------- next part --------------
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^ permalink raw reply	[flat|nested] 46+ messages in thread
* [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
  2018-11-26 12:58     ` Tom Rini
@ 2018-11-26 13:34       ` Neil Armstrong
  -1 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-26 13:34 UTC (permalink / raw)
  To: u-boot

Hi Tom,

On 26/11/2018 13:58, Tom Rini wrote:
> On Mon, Nov 26, 2018 at 09:59:33AM +0100, Neil Armstrong wrote:
>> Hi Tom,
>>
>> On 22/11/2018 10:07, Neil Armstrong wrote:
>>> This patchset will refactor the Amlogic Meson SoC support in order to
>>> easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
>>>
>>> In order :
>>> - Cleanup the mach-meson configs
>>> - Move board support to reference design common boards
>>> - Move board Kconfig into mach-meson
>>> - Add AXG pinctrl & clock support
>>> - Add AXG device tree and mach-meson support
>>> - Add support for S400 reference design
>>> - Do a final factorization of the code
>>> - Add USB boot support in U-boot
>>>
>>> At the end of the patches, the board code is lighter and we maintain
>>> only the reference designs, where each board will differ in the defconfig.
>>>
>>> It will be simpler to add custom board support for future boards with
>>> more changes against the reference designs.
>>>
>>> The complete AXG support depends on the :
>>> - mmc: meson-gx: Add AXG compatible
>>> - net: designware: add meson meson axg compatible
>>> patches submitted to the U-Boot mailing list.Hi 
>>
>> Would it be simpler if I send you a pull-request with this patchset
>> and all dependencies ?
>>
>> Tell me if you have any comments on the patchset and the 2
>> dependencies !
> 
> Sure, lets try that.  Do you want to get a tree setup on git.denx.de or
> will you use github/etc?  Traditionally we host things on git.denx.de
> but at least Alex has been doing the EFI and RPi stuff from his github
> instead, and I'm fine taking a signed tag to pull from either.  Thanks!
> 

I'll be happy to have a tree on git.denx.de if it's the best way to go,
but until it's done I can do a PR from github if it's ok for you !

Neil

-------------- next part --------------
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^ permalink raw reply	[flat|nested] 46+ messages in thread
* [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support
@ 2018-11-26 13:34       ` Neil Armstrong
  0 siblings, 0 replies; 46+ messages in thread
From: Neil Armstrong @ 2018-11-26 13:34 UTC (permalink / raw)
  To: linus-amlogic

Hi Tom,

On 26/11/2018 13:58, Tom Rini wrote:
> On Mon, Nov 26, 2018 at 09:59:33AM +0100, Neil Armstrong wrote:
>> Hi Tom,
>>
>> On 22/11/2018 10:07, Neil Armstrong wrote:
>>> This patchset will refactor the Amlogic Meson SoC support in order to
>>> easily add support for the Amlogic AXg SoC family, and later the G12x SoCs.
>>>
>>> In order :
>>> - Cleanup the mach-meson configs
>>> - Move board support to reference design common boards
>>> - Move board Kconfig into mach-meson
>>> - Add AXG pinctrl & clock support
>>> - Add AXG device tree and mach-meson support
>>> - Add support for S400 reference design
>>> - Do a final factorization of the code
>>> - Add USB boot support in U-boot
>>>
>>> At the end of the patches, the board code is lighter and we maintain
>>> only the reference designs, where each board will differ in the defconfig.
>>>
>>> It will be simpler to add custom board support for future boards with
>>> more changes against the reference designs.
>>>
>>> The complete AXG support depends on the :
>>> - mmc: meson-gx: Add AXG compatible
>>> - net: designware: add meson meson axg compatible
>>> patches submitted to the U-Boot mailing list.Hi 
>>
>> Would it be simpler if I send you a pull-request with this patchset
>> and all dependencies ?
>>
>> Tell me if you have any comments on the patchset and the 2
>> dependencies !
> 
> Sure, lets try that.  Do you want to get a tree setup on git.denx.de or
> will you use github/etc?  Traditionally we host things on git.denx.de
> but at least Alex has been doing the EFI and RPi stuff from his github
> instead, and I'm fine taking a signed tag to pull from either.  Thanks!
> 

I'll be happy to have a tree on git.denx.de if it's the best way to go,
but until it's done I can do a PR from github if it's ok for you !

Neil

-------------- next part --------------
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^ permalink raw reply	[flat|nested] 46+ messages in thread
end of thread, other threads:[~2018-11-26 13:34 UTC | newest]

Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-22  9:07 [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support Neil Armstrong
2018-11-22  9:07 ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 01/19] ARM: meson: clean-up platform selection Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 02/19] configs: meson: remove unnecessary MESON_FDTFILE_SETTING Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 03/19] board: amlogic: remove p212 derivatives Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 04/19] board: amlogic: move khadas-vim2 as q200 ref board Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 05/19] board: amlogic: factorise gxbb boards Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 06/19] ARM: rework amlogic configuration Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 07/19] configs: meson: change default load addresses Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 08/19] pinctrl: meson: rework gx pmx function Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 09/19] pinctrl: meson: select generic pinctrl Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 10/19] pinctrl: meson: add axg support Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 11/19] clk: meson: add static to meson_gates table Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 12/19] clk: meson: silence debug print Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 13/19] ARM: meson: rework soc arch file to prepare for new SoC Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 14/19] ARM: meson: Add support for AXG family Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 15/19] ARM: dts: Sync Amlogic Meson AXG DT from Linux 4.20-rc1 Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 16/19] clk: Add clock driver for AXG Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 17/19] board: amlogic: add support for S400 board Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 18/19] ARM: meson: factorize common code out amlogic's boards Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-22  9:07 ` [U-Boot] [PATCH u-boot v2 19/19] ARM: meson: Add boot device discovery Neil Armstrong
2018-11-22  9:07   ` Neil Armstrong
2018-11-26  8:59 ` [U-Boot] [PATCH u-boot v2 00/19] Amlogic Meson cleanup for AXG SoC support Neil Armstrong
2018-11-26  8:59   ` Neil Armstrong
2018-11-26 12:58   ` [U-Boot] " Tom Rini
2018-11-26 12:58     ` Tom Rini
2018-11-26 13:34     ` [U-Boot] " Neil Armstrong
2018-11-26 13:34       ` Neil Armstrong

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