[PATCH 1/6] drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entities

[PATCH 1/6] drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entities

[Alex Deucher]

Looks like it was missed when setting support was added.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index f9b54236102d..95f4c4139fc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
 	[AMDGPU_HW_IP_UVD_ENC]	=	1,
 	[AMDGPU_HW_IP_VCN_DEC]	=	1,
 	[AMDGPU_HW_IP_VCN_ENC]	=	1,
+	[AMDGPU_HW_IP_VCN_JPEG]	=	1,
 };
 
 static int amdgput_ctx_total_num_entities(void)
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/6] drm/amdgpu: make amdgpu_ctx_init more robust

[Alex Deucher]

Only set up the scheduling entities if the rings are
valid.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 83 ++++++++++++++++++++++++---------
 1 file changed, 61 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 95f4c4139fc6..d12eb863285b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 			   struct amdgpu_ctx *ctx)
 {
 	unsigned num_entities = amdgput_ctx_total_num_entities();
-	unsigned i, j;
+	unsigned i, j, k;
 	int r;
 
 	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -123,46 +123,85 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
 		struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
 		struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
-		unsigned num_rings;
+		unsigned num_rings = 0;
 
 		switch (i) {
 		case AMDGPU_HW_IP_GFX:
-			rings[0] = &adev->gfx.gfx_ring[0];
-			num_rings = 1;
+			for (j = 0; j < adev->gfx.num_gfx_rings; j++) {
+				if (adev->gfx.gfx_ring[j].sched.ready)
+					rings[num_rings++] = &adev->gfx.gfx_ring[j];
+			}
 			break;
 		case AMDGPU_HW_IP_COMPUTE:
-			for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-				rings[j] = &adev->gfx.compute_ring[j];
-			num_rings = adev->gfx.num_compute_rings;
+			for (j = 0; j < adev->gfx.num_compute_rings; ++j) {
+				if (adev->gfx.compute_ring[j].sched.ready)
+					rings[num_rings++] = &adev->gfx.compute_ring[j];
+			}
 			break;
 		case AMDGPU_HW_IP_DMA:
-			for (j = 0; j < adev->sdma.num_instances; ++j)
-				rings[j] = &adev->sdma.instance[j].ring;
-			num_rings = adev->sdma.num_instances;
+			for (j = 0; j < adev->sdma.num_instances; ++j) {
+				if (adev->sdma.instance[j].ring.sched.ready)
+					rings[num_rings++] = &adev->sdma.instance[j].ring;
+			}
 			break;
 		case AMDGPU_HW_IP_UVD:
-			rings[0] = &adev->uvd.inst[0].ring;
-			num_rings = 1;
+			for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+				if (adev->uvd.harvest_config & (1 << j))
+					continue;
+
+				if (adev->uvd.inst[j].ring.sched.ready)
+					rings[num_rings++] = &adev->uvd.inst[j].ring;
+			}
 			break;
 		case AMDGPU_HW_IP_VCE:
-			rings[0] = &adev->vce.ring[0];
-			num_rings = 1;
+			for (j = 0; j < adev->vce.num_rings; j++) {
+				if (adev->vce.ring[j].sched.ready)
+					rings[num_rings++] = &adev->vce.ring[j];
+			}
 			break;
 		case AMDGPU_HW_IP_UVD_ENC:
-			rings[0] = &adev->uvd.inst[0].ring_enc[0];
-			num_rings = 1;
+			for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+				if (adev->uvd.harvest_config & (1 << j))
+					continue;
+				for (k = 0; k < adev->uvd.num_enc_rings; k++) {
+					if (adev->uvd.inst[j].ring_enc[k].sched.ready)
+						rings[num_rings++] = &adev->uvd.inst[j].ring_enc[k];
+				}
+			}
 			break;
 		case AMDGPU_HW_IP_VCN_DEC:
-			rings[0] = &adev->vcn.ring_dec;
-			num_rings = 1;
+			if (adev->vcn.ring_dec.sched.ready)
+				rings[num_rings++] = &adev->vcn.ring_dec;
 			break;
 		case AMDGPU_HW_IP_VCN_ENC:
-			rings[0] = &adev->vcn.ring_enc[0];
-			num_rings = 1;
+			for (j = 0; j < adev->vcn.num_enc_rings; j++) {
+				if (adev->vcn.ring_enc[j].sched.ready)
+					rings[num_rings++] = &adev->vcn.ring_enc[j];
+			}
+			break;
+		case AMDGPU_HW_IP_VCN_JPEG:
+			if (adev->vcn.ring_jpeg.sched.ready)
+				rings[num_rings++] = &adev->vcn.ring_jpeg;
 			break;
+		}
+
+		/* if there are no rings, then the IP doesn't exist or is disabled  */
+		if (num_rings == 0)
+			continue;
+
+		switch (i) {
+		case AMDGPU_HW_IP_GFX:
+		case AMDGPU_HW_IP_UVD:
+		case AMDGPU_HW_IP_VCE:
+		case AMDGPU_HW_IP_UVD_ENC:
+		case AMDGPU_HW_IP_VCN_DEC:
+		case AMDGPU_HW_IP_VCN_ENC:
 		case AMDGPU_HW_IP_VCN_JPEG:
-			rings[0] = &adev->vcn.ring_jpeg;
-			num_rings = 1;
+			/* limit rings to 1 for scheduling */
+			if (num_rings > 1)
+				num_rings = 1;
+			break;
+		default:
 			break;
 		}
 
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/6] drm/amdgpu: add amdgpu_ring_get_valid_rings helper

[Alex Deucher]

Returns the number of valid rings (i.e., ready for work) for
a particular engine type. Optionally returns an array of rings
as well.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 95 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  3 +
 2 files changed, 98 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 5b75bdc8dc28..c25fcbc2603e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -526,3 +526,98 @@ int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
 	ring->sched.ready = !r;
 	return r;
 }
+
+unsigned amdgpu_ring_get_valid_rings(struct amdgpu_device *adev,
+				     int hw_ip, struct amdgpu_ring **rings)
+{
+	unsigned num_rings = 0;
+	int i, j;
+
+	switch (hw_ip) {
+	case AMDGPU_HW_IP_GFX:
+		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
+			if (adev->gfx.gfx_ring[i].sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->gfx.gfx_ring[i];
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_COMPUTE:
+		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+			if (adev->gfx.compute_ring[i].sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->gfx.compute_ring[i];
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_DMA:
+		for (i = 0; i < adev->sdma.num_instances; i++) {
+			if (adev->sdma.instance[i].ring.sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->sdma.instance[i].ring;
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_UVD:
+		for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+			if (adev->uvd.harvest_config & (1 << i))
+				continue;
+			if (adev->uvd.inst[i].ring.sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->uvd.inst[i].ring;
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_VCE:
+		for (i = 0; i < adev->vce.num_rings; i++) {
+			if (adev->vce.ring[i].sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->vce.ring[i];
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_UVD_ENC:
+		for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+			if (adev->uvd.harvest_config & (1 << i))
+				continue;
+			for (j = 0; j < adev->uvd.num_enc_rings; j++) {
+				if (adev->uvd.inst[i].ring_enc[j].sched.ready) {
+					if (rings)
+						rings[num_rings] = &adev->uvd.inst[i].ring_enc[j];
+					num_rings++;
+				}
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_VCN_DEC:
+		if (adev->vcn.ring_dec.sched.ready) {
+			if (rings)
+				rings[num_rings] = &adev->vcn.ring_dec;
+			num_rings++;
+		}
+		break;
+	case AMDGPU_HW_IP_VCN_ENC:
+		for (i = 0; i < adev->vcn.num_enc_rings; i++) {
+			if (adev->vcn.ring_enc[i].sched.ready) {
+				if (rings)
+					rings[num_rings] = &adev->vcn.ring_enc[i];
+				num_rings++;
+			}
+		}
+		break;
+	case AMDGPU_HW_IP_VCN_JPEG:
+		if (adev->vcn.ring_jpeg.sched.ready) {
+			if (rings)
+				rings[num_rings] = &adev->vcn.ring_jpeg;
+			num_rings++;
+		}
+		break;
+	}
+
+	return num_rings;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 0beb01fef83f..f3fb26644d65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -315,4 +315,7 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
 
 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
 
+unsigned amdgpu_ring_get_valid_rings(struct amdgpu_device *adev,
+				     int hw_ip, struct amdgpu_ring **rings);
+
 #endif
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/6] drm/amdgpu: convert amdgpu_ctx_init to use the new helper

[Alex Deucher]

Use the new helper to get the valid ring count and array.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 62 ++-------------------------------
 1 file changed, 2 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index d12eb863285b..9d2dfa5b83ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 			   struct amdgpu_ctx *ctx)
 {
 	unsigned num_entities = amdgput_ctx_total_num_entities();
-	unsigned i, j, k;
+	unsigned i, j;
 	int r;
 
 	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -125,65 +125,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 		struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
 		unsigned num_rings = 0;
 
-		switch (i) {
-		case AMDGPU_HW_IP_GFX:
-			for (j = 0; j < adev->gfx.num_gfx_rings; j++) {
-				if (adev->gfx.gfx_ring[j].sched.ready)
-					rings[num_rings++] = &adev->gfx.gfx_ring[j];
-			}
-			break;
-		case AMDGPU_HW_IP_COMPUTE:
-			for (j = 0; j < adev->gfx.num_compute_rings; ++j) {
-				if (adev->gfx.compute_ring[j].sched.ready)
-					rings[num_rings++] = &adev->gfx.compute_ring[j];
-			}
-			break;
-		case AMDGPU_HW_IP_DMA:
-			for (j = 0; j < adev->sdma.num_instances; ++j) {
-				if (adev->sdma.instance[j].ring.sched.ready)
-					rings[num_rings++] = &adev->sdma.instance[j].ring;
-			}
-			break;
-		case AMDGPU_HW_IP_UVD:
-			for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
-				if (adev->uvd.harvest_config & (1 << j))
-					continue;
-
-				if (adev->uvd.inst[j].ring.sched.ready)
-					rings[num_rings++] = &adev->uvd.inst[j].ring;
-			}
-			break;
-		case AMDGPU_HW_IP_VCE:
-			for (j = 0; j < adev->vce.num_rings; j++) {
-				if (adev->vce.ring[j].sched.ready)
-					rings[num_rings++] = &adev->vce.ring[j];
-			}
-			break;
-		case AMDGPU_HW_IP_UVD_ENC:
-			for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
-				if (adev->uvd.harvest_config & (1 << j))
-					continue;
-				for (k = 0; k < adev->uvd.num_enc_rings; k++) {
-					if (adev->uvd.inst[j].ring_enc[k].sched.ready)
-						rings[num_rings++] = &adev->uvd.inst[j].ring_enc[k];
-				}
-			}
-			break;
-		case AMDGPU_HW_IP_VCN_DEC:
-			if (adev->vcn.ring_dec.sched.ready)
-				rings[num_rings++] = &adev->vcn.ring_dec;
-			break;
-		case AMDGPU_HW_IP_VCN_ENC:
-			for (j = 0; j < adev->vcn.num_enc_rings; j++) {
-				if (adev->vcn.ring_enc[j].sched.ready)
-					rings[num_rings++] = &adev->vcn.ring_enc[j];
-			}
-			break;
-		case AMDGPU_HW_IP_VCN_JPEG:
-			if (adev->vcn.ring_jpeg.sched.ready)
-				rings[num_rings++] = &adev->vcn.ring_jpeg;
-			break;
-		}
+		num_rings = amdgpu_ring_get_valid_rings(adev, i, rings);
 
 		/* if there are no rings, then the IP doesn't exist or is disabled  */
 		if (num_rings == 0)
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/6] drm/amdgpu: convert amdgpu_hw_ip_info to use new helper

[Alex Deucher]

Use the new helper to get the number of rings.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 38 +++------------------------------
 1 file changed, 3 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 08d04f68dfeb..e97e18b7e0fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -327,7 +327,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 	uint32_t ib_size_alignment = 0;
 	enum amd_ip_block_type type;
 	unsigned int num_rings = 0;
-	unsigned int i, j;
+	unsigned int i;
 
 	if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 		return -EINVAL;
@@ -335,80 +335,46 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 	switch (info->query_hw_ip.type) {
 	case AMDGPU_HW_IP_GFX:
 		type = AMD_IP_BLOCK_TYPE_GFX;
-		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
-			if (adev->gfx.gfx_ring[i].sched.ready)
-				++num_rings;
 		ib_start_alignment = 32;
 		ib_size_alignment = 32;
 		break;
 	case AMDGPU_HW_IP_COMPUTE:
 		type = AMD_IP_BLOCK_TYPE_GFX;
-		for (i = 0; i < adev->gfx.num_compute_rings; i++)
-			if (adev->gfx.compute_ring[i].sched.ready)
-				++num_rings;
 		ib_start_alignment = 32;
 		ib_size_alignment = 32;
 		break;
 	case AMDGPU_HW_IP_DMA:
 		type = AMD_IP_BLOCK_TYPE_SDMA;
-		for (i = 0; i < adev->sdma.num_instances; i++)
-			if (adev->sdma.instance[i].ring.sched.ready)
-				++num_rings;
 		ib_start_alignment = 256;
 		ib_size_alignment = 4;
 		break;
 	case AMDGPU_HW_IP_UVD:
 		type = AMD_IP_BLOCK_TYPE_UVD;
-		for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
-			if (adev->uvd.harvest_config & (1 << i))
-				continue;
-
-			if (adev->uvd.inst[i].ring.sched.ready)
-				++num_rings;
-		}
 		ib_start_alignment = 64;
 		ib_size_alignment = 64;
 		break;
 	case AMDGPU_HW_IP_VCE:
 		type = AMD_IP_BLOCK_TYPE_VCE;
-		for (i = 0; i < adev->vce.num_rings; i++)
-			if (adev->vce.ring[i].sched.ready)
-				++num_rings;
 		ib_start_alignment = 4;
 		ib_size_alignment = 1;
 		break;
 	case AMDGPU_HW_IP_UVD_ENC:
 		type = AMD_IP_BLOCK_TYPE_UVD;
-		for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
-			if (adev->uvd.harvest_config & (1 << i))
-				continue;
-
-			for (j = 0; j < adev->uvd.num_enc_rings; j++)
-				if (adev->uvd.inst[i].ring_enc[j].sched.ready)
-					++num_rings;
-		}
 		ib_start_alignment = 64;
 		ib_size_alignment = 64;
 		break;
 	case AMDGPU_HW_IP_VCN_DEC:
 		type = AMD_IP_BLOCK_TYPE_VCN;
-		if (adev->vcn.ring_dec.sched.ready)
-			++num_rings;
 		ib_start_alignment = 16;
 		ib_size_alignment = 16;
 		break;
 	case AMDGPU_HW_IP_VCN_ENC:
 		type = AMD_IP_BLOCK_TYPE_VCN;
-		for (i = 0; i < adev->vcn.num_enc_rings; i++)
-			if (adev->vcn.ring_enc[i].sched.ready)
-				++num_rings;
 		ib_start_alignment = 64;
 		ib_size_alignment = 1;
 		break;
 	case AMDGPU_HW_IP_VCN_JPEG:
 		type = AMD_IP_BLOCK_TYPE_VCN;
-		if (adev->vcn.ring_jpeg.sched.ready)
-			++num_rings;
 		ib_start_alignment = 16;
 		ib_size_alignment = 16;
 		break;
@@ -416,6 +382,8 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 		return -EINVAL;
 	}
 
+	num_rings = amdgpu_ring_get_valid_rings(adev, info->query_hw_ip.type, NULL);
+
 	for (i = 0; i < adev->num_ip_blocks; i++)
 		if (adev->ip_blocks[i].version->type == type &&
 		    adev->ip_blocks[i].status.valid)
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 6/6] drm/amdgpu: don't expose entities that are not valid for a ctx

[Alex Deucher]

If a particular engine is not available, don't expose its
scheduling entity.  This will cause the CS ioctl to fail
rather than trying to use an uninitialized ring if a particular
IP is not available.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 13 ++++++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h |  1 +
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 9d2dfa5b83ea..3f76d1a7034b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -150,11 +150,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
 		for (j = 0; j < num_rings; ++j)
 			rqs[j] = &rings[j]->sched.sched_rq[priority];
 
-		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
+		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
 			r = drm_sched_entity_init(&ctx->entities[i][j].entity,
 						  rqs, num_rings, &ctx->guilty);
-		if (r)
-			goto error_cleanup_entities;
+			if (r)
+				goto error_cleanup_entities;
+			ctx->entities[i][j].valid = true;
+		}
 	}
 
 	return 0;
@@ -210,6 +212,11 @@ int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
 		return -EINVAL;
 	}
 
+	if (!ctx->entities[hw_ip][ring].valid) {
+		DRM_DEBUG("invalid entity: %d %d\n", hw_ip, ring);
+		return -EINVAL;
+	}
+
 	*entity = &ctx->entities[hw_ip][ring].entity;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index b3b012c0a7da..6dd6c206daeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -33,6 +33,7 @@ struct amdgpu_ctx_entity {
 	uint64_t		sequence;
 	struct dma_fence	**fences;
 	struct drm_sched_entity	entity;
+	bool valid;
 };
 
 struct amdgpu_ctx {
-- 
2.13.6

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/6] drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entities

[Christian König]

Maybe drop patch #2 when you refactor that code in patch #3 and #4 anyway.

On patch #3 I would put the new helper into amdgpu_ctx.c instead because 
that is rather how rings map to userspace queues.

Apart from that it looks good to me.

Christian.

Am 27.11.18 um 22:10 schrieb Alex Deucher:
> Looks like it was missed when setting support was added.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index f9b54236102d..95f4c4139fc6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
>   	[AMDGPU_HW_IP_UVD_ENC]	=	1,
>   	[AMDGPU_HW_IP_VCN_DEC]	=	1,
>   	[AMDGPU_HW_IP_VCN_ENC]	=	1,
> +	[AMDGPU_HW_IP_VCN_JPEG]	=	1,
>   };
>   
>   static int amdgput_ctx_total_num_entities(void)

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/6] drm/amdgpu: add VCN JPEG support amdgpu_ctx_num_entities

[Alex Deucher]

On Wed, Nov 28, 2018 at 3:12 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Maybe drop patch #2 when you refactor that code in patch #3 and #4 anyway.
>
> On patch #3 I would put the new helper into amdgpu_ctx.c instead because
> that is rather how rings map to userspace queues.
>
> Apart from that it looks good to me.

Doesn't seem to work just yet:

[    7.477741] BUG: unable to handle kernel NULL pointer dereference
at 0000000000000008
[    7.477744] PGD 0 P4D 0
[    7.477748] Oops: 0000 [#1] SMP NOPTI
[    7.477750] CPU: 8 PID: 1246 Comm: gnome-shell Not tainted 4.20.0-rc3+ #535
[    7.477752] Hardware name: System manufacturer System Product
Name/ROG STRIX B350-F GAMING, BIOS 4011 04/19/2018
[    7.477756] RIP: 0010:drm_sched_entity_flush+0x29/0x1c0 [gpu_sched]
[    7.477758] Code: 00 0f 1f 44 00 00 41 55 41 54 55 53 48 89 f5 48
89 fb 48 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 31 c0 48
8b 47 10 <4c> 8b 60 08 65 48 8b 04 25 00 5c 01 00 f6 40 24 04 0f 84 0f
01 00
[    7.477759] RSP: 0018:ffffafb0c8a2fc38 EFLAGS: 00010246
[    7.477761] RAX: 0000000000000000 RBX: ffff98432457b5f8 RCX: 0000000000001c43
[    7.477762] RDX: 0000000000001c42 RSI: 00000000000003e8 RDI: ffff98432457b5f8
[    7.477763] RBP: 00000000000003e8 R08: 00000000000242e0 R09: ffffffffc0518043
[    7.477764] R10: ffffe1381fe90f40 R11: ffff98433708c920 R12: ffff98433ade8ef8
[    7.477765] R13: ffff984317740000 R14: 0000000000000001 R15: ffffafb0c8a2fd90
[    7.477766] FS:  00007f8b8a778ac0(0000) GS:ffff98433ec00000(0000)
knlGS:0000000000000000
[    7.477768] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    7.477769] CR2: 0000000000000008 CR3: 00000007e594e000 CR4: 00000000003406e0
[    7.477770] Call Trace:
[    7.477776]  ? __radix_tree_delete+0x7d/0xe0
[    7.477778]  drm_sched_entity_destroy+0x13/0x20 [gpu_sched]
[    7.477812]  amdgpu_ctx_do_release+0x23/0x40 [amdgpu]
[    7.477837]  amdgpu_ctx_ioctl+0x234/0x280 [amdgpu]
[    7.477861]  ? amdgpu_ctx_get_entity+0xa0/0xa0 [amdgpu]
[    7.477870]  drm_ioctl_kernel+0xaa/0xf0 [drm]
[    7.477877]  drm_ioctl+0x2e3/0x380 [drm]
[    7.477900]  ? amdgpu_ctx_get_entity+0xa0/0xa0 [amdgpu]
[    7.477903]  ? __do_fault+0x1e/0x119
[    7.477922]  amdgpu_drm_ioctl+0x49/0x80 [amdgpu]
[    7.477927]  do_vfs_ioctl+0xa4/0x630
[    7.477929]  ? handle_mm_fault+0xdc/0x270
[    7.477931]  ksys_ioctl+0x70/0x80
[    7.477933]  __x64_sys_ioctl+0x16/0x20
[    7.477935]  do_syscall_64+0x5b/0x160
[    7.477938]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[    7.477941] RIP: 0033:0x7f8b7fe34577
[    7.477942] Code: b3 66 90 48 8b 05 11 89 2c 00 64 c7 00 26 00 00
00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d e1 88 2c 00 f7 d8 64 89
01 48
[    7.477943] RSP: 002b:00007ffc0269e108 EFLAGS: 00000246 ORIG_RAX:
0000000000000010
[    7.477944] RAX: ffffffffffffffda RBX: 0000555fce2701d0 RCX: 00007f8b7fe34577
[    7.477945] RDX: 00007ffc0269e170 RSI: 00000000c0106442 RDI: 000000000000000a
[    7.477946] RBP: 00007ffc0269e170 R08: 0000555fce277c00 R09: 000000000001ef50
[    7.477947] R10: 00007f8b800fdb38 R11: 0000000000000246 R12: 00000000c0106442
[    7.477948] R13: 000000000000000a R14: 0000555fce2775c0 R15: 0000000000000000
[    7.477950] Modules linked in: nf_conntrack_netbios_ns
nf_conntrack_broadcast xt_CT ip6t_rpfilter ip6t_REJECT nf_reject_ipv6
xt_conntrack nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 libcrc32c
ip_set nfnetlink ebtable_nat ebtable_broute bridge stp llc
ip6table_mangle ip6table_raw ip6table_security iptable_mangle
iptable_raw iptable_security ebtable_filter ebtables ip6table_filter
ip6_tables sunrpc vfat fat edac_mce_amd kvm_amd snd_hda_codec_realtek
kvm snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel
snd_hda_codec snd_hda_core irqbypass snd_hwdep snd_seq snd_seq_device
snd_pcm crct10dif_pclmul crc32_pclmul eeepc_wmi ghash_clmulni_intel
asus_wmi sparse_keymap snd_timer rfkill joydev ccp snd video
sp5100_tco wmi_bmof pcspkr soundcore k10temp i2c_piix4 pcc_cpufreq
acpi_cpufreq amdgpu chash gpu_sched amd_iommu_v2 ttm drm_kms_helper
igb ptp drm crc32c_intel pps_core dca nvme i2c_algo_bit nvme_core wmi
[    7.477978] CR2: 0000000000000008
[    7.477980] ---[ end trace 9237d2ce370f5585 ]---
[    7.477982] RIP: 0010:drm_sched_entity_flush+0x29/0x1c0 [gpu_sched]
[    7.477983] Code: 00 0f 1f 44 00 00 41 55 41 54 55 53 48 89 f5 48
89 fb 48 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 31 c0 48
8b 47 10 <4c> 8b 60 08 65 48 8b 04 25 00 5c 01 00 f6 40 24 04 0f 84 0f
01 00
[    7.477984] RSP: 0018:ffffafb0c8a2fc38 EFLAGS: 00010246
[    7.477986] RAX: 0000000000000000 RBX: ffff98432457b5f8 RCX: 0000000000001c43
[    7.477986] RDX: 0000000000001c42 RSI: 00000000000003e8 RDI: ffff98432457b5f8
[    7.477987] RBP: 00000000000003e8 R08: 00000000000242e0 R09: ffffffffc0518043
[    7.477988] R10: ffffe1381fe90f40 R11: ffff98433708c920 R12: ffff98433ade8ef8
[    7.477989] R13: ffff984317740000 R14: 0000000000000001 R15: ffffafb0c8a2fd90
[    7.477991] FS:  00007f8b8a778ac0(0000) GS:ffff98433ec00000(0000)
knlGS:0000000000000000
[    7.477992] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    7.477993] CR2: 0000000000000008 CR3: 00000007e594e000 CR4: 00000000003406e0

Any ideas?

Alex


>
> Christian.
>
> Am 27.11.18 um 22:10 schrieb Alex Deucher:
> > Looks like it was missed when setting support was added.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > index f9b54236102d..95f4c4139fc6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> > @@ -39,6 +39,7 @@ const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {
> >       [AMDGPU_HW_IP_UVD_ENC]  =       1,
> >       [AMDGPU_HW_IP_VCN_DEC]  =       1,
> >       [AMDGPU_HW_IP_VCN_ENC]  =       1,
> > +     [AMDGPU_HW_IP_VCN_JPEG] =       1,
> >   };
> >
> >   static int amdgput_ctx_total_num_entities(void)
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx