* [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20
@ 2018-11-28 8:53 Evan Quan
[not found] ` <20181128085336.22979-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Evan Quan @ 2018-11-28 8:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
New pptable upload through sysfs interface is supported.
Change-Id: Idba7aad2898c05bde1f11c7f9ef2f2f077101d9f
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index b05b153101c5..3aec7adfa5f0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -75,10 +75,12 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
+ struct amdgpu_device *adev = hwmgr->adev;
int ret = -EINVAL;;
PHM_FUNC_CHECK(hwmgr);
- if (smum_is_dpm_running(hwmgr)) {
+ /* Skip for suspend/resume case */
+ if (smum_is_dpm_running(hwmgr) && adev->in_suspend) {
pr_info("dpm has been enabled\n");
return 0;
}
--
2.19.2
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for display change event
[not found] ` <20181128085336.22979-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2018-11-28 8:53 ` Evan Quan
[not found] ` <20181128085336.22979-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-11-28 8:53 ` [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM Evan Quan
2018-12-03 3:04 ` [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20 Quan, Evan
2 siblings, 1 reply; 7+ messages in thread
From: Evan Quan @ 2018-11-28 8:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
For display config change event only, pre-display config settings are
needed.
Change-Id: Ifeee7cf35afc00e2fc0269c2a189c560b2091c49
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 2 --
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 47ac92369739..0173d0480024 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -352,6 +352,9 @@ int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
switch (task_id) {
case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
+ ret = phm_pre_display_configuration_changed(hwmgr);
+ if (ret)
+ return ret;
ret = phm_set_cpu_power_state(hwmgr);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 91ffb7bc4ee7..56437866d120 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -265,8 +265,6 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
if (skip)
return 0;
- phm_pre_display_configuration_changed(hwmgr);
-
phm_display_configuration_changed(hwmgr);
if (hwmgr->ps)
--
2.19.2
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM
[not found] ` <20181128085336.22979-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-11-28 8:53 ` [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for display change event Evan Quan
@ 2018-11-28 8:53 ` Evan Quan
[not found] ` <20181128085336.22979-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-12-03 3:04 ` [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20 Quan, Evan
2 siblings, 1 reply; 7+ messages in thread
From: Evan Quan @ 2018-11-28 8:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Evan Quan
For some case, no need to force SoftMin/Max settings for all DPMs.
It's OK to force on some specific DPM only.
Change-Id: Ic5c7658b794ec47c815aae8616bbf0a9bf01fd17
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 54 +++++++++++--------
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 2679d1240fa1..247bf9dbec5d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1660,14 +1660,15 @@ static uint32_t vega20_find_highest_dpm_level(
return i;
}
-static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
+static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
{
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
uint32_t min_freq;
int ret = 0;
- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
+ (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
hwmgr, PPSMC_MSG_SetSoftMinByFreq,
@@ -1676,7 +1677,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_UCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_UCLK].enabled &&
+ (feature_mask & FEATURE_DPM_UCLK_MASK)) {
min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
hwmgr, PPSMC_MSG_SetSoftMinByFreq,
@@ -1692,7 +1694,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_UVD].enabled) {
+ if (data->smu_features[GNLD_DPM_UVD].enabled &&
+ (feature_mask & FEATURE_DPM_UVD_MASK)) {
min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1710,7 +1713,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_VCE].enabled) {
+ if (data->smu_features[GNLD_DPM_VCE].enabled &&
+ (feature_mask & FEATURE_DPM_VCE_MASK)) {
min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1720,7 +1724,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
+ (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1733,14 +1738,15 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
return ret;
}
-static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
+static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
{
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
uint32_t max_freq;
int ret = 0;
- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
+ (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1750,7 +1756,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_UCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_UCLK].enabled &&
+ (feature_mask & FEATURE_DPM_UCLK_MASK)) {
max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1760,7 +1767,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_UVD].enabled) {
+ if (data->smu_features[GNLD_DPM_UVD].enabled &&
+ (feature_mask & FEATURE_DPM_UVD_MASK)) {
max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1777,7 +1785,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_VCE].enabled) {
+ if (data->smu_features[GNLD_DPM_VCE].enabled &&
+ (feature_mask & FEATURE_DPM_VCE_MASK)) {
max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -1787,7 +1796,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
return ret);
}
- if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
+ if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
+ (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
@@ -2126,12 +2136,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_level].value;
- ret = vega20_upload_dpm_min_level(hwmgr);
+ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to highest!",
return ret);
- ret = vega20_upload_dpm_max_level(hwmgr);
+ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload dpm max level to highest!",
return ret);
@@ -2158,12 +2168,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_level].value;
- ret = vega20_upload_dpm_min_level(hwmgr);
+ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to highest!",
return ret);
- ret = vega20_upload_dpm_max_level(hwmgr);
+ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload dpm max level to highest!",
return ret);
@@ -2176,12 +2186,12 @@ static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- ret = vega20_upload_dpm_min_level(hwmgr);
+ ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload DPM Bootup Levels!",
return ret);
- ret = vega20_upload_dpm_max_level(hwmgr);
+ ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload DPM Max Levels!",
return ret);
@@ -2239,12 +2249,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
data->dpm_table.gfx_table.dpm_state.soft_max_level =
data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
- ret = vega20_upload_dpm_min_level(hwmgr);
+ ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to lowest!",
return ret);
- ret = vega20_upload_dpm_max_level(hwmgr);
+ ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload dpm max level to highest!",
return ret);
@@ -2259,12 +2269,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
- ret = vega20_upload_dpm_min_level(hwmgr);
+ ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to lowest!",
return ret);
- ret = vega20_upload_dpm_max_level(hwmgr);
+ ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
PP_ASSERT_WITH_CODE(!ret,
"Failed to upload dpm max level to highest!",
return ret);
--
2.19.2
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20
[not found] ` <20181128085336.22979-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-11-28 8:53 ` [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for display change event Evan Quan
2018-11-28 8:53 ` [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM Evan Quan
@ 2018-12-03 3:04 ` Quan, Evan
2 siblings, 0 replies; 7+ messages in thread
From: Quan, Evan @ 2018-12-03 3:04 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Ping...
> -----Original Message-----
> From: Evan Quan <evan.quan@amd.com>
> Sent: 2018年11月28日 16:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 1/3] drm/amd/powerplay: support new pptable upload on
> Vega20
>
> New pptable upload through sysfs interface is supported.
>
> Change-Id: Idba7aad2898c05bde1f11c7f9ef2f2f077101d9f
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index b05b153101c5..3aec7adfa5f0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -75,10 +75,12 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
>
> int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) {
> + struct amdgpu_device *adev = hwmgr->adev;
> int ret = -EINVAL;;
> PHM_FUNC_CHECK(hwmgr);
>
> - if (smum_is_dpm_running(hwmgr)) {
> + /* Skip for suspend/resume case */
> + if (smum_is_dpm_running(hwmgr) && adev->in_suspend) {
> pr_info("dpm has been enabled\n");
> return 0;
> }
> --
> 2.19.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for display change event
[not found] ` <20181128085336.22979-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2018-12-03 3:05 ` Quan, Evan
0 siblings, 0 replies; 7+ messages in thread
From: Quan, Evan @ 2018-12-03 3:05 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Ping ...
> -----Original Message-----
> From: Evan Quan <evan.quan@amd.com>
> Sent: 2018年11月28日 16:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for
> display change event
>
> For display config change event only, pre-display config settings are needed.
>
> Change-Id: Ifeee7cf35afc00e2fc0269c2a189c560b2091c49
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 2 --
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 47ac92369739..0173d0480024 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -352,6 +352,9 @@ int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
> enum amd_pp_task task_id,
>
> switch (task_id) {
> case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
> + ret = phm_pre_display_configuration_changed(hwmgr);
> + if (ret)
> + return ret;
> ret = phm_set_cpu_power_state(hwmgr);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
> index 91ffb7bc4ee7..56437866d120 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
> @@ -265,8 +265,6 @@ int psm_adjust_power_state_dynamic(struct
> pp_hwmgr *hwmgr, bool skip,
> if (skip)
> return 0;
>
> - phm_pre_display_configuration_changed(hwmgr);
> -
> phm_display_configuration_changed(hwmgr);
>
> if (hwmgr->ps)
> --
> 2.19.2
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM
[not found] ` <20181128085336.22979-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2018-12-03 3:06 ` Quan, Evan
2018-12-03 3:10 ` Alex Deucher
1 sibling, 0 replies; 7+ messages in thread
From: Quan, Evan @ 2018-12-03 3:06 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Ping...
> -----Original Message-----
> From: Evan Quan <evan.quan@amd.com>
> Sent: 2018年11月28日 16:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for
> some specific DPM
>
> For some case, no need to force SoftMin/Max settings for all DPMs.
> It's OK to force on some specific DPM only.
>
> Change-Id: Ic5c7658b794ec47c815aae8616bbf0a9bf01fd17
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 54 +++++++++++------
> --
> 1 file changed, 32 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 2679d1240fa1..247bf9dbec5d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -1660,14 +1660,15 @@ static uint32_t vega20_find_highest_dpm_level(
> return i;
> }
>
> -static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> +static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr,
> uint32_t
> +feature_mask)
> {
> struct vega20_hwmgr *data =
> (struct vega20_hwmgr *)(hwmgr->backend);
> uint32_t min_freq;
> int ret = 0;
>
> - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
> + (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
> min_freq = data-
> >dpm_table.gfx_table.dpm_state.soft_min_level;
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> hwmgr,
> PPSMC_MSG_SetSoftMinByFreq, @@ -1676,7 +1677,8 @@ static int
> vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_UCLK].enabled &&
> + (feature_mask & FEATURE_DPM_UCLK_MASK)) {
> min_freq = data-
> >dpm_table.mem_table.dpm_state.soft_min_level;
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> hwmgr,
> PPSMC_MSG_SetSoftMinByFreq, @@ -1692,7 +1694,8 @@ static int
> vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UVD].enabled) {
> + if (data->smu_features[GNLD_DPM_UVD].enabled &&
> + (feature_mask & FEATURE_DPM_UVD_MASK)) {
> min_freq = data-
> >dpm_table.vclk_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1710,7 +1713,8 @@ static int vega20_upload_dpm_min_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_VCE].enabled) {
> + if (data->smu_features[GNLD_DPM_VCE].enabled &&
> + (feature_mask & FEATURE_DPM_VCE_MASK)) {
> min_freq = data-
> >dpm_table.eclk_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1720,7 +1724,8 @@ static int vega20_upload_dpm_min_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
> + (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
> min_freq = data-
> >dpm_table.soc_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1733,14 +1738,15 @@ static int vega20_upload_dpm_min_level(struct
> pp_hwmgr *hwmgr)
> return ret;
> }
>
> -static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> +static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr,
> uint32_t
> +feature_mask)
> {
> struct vega20_hwmgr *data =
> (struct vega20_hwmgr *)(hwmgr->backend);
> uint32_t max_freq;
> int ret = 0;
>
> - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
> + (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
> max_freq = data-
> >dpm_table.gfx_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1750,7 +1756,8 @@ static int vega20_upload_dpm_max_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_UCLK].enabled &&
> + (feature_mask & FEATURE_DPM_UCLK_MASK)) {
> max_freq = data-
> >dpm_table.mem_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1760,7 +1767,8 @@ static int vega20_upload_dpm_max_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UVD].enabled) {
> + if (data->smu_features[GNLD_DPM_UVD].enabled &&
> + (feature_mask & FEATURE_DPM_UVD_MASK)) {
> max_freq = data-
> >dpm_table.vclk_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1777,7 +1785,8 @@ static int vega20_upload_dpm_max_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_VCE].enabled) {
> + if (data->smu_features[GNLD_DPM_VCE].enabled &&
> + (feature_mask & FEATURE_DPM_VCE_MASK)) {
> max_freq = data-
> >dpm_table.eclk_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -1787,7 +1796,8 @@ static int vega20_upload_dpm_max_level(struct
> pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
> + (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
> max_freq = data-
> >dpm_table.soc_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret =
> smum_send_msg_to_smc_with_parameter(
> @@ -2126,12 +2136,12 @@ static int vega20_force_dpm_highest(struct
> pp_hwmgr *hwmgr)
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data->dpm_table.mem_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2158,12 +2168,12 @@ static int vega20_force_dpm_lowest(struct
> pp_hwmgr *hwmgr)
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data->dpm_table.mem_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2176,12 +2186,12 @@ static int vega20_unforce_dpm_levels(struct
> pp_hwmgr *hwmgr) {
> int ret = 0;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Bootup Levels!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Max Levels!",
> return ret);
> @@ -2239,12 +2249,12 @@ static int vega20_force_clock_level(struct
> pp_hwmgr *hwmgr,
> data->dpm_table.gfx_table.dpm_state.soft_max_level =
> data-
> >dpm_table.gfx_table.dpm_levels[soft_max_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to lowest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2259,12 +2269,12 @@ static int vega20_force_clock_level(struct
> pp_hwmgr *hwmgr,
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data-
> >dpm_table.mem_table.dpm_levels[soft_max_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr,
> FEATURE_DPM_UCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to lowest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr,
> FEATURE_DPM_UCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> --
> 2.19.2
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM
[not found] ` <20181128085336.22979-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-12-03 3:06 ` Quan, Evan
@ 2018-12-03 3:10 ` Alex Deucher
1 sibling, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2018-12-03 3:10 UTC (permalink / raw)
To: Quan, Evan; +Cc: amd-gfx list
On Wed, Nov 28, 2018 at 3:53 AM Evan Quan <evan.quan@amd.com> wrote:
>
> For some case, no need to force SoftMin/Max settings for all DPMs.
> It's OK to force on some specific DPM only.
>
> Change-Id: Ic5c7658b794ec47c815aae8616bbf0a9bf01fd17
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 54 +++++++++++--------
> 1 file changed, 32 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 2679d1240fa1..247bf9dbec5d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -1660,14 +1660,15 @@ static uint32_t vega20_find_highest_dpm_level(
> return i;
> }
>
> -static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> +static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
> {
> struct vega20_hwmgr *data =
> (struct vega20_hwmgr *)(hwmgr->backend);
> uint32_t min_freq;
> int ret = 0;
>
> - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
> + (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
> min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> hwmgr, PPSMC_MSG_SetSoftMinByFreq,
> @@ -1676,7 +1677,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_UCLK].enabled &&
> + (feature_mask & FEATURE_DPM_UCLK_MASK)) {
> min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> hwmgr, PPSMC_MSG_SetSoftMinByFreq,
> @@ -1692,7 +1694,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UVD].enabled) {
> + if (data->smu_features[GNLD_DPM_UVD].enabled &&
> + (feature_mask & FEATURE_DPM_UVD_MASK)) {
> min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1710,7 +1713,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_VCE].enabled) {
> + if (data->smu_features[GNLD_DPM_VCE].enabled &&
> + (feature_mask & FEATURE_DPM_VCE_MASK)) {
> min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1720,7 +1724,8 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
> + (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
> min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1733,14 +1738,15 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> return ret;
> }
>
> -static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> +static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
> {
> struct vega20_hwmgr *data =
> (struct vega20_hwmgr *)(hwmgr->backend);
> uint32_t max_freq;
> int ret = 0;
>
> - if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
> + (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
> max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1750,7 +1756,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_UCLK].enabled &&
> + (feature_mask & FEATURE_DPM_UCLK_MASK)) {
> max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1760,7 +1767,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_UVD].enabled) {
> + if (data->smu_features[GNLD_DPM_UVD].enabled &&
> + (feature_mask & FEATURE_DPM_UVD_MASK)) {
> max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1777,7 +1785,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_VCE].enabled) {
> + if (data->smu_features[GNLD_DPM_VCE].enabled &&
> + (feature_mask & FEATURE_DPM_VCE_MASK)) {
> max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -1787,7 +1796,8 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> return ret);
> }
>
> - if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
> + if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
> + (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
> max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
>
> PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
> @@ -2126,12 +2136,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data->dpm_table.mem_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2158,12 +2168,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data->dpm_table.mem_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2176,12 +2186,12 @@ static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> {
> int ret = 0;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Bootup Levels!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Max Levels!",
> return ret);
> @@ -2239,12 +2249,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
> data->dpm_table.gfx_table.dpm_state.soft_max_level =
> data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to lowest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2259,12 +2269,12 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
> data->dpm_table.mem_table.dpm_state.soft_max_level =
> data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr);
> + ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to lowest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr);
> + ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> --
> 2.19.2
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-12-03 3:10 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-28 8:53 [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20 Evan Quan
[not found] ` <20181128085336.22979-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-11-28 8:53 ` [PATCH 2/3] drm/amd/powerplay: issue pre-display settings for display change event Evan Quan
[not found] ` <20181128085336.22979-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-12-03 3:05 ` Quan, Evan
2018-11-28 8:53 ` [PATCH 3/3] drm/amd/powerplay: support SoftMin/Max setting for some specific DPM Evan Quan
[not found] ` <20181128085336.22979-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
2018-12-03 3:06 ` Quan, Evan
2018-12-03 3:10 ` Alex Deucher
2018-12-03 3:04 ` [PATCH 1/3] drm/amd/powerplay: support new pptable upload on Vega20 Quan, Evan
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