* [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
@ 2018-11-28 12:26 Chris Wilson
2018-11-28 12:26 ` [PATCH 2/3] drm/i915: Allocate a common scratch page Chris Wilson
` (9 more replies)
0 siblings, 10 replies; 17+ messages in thread
From: Chris Wilson @ 2018-11-28 12:26 UTC (permalink / raw)
To: intel-gfx
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e18a64d41843..82c844488755 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
+ if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+ I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+ I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+ if (HAS_VEBOX(dev_priv))
+ I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+ }
+
/* Enforce ordering by reading HEAD register back */
I915_READ_HEAD(engine);
--
2.20.0.rc1
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 2/3] drm/i915: Allocate a common scratch page 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson @ 2018-11-28 12:26 ` Chris Wilson 2018-11-28 13:21 ` Mika Kuoppala 2018-11-28 12:26 ` [PATCH 3/3] drm/i915: Pipeline PDP updates for Braswell Chris Wilson ` (8 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Chris Wilson @ 2018-11-28 12:26 UTC (permalink / raw) To: intel-gfx Currently we allocate a scratch page for each engine, but since we only ever write into it for post-sync operations, it is not exposed to userspace nor do we care for coherency. As we then do not care about its contents, we can use one page for all, reducing our allocations and avoid complications by not assuming per-engine isolation. For later use, it simplifies engine initialisation (by removing the allocation that required struct_mutex!) and means that we can always rely on there being a scratch page. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem.c | 50 ++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 42 --------------------- drivers/gpu/drm/i915/intel_lrc.c | 21 ++++------- drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++--------- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 --- 7 files changed, 68 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f763b30f98d9..c559194e9e3c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1997,6 +1997,8 @@ struct drm_i915_private { struct delayed_work idle_work; ktime_t last_init_time; + + struct i915_vma *scratch; } gt; /* perform PHY state sanity checks? */ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c55b1f75c980..417c265fd93c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5529,6 +5529,44 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) goto out_ctx; } +static int +i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size) +{ + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int ret; + + obj = i915_gem_object_create_stolen(i915, size); + if (!obj) + obj = i915_gem_object_create_internal(i915, size); + if (IS_ERR(obj)) { + DRM_ERROR("Failed to allocate scratch page\n"); + return PTR_ERR(obj); + } + + vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto err_unref; + } + + ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); + if (ret) + goto err_unref; + + i915->gt.scratch = vma; + return 0; + +err_unref: + i915_gem_object_put(obj); + return ret; +} + +static void i915_gem_fini_scratch(struct drm_i915_private *i915) +{ + i915_vma_unpin_and_release(&i915->gt.scratch, 0); +} + int i915_gem_init(struct drm_i915_private *dev_priv) { int ret; @@ -5575,12 +5613,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv) goto err_unlock; } - ret = i915_gem_contexts_init(dev_priv); + ret = i915_gem_init_scratch(dev_priv, + IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE); if (ret) { GEM_BUG_ON(ret == -EIO); goto err_ggtt; } + ret = i915_gem_contexts_init(dev_priv); + if (ret) { + GEM_BUG_ON(ret == -EIO); + goto err_scratch; + } + ret = intel_engines_init(dev_priv); if (ret) { GEM_BUG_ON(ret == -EIO); @@ -5653,6 +5698,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) err_context: if (ret != -EIO) i915_gem_contexts_fini(dev_priv); +err_scratch: + i915_gem_fini_scratch(dev_priv); err_ggtt: err_unlock: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); @@ -5704,6 +5751,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv) intel_uc_fini(dev_priv); i915_gem_cleanup_engines(dev_priv); i915_gem_contexts_fini(dev_priv); + i915_gem_fini_scratch(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); intel_cleanup_gt_powersave(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index a6885a59568b..07465123c166 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1571,7 +1571,7 @@ static void gem_record_rings(struct i915_gpu_state *error) if (HAS_BROKEN_CS_TLB(i915)) ee->wa_batchbuffer = i915_error_object_create(i915, - engine->scratch); + i915->gt.scratch); request_record_user_bo(request, ee); ee->ctx = diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 759c0fd58f8c..2390985384d6 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -493,46 +493,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine) intel_engine_init_cmd_parser(engine); } -int intel_engine_create_scratch(struct intel_engine_cs *engine, - unsigned int size) -{ - struct drm_i915_gem_object *obj; - struct i915_vma *vma; - int ret; - - WARN_ON(engine->scratch); - - obj = i915_gem_object_create_stolen(engine->i915, size); - if (!obj) - obj = i915_gem_object_create_internal(engine->i915, size); - if (IS_ERR(obj)) { - DRM_ERROR("Failed to allocate scratch page\n"); - return PTR_ERR(obj); - } - - vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto err_unref; - } - - ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); - if (ret) - goto err_unref; - - engine->scratch = vma; - return 0; - -err_unref: - i915_gem_object_put(obj); - return ret; -} - -void intel_engine_cleanup_scratch(struct intel_engine_cs *engine) -{ - i915_vma_unpin_and_release(&engine->scratch, 0); -} - static void cleanup_status_page(struct intel_engine_cs *engine) { if (HWS_NEEDS_PHYSICAL(engine->i915)) { @@ -707,8 +667,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; - intel_engine_cleanup_scratch(engine); - cleanup_status_page(engine); intel_engine_fini_breadcrumbs(engine); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 08fd9b12e4d7..3464058cbfc7 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1281,7 +1281,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) { *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); - *batch++ = i915_ggtt_offset(engine->scratch) + 256; + *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256; *batch++ = 0; *batch++ = MI_LOAD_REGISTER_IMM(1); @@ -1295,7 +1295,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); - *batch++ = i915_ggtt_offset(engine->scratch) + 256; + *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256; *batch++ = 0; return batch; @@ -1332,7 +1332,7 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | PIPE_CONTROL_QW_WRITE, - i915_ggtt_offset(engine->scratch) + + i915_ggtt_offset(engine->i915->gt.scratch) + 2 * CACHELINE_BYTES); *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; @@ -1409,8 +1409,8 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | PIPE_CONTROL_QW_WRITE, - i915_ggtt_offset(engine->scratch) - + 2 * CACHELINE_BYTES); + i915_ggtt_offset(engine->i915->gt.scratch) + + 2 * CACHELINE_BYTES); } /* WaMediaPoolStateCmdInWABB:bxt,glk */ @@ -1974,7 +1974,8 @@ static int gen8_emit_flush_render(struct i915_request *request, { struct intel_engine_cs *engine = request->engine; u32 scratch_addr = - i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; + i915_ggtt_offset(engine->i915->gt.scratch) + + 2 * CACHELINE_BYTES; bool vf_flush_wa = false, dc_flush_wa = false; u32 *cs, flags = 0; int len; @@ -2311,10 +2312,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine) if (ret) return ret; - ret = intel_engine_create_scratch(engine, PAGE_SIZE); - if (ret) - goto err_cleanup_common; - ret = intel_init_workaround_bb(engine); if (ret) { /* @@ -2327,10 +2324,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine) } return 0; - -err_cleanup_common: - intel_engine_cleanup_common(engine); - return ret; } int logical_xcs_ring_init(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 82c844488755..de3abca7df18 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -150,7 +150,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) */ if (mode & EMIT_INVALIDATE) { *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; - *cs++ = i915_ggtt_offset(rq->engine->scratch) | + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch) | PIPE_CONTROL_GLOBAL_GTT; *cs++ = 0; *cs++ = 0; @@ -159,7 +159,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) *cs++ = MI_FLUSH; *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; - *cs++ = i915_ggtt_offset(rq->engine->scratch) | + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch) | PIPE_CONTROL_GLOBAL_GTT; *cs++ = 0; *cs++ = 0; @@ -213,7 +213,7 @@ static int intel_emit_post_sync_nonzero_flush(struct i915_request *rq) { u32 scratch_addr = - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; u32 *cs; cs = intel_ring_begin(rq, 6); @@ -247,7 +247,7 @@ static int gen6_render_ring_flush(struct i915_request *rq, u32 mode) { u32 scratch_addr = - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; u32 *cs, flags = 0; int ret; @@ -317,7 +317,7 @@ static int gen7_render_ring_flush(struct i915_request *rq, u32 mode) { u32 scratch_addr = - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; u32 *cs, flags = 0; /* @@ -995,7 +995,7 @@ i830_emit_bb_start(struct i915_request *rq, u64 offset, u32 len, unsigned int dispatch_flags) { - u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); + u32 *cs, cs_offset = i915_ggtt_offset(rq->i915->gt.scratch); cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) @@ -1452,7 +1452,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) { struct i915_timeline *timeline; struct intel_ring *ring; - unsigned int size; int err; intel_engine_setup_common(engine); @@ -1477,21 +1476,12 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) GEM_BUG_ON(engine->buffer); engine->buffer = ring; - size = PAGE_SIZE; - if (HAS_BROKEN_CS_TLB(engine->i915)) - size = I830_WA_SIZE; - err = intel_engine_create_scratch(engine, size); - if (err) - goto err_unpin; - err = intel_engine_init_common(engine); if (err) - goto err_scratch; + goto err_unpin; return 0; -err_scratch: - intel_engine_cleanup_scratch(engine); err_unpin: intel_ring_unpin(ring); err_ring: @@ -1565,7 +1555,7 @@ static int flush_pd_dir(struct i915_request *rq) /* Stall until the page table load is complete */ *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); - *cs++ = i915_ggtt_offset(engine->scratch); + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch); *cs++ = MI_NOOP; intel_ring_advance(rq, cs); @@ -1674,7 +1664,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) /* Insert a delay before the next switch! */ *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; *cs++ = i915_mmio_reg_offset(last_reg); - *cs++ = i915_ggtt_offset(engine->scratch); + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch); *cs++ = MI_NOOP; } *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8a2270b209b0..970fb5c05c36 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -451,7 +451,6 @@ struct intel_engine_cs { struct intel_hw_status_page status_page; struct i915_ctx_workarounds wa_ctx; - struct i915_vma *scratch; u32 irq_keep_mask; /* always keep these interrupts */ u32 irq_enable_mask; /* bitmask to enable ring interrupt */ @@ -908,10 +907,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine); int intel_engine_init_common(struct intel_engine_cs *engine); void intel_engine_cleanup_common(struct intel_engine_cs *engine); -int intel_engine_create_scratch(struct intel_engine_cs *engine, - unsigned int size); -void intel_engine_cleanup_scratch(struct intel_engine_cs *engine); - int intel_init_render_ring_buffer(struct intel_engine_cs *engine); int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); -- 2.20.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] drm/i915: Allocate a common scratch page 2018-11-28 12:26 ` [PATCH 2/3] drm/i915: Allocate a common scratch page Chris Wilson @ 2018-11-28 13:21 ` Mika Kuoppala 2018-11-28 13:37 ` Chris Wilson 0 siblings, 1 reply; 17+ messages in thread From: Mika Kuoppala @ 2018-11-28 13:21 UTC (permalink / raw) To: Chris Wilson, intel-gfx Chris Wilson <chris@chris-wilson.co.uk> writes: > Currently we allocate a scratch page for each engine, but since we only > ever write into it for post-sync operations, it is not exposed to > userspace nor do we care for coherency. As we then do not care about its > contents, we can use one page for all, reducing our allocations and > avoid complications by not assuming per-engine isolation. > > For later use, it simplifies engine initialisation (by removing the > allocation that required struct_mutex!) and means that we can always rely > on there being a scratch page. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_gem.c | 50 ++++++++++++++++++++++++- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 42 --------------------- > drivers/gpu/drm/i915/intel_lrc.c | 21 ++++------- > drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++--------- > drivers/gpu/drm/i915/intel_ringbuffer.h | 5 --- > 7 files changed, 68 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f763b30f98d9..c559194e9e3c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1997,6 +1997,8 @@ struct drm_i915_private { > struct delayed_work idle_work; > > ktime_t last_init_time; > + > + struct i915_vma *scratch; > } gt; > > /* perform PHY state sanity checks? */ > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index c55b1f75c980..417c265fd93c 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -5529,6 +5529,44 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) > goto out_ctx; > } > > +static int > +i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size) > +{ > + struct drm_i915_gem_object *obj; > + struct i915_vma *vma; > + int ret; > + > + obj = i915_gem_object_create_stolen(i915, size); > + if (!obj) > + obj = i915_gem_object_create_internal(i915, size); > + if (IS_ERR(obj)) { > + DRM_ERROR("Failed to allocate scratch page\n"); > + return PTR_ERR(obj); > + } > + > + vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); > + if (IS_ERR(vma)) { > + ret = PTR_ERR(vma); > + goto err_unref; > + } > + > + ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); > + if (ret) > + goto err_unref; > + > + i915->gt.scratch = vma; > + return 0; > + > +err_unref: > + i915_gem_object_put(obj); > + return ret; > +} > + > +static void i915_gem_fini_scratch(struct drm_i915_private *i915) > +{ > + i915_vma_unpin_and_release(&i915->gt.scratch, 0); > +} > + > int i915_gem_init(struct drm_i915_private *dev_priv) > { > int ret; > @@ -5575,12 +5613,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv) > goto err_unlock; > } > > - ret = i915_gem_contexts_init(dev_priv); > + ret = i915_gem_init_scratch(dev_priv, > + IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE); > if (ret) { > GEM_BUG_ON(ret == -EIO); > goto err_ggtt; > } > > + ret = i915_gem_contexts_init(dev_priv); > + if (ret) { > + GEM_BUG_ON(ret == -EIO); > + goto err_scratch; > + } > + > ret = intel_engines_init(dev_priv); > if (ret) { > GEM_BUG_ON(ret == -EIO); > @@ -5653,6 +5698,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) > err_context: > if (ret != -EIO) > i915_gem_contexts_fini(dev_priv); > +err_scratch: > + i915_gem_fini_scratch(dev_priv); > err_ggtt: > err_unlock: > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > @@ -5704,6 +5751,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv) > intel_uc_fini(dev_priv); > i915_gem_cleanup_engines(dev_priv); > i915_gem_contexts_fini(dev_priv); > + i915_gem_fini_scratch(dev_priv); > mutex_unlock(&dev_priv->drm.struct_mutex); > > intel_cleanup_gt_powersave(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index a6885a59568b..07465123c166 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1571,7 +1571,7 @@ static void gem_record_rings(struct i915_gpu_state *error) > if (HAS_BROKEN_CS_TLB(i915)) > ee->wa_batchbuffer = > i915_error_object_create(i915, > - engine->scratch); > + i915->gt.scratch); > request_record_user_bo(request, ee); > > ee->ctx = > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 759c0fd58f8c..2390985384d6 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -493,46 +493,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine) > intel_engine_init_cmd_parser(engine); > } > > -int intel_engine_create_scratch(struct intel_engine_cs *engine, > - unsigned int size) > -{ > - struct drm_i915_gem_object *obj; > - struct i915_vma *vma; > - int ret; > - > - WARN_ON(engine->scratch); > - > - obj = i915_gem_object_create_stolen(engine->i915, size); > - if (!obj) > - obj = i915_gem_object_create_internal(engine->i915, size); > - if (IS_ERR(obj)) { > - DRM_ERROR("Failed to allocate scratch page\n"); > - return PTR_ERR(obj); > - } > - > - vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); > - if (IS_ERR(vma)) { > - ret = PTR_ERR(vma); > - goto err_unref; > - } > - > - ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); > - if (ret) > - goto err_unref; > - > - engine->scratch = vma; > - return 0; > - > -err_unref: > - i915_gem_object_put(obj); > - return ret; > -} > - > -void intel_engine_cleanup_scratch(struct intel_engine_cs *engine) > -{ > - i915_vma_unpin_and_release(&engine->scratch, 0); > -} > - > static void cleanup_status_page(struct intel_engine_cs *engine) > { > if (HWS_NEEDS_PHYSICAL(engine->i915)) { > @@ -707,8 +667,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) > { > struct drm_i915_private *i915 = engine->i915; > > - intel_engine_cleanup_scratch(engine); > - > cleanup_status_page(engine); > > intel_engine_fini_breadcrumbs(engine); > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 08fd9b12e4d7..3464058cbfc7 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1281,7 +1281,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) > { > *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; > *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); > - *batch++ = i915_ggtt_offset(engine->scratch) + 256; > + *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256; How do we get away with these rmws? Because we only have one render engine or that we sync after each engine init? -Mika > *batch++ = 0; > > *batch++ = MI_LOAD_REGISTER_IMM(1); > @@ -1295,7 +1295,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) > > *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; > *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); > - *batch++ = i915_ggtt_offset(engine->scratch) + 256; > + *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256; > *batch++ = 0; > > return batch; > @@ -1332,7 +1332,7 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) > PIPE_CONTROL_GLOBAL_GTT_IVB | > PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_QW_WRITE, > - i915_ggtt_offset(engine->scratch) + > + i915_ggtt_offset(engine->i915->gt.scratch) + > 2 * CACHELINE_BYTES); > > *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; > @@ -1409,8 +1409,8 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) > PIPE_CONTROL_GLOBAL_GTT_IVB | > PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_QW_WRITE, > - i915_ggtt_offset(engine->scratch) > - + 2 * CACHELINE_BYTES); > + i915_ggtt_offset(engine->i915->gt.scratch) + > + 2 * CACHELINE_BYTES); > } > > /* WaMediaPoolStateCmdInWABB:bxt,glk */ > @@ -1974,7 +1974,8 @@ static int gen8_emit_flush_render(struct i915_request *request, > { > struct intel_engine_cs *engine = request->engine; > u32 scratch_addr = > - i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; > + i915_ggtt_offset(engine->i915->gt.scratch) + > + 2 * CACHELINE_BYTES; > bool vf_flush_wa = false, dc_flush_wa = false; > u32 *cs, flags = 0; > int len; > @@ -2311,10 +2312,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine) > if (ret) > return ret; > > - ret = intel_engine_create_scratch(engine, PAGE_SIZE); > - if (ret) > - goto err_cleanup_common; > - > ret = intel_init_workaround_bb(engine); > if (ret) { > /* > @@ -2327,10 +2324,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine) > } > > return 0; > - > -err_cleanup_common: > - intel_engine_cleanup_common(engine); > - return ret; > } > > int logical_xcs_ring_init(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 82c844488755..de3abca7df18 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -150,7 +150,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) > */ > if (mode & EMIT_INVALIDATE) { > *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > - *cs++ = i915_ggtt_offset(rq->engine->scratch) | > + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch) | > PIPE_CONTROL_GLOBAL_GTT; > *cs++ = 0; > *cs++ = 0; > @@ -159,7 +159,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) > *cs++ = MI_FLUSH; > > *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > - *cs++ = i915_ggtt_offset(rq->engine->scratch) | > + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch) | > PIPE_CONTROL_GLOBAL_GTT; > *cs++ = 0; > *cs++ = 0; > @@ -213,7 +213,7 @@ static int > intel_emit_post_sync_nonzero_flush(struct i915_request *rq) > { > u32 scratch_addr = > - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; > + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; > u32 *cs; > > cs = intel_ring_begin(rq, 6); > @@ -247,7 +247,7 @@ static int > gen6_render_ring_flush(struct i915_request *rq, u32 mode) > { > u32 scratch_addr = > - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; > + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; > u32 *cs, flags = 0; > int ret; > > @@ -317,7 +317,7 @@ static int > gen7_render_ring_flush(struct i915_request *rq, u32 mode) > { > u32 scratch_addr = > - i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; > + i915_ggtt_offset(rq->i915->gt.scratch) + 2 * CACHELINE_BYTES; > u32 *cs, flags = 0; > > /* > @@ -995,7 +995,7 @@ i830_emit_bb_start(struct i915_request *rq, > u64 offset, u32 len, > unsigned int dispatch_flags) > { > - u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); > + u32 *cs, cs_offset = i915_ggtt_offset(rq->i915->gt.scratch); > > cs = intel_ring_begin(rq, 6); > if (IS_ERR(cs)) > @@ -1452,7 +1452,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) > { > struct i915_timeline *timeline; > struct intel_ring *ring; > - unsigned int size; > int err; > > intel_engine_setup_common(engine); > @@ -1477,21 +1476,12 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine) > GEM_BUG_ON(engine->buffer); > engine->buffer = ring; > > - size = PAGE_SIZE; > - if (HAS_BROKEN_CS_TLB(engine->i915)) > - size = I830_WA_SIZE; > - err = intel_engine_create_scratch(engine, size); > - if (err) > - goto err_unpin; > - > err = intel_engine_init_common(engine); > if (err) > - goto err_scratch; > + goto err_unpin; > > return 0; > > -err_scratch: > - intel_engine_cleanup_scratch(engine); > err_unpin: > intel_ring_unpin(ring); > err_ring: > @@ -1565,7 +1555,7 @@ static int flush_pd_dir(struct i915_request *rq) > /* Stall until the page table load is complete */ > *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; > *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); > - *cs++ = i915_ggtt_offset(engine->scratch); > + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch); > *cs++ = MI_NOOP; > > intel_ring_advance(rq, cs); > @@ -1674,7 +1664,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > /* Insert a delay before the next switch! */ > *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; > *cs++ = i915_mmio_reg_offset(last_reg); > - *cs++ = i915_ggtt_offset(engine->scratch); > + *cs++ = i915_ggtt_offset(rq->i915->gt.scratch); > *cs++ = MI_NOOP; > } > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 8a2270b209b0..970fb5c05c36 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -451,7 +451,6 @@ struct intel_engine_cs { > > struct intel_hw_status_page status_page; > struct i915_ctx_workarounds wa_ctx; > - struct i915_vma *scratch; > > u32 irq_keep_mask; /* always keep these interrupts */ > u32 irq_enable_mask; /* bitmask to enable ring interrupt */ > @@ -908,10 +907,6 @@ void intel_engine_setup_common(struct intel_engine_cs *engine); > int intel_engine_init_common(struct intel_engine_cs *engine); > void intel_engine_cleanup_common(struct intel_engine_cs *engine); > > -int intel_engine_create_scratch(struct intel_engine_cs *engine, > - unsigned int size); > -void intel_engine_cleanup_scratch(struct intel_engine_cs *engine); > - > int intel_init_render_ring_buffer(struct intel_engine_cs *engine); > int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); > int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); > -- > 2.20.0.rc1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] drm/i915: Allocate a common scratch page 2018-11-28 13:21 ` Mika Kuoppala @ 2018-11-28 13:37 ` Chris Wilson 0 siblings, 0 replies; 17+ messages in thread From: Chris Wilson @ 2018-11-28 13:37 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx Quoting Mika Kuoppala (2018-11-28 13:21:41) > Chris Wilson <chris@chris-wilson.co.uk> writes: > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > > index 08fd9b12e4d7..3464058cbfc7 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1281,7 +1281,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) > > { > > *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; > > *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); > > - *batch++ = i915_ggtt_offset(engine->scratch) + 256; > > + *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256; > > How do we get away with these rmws? Because we only have one render engine > or that we sync after each engine init? We get away with it because it's the only engine in this gen using this dword. We can make it more official by marking reserved portions of the scratch page. Why is L3SQCREG4 whitelisted? mesa doesn't seem to be using it. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/3] drm/i915: Pipeline PDP updates for Braswell 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson 2018-11-28 12:26 ` [PATCH 2/3] drm/i915: Allocate a common scratch page Chris Wilson @ 2018-11-28 12:26 ` Chris Wilson 2018-11-28 13:48 ` [PATCH v2] " Chris Wilson 2018-11-28 12:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork ` (7 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Chris Wilson @ 2018-11-28 12:26 UTC (permalink / raw) To: intel-gfx Currently we face a severe problem on Braswell that manifests as invalid ppGTT accesses. The code tries to maintain the PDP (page directory pointers) inside the context in two ways, direct write into the context and a pipelined LRI update. The direct write into the context is fundamentally racy as it is unserialised with any access (read or write) the GPU is doing. By asserting that Braswell is not used with vGPU (currently an unsupported platform) we can eliminate the dangerous direct write into the context image and solely use the pipelined update. However, the LRI of the PDP fouls up the GPU, causing it to freeze and take out the machine with "forcewake ack timeouts". This seems possible to workaround by preventing the GPU from sleeping (via means of disabling the power-state management interface, i.e. forcing each ring to remain awake) around the update. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656 References: https://bugs.freedesktop.org/show_bug.cgi?id=108714 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 143 ++++++++++++++++--------------- 1 file changed, 76 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3464058cbfc7..50b871e922d3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -363,31 +363,12 @@ execlists_context_schedule_out(struct i915_request *rq, unsigned long status) trace_i915_request_out(rq); } -static void -execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) -{ - ASSIGN_CTX_PDP(ppgtt, reg_state, 3); - ASSIGN_CTX_PDP(ppgtt, reg_state, 2); - ASSIGN_CTX_PDP(ppgtt, reg_state, 1); - ASSIGN_CTX_PDP(ppgtt, reg_state, 0); -} - static u64 execlists_update_context(struct i915_request *rq) { - struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt; struct intel_context *ce = rq->hw_context; - u32 *reg_state = ce->lrc_reg_state; - - reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); - /* - * True 32b PPGTT with dynamic page allocation: update PDP - * registers and point the unallocated PDPs to scratch page. - * PML4 is allocated during ppgtt init, so this is not needed - * in 48-bit mode. - */ - if (!i915_vm_is_48bit(&ppgtt->vm)) - execlists_update_context_pdps(ppgtt, reg_state); + ce->lrc_reg_state[CTX_RING_TAIL+1] = + intel_ring_set_tail(rq->ring, rq->tail); /* * Make sure the context image is complete before we submit it to HW. @@ -1233,6 +1214,64 @@ execlists_context_pin(struct intel_engine_cs *engine, return __execlists_context_pin(engine, ctx, ce); } +static int emit_pdps(struct i915_request *rq) +{ + const struct intel_engine_cs * const engine = rq->engine; + struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; + const unsigned int num_rings = INTEL_INFO(rq->i915)->num_rings; + struct intel_engine_cs *other; + enum intel_engine_id id; + u32 *cs; + int i; + + if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine))) + return 0; + + cs = intel_ring_begin(rq, 4 * (GEN8_3LVL_PDPES + num_rings) + 8); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* + * Force the GPU (not just the local engine/powerwell!) to remain awake, + * or else we may kill the machine with "timed out waiting for + * forcewake ack request". + */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(other, rq->i915, id) { + *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES); + for (i = GEN8_3LVL_PDPES; i--; ) { + const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); + + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); + *cs++ = upper_32_bits(pd_daddr); + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); + *cs++ = lower_32_bits(pd_daddr); + } + *cs++ = MI_NOOP; + + /* Posting read to flush the mmio before letting the GPU sleep again */ + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0)); + *cs++ = i915_ggtt_offset(engine->i915->gt.scratch); + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(other, rq->i915, id) { + *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); + *cs++ = _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + intel_ring_advance(rq, cs); + + ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + return 0; +} + static int execlists_request_alloc(struct i915_request *request) { int ret; @@ -1249,13 +1288,22 @@ static int execlists_request_alloc(struct i915_request *request) if (ret) return ret; - /* Note that after this point, we have committed to using + /* + * Note that after this point, we have committed to using * this request as it is being used to both track the * state of engine initialisation and liveness of the * golden renderstate above. Think twice before you try * to cancel/unwind this request now. */ + if (!i915_vm_is_48bit(&request->gem_context->ppgtt->vm)) { + GEM_BUG_ON(intel_vgpu_active(request->i915)); + + ret = emit_pdps(request); + if (ret) + return ret; + } + request->reserved_space -= EXECLISTS_REQUEST_SIZE; return 0; } @@ -1836,56 +1884,11 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) atomic_read(&execlists->tasklet.count)); } -static int intel_logical_ring_emit_pdps(struct i915_request *rq) -{ - struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt; - struct intel_engine_cs *engine = rq->engine; - const int num_lri_cmds = GEN8_3LVL_PDPES * 2; - u32 *cs; - int i; - - cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); - for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { - const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); - - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); - *cs++ = upper_32_bits(pd_daddr); - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); - *cs++ = lower_32_bits(pd_daddr); - } - - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - return 0; -} - static int gen8_emit_bb_start(struct i915_request *rq, u64 offset, u32 len, const unsigned int flags) { u32 *cs; - int ret; - - /* Don't rely in hw updating PDPs, specially in lite-restore. - * Ideally, we should set Force PD Restore in ctx descriptor, - * but we can't. Force Restore would be a second option, but - * it is unsafe in case of lite-restore (because the ctx is - * not idle). PML4 is allocated during ppgtt init so this is - * not needed in 48-bit.*/ - if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) && - !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) && - !intel_vgpu_active(rq->i915)) { - ret = intel_logical_ring_emit_pdps(rq); - if (ret) - return ret; - - rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); - } cs = intel_ring_begin(rq, 6); if (IS_ERR(cs)) @@ -1918,6 +1921,7 @@ static int gen8_emit_bb_start(struct i915_request *rq, *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); return 0; @@ -2549,6 +2553,11 @@ static void execlists_init_reg_state(u32 *regs, * other PDP Descriptors are ignored. */ ASSIGN_CTX_PML4(ctx->ppgtt, regs); + } else { + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 3); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 2); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 1); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 0); } if (rcs) { -- 2.20.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2] drm/i915: Pipeline PDP updates for Braswell 2018-11-28 12:26 ` [PATCH 3/3] drm/i915: Pipeline PDP updates for Braswell Chris Wilson @ 2018-11-28 13:48 ` Chris Wilson 2018-11-29 23:18 ` kbuild test robot 0 siblings, 1 reply; 17+ messages in thread From: Chris Wilson @ 2018-11-28 13:48 UTC (permalink / raw) To: intel-gfx Currently we face a severe problem on Braswell that manifests as invalid ppGTT accesses. The code tries to maintain the PDP (page directory pointers) inside the context in two ways, direct write into the context and a pipelined LRI update. The direct write into the context is fundamentally racy as it is unserialised with any access (read or write) the GPU is doing. By asserting that Braswell is not used with vGPU (currently an unsupported platform) we can eliminate the dangerous direct write into the context image and solely use the pipelined update. However, the LRI of the PDP fouls up the GPU, causing it to freeze and take out the machine with "forcewake ack timeouts". This seems possible to workaround by preventing the GPU from sleeping (via means of disabling the power-state management interface, i.e. forcing each ring to remain awake) around the update. v2: Keep the LRI in emit_bb_start for the time being as several selftests are disorganized and overlap request construction with GTT insertion. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656 References: https://bugs.freedesktop.org/show_bug.cgi?id=108714 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 95 ++++++++++++++++++-------------- 1 file changed, 53 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3464058cbfc7..1ec9ec9e9105 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -363,31 +363,12 @@ execlists_context_schedule_out(struct i915_request *rq, unsigned long status) trace_i915_request_out(rq); } -static void -execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) -{ - ASSIGN_CTX_PDP(ppgtt, reg_state, 3); - ASSIGN_CTX_PDP(ppgtt, reg_state, 2); - ASSIGN_CTX_PDP(ppgtt, reg_state, 1); - ASSIGN_CTX_PDP(ppgtt, reg_state, 0); -} - static u64 execlists_update_context(struct i915_request *rq) { - struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt; struct intel_context *ce = rq->hw_context; - u32 *reg_state = ce->lrc_reg_state; - reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); - - /* - * True 32b PPGTT with dynamic page allocation: update PDP - * registers and point the unallocated PDPs to scratch page. - * PML4 is allocated during ppgtt init, so this is not needed - * in 48-bit mode. - */ - if (!i915_vm_is_48bit(&ppgtt->vm)) - execlists_update_context_pdps(ppgtt, reg_state); + ce->lrc_reg_state[CTX_RING_TAIL+1] = + intel_ring_set_tail(rq->ring, rq->tail); /* * Make sure the context image is complete before we submit it to HW. @@ -1249,7 +1230,8 @@ static int execlists_request_alloc(struct i915_request *request) if (ret) return ret; - /* Note that after this point, we have committed to using + /* + * Note that after this point, we have committed to using * this request as it is being used to both track the * state of engine initialisation and liveness of the * golden renderstate above. Think twice before you try @@ -1836,20 +1818,37 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) atomic_read(&execlists->tasklet.count)); } -static int intel_logical_ring_emit_pdps(struct i915_request *rq) +static int emit_pdps(struct i915_request *rq) { - struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt; - struct intel_engine_cs *engine = rq->engine; - const int num_lri_cmds = GEN8_3LVL_PDPES * 2; + const struct intel_engine_cs * const engine = rq->engine; + struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; + const unsigned int num_rings = INTEL_INFO(rq->i915)->num_rings; + struct intel_engine_cs *other; + enum intel_engine_id id; u32 *cs; int i; - cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2); + if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine))) + return 0; + + cs = intel_ring_begin(rq, 4 * (GEN8_3LVL_PDPES + num_rings) + 8); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); - for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { + /* + * Force the GPU (not just the local engine/powerwell!) to remain awake, + * or else we may kill the machine with "timed out waiting for + * forcewake ack request". + */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(other, rq->i915, id) { + *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES); + for (i = GEN8_3LVL_PDPES; i--; ) { const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); @@ -1857,10 +1856,23 @@ static int intel_logical_ring_emit_pdps(struct i915_request *rq) *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); *cs++ = lower_32_bits(pd_daddr); } - *cs++ = MI_NOOP; + + /* Posting read to flush the mmio before letting the GPU sleep again */ + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0)); + *cs++ = i915_ggtt_offset(engine->i915->gt.scratch); + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM(num_rings); + for_each_engine(other, rq->i915, id) { + *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); + *cs++ = _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); + } + intel_ring_advance(rq, cs); + ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); return 0; } @@ -1871,20 +1883,13 @@ static int gen8_emit_bb_start(struct i915_request *rq, u32 *cs; int ret; - /* Don't rely in hw updating PDPs, specially in lite-restore. - * Ideally, we should set Force PD Restore in ctx descriptor, - * but we can't. Force Restore would be a second option, but - * it is unsafe in case of lite-restore (because the ctx is - * not idle). PML4 is allocated during ppgtt init so this is - * not needed in 48-bit.*/ - if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) && - !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) && - !intel_vgpu_active(rq->i915)) { - ret = intel_logical_ring_emit_pdps(rq); + /* XXX review selftests request allocation vs vma pinning order */ + if (!i915_vm_is_48bit(&rq->gem_context->ppgtt->vm)) { + GEM_BUG_ON(intel_vgpu_active(rq->i915)); + + ret = emit_pdps(rq); if (ret) return ret; - - rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); } cs = intel_ring_begin(rq, 6); @@ -1918,6 +1923,7 @@ static int gen8_emit_bb_start(struct i915_request *rq, *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); return 0; @@ -2549,6 +2555,11 @@ static void execlists_init_reg_state(u32 *regs, * other PDP Descriptors are ignored. */ ASSIGN_CTX_PML4(ctx->ppgtt, regs); + } else { + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 3); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 2); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 1); + ASSIGN_CTX_PDP(ctx->ppgtt, regs, 0); } if (rcs) { -- 2.20.0.rc1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2] drm/i915: Pipeline PDP updates for Braswell 2018-11-28 13:48 ` [PATCH v2] " Chris Wilson @ 2018-11-29 23:18 ` kbuild test robot 0 siblings, 0 replies; 17+ messages in thread From: kbuild test robot @ 2018-11-29 23:18 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, kbuild-all [-- Attachment #1: Type: text/plain, Size: 3554 bytes --] Hi Chris, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on next-20181129] [cannot apply to v4.20-rc4] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Pipeline-PDP-updates-for-Braswell/20181129-054757 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): >> drivers/gpu/drm/i915/intel_lrc.c:1852:50: error: no member 'scratch' in struct <unnamed> include/linux/slab.h:332:43: warning: dubious: x & !y drivers/gpu/drm/i915/intel_lrc.c: In function 'emit_pdps': drivers/gpu/drm/i915/intel_lrc.c:1852:43: error: 'struct <anonymous>' has no member named 'scratch' *cs++ = i915_ggtt_offset(engine->i915->gt.scratch); ^ vim +/scratch +1852 drivers/gpu/drm/i915/intel_lrc.c 1808 1809 static int emit_pdps(struct i915_request *rq) 1810 { 1811 const struct intel_engine_cs * const engine = rq->engine; 1812 struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; 1813 const unsigned int num_rings = INTEL_INFO(rq->i915)->num_rings; 1814 struct intel_engine_cs *other; 1815 enum intel_engine_id id; 1816 u32 *cs; 1817 int i; 1818 1819 if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine))) 1820 return 0; 1821 1822 cs = intel_ring_begin(rq, 4 * (GEN8_3LVL_PDPES + num_rings) + 8); 1823 if (IS_ERR(cs)) 1824 return PTR_ERR(cs); 1825 1826 /* 1827 * Force the GPU (not just the local engine/powerwell!) to remain awake, 1828 * or else we may kill the machine with "timed out waiting for 1829 * forcewake ack request". 1830 */ 1831 1832 *cs++ = MI_LOAD_REGISTER_IMM(num_rings); 1833 for_each_engine(other, rq->i915, id) { 1834 *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); 1835 *cs++ = _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); 1836 } 1837 1838 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES); 1839 for (i = GEN8_3LVL_PDPES; i--; ) { 1840 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1841 1842 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); 1843 *cs++ = upper_32_bits(pd_daddr); 1844 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); 1845 *cs++ = lower_32_bits(pd_daddr); 1846 } 1847 *cs++ = MI_NOOP; 1848 1849 /* Posting read to flush the mmio before letting the GPU sleep again */ 1850 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; 1851 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0)); > 1852 *cs++ = i915_ggtt_offset(engine->i915->gt.scratch); 1853 *cs++ = 0; 1854 1855 *cs++ = MI_LOAD_REGISTER_IMM(num_rings); 1856 for_each_engine(other, rq->i915, id) { 1857 *cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base)); 1858 *cs++ = _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE); 1859 } 1860 1861 intel_ring_advance(rq, cs); 1862 1863 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); 1864 return 0; 1865 } 1866 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 66662 bytes --] [-- Attachment #3: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson 2018-11-28 12:26 ` [PATCH 2/3] drm/i915: Allocate a common scratch page Chris Wilson 2018-11-28 12:26 ` [PATCH 3/3] drm/i915: Pipeline PDP updates for Braswell Chris Wilson @ 2018-11-28 12:54 ` Patchwork 2018-11-28 12:55 ` ✗ Fi.CI.SPARSE: " Patchwork ` (6 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 12:54 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53154/ State : warning == Summary == $ dim checkpatch origin/drm-tip 300cb53c30ed drm/i915/ringbuffer: Clear semaphore sync registers on ring init fe0f5b2e0347 drm/i915: Allocate a common scratch page cac681fb3ab1 drm/i915: Pipeline PDP updates for Braswell -:59: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #59: FILE: drivers/gpu/drm/i915/intel_lrc.c:370: + ce->lrc_reg_state[CTX_RING_TAIL+1] = ^ total: 0 errors, 0 warnings, 1 checks, 194 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (2 preceding siblings ...) 2018-11-28 12:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork @ 2018-11-28 12:55 ` Patchwork 2018-11-28 13:19 ` ✓ Fi.CI.BAT: success " Patchwork ` (5 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 12:55 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53154/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/ringbuffer: Clear semaphore sync registers on ring init Okay! Commit: drm/i915: Allocate a common scratch page -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void) Commit: drm/i915: Pipeline PDP updates for Braswell Okay! _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (3 preceding siblings ...) 2018-11-28 12:55 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-11-28 13:19 ` Patchwork 2018-11-28 13:31 ` Saarinen, Jani 2018-11-28 14:01 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork ` (4 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Patchwork @ 2018-11-28 13:19 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10926 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53154/revisions/1/mbox/ Known issues ------------ Here are the changes found in Patchwork_10926 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] #### Possible fixes #### * igt@gem_basic@create-fd-close: - fi-kbl-7560u: INCOMPLETE -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 Participating hosts (51 -> 42) ------------------------------ Missing (9): fi-kbl-soraka fi-kbl-7567u fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka Build changes ------------- * Linux: CI_DRM_5213 -> Patchwork_10926 CI_DRM_5213: 5912c54d9804fb15d6a9fa2798bfef1e837c8938 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10926: cac681fb3ab1deb0e04537703640e08bf43b093c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cac681fb3ab1 drm/i915: Pipeline PDP updates for Braswell fe0f5b2e0347 drm/i915: Allocate a common scratch page 300cb53c30ed drm/i915/ringbuffer: Clear semaphore sync registers on ring init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10926/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init 2018-11-28 13:19 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-11-28 13:31 ` Saarinen, Jani 0 siblings, 0 replies; 17+ messages in thread From: Saarinen, Jani @ 2018-11-28 13:31 UTC (permalink / raw) To: intel-gfx, Chris Wilson Hi, > -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of > Patchwork > Sent: keskiviikko 28. marraskuuta 2018 15.20 > To: Chris Wilson <chris@chris-wilson.co.uk> > Cc: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] > drm/i915/ringbuffer: Clear semaphore sync registers on ring init > > == Series Details == > > Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync > registers on ring init > URL : https://patchwork.freedesktop.org/series/53154/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10926 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: > https://patchwork.freedesktop.org/api/1.0/series/53154/revisions/1/mbox/ > > Known issues > ------------ > > Here are the changes found in Patchwork_10926 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@kms_frontbuffer_tracking@basic: > - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614] > > * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: > - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] > > > #### Possible fixes #### > > * igt@gem_basic@create-fd-close: > - fi-kbl-7560u: INCOMPLETE -> PASS > > * igt@kms_frontbuffer_tracking@basic: > - fi-byt-clapper: FAIL [fdo#103167] -> PASS > > * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: > - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS > > > [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 > [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 > > > Participating hosts (51 -> 42) > ------------------------------ > > Missing (9): fi-kbl-soraka fi-kbl-7567u fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u > fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka No regressions but missing this many expected? > > > Build changes > ------------- > > * Linux: CI_DRM_5213 -> Patchwork_10926 > > CI_DRM_5213: 5912c54d9804fb15d6a9fa2798bfef1e837c8938 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_10926: cac681fb3ab1deb0e04537703640e08bf43b093c @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > cac681fb3ab1 drm/i915: Pipeline PDP updates for Braswell > fe0f5b2e0347 drm/i915: Allocate a common scratch page 300cb53c30ed > drm/i915/ringbuffer: Clear semaphore sync registers on ring init > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_10926/ > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (4 preceding siblings ...) 2018-11-28 13:19 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-11-28 14:01 ` Patchwork 2018-11-28 14:02 ` ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 14:01 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) URL : https://patchwork.freedesktop.org/series/53154/ State : warning == Summary == $ dim checkpatch origin/drm-tip 82f42511a45b drm/i915/ringbuffer: Clear semaphore sync registers on ring init f5020e9d35d7 drm/i915: Allocate a common scratch page 97ab9b143916 drm/i915: Pipeline PDP updates for Braswell -:63: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #63: FILE: drivers/gpu/drm/i915/intel_lrc.c:370: + ce->lrc_reg_state[CTX_RING_TAIL+1] = ^ total: 0 errors, 0 warnings, 1 checks, 153 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (5 preceding siblings ...) 2018-11-28 14:01 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork @ 2018-11-28 14:02 ` Patchwork 2018-11-28 14:18 ` ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 14:02 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) URL : https://patchwork.freedesktop.org/series/53154/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/ringbuffer: Clear semaphore sync registers on ring init Okay! Commit: drm/i915: Allocate a common scratch page -drivers/gpu/drm/i915/selftests/../i915_drv.h:3569:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3571:16: warning: expression using sizeof(void) Commit: drm/i915: Pipeline PDP updates for Braswell Okay! _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (6 preceding siblings ...) 2018-11-28 14:02 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-11-28 14:18 ` Patchwork 2018-11-28 14:21 ` Chris Wilson 2018-11-28 18:50 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork 2018-11-28 19:39 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork 9 siblings, 1 reply; 17+ messages in thread From: Patchwork @ 2018-11-28 14:18 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10927 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53154/revisions/2/mbox/ Known issues ------------ Here are the changes found in Patchwork_10927 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_create@basic-files: - fi-bsw-kefka: PASS -> DMESG-FAIL [fdo#108656] * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-apl-guc: PASS -> DMESG-WARN [fdo#108529] / [fdo#108566] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * {igt@runner@aborted}: - fi-bsw-kefka: NOTRUN -> FAIL [fdo#108656] #### Possible fixes #### * igt@gem_basic@create-fd-close: - fi-kbl-7560u: INCOMPLETE -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: FAIL [fdo#103182] -> PASS {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656 Participating hosts (51 -> 43) ------------------------------ Missing (8): fi-kbl-soraka fi-kbl-7567u fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 Build changes ------------- * Linux: CI_DRM_5213 -> Patchwork_10927 CI_DRM_5213: 5912c54d9804fb15d6a9fa2798bfef1e837c8938 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10927: 97ab9b14391670d70529fc1081f211d606e6f369 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 97ab9b143916 drm/i915: Pipeline PDP updates for Braswell f5020e9d35d7 drm/i915: Allocate a common scratch page 82f42511a45b drm/i915/ringbuffer: Clear semaphore sync registers on ring init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10927/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) 2018-11-28 14:18 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-11-28 14:21 ` Chris Wilson 0 siblings, 0 replies; 17+ messages in thread From: Chris Wilson @ 2018-11-28 14:21 UTC (permalink / raw) To: Patchwork; +Cc: intel-gfx Quoting Patchwork (2018-11-28 14:18:05) > == Series Details == > > Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) > URL : https://patchwork.freedesktop.org/series/53154/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10927 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://patchwork.freedesktop.org/api/1.0/series/53154/revisions/2/mbox/ > > Known issues > ------------ > > Here are the changes found in Patchwork_10927 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_create@basic-files: > - fi-bsw-kefka: PASS -> DMESG-FAIL [fdo#108656] And there went my dream of a fix. However, in this v2 we lost the EMIT_INVALIDATE ordering. :( -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (7 preceding siblings ...) 2018-11-28 14:18 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-11-28 18:50 ` Patchwork 2018-11-28 19:39 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 18:50 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10926_full ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_10926_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10926_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_10926_full: ### IGT changes ### #### Warnings #### * igt@pm_rc6_residency@rc6-accuracy: - shard-snb: SKIP -> PASS Known issues ------------ Here are the changes found in Patchwork_10926_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_cursor_crc@cursor-128x128-offscreen: - shard-glk: PASS -> DMESG-WARN [fdo#105763] / [fdo#106538] +2 * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: PASS -> FAIL [fdo#103232] +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-glk: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-glk: PASS -> FAIL [fdo#103167] +3 * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-kbl: NOTRUN -> FAIL [fdo#103166] * igt@kms_setmode@basic: - shard-hsw: PASS -> FAIL [fdo#99912] * {igt@runner@aborted}: - shard-hsw: NOTRUN -> FAIL [fdo#108770] #### Possible fixes #### * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing: - shard-apl: INCOMPLETE [fdo#103927] -> PASS +1 * igt@kms_color@pipe-a-ctm-max: - shard-apl: FAIL [fdo#108147] -> PASS * igt@kms_color@pipe-b-degamma: - shard-apl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-128x128-sliding: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS +1 * igt@kms_cursor_crc@cursor-256x256-dpms: - shard-glk: FAIL [fdo#103232] -> PASS +2 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-apl: FAIL [fdo#103167] -> PASS +2 * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: FAIL [fdo#103167] / [fdo#105682] -> PASS * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc: - shard-glk: FAIL [fdo#103167] -> PASS +2 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +27 * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - shard-glk: FAIL [fdo#103166] -> PASS +2 * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-apl: FAIL [fdo#103166] -> PASS * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-kbl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +13 * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS * igt@perf@blocking: - shard-hsw: FAIL [fdo#102252] -> PASS #### Warnings #### * igt@i915_suspend@shrink: - shard-kbl: INCOMPLETE [fdo#103665] / [fdo#106886] -> DMESG-WARN [fdo#108784] {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682 [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538 [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147 [fdo#108770]: https://bugs.freedesktop.org/show_bug.cgi?id=108770 [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (7 -> 5) ------------------------------ Missing (2): shard-skl shard-iclb Build changes ------------- * Linux: CI_DRM_5213 -> Patchwork_10926 CI_DRM_5213: 5912c54d9804fb15d6a9fa2798bfef1e837c8938 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10926: cac681fb3ab1deb0e04537703640e08bf43b093c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10926/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson ` (8 preceding siblings ...) 2018-11-28 18:50 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork @ 2018-11-28 19:39 ` Patchwork 9 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2018-11-28 19:39 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) URL : https://patchwork.freedesktop.org/series/53154/ State : success == Summary == CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10927_full ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_10927_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10927_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_10927_full: ### IGT changes ### #### Warnings #### * igt@pm_rc6_residency@rc6-accuracy: - shard-snb: SKIP -> PASS Known issues ------------ Here are the changes found in Patchwork_10927_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_schedule@pi-ringfull-blt: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@kms_available_modes_crc@available_mode_test_crc: - {shard-iclb}: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-render-b: - {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-c-crc-primary-basic: - {shard-iclb}: NOTRUN -> FAIL [fdo#107725] * igt@kms_cursor_crc@cursor-128x128-random: - shard-apl: PASS -> FAIL [fdo#103232] +3 * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-glk: PASS -> FAIL [fdo#103232] +2 * igt@kms_cursor_crc@cursor-256x256-dpms: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-dpms: - {shard-iclb}: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_flip@plain-flip-fb-recreate: - shard-skl: PASS -> FAIL [fdo#100368] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-skl: NOTRUN -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - {shard-iclb}: PASS -> FAIL [fdo#103167] +5 * igt@kms_plane@pixel-format-pipe-c-planes: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - {shard-iclb}: PASS -> INCOMPLETE [fdo#107713] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1 * igt@kms_plane@plane-position-covered-pipe-a-planes: - {shard-iclb}: PASS -> FAIL [fdo#103166] +3 * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-c-scaler-with-rotation: - {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107724] * igt@kms_rmfb@close-fd: - {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +1 * igt@kms_setmode@basic: - shard-hsw: PASS -> FAIL [fdo#99912] * igt@pm_rpm@dpms-mode-unset-non-lpsp: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] * igt@pm_rpm@gem-pread: - {shard-iclb}: PASS -> INCOMPLETE [fdo#107713] / [fdo#108840] * igt@pm_rpm@legacy-planes-dpms: - shard-skl: PASS -> INCOMPLETE [fdo#105959] / [fdo#107807] #### Possible fixes #### * igt@drm_import_export@import-close-race-flink: - shard-skl: TIMEOUT [fdo#108667] -> PASS * igt@kms_ccs@pipe-a-crc-primary-basic: - shard-skl: FAIL [fdo#107725] -> PASS * igt@kms_color@pipe-a-ctm-max: - shard-apl: FAIL [fdo#108147] -> PASS * igt@kms_color@pipe-b-degamma: - shard-apl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS +1 * igt@kms_cursor_crc@cursor-256x256-dpms: - shard-glk: FAIL [fdo#103232] -> PASS +1 * igt@kms_cursor_crc@cursor-256x85-onscreen: - shard-apl: FAIL [fdo#103232] -> PASS +2 * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled: - shard-skl: FAIL [fdo#107791] -> PASS * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-apl: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - {shard-iclb}: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-stridechange: - {shard-iclb}: FAIL [fdo#105683] -> PASS +1 * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +27 * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-kbl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +13 * igt@kms_plane_multiple@atomic-pipe-c-tiling-y: - shard-glk: FAIL [fdo#103166] -> PASS - {shard-iclb}: FAIL [fdo#103166] -> PASS * igt@kms_plane_scaling@pipe-b-scaler-with-rotation: - {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS +1 * igt@kms_setmode@basic: - shard-apl: FAIL [fdo#99912] -> PASS - shard-kbl: FAIL [fdo#99912] -> PASS * igt@perf@blocking: - shard-hsw: FAIL [fdo#102252] -> PASS * igt@pm_rpm@modeset-non-lpsp: - shard-skl: INCOMPLETE [fdo#107807] -> SKIP * igt@pm_rpm@system-suspend-execbuf: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107807] -> PASS * igt@pm_rpm@universal-planes-dpms: - shard-skl: INCOMPLETE [fdo#107807] -> PASS * igt@sw_sync@sync_busy_fork: - shard-apl: INCOMPLETE [fdo#103927] -> PASS #### Warnings #### * igt@kms_content_protection@legacy: - shard-apl: FAIL [fdo#108597] -> INCOMPLETE [fdo#103927] {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252 [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683 [fdo#105959]: https://bugs.freedesktop.org/show_bug.cgi?id=105959 [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641 [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815 [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147 [fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597 [fdo#108667]: https://bugs.freedesktop.org/show_bug.cgi?id=108667 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_5213 -> Patchwork_10927 CI_DRM_5213: 5912c54d9804fb15d6a9fa2798bfef1e837c8938 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10927: 97ab9b14391670d70529fc1081f211d606e6f369 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10927/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-11-29 23:19 UTC | newest] Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-28 12:26 [PATCH 1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Chris Wilson 2018-11-28 12:26 ` [PATCH 2/3] drm/i915: Allocate a common scratch page Chris Wilson 2018-11-28 13:21 ` Mika Kuoppala 2018-11-28 13:37 ` Chris Wilson 2018-11-28 12:26 ` [PATCH 3/3] drm/i915: Pipeline PDP updates for Braswell Chris Wilson 2018-11-28 13:48 ` [PATCH v2] " Chris Wilson 2018-11-29 23:18 ` kbuild test robot 2018-11-28 12:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork 2018-11-28 12:55 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-11-28 13:19 ` ✓ Fi.CI.BAT: success " Patchwork 2018-11-28 13:31 ` Saarinen, Jani 2018-11-28 14:01 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork 2018-11-28 14:02 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-11-28 14:18 ` ✓ Fi.CI.BAT: success " Patchwork 2018-11-28 14:21 ` Chris Wilson 2018-11-28 18:50 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init Patchwork 2018-11-28 19:39 ` ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync registers on ring init (rev2) Patchwork
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