* [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets
@ 2018-11-29 2:24 Radhakrishna Sripada
2018-11-29 3:09 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Radhakrishna Sripada @ 2018-11-29 2:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi, Lucs De Marchi
For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well
for higher slices.
v2: Use _PICK instead of formulae(Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Lucs De Marchi <lucas.demarchi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++++++++++++++++++++++++++++-----
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47baf2fe8f71..3b8ee7dd9b62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8662,18 +8662,60 @@ enum {
#define CHV_EU311_PG_ENABLE (1 << 1)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
-#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
- ((slice) % 3) * 0x4)
+
+#define _CNL_SLICE0_PGCTL_ACK 0x804c
+#define _CNL_SLICE1_PGCTL_ACK 0x8050
+#define _CNL_SLICE2_PGCTL_ACK 0x8054
+#define _CNL_SLICE3_PGCTL_ACK 0x8080
+#define _CNL_SLICE4_PGCTL_ACK 0x8084
+#define _CNL_SLICE5_PGCTL_ACK 0x8088
+
+#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
+ _CNL_SLICE0_PGCTL_ACK, \
+ _CNL_SLICE1_PGCTL_ACK, \
+ _CNL_SLICE2_PGCTL_ACK, \
+ _CNL_SLICE3_PGCTL_ACK, \
+ _CNL_SLICE4_PGCTL_ACK, \
+ _CNL_SLICE5_PGCTL_ACK))
+
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
-#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
- ((slice) % 3) * 0x8)
+
+#define _CNL_SLICE0_SS01_EU_PGCTL_ACK 0x805c
+#define _CNL_SLICE1_SS01_EU_PGCTL_ACK 0x8064
+#define _CNL_SLICE2_SS01_EU_PGCTL_ACK 0x806c
+#define _CNL_SLICE3_SS01_EU_PGCTL_ACK 0x808c
+#define _CNL_SLICE4_SS01_EU_PGCTL_ACK 0x8094
+#define _CNL_SLICE5_SS01_EU_PGCTL_ACK 0x809c
+
+#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
+ _CNL_SLICE0_SS01_EU_PGCTL_ACK, \
+ _CNL_SLICE1_SS01_EU_PGCTL_ACK, \
+ _CNL_SLICE2_SS01_EU_PGCTL_ACK, \
+ _CNL_SLICE3_SS01_EU_PGCTL_ACK, \
+ _CNL_SLICE4_SS01_EU_PGCTL_ACK, \
+ _CNL_SLICE5_SS01_EU_PGCTL_ACK))
+
#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
-#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
- ((slice) % 3) * 0x8)
+
+#define _CNL_SLICE0_SS23_EU_PGCTL_ACK 0x8060
+#define _CNL_SLICE1_SS23_EU_PGCTL_ACK 0x8068
+#define _CNL_SLICE2_SS23_EU_PGCTL_ACK 0x8070
+#define _CNL_SLICE3_SS23_EU_PGCTL_ACK 0x8090
+#define _CNL_SLICE4_SS23_EU_PGCTL_ACK 0x8098
+#define _CNL_SLICE5_SS23_EU_PGCTL_ACK 0x80a0
+
+#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
+ _CNL_SLICE0_SS23_EU_PGCTL_ACK, \
+ _CNL_SLICE1_SS23_EU_PGCTL_ACK, \
+ _CNL_SLICE2_SS23_EU_PGCTL_ACK, \
+ _CNL_SLICE3_SS23_EU_PGCTL_ACK, \
+ _CNL_SLICE4_SS23_EU_PGCTL_ACK, \
+ _CNL_SLICE5_SS23_EU_PGCTL_ACK))
+
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.9.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2)
2018-11-29 2:24 [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
@ 2018-11-29 3:09 ` Patchwork
2018-11-29 8:26 ` [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Jani Nikula
2018-11-29 15:52 ` ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-11-29 3:09 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix the formulae for register offsets (rev2)
URL : https://patchwork.freedesktop.org/series/52960/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5220 -> Patchwork_10944
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/52960/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_10944 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u3}: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: FAIL [fdo#108880] -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-kbl-7500u}: FAIL [fdo#108769] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108769]: https://bugs.freedesktop.org/show_bug.cgi?id=108769
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-byt-j1900
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510
Build changes
-------------
* Linux: CI_DRM_5220 -> Patchwork_10944
CI_DRM_5220: b3a448de6828d0bd0397318d15ec143a3dfb553a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10944: 70af57c2affce2b9eaa8dfbd777a6d4395d2ce79 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
70af57c2affc drm/i915/cnl: Fix the formulae for register offsets
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10944/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets
2018-11-29 2:24 [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
2018-11-29 3:09 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
@ 2018-11-29 8:26 ` Jani Nikula
2018-11-29 15:52 ` ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Jani Nikula @ 2018-11-29 8:26 UTC (permalink / raw)
To: Radhakrishna Sripada, intel-gfx; +Cc: Rodrigo Vivi, Lucs De Marchi
On Wed, 28 Nov 2018, Radhakrishna Sripada <radhakrishna.sripada@intel.com> wrote:
> For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well
> for higher slices.
>
> v2: Use _PICK instead of formulae(Jani)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Lucs De Marchi <lucas.demarchi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 54 ++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 48 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe8f71..3b8ee7dd9b62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8662,18 +8662,60 @@ enum {
> #define CHV_EU311_PG_ENABLE (1 << 1)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
> -#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> - ((slice) % 3) * 0x4)
> +
> +#define _CNL_SLICE0_PGCTL_ACK 0x804c
> +#define _CNL_SLICE1_PGCTL_ACK 0x8050
> +#define _CNL_SLICE2_PGCTL_ACK 0x8054
> +#define _CNL_SLICE3_PGCTL_ACK 0x8080
> +#define _CNL_SLICE4_PGCTL_ACK 0x8084
> +#define _CNL_SLICE5_PGCTL_ACK 0x8088
> +
Superfluous newline.
> +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
> + _CNL_SLICE0_PGCTL_ACK, \
> + _CNL_SLICE1_PGCTL_ACK, \
> + _CNL_SLICE2_PGCTL_ACK, \
> + _CNL_SLICE3_PGCTL_ACK, \
> + _CNL_SLICE4_PGCTL_ACK, \
> + _CNL_SLICE5_PGCTL_ACK))
> +
> #define GEN9_PGCTL_SLICE_ACK (1 << 0)
> #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2))
> #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>
> #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8)
> -#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
> - ((slice) % 3) * 0x8)
> +
> +#define _CNL_SLICE0_SS01_EU_PGCTL_ACK 0x805c
> +#define _CNL_SLICE1_SS01_EU_PGCTL_ACK 0x8064
> +#define _CNL_SLICE2_SS01_EU_PGCTL_ACK 0x806c
> +#define _CNL_SLICE3_SS01_EU_PGCTL_ACK 0x808c
> +#define _CNL_SLICE4_SS01_EU_PGCTL_ACK 0x8094
> +#define _CNL_SLICE5_SS01_EU_PGCTL_ACK 0x809c
> +
Superfluous newline.
> +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
> + _CNL_SLICE0_SS01_EU_PGCTL_ACK, \
> + _CNL_SLICE1_SS01_EU_PGCTL_ACK, \
> + _CNL_SLICE2_SS01_EU_PGCTL_ACK, \
> + _CNL_SLICE3_SS01_EU_PGCTL_ACK, \
> + _CNL_SLICE4_SS01_EU_PGCTL_ACK, \
> + _CNL_SLICE5_SS01_EU_PGCTL_ACK))
> +
> #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8)
> -#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> - ((slice) % 3) * 0x8)
> +
Superfluous newline.
Otherwise looks good, I didn't much care for the formulas for
calculating register offsets.
With the extra newlines removed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +#define _CNL_SLICE0_SS23_EU_PGCTL_ACK 0x8060
> +#define _CNL_SLICE1_SS23_EU_PGCTL_ACK 0x8068
> +#define _CNL_SLICE2_SS23_EU_PGCTL_ACK 0x8070
> +#define _CNL_SLICE3_SS23_EU_PGCTL_ACK 0x8090
> +#define _CNL_SLICE4_SS23_EU_PGCTL_ACK 0x8098
> +#define _CNL_SLICE5_SS23_EU_PGCTL_ACK 0x80a0
> +
> +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \
> + _CNL_SLICE0_SS23_EU_PGCTL_ACK, \
> + _CNL_SLICE1_SS23_EU_PGCTL_ACK, \
> + _CNL_SLICE2_SS23_EU_PGCTL_ACK, \
> + _CNL_SLICE3_SS23_EU_PGCTL_ACK, \
> + _CNL_SLICE4_SS23_EU_PGCTL_ACK, \
> + _CNL_SLICE5_SS23_EU_PGCTL_ACK))
> +
> #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
> #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
> #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2)
2018-11-29 2:24 [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
2018-11-29 3:09 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
2018-11-29 8:26 ` [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Jani Nikula
@ 2018-11-29 15:52 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2018-11-29 15:52 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix the formulae for register offsets (rev2)
URL : https://patchwork.freedesktop.org/series/52960/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5220_full -> Patchwork_10944_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_10944_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10944_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_10944_full:
### IGT changes ###
#### Warnings ####
* igt@tools_test@tools_test:
- shard-hsw: SKIP -> PASS
Known issues
------------
Here are the changes found in Patchwork_10944_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@vecs0-s3:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@gem_eio@in-flight-1us:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +8
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956]
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#103166] / [fdo#107724]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- {shard-iclb}: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* igt@kms_rotation_crc@primary-rotation-180:
- shard-snb: NOTRUN -> FAIL [fdo#103925]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@pm_rpm@universal-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
#### Possible fixes ####
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_color@pipe-b-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}: FAIL [fdo#103167] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- {shard-iclb}: FAIL [fdo#103166] -> PASS +1
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- {shard-iclb}: INCOMPLETE [fdo#108840] -> PASS +1
#### Warnings ####
* igt@kms_cursor_crc@cursor-64x64-suspend:
- {shard-iclb}: FAIL [fdo#103232] -> INCOMPLETE [fdo#107713]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103925]: https://bugs.freedesktop.org/show_bug.cgi?id=103925
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 6)
------------------------------
Missing (1): shard-skl
Build changes
-------------
* Linux: CI_DRM_5220 -> Patchwork_10944
CI_DRM_5220: b3a448de6828d0bd0397318d15ec143a3dfb553a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10944: 70af57c2affce2b9eaa8dfbd777a6d4395d2ce79 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10944/shards.html
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
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-- links below jump to the message on this page --
2018-11-29 2:24 [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Radhakrishna Sripada
2018-11-29 3:09 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
2018-11-29 8:26 ` [PATCH v2] drm/i915/cnl: Fix the formulae for register offsets Jani Nikula
2018-11-29 15:52 ` ✓ Fi.CI.IGT: success for drm/i915/cnl: Fix the formulae for register offsets (rev2) Patchwork
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