[U-Boot] [PATCH v2 0/2] SiFive UART support

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

This patchset adds SiFive UART driver for SiFive UART
found on SiFive boards.

The driver is tested on QEMU sifive_u machine. In fact,
with this patchset same U-Boot binary boots on QEMU virt
machine and QEMU sifive_u machine in both M-mode and
S-mode.

The patches are based upon latest RISC-V UBoot tree
(git://git.denx.de/u-boot-riscv.git) at commit id
48cbf6246052de10d35b616b5efb2f783904a49d

Changes since v1:
 - Fixed copyright header in SiFive UART driver
 - Imply SIFIVE_SERIAL for QEMU emulation instead
   of enabling it in defconfigs.

Anup Patel (2):
  drivers: serial: Add SiFive UART driver
  riscv: qemu: Imply SIFIVE_SERIAL for emulation

 board/emulation/qemu-riscv/Kconfig |   1 +
 drivers/serial/Kconfig             |  13 ++
 drivers/serial/Makefile            |   1 +
 drivers/serial/serial_sifive.c     | 191 +++++++++++++++++++++++++++++
 4 files changed, 206 insertions(+)
 create mode 100644 drivers/serial/serial_sifive.c

-- 
2.17.1

[U-Boot] [PATCH v2 1/2] drivers: serial: Add SiFive UART driver

[Anup Patel]

This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 drivers/serial/Kconfig         |  13 +++
 drivers/serial/Makefile        |   1 +
 drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++++++
 3 files changed, 205 insertions(+)
 create mode 100644 drivers/serial/serial_sifive.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 3bcc61e731..30f7e00557 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX
 	  start up driver model. The driver will be available until the real
 	  driver model serial is running.
 
+config DEBUG_UART_SIFIVE
+	bool "SiFive UART"
+	help
+	  Select this to enable a debug UART using the serial_sifive driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver-model serial is running.
+
 config DEBUG_UART_STM32
 	bool "STMicroelectronics STM32"
 	depends on STM32_SERIAL
@@ -685,6 +692,12 @@ config PXA_SERIAL
 	  If you have a machine based on a Marvell XScale PXA2xx CPU you
 	  can enable its onboard serial ports by enabling this option.
 
+config SIFIVE_SERIAL
+	bool "SiFive UART support"
+	depends on DM_SERIAL
+	help
+	  This driver supports the SiFive UART. If unsure say N.
+
 config STI_ASC_SERIAL
 	bool "STMicroelectronics on-chip UART"
 	depends on DM_SERIAL && ARCH_STI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b6377b1076..b6781535a8 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
 obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
 obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
+obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
new file mode 100644
index 0000000000..252f0921ae
--- /dev/null
+++ b/drivers/serial/serial_sifive.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Anup Patel <anup@brainfault.org>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_TXFIFO_FULL	0x80000000
+#define UART_RXFIFO_EMPTY	0x80000000
+#define UART_RXFIFO_DATA	0x000000ff
+#define UART_TXCTRL_TXEN	0x1
+#define UART_RXCTRL_RXEN	0x1
+
+struct uart_sifive {
+	u32 txfifo;
+	u32 rxfifo;
+	u32 txctrl;
+	u32 rxctrl;
+	u32 ie;
+	u32 ip;
+	u32 div;
+};
+
+struct sifive_uart_platdata {
+	unsigned int clock;
+	struct uart_sifive *regs;
+};
+
+/* Set up the baud rate in gd struct */
+static void _sifive_serial_setbrg(struct uart_sifive *regs,
+				  unsigned long clock, unsigned long baud)
+{
+	writel((u32)((clock / baud) - 1), &regs->div);
+}
+
+static void _sifive_serial_init(struct uart_sifive *regs)
+{
+	writel(UART_TXCTRL_TXEN, &regs->txctrl);
+	writel(UART_RXCTRL_RXEN, &regs->rxctrl);
+	writel(0, &regs->ie);
+}
+
+static int _sifive_serial_putc(struct uart_sifive *regs, const char c)
+{
+	if (readl(&regs->txfifo) & UART_TXFIFO_FULL)
+		return -EAGAIN;
+
+	writel(c, &regs->txfifo);
+
+	return 0;
+}
+
+static int _sifive_serial_getc(struct uart_sifive *regs)
+{
+	int ch = readl(&regs->rxfifo);
+
+	if (ch & UART_RXFIFO_EMPTY)
+		return -EAGAIN;
+	ch &= UART_RXFIFO_DATA;
+
+	return (!ch) ? -EAGAIN : ch;
+}
+
+static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	int err;
+	struct clk clk;
+	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+
+	err = clk_get_by_index(dev, 0, &clk);
+	if (!err) {
+		err = clk_get_rate(&clk);
+		if (!IS_ERR_VALUE(err))
+			platdata->clock = err;
+	} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+		debug("SiFive UART failed to get clock\n");
+		return err;
+	}
+
+	if (!platdata->clock)
+		platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
+	if (!platdata->clock) {
+		debug("SiFive UART clock not defined\n");
+		return -EINVAL;
+	}
+
+	_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
+
+	return 0;
+}
+
+static int sifive_serial_probe(struct udevice *dev)
+{
+	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+
+	/* No need to reinitialize the UART after relocation */
+	if (gd->flags & GD_FLG_RELOC)
+		return 0;
+
+	_sifive_serial_init(platdata->regs);
+
+	return 0;
+}
+
+static int sifive_serial_getc(struct udevice *dev)
+{
+	int c;
+	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+	struct uart_sifive *regs = platdata->regs;
+
+	while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
+
+	return c;
+}
+
+static int sifive_serial_putc(struct udevice *dev, const char ch)
+{
+	int rc;
+	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+
+	while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ;
+
+	return rc;
+}
+
+static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+
+	platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
+	if (IS_ERR(platdata->regs))
+		return PTR_ERR(platdata->regs);
+
+	return 0;
+}
+
+static const struct dm_serial_ops sifive_serial_ops = {
+	.putc = sifive_serial_putc,
+	.getc = sifive_serial_getc,
+	.setbrg = sifive_serial_setbrg,
+};
+
+static const struct udevice_id sifive_serial_ids[] = {
+	{ .compatible = "sifive,uart0" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_sifive) = {
+	.name	= "serial_sifive",
+	.id	= UCLASS_SERIAL,
+	.of_match = sifive_serial_ids,
+	.ofdata_to_platdata = sifive_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata),
+	.probe = sifive_serial_probe,
+	.ops	= &sifive_serial_ops,
+};
+
+#ifdef CONFIG_DEBUG_UART_SIFIVE
+static inline void _debug_uart_init(void)
+{
+	struct uart_sifive *regs =
+			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+
+	_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+			      CONFIG_BAUDRATE);
+	_sifive_serial_init(regs);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct uart_sifive *regs =
+			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+
+	while (_sifive_serial_putc(regs, ch) == -EAGAIN)
+		WATCHDOG_RESET();
+}
+
+DEBUG_UART_FUNCS
+
+#endif
-- 
2.17.1

[U-Boot] [PATCH v2 2/2] riscv: qemu: Imply SIFIVE_SERIAL for emulation

[Anup Patel]

This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
---
 board/emulation/qemu-riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 56bb5337d4..436db01a53 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -32,5 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply CMD_FAT
 	imply BOARD_LATE_INIT
 	imply OF_BOARD_SETUP
+	imply SIFIVE_SERIAL
 
 endif
-- 
2.17.1

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Bin Meng]

Hi Anup,

On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patchset adds SiFive UART driver for SiFive UART
> found on SiFive boards.
>
> The driver is tested on QEMU sifive_u machine. In fact,
> with this patchset same U-Boot binary boots on QEMU virt
> machine and QEMU sifive_u machine in both M-mode and
> S-mode.
>

Could you please specify how to test this? I tried your v1 patch but
U-Boot did not boot. I must have missed something ...

> The patches are based upon latest RISC-V UBoot tree
> (git://git.denx.de/u-boot-riscv.git) at commit id
> 48cbf6246052de10d35b616b5efb2f783904a49d
>
> Changes since v1:
>  - Fixed copyright header in SiFive UART driver
>  - Imply SIFIVE_SERIAL for QEMU emulation instead
>    of enabling it in defconfigs.
>

Regards,
Bin

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Anup,
>
> On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > This patchset adds SiFive UART driver for SiFive UART
> > found on SiFive boards.
> >
> > The driver is tested on QEMU sifive_u machine. In fact,
> > with this patchset same U-Boot binary boots on QEMU virt
> > machine and QEMU sifive_u machine in both M-mode and
> > S-mode.
> >
>
> Could you please specify how to test this? I tried your v1 patch but
> U-Boot did not boot. I must have missed something ...

To try this patches in M-mode do the following (in u-boot source directory):
# ARCH=riscv
# CROSS_COMPILE=riscv64-unknown-linux-gnu-
# make qemu-riscv64_defconfig
# make
# qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio
-kernel ./u-boot
OR
# qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
-kernel ./u-boot

Regards,
Anup

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Bin Meng]

Hi Anup,

On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Anup,
> >
> > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > This patchset adds SiFive UART driver for SiFive UART
> > > found on SiFive boards.
> > >
> > > The driver is tested on QEMU sifive_u machine. In fact,
> > > with this patchset same U-Boot binary boots on QEMU virt
> > > machine and QEMU sifive_u machine in both M-mode and
> > > S-mode.
> > >
> >
> > Could you please specify how to test this? I tried your v1 patch but
> > U-Boot did not boot. I must have missed something ...
>
> To try this patches in M-mode do the following (in u-boot source directory):
> # ARCH=riscv
> # CROSS_COMPILE=riscv64-unknown-linux-gnu-
> # make qemu-riscv64_defconfig
> # make
> # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio
> -kernel ./u-boot

I tried exactly the same, but no console output.

> OR
> # qemu-system-riscv64 -M virt -m 256M -display none -serial stdio
> -kernel ./u-boot
>

Regards,
Bin

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

On Tue, Dec 11, 2018 at 9:45 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Anup,
>
> On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > Hi Anup,
> > >
> > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
> > > >
> > > > This patchset adds SiFive UART driver for SiFive UART
> > > > found on SiFive boards.
> > > >
> > > > The driver is tested on QEMU sifive_u machine. In fact,
> > > > with this patchset same U-Boot binary boots on QEMU virt
> > > > machine and QEMU sifive_u machine in both M-mode and
> > > > S-mode.
> > > >
> > >
> > > Could you please specify how to test this? I tried your v1 patch but
> > > U-Boot did not boot. I must have missed something ...
> >
> > To try this patches in M-mode do the following (in u-boot source directory):
> > # ARCH=riscv
> > # CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > # make qemu-riscv64_defconfig
> > # make
> > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio
> > -kernel ./u-boot
>
> I tried exactly the same, but no console output.
>

Ahh, understood your problem.

There is a bug in QEMU FDT generation for sifive_u.

Here's the QEMU fix (which I have send to QEMU mailing list):

Return-Path: <anup@brainfault.org>
Received: from anup-ubuntu64.qualcomm.com ([49.207.50.107])
        by smtp.googlemail.com with ESMTPSA id
19sm33410406pfs.108.2018.12.05.00.27.14
        (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);
        Wed, 05 Dec 2018 00:27:15 -0800 (PST)
From: Anup Patel <anup@brainfault.org>
To: qemu-riscv at nongnu.org
Cc: Anup Patel <anup@brainfault.org>
Subject: [PATCH 2/2] hw/riscv/sifive_u: Set 'clock-frequency' DT
property for SiFive UART
Date: Wed,
  5 Dec 2018 13:57:03 +0530
Message-Id: <20181205082703.13945-2-anup@brainfault.org>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20181205082703.13945-1-anup@brainfault.org>
References: <20181205082703.13945-1-anup@brainfault.org>

The 'clock-frequency' DT property is required by U-Boot to compute
divider value. This patch sets 'clock-frequency' DT property of
SiFive UART DT node (similar to virt machine).

Signed-off-by: Anup Patel <anup@brainfault.org>
---
 hw/riscv/sifive_u.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b3a4352986..5fa666fefc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -238,6 +238,8 @@ static void create_fdt(SiFiveUState *s, const
struct MemmapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_UART0].base,
         0x0, memmap[SIFIVE_U_UART0].size);
+    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+        SIFIVE_U_CLOCK_FREQ / 2);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);

-- 
2.17.1


Regards,
Anup

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Bin Meng]

On Wed, Dec 12, 2018 at 12:20 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Dec 11, 2018 at 9:45 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Hi Anup,
> >
> > On Wed, Dec 12, 2018 at 12:07 AM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Tue, Dec 11, 2018 at 9:03 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > > >
> > > > Hi Anup,
> > > >
> > > > On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
> > > > >
> > > > > This patchset adds SiFive UART driver for SiFive UART
> > > > > found on SiFive boards.
> > > > >
> > > > > The driver is tested on QEMU sifive_u machine. In fact,
> > > > > with this patchset same U-Boot binary boots on QEMU virt
> > > > > machine and QEMU sifive_u machine in both M-mode and
> > > > > S-mode.
> > > > >
> > > >
> > > > Could you please specify how to test this? I tried your v1 patch but
> > > > U-Boot did not boot. I must have missed something ...
> > >
> > > To try this patches in M-mode do the following (in u-boot source directory):
> > > # ARCH=riscv
> > > # CROSS_COMPILE=riscv64-unknown-linux-gnu-
> > > # make qemu-riscv64_defconfig
> > > # make
> > > # qemu-system-riscv64 -M sifive_u -m 256M -display none -serial stdio
> > > -kernel ./u-boot
> >
> > I tried exactly the same, but no console output.
> >
>
> Ahh, understood your problem.
>
> There is a bug in QEMU FDT generation for sifive_u.
>
> Here's the QEMU fix (which I have send to QEMU mailing list):
>

With the new info, now I am able to boot U-Boot on QEMU sifive_u.

Regards,
Bin

[U-Boot] [PATCH v2 1/2] drivers: serial: Add SiFive UART driver

[Bin Meng]

On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patch adds SiFive UART driver. The driver is 100% DM driver
> and it determines input clock using clk framework.
>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> ---
>  drivers/serial/Kconfig         |  13 +++
>  drivers/serial/Makefile        |   1 +
>  drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++++++
>  3 files changed, 205 insertions(+)
>  create mode 100644 drivers/serial/serial_sifive.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 2/2] riscv: qemu: Imply SIFIVE_SERIAL for emulation

[Bin Meng]

On Tue, Dec 11, 2018 at 11:02 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patch enables SiFive UART driver for QEMU RISC-V emulation
> by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.
>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> ---
>  board/emulation/qemu-riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patchset adds SiFive UART driver for SiFive UART
> found on SiFive boards.
>
> The driver is tested on QEMU sifive_u machine. In fact,
> with this patchset same U-Boot binary boots on QEMU virt
> machine and QEMU sifive_u machine in both M-mode and
> S-mode.
>
> The patches are based upon latest RISC-V UBoot tree
> (git://git.denx.de/u-boot-riscv.git) at commit id
> 48cbf6246052de10d35b616b5efb2f783904a49d
>
> Changes since v1:
>  - Fixed copyright header in SiFive UART driver
>  - Imply SIFIVE_SERIAL for QEMU emulation instead
>    of enabling it in defconfigs.
>
> Anup Patel (2):
>   drivers: serial: Add SiFive UART driver
>   riscv: qemu: Imply SIFIVE_SERIAL for emulation
>
>  board/emulation/qemu-riscv/Kconfig |   1 +
>  drivers/serial/Kconfig             |  13 ++
>  drivers/serial/Makefile            |   1 +
>  drivers/serial/serial_sifive.c     | 191 +++++++++++++++++++++++++++++
>  4 files changed, 206 insertions(+)
>  create mode 100644 drivers/serial/serial_sifive.c
>
> --
> 2.17.1
>

Hi Rick,

The required QEMU fix has been submitted by Alistair Francis on
QEMU mailing list.
(QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property
for SiFive UART")

Can you please consider this series for U-Boot v2019.01?

Thanks,
Anup

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Rick Chen]

Hi Anup

> > From: Anup Patel [mailto:anup at brainfault.org]
> > Sent: Friday, December 14, 2018 5:23 PM
> > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer
> > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot
> > Mailing List
> > Subject: Re: [PATCH v2 0/2] SiFive UART support
> >
> > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > This patchset adds SiFive UART driver for SiFive UART found on SiFive
> > > boards.
> > >
> > > The driver is tested on QEMU sifive_u machine. In fact, with this
> > > patchset same U-Boot binary boots on QEMU virt machine and QEMU
> > > sifive_u machine in both M-mode and S-mode.
> > >
> > > The patches are based upon latest RISC-V UBoot tree
> > > (git://git.denx.de/u-boot-riscv.git) at commit id
> > > 48cbf6246052de10d35b616b5efb2f783904a49d
> > >
> > > Changes since v1:
> > >  - Fixed copyright header in SiFive UART driver
> > >  - Imply SIFIVE_SERIAL for QEMU emulation instead
> > >    of enabling it in defconfigs.
> > >
> > > Anup Patel (2):
> > >   drivers: serial: Add SiFive UART driver
> > >   riscv: qemu: Imply SIFIVE_SERIAL for emulation
> > >
> > >  board/emulation/qemu-riscv/Kconfig |   1 +
> > >  drivers/serial/Kconfig             |  13 ++
> > >  drivers/serial/Makefile            |   1 +
> > >  drivers/serial/serial_sifive.c     | 191 +++++++++++++++++++++++++++++
> > >  4 files changed, 206 insertions(+)
> > >  create mode 100644 drivers/serial/serial_sifive.c
> > >
> > > --
> > > 2.17.1
> > >
> >
> > Hi Rick,
> >
> > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing
> > list.
> > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive
> > UART")
> >
> > Can you please consider this series for U-Boot v2019.01?
> >

OK
I will include yours in this PR.

B.R
Rick

> > Thanks,
> > Anup

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Anup Patel]

On Mon, Dec 17, 2018 at 7:21 AM Rick Chen <rickchen36@gmail.com> wrote:
>
> Hi Anup
>
> > > From: Anup Patel [mailto:anup at brainfault.org]
> > > Sent: Friday, December 14, 2018 5:23 PM
> > > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer
> > > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot
> > > Mailing List
> > > Subject: Re: [PATCH v2 0/2] SiFive UART support
> > >
> > > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote:
> > > >
> > > > This patchset adds SiFive UART driver for SiFive UART found on SiFive
> > > > boards.
> > > >
> > > > The driver is tested on QEMU sifive_u machine. In fact, with this
> > > > patchset same U-Boot binary boots on QEMU virt machine and QEMU
> > > > sifive_u machine in both M-mode and S-mode.
> > > >
> > > > The patches are based upon latest RISC-V UBoot tree
> > > > (git://git.denx.de/u-boot-riscv.git) at commit id
> > > > 48cbf6246052de10d35b616b5efb2f783904a49d
> > > >
> > > > Changes since v1:
> > > >  - Fixed copyright header in SiFive UART driver
> > > >  - Imply SIFIVE_SERIAL for QEMU emulation instead
> > > >    of enabling it in defconfigs.
> > > >
> > > > Anup Patel (2):
> > > >   drivers: serial: Add SiFive UART driver
> > > >   riscv: qemu: Imply SIFIVE_SERIAL for emulation
> > > >
> > > >  board/emulation/qemu-riscv/Kconfig |   1 +
> > > >  drivers/serial/Kconfig             |  13 ++
> > > >  drivers/serial/Makefile            |   1 +
> > > >  drivers/serial/serial_sifive.c     | 191 +++++++++++++++++++++++++++++
> > > >  4 files changed, 206 insertions(+)
> > > >  create mode 100644 drivers/serial/serial_sifive.c
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > Hi Rick,
> > >
> > > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing
> > > list.
> > > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive
> > > UART")
> > >
> > > Can you please consider this series for U-Boot v2019.01?
> > >
>
> OK
> I will include yours in this PR.

I have send v3 of this patch. Please include that.

Thanks,
Anup

[U-Boot] [PATCH v2 0/2] SiFive UART support

[Rick Chen]

Hi Anup

Anup Patel <anup@brainfault.org> 於 2018年12月17日 週一 下午12:15寫道：
>
> On Mon, Dec 17, 2018 at 7:21 AM Rick Chen <rickchen36@gmail.com> wrote:
> >
> > Hi Anup
> >
> > > > From: Anup Patel [mailto:anup at brainfault.org]
> > > > Sent: Friday, December 14, 2018 5:23 PM
> > > > To: Rick Jian-Zhi Chen(陳建志); Bin Meng; Lukas Auer
> > > > Cc: Alexander Graf; Palmer Dabbelt; Atish Patra; Christoph Hellwig; U-Boot
> > > > Mailing List
> > > > Subject: Re: [PATCH v2 0/2] SiFive UART support
> > > >
> > > > On Tue, Dec 11, 2018 at 8:32 PM Anup Patel <anup@brainfault.org> wrote:
> > > > >
> > > > > This patchset adds SiFive UART driver for SiFive UART found on SiFive
> > > > > boards.
> > > > >
> > > > > The driver is tested on QEMU sifive_u machine. In fact, with this
> > > > > patchset same U-Boot binary boots on QEMU virt machine and QEMU
> > > > > sifive_u machine in both M-mode and S-mode.
> > > > >
> > > > > The patches are based upon latest RISC-V UBoot tree
> > > > > (git://git.denx.de/u-boot-riscv.git) at commit id
> > > > > 48cbf6246052de10d35b616b5efb2f783904a49d
> > > > >
> > > > > Changes since v1:
> > > > >  - Fixed copyright header in SiFive UART driver
> > > > >  - Imply SIFIVE_SERIAL for QEMU emulation instead
> > > > >    of enabling it in defconfigs.
> > > > >
> > > > > Anup Patel (2):
> > > > >   drivers: serial: Add SiFive UART driver
> > > > >   riscv: qemu: Imply SIFIVE_SERIAL for emulation
> > > > >
> > > > >  board/emulation/qemu-riscv/Kconfig |   1 +
> > > > >  drivers/serial/Kconfig             |  13 ++
> > > > >  drivers/serial/Makefile            |   1 +
> > > > >  drivers/serial/serial_sifive.c     | 191 +++++++++++++++++++++++++++++
> > > > >  4 files changed, 206 insertions(+)
> > > > >  create mode 100644 drivers/serial/serial_sifive.c
> > > > >
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > Hi Rick,
> > > >
> > > > The required QEMU fix has been submitted by Alistair Francis on QEMU mailing
> > > > list.
> > > > (QEMU PATCH subject "sifive_u: Set 'clock-frequency' DT property for SiFive
> > > > UART")
> > > >
> > > > Can you please consider this series for U-Boot v2019.01?
> > > >
> >
> > OK
> > I will include yours in this PR.
>
> I have send v3 of this patch. Please include that.
>

Yes.
I fetch your v3 and apply to u-boot-riscv.git.
Travis is verifying.
Then I will send a PR later.

B.R
Rick

> Thanks,
> Anup