* [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 2/7] drm/i915: Record the sseu configuration per-context & engine Tvrtko Ursulin
` (9 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Configuring RPCS in context image just before pin is sufficient and will
come extra handy in one of the following patches.
v2:
* Split image setup a bit differently. (Chris Wilson)
v3:
* Update context image after reset as well - otherwise the application
of pinned default state clears the RPCS.
v4:
* Use local variable throughout the function. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_lrc.c | 45 ++++++++++++++++++++------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c9748f391fe..75d90918cac4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1170,6 +1170,24 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
+static u32 make_rpcs(struct drm_i915_private *dev_priv);
+
+static void
+__execlists_update_reg_state(struct intel_engine_cs *engine,
+ struct intel_context *ce)
+{
+ u32 *regs = ce->lrc_reg_state;
+ struct intel_ring *ring = ce->ring;
+
+ regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
+ regs[CTX_RING_HEAD + 1] = ring->head;
+ regs[CTX_RING_TAIL + 1] = ring->tail;
+
+ /* RPCS */
+ if (engine->class == RENDER_CLASS)
+ regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
+}
+
static struct intel_context *
__execlists_context_pin(struct intel_engine_cs *engine,
struct i915_gem_context *ctx,
@@ -1208,10 +1226,8 @@ __execlists_context_pin(struct intel_engine_cs *engine,
GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
- i915_ggtt_offset(ce->ring->vma);
- ce->lrc_reg_state[CTX_RING_HEAD + 1] = ce->ring->head;
- ce->lrc_reg_state[CTX_RING_TAIL + 1] = ce->ring->tail;
+
+ __execlists_update_reg_state(engine, ce);
ce->state->obj->pin_global++;
i915_gem_context_get(ctx);
@@ -1835,14 +1851,14 @@ static void execlists_reset(struct intel_engine_cs *engine,
engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
engine->context_size - PAGE_SIZE);
}
- execlists_init_reg_state(regs,
- request->gem_context, engine, request->ring);
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
- regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
-
request->ring->head = intel_ring_wrap(request->ring, request->postfix);
- regs[CTX_RING_HEAD + 1] = request->ring->head;
+
+ execlists_init_reg_state(regs, request->gem_context, engine,
+ request->ring);
+
+ __execlists_update_reg_state(engine, request->hw_context);
intel_ring_update_space(request->ring);
@@ -2526,8 +2542,7 @@ static void execlists_init_reg_state(u32 *regs,
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
- CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev_priv));
+ CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
i915_oa_init_reg_state(engine, ctx, regs);
}
@@ -2688,12 +2703,8 @@ void intel_lr_context_resume(struct drm_i915_private *i915)
intel_ring_reset(ce->ring, 0);
- if (ce->pin_count) { /* otherwise done in context_pin */
- u32 *regs = ce->lrc_reg_state;
-
- regs[CTX_RING_HEAD + 1] = ce->ring->head;
- regs[CTX_RING_TAIL + 1] = ce->ring->tail;
- }
+ if (ce->pin_count) /* otherwise done in context_pin */
+ __execlists_update_reg_state(engine, ce);
}
}
}
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/7] drm/i915: Record the sseu configuration per-context & engine
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 3/7] drm/i915/perf: lock powergating configuration to default when active Tvrtko Ursulin
` (8 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration per context & engine (Chris)
v3: introduce the i915_gem_context_sseu to store powergating
programming, sseu_dev_info has grown quite a bit (Lionel)
v4: rename i915_gem_sseu into intel_sseu (Chris)
use to_intel_context() (Chris)
v5: More to_intel_context() (Tvrtko)
Switch intel_sseu from union to struct (Tvrtko)
Move context default sseu in existing loop (Chris)
v6: s/intel_sseu_from_device_sseu/intel_device_default_sseu/ (Tvrtko)
Tvrtko Ursulin:
v7:
* Pass intel_sseu by pointer instead of value to make_rpcs.
* Rebase for make_rpcs changes.
v8:
* Rebase for RPCS edit on pin.
v9:
* Rebase for context image setup changes.
v10:
* Rename dev_priv to i915. (Chris Wilson)
v11:
* Rebase.
v12:
* Rebase for IS_GEN changes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++++++++++
drivers/gpu/drm/i915/i915_gem_context.c | 2 ++
drivers/gpu/drm/i915/i915_gem_context.h | 4 ++++
drivers/gpu/drm/i915/i915_request.h | 10 ++++++++
drivers/gpu/drm/i915/intel_lrc.c | 31 +++++++++++++------------
5 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c34198f51b13..f834602ed157 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3302,6 +3302,20 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)&dev_priv->info;
}
+static inline struct intel_sseu
+intel_device_default_sseu(struct drm_i915_private *i915)
+{
+ const struct sseu_dev_info *sseu = &INTEL_INFO(i915)->sseu;
+ struct intel_sseu value = {
+ .slice_mask = sseu->slice_mask,
+ .subslice_mask = sseu->subslice_mask[0],
+ .min_eus_per_subslice = sseu->max_eus_per_subslice,
+ .max_eus_per_subslice = sseu->max_eus_per_subslice,
+ };
+
+ return value;
+}
+
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
extern int intel_modeset_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 5905b6d8f291..a565643e9a26 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -343,6 +343,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct intel_context *ce = &ctx->__engine[n];
ce->gem_context = ctx;
+ /* Use the whole device by default */
+ ce->sseu = intel_device_default_sseu(dev_priv);
}
INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index f6d870b1f73e..ef04e422cf9a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -31,6 +31,7 @@
#include "i915_gem.h"
#include "i915_scheduler.h"
+#include "intel_device_info.h"
struct pid;
@@ -171,6 +172,9 @@ struct i915_gem_context {
int pin_count;
const struct intel_context_ops *ops;
+
+ /** sseu: Control eu/slice partitioning */
+ struct intel_sseu sseu;
} __engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 90e9d170a0cd..07aaf9b43716 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -39,6 +39,16 @@ struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+/*
+ * Powergating configuration for a particular (context,engine).
+ */
+struct intel_sseu {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 min_eus_per_subslice;
+ u8 max_eus_per_subslice;
+};
+
struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 75d90918cac4..bfc31ccf5382 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1170,7 +1170,8 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32 make_rpcs(struct drm_i915_private *dev_priv);
+static u32
+make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
static void
__execlists_update_reg_state(struct intel_engine_cs *engine,
@@ -1185,7 +1186,8 @@ __execlists_update_reg_state(struct intel_engine_cs *engine,
/* RPCS */
if (engine->class == RENDER_CLASS)
- regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
+ regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915,
+ &ce->sseu);
}
static struct intel_context *
@@ -2318,18 +2320,19 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
}
static u32
-make_rpcs(struct drm_i915_private *dev_priv)
+make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
{
- bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
- u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
- u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
+ const struct sseu_dev_info *sseu = &INTEL_INFO(i915)->sseu;
+ bool subslice_pg = sseu->has_subslice_pg;
+ u8 slices = hweight8(ctx_sseu->slice_mask);
+ u8 subslices = hweight8(ctx_sseu->subslice_mask);
u32 rpcs = 0;
/*
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_GEN(dev_priv) < 9)
+ if (INTEL_GEN(i915) < 9)
return 0;
/*
@@ -2357,7 +2360,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
* subslices are enabled, or a count between one and four on the first
* slice.
*/
- if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) {
+ if (IS_GEN(i915, 11) && slices == 1 && subslices >= 4) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -2370,10 +2373,10 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (sseu->has_slice_pg) {
u32 mask, val = slices;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(i915) >= 11) {
mask = GEN11_RPCS_S_CNT_MASK;
val <<= GEN11_RPCS_S_CNT_SHIFT;
} else {
@@ -2398,18 +2401,16 @@ make_rpcs(struct drm_i915_private *dev_priv)
rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
}
- if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
+ if (sseu->has_eu_pg) {
u32 val;
- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
- GEN8_RPCS_EU_MIN_SHIFT;
+ val = ctx_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
val &= GEN8_RPCS_EU_MIN_MASK;
rpcs |= val;
- val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
- GEN8_RPCS_EU_MAX_SHIFT;
+ val = ctx_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
val &= GEN8_RPCS_EU_MAX_MASK;
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 3/7] drm/i915/perf: lock powergating configuration to default when active
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 2/7] drm/i915: Record the sseu configuration per-context & engine Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 4/7] drm/i915: Add timeline barrier support Tvrtko Ursulin
` (7 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram the NOA muxes
when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about the cost
of reprogramming at every context switch. This solution is also not
without consequences from the userspace point of view. Reprogramming
of the muxes can only happen once the powergating configuration has
changed (which happens after context switch). This means for a window
of time during the recording, counters recorded by the OA unit might
be invalid. This requires userspace dealing with OA reports to discard
the invalid values.
Minimizing the reprogramming could be implemented by tracking of the
last programmed configuration somewhere in GGTT and use MI_PREDICATE
to discard some of the programming commands, but the command streamer
would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.
Another solution, which this change implements, is to simply disregard
the user requested configuration for the period of time when i915/perf
is active. There is no known issue with this apart from a performance
penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from affecting the
programming so it doesn't sound completely unreasonable to hold on
powergating for the same reason.
v2: Leave RPCS programming in intel_lrc.c (Lionel)
v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
More to_intel_context() (Tvrtko)
s/dev_priv/i915/ (Tvrtko)
Tvrtko Ursulin:
v4:
* Rebase for make_rpcs changes.
v5:
* Apply OA restriction from make_rpcs directly.
v6:
* Rebase for context image setup changes.
v7:
* Move stream assignment before metric enable.
v8-9:
* Rebase.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++----
drivers/gpu/drm/i915/intel_lrc.c | 31 ++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_lrc.h | 2 ++
3 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 4288c0e02f0c..7ac76c7aa4bf 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1677,6 +1677,11 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
CTX_REG(reg_state, state_offset, flex_regs[i], value);
}
+
+ CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+ gen8_make_rpcs(dev_priv,
+ &to_intel_context(ctx,
+ dev_priv->engine[RCS])->sseu));
}
/*
@@ -2098,21 +2103,21 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
if (ret)
goto err_lock;
+ stream->ops = &i915_oa_stream_ops;
+ dev_priv->perf.oa.exclusive_stream = stream;
+
ret = dev_priv->perf.oa.ops.enable_metric_set(stream);
if (ret) {
DRM_DEBUG("Unable to enable metric set\n");
goto err_enable;
}
- stream->ops = &i915_oa_stream_ops;
-
- dev_priv->perf.oa.exclusive_stream = stream;
-
mutex_unlock(&dev_priv->drm.struct_mutex);
return 0;
err_enable:
+ dev_priv->perf.oa.exclusive_stream = NULL;
dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bfc31ccf5382..59e90d3e76f6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1170,9 +1170,6 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
return i915_vma_pin(vma, 0, 0, flags);
}
-static u32
-make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
-
static void
__execlists_update_reg_state(struct intel_engine_cs *engine,
struct intel_context *ce)
@@ -1186,8 +1183,8 @@ __execlists_update_reg_state(struct intel_engine_cs *engine,
/* RPCS */
if (engine->class == RENDER_CLASS)
- regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915,
- &ce->sseu);
+ regs[CTX_R_PWR_CLK_STATE + 1] = gen8_make_rpcs(engine->i915,
+ &ce->sseu);
}
static struct intel_context *
@@ -2319,13 +2316,12 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
return logical_ring_init(engine);
}
-static u32
-make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
+u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
{
const struct sseu_dev_info *sseu = &INTEL_INFO(i915)->sseu;
bool subslice_pg = sseu->has_subslice_pg;
- u8 slices = hweight8(ctx_sseu->slice_mask);
- u8 subslices = hweight8(ctx_sseu->subslice_mask);
+ struct intel_sseu ctx_sseu;
+ u8 slices, subslices;
u32 rpcs = 0;
/*
@@ -2335,6 +2331,19 @@ make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
if (INTEL_GEN(i915) < 9)
return 0;
+ /*
+ * If i915/perf is active, we want a stable powergating configuration
+ * on the system. The most natural configuration to take in that case
+ * is the default (i.e maximum the hardware can do).
+ */
+ if (unlikely(i915->perf.oa.exclusive_stream))
+ ctx_sseu = intel_device_default_sseu(i915);
+ else
+ ctx_sseu = *req_sseu;
+
+ slices = hweight8(ctx_sseu.slice_mask);
+ subslices = hweight8(ctx_sseu.subslice_mask);
+
/*
* Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
* wide and Icelake has up to eight subslices, specfial programming is
@@ -2404,13 +2413,13 @@ make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
if (sseu->has_eu_pg) {
u32 val;
- val = ctx_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
+ val = ctx_sseu.min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
val &= GEN8_RPCS_EU_MIN_MASK;
rpcs |= val;
- val = ctx_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
+ val = ctx_sseu.max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
val &= GEN8_RPCS_EU_MAX_MASK;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..a4e28cc55fda 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -104,4 +104,6 @@ void intel_lr_context_resume(struct drm_i915_private *dev_priv);
void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
+u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
+
#endif /* _INTEL_LRC_H_ */
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 4/7] drm/i915: Add timeline barrier support
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (2 preceding siblings ...)
2018-12-14 12:34 ` [PATCH 3/7] drm/i915/perf: lock powergating configuration to default when active Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 13:26 ` Chris Wilson
2018-12-14 12:34 ` [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) Tvrtko Ursulin
` (6 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Timeline barrier allows serialization between different timelines.
After calling i915_timeline_set_barrier with a request, all following
submissions on this timeline will be set up as depending on this request,
or barrier. Once the barrier has been completed it automatically gets
cleared and things continue as normal.
This facility will be used by the upcoming context SSEU code.
v2:
* Assert barrier has been retired on timeline_fini. (Chris Wilson)
* Fix mock_timeline.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_request.c | 13 +++++++++
drivers/gpu/drm/i915/i915_timeline.c | 3 +++
drivers/gpu/drm/i915/i915_timeline.h | 27 +++++++++++++++++++
.../gpu/drm/i915/selftests/mock_timeline.c | 2 ++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 637909c59f1f..48c615db1810 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -566,6 +566,15 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
return NOTIFY_DONE;
}
+static int add_timeline_barrier(struct i915_request *rq)
+{
+ struct i915_request *barrier =
+ i915_gem_active_raw(&rq->timeline->barrier,
+ &rq->i915->drm.struct_mutex);
+
+ return barrier ? i915_request_await_dma_fence(rq, &barrier->fence) : 0;
+}
+
/**
* i915_request_alloc - allocate a request structure
*
@@ -719,6 +728,10 @@ i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
*/
rq->head = rq->ring->emit;
+ ret = add_timeline_barrier(rq);
+ if (ret)
+ goto err_unwind;
+
ret = engine->request_alloc(rq);
if (ret)
goto err_unwind;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 4667cc08c416..5a87c5bd5154 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -37,6 +37,8 @@ void i915_timeline_init(struct drm_i915_private *i915,
INIT_LIST_HEAD(&timeline->requests);
i915_syncmap_init(&timeline->sync);
+
+ init_request_active(&timeline->barrier, NULL);
}
/**
@@ -69,6 +71,7 @@ void i915_timelines_park(struct drm_i915_private *i915)
void i915_timeline_fini(struct i915_timeline *timeline)
{
GEM_BUG_ON(!list_empty(&timeline->requests));
+ GEM_BUG_ON(i915_gem_active_isset(&timeline->barrier));
i915_syncmap_free(&timeline->sync);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h
index ebd71b487220..6ee301f20bab 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -72,6 +72,16 @@ struct i915_timeline {
*/
u32 global_sync[I915_NUM_ENGINES];
+ /**
+ * Barrier provides the ability to serialize ordering between different
+ * timelines.
+ *
+ * Users can call i915_timeline_set_barrier which will make all
+ * subsequent submissions be executed only after this barrier has been
+ * completed.
+ */
+ struct i915_gem_active barrier;
+
struct list_head link;
const char *name;
@@ -144,4 +154,21 @@ static inline bool i915_timeline_sync_is_later(struct i915_timeline *tl,
void i915_timelines_park(struct drm_i915_private *i915);
+/**
+ * i915_timeline_set_barrier - orders submission between different timelines
+ * @timeline: timeline to set the barrier on
+ * @rq: request after which new submissions can proceed
+ *
+ * Sets the passed in request as the serialization point for all subsequent
+ * submissions on @timeline. Subsequent requests will not be submitted to GPU
+ * until the barrier has been completed.
+ */
+static inline void
+i915_timeline_set_barrier(struct i915_timeline *timeline,
+ struct i915_request *rq)
+{
+ GEM_BUG_ON(timeline->fence_context == rq->timeline->fence_context);
+ i915_gem_active_set(&timeline->barrier, rq);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index dcf3b16f5a07..a718b64c988e 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -19,6 +19,8 @@ void mock_timeline_init(struct i915_timeline *timeline, u64 context)
i915_syncmap_init(&timeline->sync);
+ init_request_active(&timeline->barrier, NULL);
+
INIT_LIST_HEAD(&timeline->link);
}
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 4/7] drm/i915: Add timeline barrier support
2018-12-14 12:34 ` [PATCH 4/7] drm/i915: Add timeline barrier support Tvrtko Ursulin
@ 2018-12-14 13:26 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2018-12-14 13:26 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-12-14 12:34:46)
> diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h
> index ebd71b487220..6ee301f20bab 100644
> --- a/drivers/gpu/drm/i915/i915_timeline.h
> +++ b/drivers/gpu/drm/i915/i915_timeline.h
> @@ -72,6 +72,16 @@ struct i915_timeline {
> */
> u32 global_sync[I915_NUM_ENGINES];
>
> + /**
> + * Barrier provides the ability to serialize ordering between different
> + * timelines.
> + *
> + * Users can call i915_timeline_set_barrier which will make all
> + * subsequent submissions be executed only after this barrier has been
submissions on/to this timeline
then s/this barrier/the barrier/ to avoid repitation of this.
> + * completed.
> + */
> + struct i915_gem_active barrier;
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (3 preceding siblings ...)
2018-12-14 12:34 ` [PATCH 4/7] drm/i915: Add timeline barrier support Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 13:33 ` Chris Wilson
2018-12-14 12:34 ` [PATCH 6/7] drm/i915/icl: Support co-existence between per-context SSEU and OA Tvrtko Ursulin
` (5 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
We want to allow userspace to reconfigure the subslice configuration on a
per context basis.
This is required for the functional requirement of shutting down non-VME
enabled sub-slices on Gen11 parts.
To do so, we expose a context parameter to allow adjustment of the RPCS
register stored within the context image (and currently not accessible via
LRI).
If the context is adjusted before first use or whilst idle, the adjustment
is for "free"; otherwise if the context is active we queue a request to do
so (using the kernel context), following all other activity by that
context, which is also marked as barrier for all following submission
against the same context.
Since the overhead of device re-configuration during context switching can
be significant, especially in multi-context workloads, we limit this new
uAPI to only support the Gen11 VME use case. In this use case either the
device is fully enabled, and exactly one slice and half of the subslices
are enabled.
Example usage:
struct drm_i915_gem_context_param_sseu sseu = { };
struct drm_i915_gem_context_param arg =
{ .param = I915_CONTEXT_PARAM_SSEU,
.ctx_id = gem_context_create(fd),
.size = sizeof(sseu),
.value = to_user_pointer(&sseu)
};
/* Query device defaults. */
gem_context_get_param(fd, &arg);
/* Set VME configuration on a 1x6x8 part. */
sseu.slice_mask = 0x1;
sseu.subslice_mask = 0xe0;
gem_context_set_param(fd, &arg);
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
v3: Add ability to program this per engine (Chris)
v4: Move most get_sseu() into i915_gem_context.c (Lionel)
v5: Validate sseu configuration against the device's capabilities (Lionel)
v6: Change context powergating settings through MI_SDM on kernel context (Chris)
v7: Synchronize the requests following a powergating setting change using a global
dependency (Chris)
Iterate timelines through dev_priv.gt.active_rings (Tvrtko)
Disable RPCS configuration setting for non capable users (Lionel/Tvrtko)
v8: s/union intel_sseu/struct intel_sseu/ (Lionel)
s/dev_priv/i915/ (Tvrtko)
Change uapi class/instance fields to u16 (Tvrtko)
Bump mask fields to 64bits (Lionel)
Don't return EPERM when dynamic sseu is disabled (Tvrtko)
v9: Import context image into kernel context's ppgtt only when
reconfiguring powergated slice/subslices (Chris)
Use aliasing ppgtt when needed (Michel)
Tvrtko Ursulin:
v10:
* Update for upstream changes.
* Request submit needs a RPM reference.
* Reject on !FULL_PPGTT for simplicity.
* Pull out get/set param to helpers for readability and less indent.
* Use i915_request_await_dma_fence in add_global_barrier to skip waits
on the same timeline and avoid GEM_BUG_ON.
* No need to explicitly assign a NULL pointer to engine in legacy mode.
* No need to move gen8_make_rpcs up.
* Factored out global barrier as prep patch.
* Allow to only CAP_SYS_ADMIN if !Gen11.
v11:
* Remove engine vfunc in favour of local helper. (Chris Wilson)
* Stop retiring requests before updates since it is not needed
(Chris Wilson)
* Implement direct CPU update path for idle contexts. (Chris Wilson)
* Left side dependency needs only be on the same context timeline.
(Chris Wilson)
* It is sufficient to order the timeline. (Chris Wilson)
* Reject !RCS configuration attempts with -ENODEV for now.
v12:
* Rebase for make_rpcs.
v13:
* Centralize SSEU normalization to make_rpcs.
* Type width checking (uAPI <-> implementation).
* Gen11 restrictions uAPI checks.
* Gen11 subslice count differences handling.
Chris Wilson:
* args->size handling fixes.
* Update context image from GGTT.
* Postpone context image update to pinning.
* Use i915_gem_active_raw instead of last_request_on_engine.
v14:
* Add activity tracker on intel_context to fix the lifetime issues
and simplify the code. (Chris Wilson)
v15:
* Fix context pin leak if no space in ring by simplifying the
context pinning sequence.
v16:
* Rebase for context get/set param locking changes.
* Just -ENODEV on !Gen11. (Joonas)
v17:
* Fix one Gen11 subslice enablement rule.
* Handle error from i915_sw_fence_await_sw_fence_gfp. (Chris Wilson)
v18:
* Update commit message. (Joonas)
* Restrict uAPI to VME use case. (Joonas)
v19:
* Rebase.
v20:
* Rebase for ce->active_tracker.
v21:
* Rebase for IS_GEN changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107634
Issue: https://github.com/intel/media-driver/issues/267
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Zhipeng Gong <zhipeng.gong@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_context.c | 341 +++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_gem_context.h | 6 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +-
include/uapi/drm/i915_drm.h | 43 +++
4 files changed, 391 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index a565643e9a26..78d449b6245e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
+#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -322,6 +323,15 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
return desc;
}
+static void intel_context_retire(struct i915_gem_active *active,
+ struct i915_request *rq)
+{
+ struct intel_context *ce =
+ container_of(active, typeof(*ce), active_tracker);
+
+ intel_context_unpin(ce);
+}
+
static struct i915_gem_context *
__create_hw_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
@@ -345,6 +355,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ce->gem_context = ctx;
/* Use the whole device by default */
ce->sseu = intel_device_default_sseu(dev_priv);
+
+ init_request_active(&ce->active_tracker, intel_context_retire);
}
INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
@@ -842,6 +854,56 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
return 0;
}
+static int get_sseu(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ struct drm_i915_gem_context_param_sseu user_sseu;
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+ int ret;
+
+ if (args->size == 0)
+ goto out;
+ else if (args->size < sizeof(user_sseu))
+ return -EINVAL;
+
+ if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
+ sizeof(user_sseu)))
+ return -EFAULT;
+
+ if (user_sseu.rsvd1 || user_sseu.rsvd2)
+ return -EINVAL;
+
+ engine = intel_engine_lookup_user(ctx->i915,
+ user_sseu.class,
+ user_sseu.instance);
+ if (!engine)
+ return -EINVAL;
+
+ /* Only use for mutex here is to serialize get_param and set_param. */
+ ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
+ if (ret)
+ return ret;
+
+ ce = to_intel_context(ctx, engine);
+
+ user_sseu.slice_mask = ce->sseu.slice_mask;
+ user_sseu.subslice_mask = ce->sseu.subslice_mask;
+ user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
+ user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
+
+ mutex_unlock(&ctx->i915->drm.struct_mutex);
+
+ if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
+ sizeof(user_sseu)))
+ return -EFAULT;
+
+out:
+ args->size = sizeof(user_sseu);
+
+ return 0;
+}
+
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
@@ -854,15 +916,17 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
if (!ctx)
return -ENOENT;
- args->size = 0;
switch (args->param) {
case I915_CONTEXT_PARAM_BAN_PERIOD:
ret = -EINVAL;
break;
case I915_CONTEXT_PARAM_NO_ZEROMAP:
+ args->size = 0;
args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
break;
case I915_CONTEXT_PARAM_GTT_SIZE:
+ args->size = 0;
+
if (ctx->ppgtt)
args->value = ctx->ppgtt->vm.total;
else if (to_i915(dev)->mm.aliasing_ppgtt)
@@ -871,14 +935,20 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
args->value = to_i915(dev)->ggtt.vm.total;
break;
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
+ args->size = 0;
args->value = i915_gem_context_no_error_capture(ctx);
break;
case I915_CONTEXT_PARAM_BANNABLE:
+ args->size = 0;
args->value = i915_gem_context_is_bannable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
+ args->size = 0;
args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
break;
+ case I915_CONTEXT_PARAM_SSEU:
+ ret = get_sseu(ctx, args);
+ break;
default:
ret = -EINVAL;
break;
@@ -888,6 +958,271 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
return ret;
}
+static int gen8_emit_rpcs_config(struct i915_request *rq,
+ struct intel_context *ce,
+ struct intel_sseu sseu)
+{
+ u64 offset;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ offset = ce->state->node.start +
+ LRC_STATE_PN * PAGE_SIZE +
+ (CTX_R_PWR_CLK_STATE + 1) * 4;
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+ *cs++ = gen8_make_rpcs(rq->i915, &sseu);
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int
+gen8_modify_rpcs_gpu(struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
+{
+ struct drm_i915_private *i915 = engine->i915;
+ struct i915_request *rq, *prev;
+ int ret;
+
+ GEM_BUG_ON(!ce->pin_count);
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+
+ /* Submitting requests etc needs the hw awake. */
+ intel_runtime_pm_get(i915);
+
+ rq = i915_request_alloc(engine, i915->kernel_context);
+ if (IS_ERR(rq)) {
+ ret = PTR_ERR(rq);
+ goto out_put;
+ }
+
+ /* Queue this switch after all other activity by this context. */
+ prev = i915_gem_active_raw(&ce->ring->timeline->last_request,
+ &i915->drm.struct_mutex);
+ if (prev && !i915_request_completed(prev)) {
+ ret = i915_sw_fence_await_sw_fence_gfp(&rq->submit,
+ &prev->submit,
+ I915_FENCE_GFP);
+ if (ret < 0)
+ goto out_add;
+ }
+
+ ret = gen8_emit_rpcs_config(rq, ce, sseu);
+ if (ret)
+ goto out_add;
+
+ /* Order all following requests to be after. */
+ i915_timeline_set_barrier(ce->ring->timeline, rq);
+
+ /*
+ * Guarantee context image and the timeline remains pinned until the
+ * modifying request is retired by setting the ce activity tracker.
+ *
+ * But we only need to take one pin on the account of it. Or in other
+ * words transfer the pinned ce object to tracked active request.
+ */
+ if (!i915_gem_active_isset(&ce->active_tracker))
+ __intel_context_pin(ce);
+ i915_gem_active_set(&ce->active_tracker, rq);
+
+out_add:
+ i915_request_add(rq);
+out_put:
+ intel_runtime_pm_put(i915);
+
+ return ret;
+}
+
+static int
+i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
+{
+ struct intel_context *ce = to_intel_context(ctx, engine);
+ int ret;
+
+ GEM_BUG_ON(INTEL_GEN(ctx->i915) < 8);
+ GEM_BUG_ON(engine->id != RCS);
+
+ ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
+ if (ret)
+ return ret;
+
+ /* Nothing to do if unmodified. */
+ if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
+ goto out;
+
+ /*
+ * If context is not idle we have to submit an ordered request to modify
+ * its context image via the kernel context. Pristine and idle contexts
+ * will be configured on pinning.
+ */
+ if (ce->pin_count)
+ ret = gen8_modify_rpcs_gpu(ce, engine, sseu);
+
+ if (!ret)
+ ce->sseu = sseu;
+
+out:
+ mutex_unlock(&ctx->i915->drm.struct_mutex);
+
+ return ret;
+}
+
+static int
+user_to_context_sseu(struct drm_i915_private *i915,
+ const struct drm_i915_gem_context_param_sseu *user,
+ struct intel_sseu *context)
+{
+ const struct sseu_dev_info *device = &INTEL_INFO(i915)->sseu;
+
+ /* No zeros in any field. */
+ if (!user->slice_mask || !user->subslice_mask ||
+ !user->min_eus_per_subslice || !user->max_eus_per_subslice)
+ return -EINVAL;
+
+ /* Max > min. */
+ if (user->max_eus_per_subslice < user->min_eus_per_subslice)
+ return -EINVAL;
+
+ /* Check validity against hardware. */
+ if (user->slice_mask & ~device->slice_mask)
+ return -EINVAL;
+
+ if (user->subslice_mask & ~device->subslice_mask[0])
+ return -EINVAL;
+
+ if (user->max_eus_per_subslice > device->max_eus_per_subslice)
+ return -EINVAL;
+
+ /*
+ * Some future proofing on the types since the uAPI is wider than the
+ * current internal implementation.
+ */
+ if (WARN_ON((fls(user->slice_mask) >
+ sizeof(context->slice_mask) * BITS_PER_BYTE) ||
+ (fls(user->subslice_mask) >
+ sizeof(context->subslice_mask) * BITS_PER_BYTE) ||
+ overflows_type(user->min_eus_per_subslice,
+ context->min_eus_per_subslice) ||
+ overflows_type(user->max_eus_per_subslice,
+ context->max_eus_per_subslice)))
+ return -EINVAL;
+
+ context->slice_mask = user->slice_mask;
+ context->subslice_mask = user->subslice_mask;
+ context->min_eus_per_subslice = user->min_eus_per_subslice;
+ context->max_eus_per_subslice = user->max_eus_per_subslice;
+
+ /* Part specific restrictions. */
+ if (IS_GEN(i915, 11)) {
+ unsigned int hw_s = hweight8(device->slice_mask);
+ unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int req_s = hweight8(context->slice_mask);
+ unsigned int req_ss = hweight8(context->subslice_mask);
+
+ /*
+ * Only full subslice enablement is possible if more than one
+ * slice is turned on.
+ */
+ if (req_s > 1 && req_ss != hw_ss_per_s)
+ return -EINVAL;
+
+ /*
+ * If more than four (SScount bitfield limit) subslices are
+ * requested then the number has to be even.
+ */
+ if (req_ss > 4 && (req_ss & 1))
+ return -EINVAL;
+
+ /*
+ * If only one slice is enabled and subslice count is below the
+ * device full enablement, it must be at most half of the all
+ * available subslices.
+ */
+ if (req_s == 1 && req_ss < hw_ss_per_s &&
+ req_ss > (hw_ss_per_s / 2))
+ return -EINVAL;
+
+ /* ABI restriction - VME use case only. */
+
+ /* All slices or one slice only. */
+ if (req_s != 1 && req_s != hw_s)
+ return -EINVAL;
+
+ /*
+ * Half subslices or full enablement only when one slice is
+ * enabled.
+ */
+ if (req_s == 1 &&
+ (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
+ return -EINVAL;
+
+ /* No EU configuration changes. */
+ if ((user->min_eus_per_subslice !=
+ device->max_eus_per_subslice) ||
+ (user->max_eus_per_subslice !=
+ device->max_eus_per_subslice))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int set_sseu(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_context_param_sseu user_sseu;
+ struct intel_engine_cs *engine;
+ struct intel_sseu sseu;
+ int ret;
+
+ if (args->size < sizeof(user_sseu))
+ return -EINVAL;
+
+ if (!IS_GEN(i915, 11))
+ return -ENODEV;
+
+ if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
+ sizeof(user_sseu)))
+ return -EFAULT;
+
+ if (user_sseu.rsvd1 || user_sseu.rsvd2)
+ return -EINVAL;
+
+ engine = intel_engine_lookup_user(i915,
+ user_sseu.class,
+ user_sseu.instance);
+ if (!engine)
+ return -EINVAL;
+
+ /* Only render engine supports RPCS configuration. */
+ if (engine->class != RENDER_CLASS)
+ return -ENODEV;
+
+ ret = user_to_context_sseu(i915, &user_sseu, &sseu);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
+ if (ret)
+ return ret;
+
+ args->size = sizeof(user_sseu);
+
+ return 0;
+}
+
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
@@ -950,7 +1285,9 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
I915_USER_PRIORITY(priority);
}
break;
-
+ case I915_CONTEXT_PARAM_SSEU:
+ ret = set_sseu(ctx, args);
+ break;
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index ef04e422cf9a..2ded4b8c9b9f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -171,6 +171,12 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
+ /**
+ * active_tracker: Active tracker for the external rq activity
+ * on this intel_context object.
+ */
+ struct i915_gem_active active_tracker;
+
const struct intel_context_ops *ops;
/** sseu: Control eu/slice partitioning */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 59e90d3e76f6..d392c2cef1d7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2369,7 +2369,9 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
* subslices are enabled, or a count between one and four on the first
* slice.
*/
- if (IS_GEN(i915, 11) && slices == 1 && subslices >= 4) {
+ if (IS_GEN(i915, 11) &&
+ slices == 1 &&
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 298b2e197744..22021d14efd4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1486,9 +1486,52 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
+ /*
+ * When using the following param, value should be a pointer to
+ * drm_i915_gem_context_param_sseu.
+ */
+#define I915_CONTEXT_PARAM_SSEU 0x7
__u64 value;
};
+struct drm_i915_gem_context_param_sseu {
+ /*
+ * Engine class & instance to be configured or queried.
+ */
+ __u16 class;
+ __u16 instance;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 rsvd1;
+
+ /*
+ * Mask of slices to enable for the context. Valid values are a subset
+ * of the bitmask value returned for I915_PARAM_SLICE_MASK.
+ */
+ __u64 slice_mask;
+
+ /*
+ * Mask of subslices to enable for the context. Valid values are a
+ * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
+ */
+ __u64 subslice_mask;
+
+ /*
+ * Minimum/Maximum number of EUs to enable per subslice for the
+ * context. min_eus_per_subslice must be inferior or equal to
+ * max_eus_per_subslice.
+ */
+ __u16 min_eus_per_subslice;
+ __u16 max_eus_per_subslice;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 rsvd2;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
2018-12-14 12:34 ` [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) Tvrtko Ursulin
@ 2018-12-14 13:33 ` Chris Wilson
2018-12-31 15:21 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2018-12-14 13:33 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-12-14 12:34:47)
> +static int get_sseu(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + struct drm_i915_gem_context_param_sseu user_sseu;
> + struct intel_engine_cs *engine;
> + struct intel_context *ce;
> + int ret;
> +
> + if (args->size == 0)
> + goto out;
> + else if (args->size < sizeof(user_sseu))
> + return -EINVAL;
> +
> + if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
> + sizeof(user_sseu)))
> + return -EFAULT;
> +
> + if (user_sseu.rsvd1 || user_sseu.rsvd2)
> + return -EINVAL;
I'd vote for s/rsvd2/flags/ straight away as already I can suggest we
allow for USE_CTX_ENGINE to swap class/instance for engine-id so that we
can set rpcs for, and not least, a virtual engine.
> +
> + engine = intel_engine_lookup_user(ctx->i915,
> + user_sseu.class,
> + user_sseu.instance);
> + if (!engine)
> + return -EINVAL;
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
2018-12-14 13:33 ` Chris Wilson
@ 2018-12-31 15:21 ` Tvrtko Ursulin
2018-12-31 15:33 ` Chris Wilson
0 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-31 15:21 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 14/12/2018 13:33, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-12-14 12:34:47)
>> +static int get_sseu(struct i915_gem_context *ctx,
>> + struct drm_i915_gem_context_param *args)
>> +{
>> + struct drm_i915_gem_context_param_sseu user_sseu;
>> + struct intel_engine_cs *engine;
>> + struct intel_context *ce;
>> + int ret;
>> +
>> + if (args->size == 0)
>> + goto out;
>> + else if (args->size < sizeof(user_sseu))
>> + return -EINVAL;
>> +
>> + if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
>> + sizeof(user_sseu)))
>> + return -EFAULT;
>> +
>> + if (user_sseu.rsvd1 || user_sseu.rsvd2)
>> + return -EINVAL;
>
> I'd vote for s/rsvd2/flags/ straight away as already I can suggest we
> allow for USE_CTX_ENGINE to swap class/instance for engine-id so that we
> can set rpcs for, and not least, a virtual engine.
Hm.. would it be useful? It would just be a way of indirection.
engines = [vcs:0, vcs:1]
ctx.set_map(engines)
And then a):
foreach engine in engines:
ctx.set_sseu(engine, flags=0)
vs b):
for i = 0; i < len(engines); i++:
ctx.set_sseu(i, flags=USE_CTX_ENGINE)
So I don't see any benefit. But maybe I missed your idea.
Regards,
Tvrtko
>
>> +
>> + engine = intel_engine_lookup_user(ctx->i915,
>> + user_sseu.class,
>> + user_sseu.instance);
>> + if (!engine)
>> + return -EINVAL;
> -Chris
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
2018-12-31 15:21 ` Tvrtko Ursulin
@ 2018-12-31 15:33 ` Chris Wilson
2018-12-31 15:39 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2018-12-31 15:33 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-12-31 15:21:15)
>
> On 14/12/2018 13:33, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-12-14 12:34:47)
> >> +static int get_sseu(struct i915_gem_context *ctx,
> >> + struct drm_i915_gem_context_param *args)
> >> +{
> >> + struct drm_i915_gem_context_param_sseu user_sseu;
> >> + struct intel_engine_cs *engine;
> >> + struct intel_context *ce;
> >> + int ret;
> >> +
> >> + if (args->size == 0)
> >> + goto out;
> >> + else if (args->size < sizeof(user_sseu))
> >> + return -EINVAL;
> >> +
> >> + if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
> >> + sizeof(user_sseu)))
> >> + return -EFAULT;
> >> +
> >> + if (user_sseu.rsvd1 || user_sseu.rsvd2)
> >> + return -EINVAL;
> >
> > I'd vote for s/rsvd2/flags/ straight away as already I can suggest we
> > allow for USE_CTX_ENGINE to swap class/instance for engine-id so that we
> > can set rpcs for, and not least, a virtual engine.
>
> Hm.. would it be useful? It would just be a way of indirection.
>
> engines = [vcs:0, vcs:1]
> ctx.set_map(engines)
>
> And then a):
>
> foreach engine in engines:
> ctx.set_sseu(engine, flags=0)
>
> vs b):
>
> for i = 0; i < len(engines); i++:
> ctx.set_sseu(i, flags=USE_CTX_ENGINE)
>
> So I don't see any benefit. But maybe I missed your idea.
The virtual engine doesn't have a valid class:instance, only its index
in the per-context engines[]. And we want to control its context image,
not the context images on each of the real engine.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
2018-12-31 15:33 ` Chris Wilson
@ 2018-12-31 15:39 ` Tvrtko Ursulin
0 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-31 15:39 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 31/12/2018 15:33, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-12-31 15:21:15)
>>
>> On 14/12/2018 13:33, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2018-12-14 12:34:47)
>>>> +static int get_sseu(struct i915_gem_context *ctx,
>>>> + struct drm_i915_gem_context_param *args)
>>>> +{
>>>> + struct drm_i915_gem_context_param_sseu user_sseu;
>>>> + struct intel_engine_cs *engine;
>>>> + struct intel_context *ce;
>>>> + int ret;
>>>> +
>>>> + if (args->size == 0)
>>>> + goto out;
>>>> + else if (args->size < sizeof(user_sseu))
>>>> + return -EINVAL;
>>>> +
>>>> + if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
>>>> + sizeof(user_sseu)))
>>>> + return -EFAULT;
>>>> +
>>>> + if (user_sseu.rsvd1 || user_sseu.rsvd2)
>>>> + return -EINVAL;
>>>
>>> I'd vote for s/rsvd2/flags/ straight away as already I can suggest we
>>> allow for USE_CTX_ENGINE to swap class/instance for engine-id so that we
>>> can set rpcs for, and not least, a virtual engine.
>>
>> Hm.. would it be useful? It would just be a way of indirection.
>>
>> engines = [vcs:0, vcs:1]
>> ctx.set_map(engines)
>>
>> And then a):
>>
>> foreach engine in engines:
>> ctx.set_sseu(engine, flags=0)
>>
>> vs b):
>>
>> for i = 0; i < len(engines); i++:
>> ctx.set_sseu(i, flags=USE_CTX_ENGINE)
>>
>> So I don't see any benefit. But maybe I missed your idea.
>
> The virtual engine doesn't have a valid class:instance, only its index
> in the per-context engines[]. And we want to control its context image,
> not the context images on each of the real engine.
True. At first I was thinking that it is equivalent to setting SSEU to
all engines from the map but of course we only have one context image..
Okay, I will rename this to flags straight away.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 6/7] drm/i915/icl: Support co-existence between per-context SSEU and OA
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (4 preceding siblings ...)
2018-12-14 12:34 ` [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only) Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 12:34 ` [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests Tvrtko Ursulin
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
When OA is active we want to lock the powergating configuration, but on
Icelake, users like the media stack will have issues if we lock to the
full device configuration.
Instead lock to a subset of (sub)slices which are currently a known
working configuration for all users.
v2:
* Fix commit message spelling.
v3:
Lionel:
* Add bspec reference.
* Fix spelling in comment.
v4:
* Rebase for IS_GEN changes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Bspec: 21140
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d392c2cef1d7..57a43d3d07f1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2333,13 +2333,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
/*
* If i915/perf is active, we want a stable powergating configuration
- * on the system. The most natural configuration to take in that case
- * is the default (i.e maximum the hardware can do).
+ * on the system.
+ *
+ * We could choose full enablement, but on ICL we know there are use
+ * cases which disable slices for functional, apart for performance
+ * reasons. So in this case we select a known stable subset.
*/
- if (unlikely(i915->perf.oa.exclusive_stream))
- ctx_sseu = intel_device_default_sseu(i915);
- else
+ if (!i915->perf.oa.exclusive_stream) {
ctx_sseu = *req_sseu;
+ } else {
+ ctx_sseu = intel_device_default_sseu(i915);
+
+ if (IS_GEN(i915, 11)) {
+ /*
+ * We only need subslice count so it doesn't matter
+ * which ones we select - just turn off low bits in the
+ * amount of half of all available subslices per slice.
+ */
+ ctx_sseu.subslice_mask =
+ ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
+ ctx_sseu.slice_mask = 0x1;
+ }
+ }
slices = hweight8(ctx_sseu.slice_mask);
subslices = hweight8(ctx_sseu.subslice_mask);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (5 preceding siblings ...)
2018-12-14 12:34 ` [PATCH 6/7] drm/i915/icl: Support co-existence between per-context SSEU and OA Tvrtko Ursulin
@ 2018-12-14 12:34 ` Tvrtko Ursulin
2018-12-14 13:04 ` Chris Wilson
2018-12-14 13:22 ` Chris Wilson
2018-12-14 12:55 ` ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev8) Patchwork
` (3 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2018-12-14 12:34 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Exercise the context image reconfiguration logic for idle and busy
contexts, with the resets thrown into the mix as well.
Free from the uAPI restrictions this test runs on all Gen9+ platforms
with slice power gating.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_gem_context.c | 36 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 489 ++++++++++++++++++
2 files changed, 514 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 78d449b6245e..fcb19b6f635e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1042,24 +1042,23 @@ gen8_modify_rpcs_gpu(struct intel_context *ce,
return ret;
}
-static int
-i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_sseu sseu)
+#if !IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+static
+#endif
+int
+__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
{
struct intel_context *ce = to_intel_context(ctx, engine);
- int ret;
+ int ret = 0;
GEM_BUG_ON(INTEL_GEN(ctx->i915) < 8);
GEM_BUG_ON(engine->id != RCS);
- ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
- if (ret)
- return ret;
-
/* Nothing to do if unmodified. */
if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
- goto out;
+ return 0;
/*
* If context is not idle we have to submit an ordered request to modify
@@ -1072,7 +1071,22 @@ i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
if (!ret)
ce->sseu = sseu;
-out:
+ return ret;
+}
+
+static int
+i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
+{
+ int ret;
+
+ ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
+ if (ret)
+ return ret;
+
+ ret = __i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
+
mutex_unlock(&ctx->i915->drm.struct_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7d82043aff10..2b4eb5d05915 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -27,6 +27,8 @@
#include "../i915_selftest.h"
#include "i915_random.h"
#include "igt_flush_test.h"
+#include "igt_reset.h"
+#include "igt_spinner.h"
#include "mock_drm.h"
#include "mock_gem_device.h"
@@ -650,6 +652,487 @@ static int igt_ctx_exec(void *arg)
return err;
}
+static struct i915_vma *rpcs_query_batch(struct i915_vma *vma)
+{
+ struct drm_i915_gem_object *obj;
+ u32 *cmd;
+ int err;
+
+ if (INTEL_GEN(vma->vm->i915) < 8)
+ return ERR_PTR(-EINVAL);
+
+ obj = i915_gem_object_create_internal(vma->vm->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto err;
+ }
+
+ *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
+ *cmd++ = lower_32_bits(vma->node.start);
+ *cmd++ = upper_32_bits(vma->node.start);
+ *cmd = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ goto err;
+
+ vma = i915_vma_instance(obj, vma->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err;
+
+ return vma;
+
+err:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static int
+emit_rpcs_query(struct drm_i915_gem_object *obj,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct i915_request **rq_out)
+{
+ struct i915_address_space *vm;
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ struct i915_vma *vma;
+ int err;
+
+ GEM_BUG_ON(!ctx->ppgtt);
+ GEM_BUG_ON(!intel_engine_can_store_dword(engine));
+
+ vm = &ctx->ppgtt->vm;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ return err;
+
+ err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
+ if (err)
+ return err;
+
+ batch = rpcs_query_batch(vma);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto err_vma;
+ }
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_batch;
+ }
+
+ err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+ if (err)
+ goto err_request;
+
+ err = i915_vma_move_to_active(batch, rq, 0);
+ if (err)
+ goto skip_request;
+
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ if (err)
+ goto skip_request;
+
+ i915_gem_object_set_active_reference(batch->obj);
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
+
+ i915_vma_unpin(vma);
+
+ *rq_out = i915_request_get(rq);
+
+ i915_request_add(rq);
+
+ return 0;
+
+skip_request:
+ i915_request_skip(rq, err);
+err_request:
+ i915_request_add(rq);
+err_batch:
+ i915_vma_unpin(batch);
+err_vma:
+ i915_vma_unpin(vma);
+
+ return err;
+}
+
+#define TEST_IDLE (1 << 0)
+#define TEST_BUSY (1 << 1)
+#define TEST_RESET (1 << 2)
+
+int
+__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu);
+
+static int
+__pre_set(struct drm_i915_private *i915,
+ unsigned int flags,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct igt_spinner **spin_out)
+{
+ int ret = 0;
+
+ if (flags & (TEST_BUSY | TEST_RESET)) {
+ struct igt_spinner *spin;
+ struct i915_request *rq;
+
+ spin = kzalloc(sizeof(*spin), GFP_KERNEL);
+ if (!spin) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = igt_spinner_init(spin, i915);
+ if (ret)
+ return ret;
+
+ rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
+ if (IS_ERR(rq)) {
+ ret = PTR_ERR(rq);
+ igt_spinner_fini(spin);
+ kfree(spin);
+ goto out;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(spin, rq)) {
+ pr_err("Spinner failed to start!\n");
+ igt_spinner_end(spin);
+ igt_spinner_fini(spin);
+ kfree(spin);
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ *spin_out = spin;
+ }
+
+out:
+ return ret;
+}
+
+static int
+__read_slice_count(struct drm_i915_private *i915,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ struct igt_spinner *spin,
+ u32 *rpcs)
+{
+ struct i915_request *rq = NULL;
+ u32 s_mask, s_shift;
+ unsigned int cnt;
+ u32 *buf, val;
+ long ret;
+
+ ret = emit_rpcs_query(obj, ctx, engine, &rq);
+ if (ret)
+ return ret;
+
+ if (spin)
+ igt_spinner_end(spin);
+
+ ret = i915_request_wait(rq, I915_WAIT_LOCKED, MAX_SCHEDULE_TIMEOUT);
+ if (ret <= 0)
+ return ret < 0 ? ret : -ETIME;
+
+ i915_request_put(rq);
+
+ buf = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(buf)) {
+ ret = PTR_ERR(buf);
+ return ret;
+ }
+
+ if (INTEL_GEN(i915) >= 11) {
+ s_mask = GEN11_RPCS_S_CNT_MASK;
+ s_shift = GEN11_RPCS_S_CNT_SHIFT;
+ } else {
+ s_mask = GEN8_RPCS_S_CNT_MASK;
+ s_shift = GEN8_RPCS_S_CNT_SHIFT;
+ }
+
+ val = *buf;
+ cnt = (val & s_mask) >> s_shift;
+ *rpcs = val;
+
+ i915_gem_object_unpin_map(obj);
+
+ return cnt;
+}
+
+static void __err_rpcs(u32 rpcs, unsigned int slices)
+{
+ pr_info("RPCS=0x%x; %u%sx%u%s\n",
+ rpcs, slices,
+ (rpcs & GEN8_RPCS_S_CNT_ENABLE) ? "*" : "",
+ (rpcs & GEN8_RPCS_SS_CNT_MASK) >> GEN8_RPCS_SS_CNT_SHIFT,
+ (rpcs & GEN8_RPCS_SS_CNT_ENABLE) ? "*" : "");
+}
+
+static int
+__post_set(struct drm_i915_private *i915,
+ unsigned int flags,
+ struct i915_gem_context *ctx,
+ struct i915_gem_context *kctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ unsigned int expected,
+ struct igt_spinner *spin)
+{
+ unsigned int slices =
+ hweight32(intel_device_default_sseu(i915).slice_mask);
+ u32 rpcs = 0;
+ int ret = 0;
+
+ if (flags & TEST_RESET) {
+ ret = i915_reset_engine(engine, "sseu");
+ if (ret)
+ goto out;
+ }
+
+ ret = __read_slice_count(i915, ctx, engine, obj,
+ flags & TEST_RESET ? NULL : spin, &rpcs);
+ if (ret < 0) {
+ goto out;
+ } else if (ret != expected) {
+ pr_err("Context slice count %d is not %u!\n",
+ ret, expected);
+ __err_rpcs(rpcs, ret);
+ ret = -EINVAL;
+ goto out;
+ } else {
+ ret = 0;
+ }
+
+ ret = __read_slice_count(i915, kctx, engine, obj, NULL, &rpcs);
+ if (ret < 0) {
+ goto out;
+ } else if (ret != slices) {
+ pr_err("Kernel context slice count %d is not %u!\n",
+ ret, slices);
+ __err_rpcs(rpcs, ret);
+ ret = -EINVAL;
+ goto out;
+ } else {
+ ret = 0;
+ }
+
+out:
+ if (spin)
+ igt_spinner_end(spin);
+
+ if (flags & TEST_IDLE) {
+ ret = i915_gem_wait_for_idle(i915,
+ I915_WAIT_LOCKED,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = __read_slice_count(i915, ctx, engine, obj, NULL, &rpcs);
+ if (ret < 0) {
+ return ret;
+ } else if (ret != expected) {
+ pr_err("Context slice count %d is not %u after idle!\n",
+ ret, expected);
+ __err_rpcs(rpcs, ret);
+ return -EINVAL;
+ } else {
+ ret = 0;
+ }
+ }
+
+ return ret;
+
+}
+
+static int
+__sseu_test(struct drm_i915_private *i915,
+ unsigned int flags,
+ struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ struct intel_sseu sseu)
+{
+ struct igt_spinner *spin = NULL;
+ struct i915_gem_context *kctx;
+ int ret;
+
+ kctx = kernel_context(i915);
+ if (IS_ERR(kctx))
+ return PTR_ERR(kctx);
+
+ ret = __pre_set(i915, flags, ctx, engine, &spin);
+ if (ret)
+ goto out;
+
+ ret = __i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
+ if (ret)
+ goto out;
+
+ ret = __post_set(i915, flags, ctx, kctx, engine, obj,
+ hweight32(sseu.slice_mask), spin);
+
+out:
+ if (spin) {
+ igt_spinner_end(spin);
+ igt_spinner_fini(spin);
+ kfree(spin);
+ }
+
+ kernel_context_close(kctx);
+
+ return ret;
+}
+
+static int __igt_ctx_sseu(struct drm_i915_private *i915, unsigned int flags)
+{
+ struct intel_sseu default_sseu = intel_device_default_sseu(i915);
+ struct intel_engine_cs *engine = i915->engine[RCS];
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct intel_sseu pg_sseu;
+ struct drm_file *file;
+ int ret;
+
+ if (INTEL_GEN(i915) < 9)
+ return 0;
+
+ if (!INTEL_INFO(i915)->sseu.has_slice_pg)
+ return 0;
+
+ if (hweight32(default_sseu.slice_mask) < 2)
+ return 0;
+
+ /*
+ * Gen11 VME friendly power-gated configuration with half enabled
+ * sub-slices.
+ */
+ pg_sseu = default_sseu;
+ pg_sseu.slice_mask = 1;
+ pg_sseu.subslice_mask =
+ ~(~0 << (hweight32(default_sseu.subslice_mask) / 2));
+
+ pr_info("SSE subtest flags=%x, def_slices=%u, pg_slices=%u\n",
+ flags, hweight32(default_sseu.slice_mask),
+ hweight32(pg_sseu.slice_mask));
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ if (flags & TEST_RESET)
+ igt_global_reset_lock(i915);
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ ctx = i915_gem_create_context(i915, file->driver_priv);
+ if (IS_ERR(ctx)) {
+ ret = PTR_ERR(ctx);
+ goto out_unlock;
+ }
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ ret = PTR_ERR(obj);
+ goto out_unlock;
+ }
+
+ intel_runtime_pm_get(i915);
+
+ /* First set the default mask. */
+ ret = __sseu_test(i915, flags, ctx, engine, obj, default_sseu);
+ if (ret)
+ goto out_fail;
+
+ /* Then set a power-gated configuration. */
+ ret = __sseu_test(i915, flags, ctx, engine, obj, pg_sseu);
+ if (ret)
+ goto out_fail;
+
+ /* Back to defaults. */
+ ret = __sseu_test(i915, flags, ctx, engine, obj, default_sseu);
+ if (ret)
+ goto out_fail;
+
+ /* One last power-gated configuration for the road. */
+ ret = __sseu_test(i915, flags, ctx, engine, obj, pg_sseu);
+ if (ret)
+ goto out_fail;
+
+out_fail:
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ ret = -EIO;
+
+ i915_gem_object_put(obj);
+
+ intel_runtime_pm_put(i915);
+
+out_unlock:
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ if (flags & TEST_RESET)
+ igt_global_reset_unlock(i915);
+
+ mock_file_free(i915, file);
+
+ return ret;
+}
+
+static int igt_ctx_sseu(void *arg)
+{
+ return __igt_ctx_sseu(arg, 0);
+}
+
+static int igt_ctx_sseu_idle(void *arg)
+{
+ return __igt_ctx_sseu(arg, TEST_IDLE);
+}
+
+static int igt_ctx_sseu_busy(void *arg)
+{
+ return __igt_ctx_sseu(arg, TEST_BUSY);
+}
+
+static int igt_ctx_sseu_busy_reset(void *arg)
+{
+ return __igt_ctx_sseu(arg, TEST_BUSY | TEST_RESET);
+}
+
+static int igt_ctx_sseu_busy_idle(void *arg)
+{
+ return __igt_ctx_sseu(arg, TEST_BUSY | TEST_IDLE);
+}
+
+static int igt_ctx_sseu_reset_idle(void *arg)
+{
+ return __igt_ctx_sseu(arg, TEST_RESET | TEST_IDLE);
+}
+
static int igt_ctx_readonly(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1232,6 +1715,12 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
SUBTEST(live_nop_switch),
SUBTEST(igt_ctx_exec),
SUBTEST(igt_ctx_readonly),
+ SUBTEST(igt_ctx_sseu),
+ SUBTEST(igt_ctx_sseu_idle),
+ SUBTEST(igt_ctx_sseu_busy),
+ SUBTEST(igt_ctx_sseu_busy_reset),
+ SUBTEST(igt_ctx_sseu_busy_idle),
+ SUBTEST(igt_ctx_sseu_reset_idle),
SUBTEST(igt_vm_isolation),
};
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests
2018-12-14 12:34 ` [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests Tvrtko Ursulin
@ 2018-12-14 13:04 ` Chris Wilson
2018-12-14 13:22 ` Chris Wilson
1 sibling, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2018-12-14 13:04 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-12-14 12:34:49)
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 78d449b6245e..fcb19b6f635e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -1042,24 +1042,23 @@ gen8_modify_rpcs_gpu(struct intel_context *ce,
> return ret;
> }
>
> -static int
> -i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
> - struct intel_engine_cs *engine,
> - struct intel_sseu sseu)
> +#if !IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> +static
> +#endif
> +int
> +__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct intel_sseu sseu)
> {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 7d82043aff10..2b4eb5d05915 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
selftests/i915_gem_context.c a continuation of i915_gem_context.c so it
has sneaky access to statics.
See the #include "selftests/i915_gem_context.c" at the end.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests
2018-12-14 12:34 ` [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests Tvrtko Ursulin
2018-12-14 13:04 ` Chris Wilson
@ 2018-12-14 13:22 ` Chris Wilson
1 sibling, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2018-12-14 13:22 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2018-12-14 12:34:49)
> +static struct i915_vma *rpcs_query_batch(struct i915_vma *vma)
> +{
> + struct drm_i915_gem_object *obj;
> + u32 *cmd;
> + int err;
> +
> + if (INTEL_GEN(vma->vm->i915) < 8)
> + return ERR_PTR(-EINVAL);
> +
> + obj = i915_gem_object_create_internal(vma->vm->i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(cmd)) {
> + err = PTR_ERR(cmd);
> + goto err;
> + }
> +
> + *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> + *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE);
> + *cmd++ = lower_32_bits(vma->node.start);
> + *cmd++ = upper_32_bits(vma->node.start);
> + *cmd = MI_BATCH_BUFFER_END;
> +
> + i915_gem_object_unpin_map(obj);
> +
> + err = i915_gem_object_set_to_gtt_domain(obj, false);
> + if (err)
> + goto err;
> +
> + vma = i915_vma_instance(obj, vma->vm, NULL);
> + if (IS_ERR(vma)) {
> + err = PTR_ERR(vma);
> + goto err;
> + }
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err)
> + goto err;
> +
> + return vma;
> +
> +err:
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> +}
> +
> +static int
> +emit_rpcs_query(struct drm_i915_gem_object *obj,
> + struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct i915_request **rq_out)
> +{
> + struct i915_address_space *vm;
> + struct i915_request *rq;
> + struct i915_vma *batch;
> + struct i915_vma *vma;
> + int err;
> +
> + GEM_BUG_ON(!ctx->ppgtt);
> + GEM_BUG_ON(!intel_engine_can_store_dword(engine));
> +
> + vm = &ctx->ppgtt->vm;
> +
> + vma = i915_vma_instance(obj, vm, NULL);
> + if (IS_ERR(vma))
> + return PTR_ERR(vma);
> +
> + err = i915_gem_object_set_to_gtt_domain(obj, false);
> + if (err)
> + return err;
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_HIGH | PIN_USER);
> + if (err)
> + return err;
> +
> + batch = rpcs_query_batch(vma);
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto err_vma;
> + }
Simpler would be to just emit the SRM into the ring. One less object+vma
to handle.
> +
> + rq = i915_request_alloc(engine, ctx);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto err_batch;
> + }
> +
> + err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
> + if (err)
> + goto err_request;
> +
> + err = i915_vma_move_to_active(batch, rq, 0);
> + if (err)
> + goto skip_request;
> +
> + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
> + if (err)
> + goto skip_request;
> +
> + i915_gem_object_set_active_reference(batch->obj);
> + i915_vma_unpin(batch);
> + i915_vma_close(batch);
> +
> + i915_vma_unpin(vma);
> +
> + *rq_out = i915_request_get(rq);
> +
> + i915_request_add(rq);
> +
> + return 0;
> +
> +skip_request:
> + i915_request_skip(rq, err);
> +err_request:
> + i915_request_add(rq);
> +err_batch:
> + i915_vma_unpin(batch);
> +err_vma:
> + i915_vma_unpin(vma);
> +
> + return err;
> +}
> +
> +#define TEST_IDLE (1 << 0)
> +#define TEST_BUSY (1 << 1)
> +#define TEST_RESET (1 << 2)
> +
> +int
> +__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct intel_sseu sseu);
> +
> +static int
> +__pre_set(struct drm_i915_private *i915,
> + unsigned int flags,
> + struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct igt_spinner **spin_out)
> +{
> + int ret = 0;
> +
> + if (flags & (TEST_BUSY | TEST_RESET)) {
> + struct igt_spinner *spin;
> + struct i915_request *rq;
> +
> + spin = kzalloc(sizeof(*spin), GFP_KERNEL);
> + if (!spin) {
> + ret = -ENOMEM;
> + goto out;
> + }
> +
> + ret = igt_spinner_init(spin, i915);
> + if (ret)
> + return ret;
> +
> + rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
> + if (IS_ERR(rq)) {
> + ret = PTR_ERR(rq);
> + igt_spinner_fini(spin);
> + kfree(spin);
> + goto out;
> + }
> +
> + i915_request_add(rq);
> +
> + if (!igt_wait_for_spinner(spin, rq)) {
> + pr_err("Spinner failed to start!\n");
> + igt_spinner_end(spin);
> + igt_spinner_fini(spin);
> + kfree(spin);
> + ret = -ETIMEDOUT;
> + goto out;
> + }
> +
> + *spin_out = spin;
> + }
> +
> +out:
> + return ret;
> +}
> +
> +static int
> +__read_slice_count(struct drm_i915_private *i915,
> + struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct drm_i915_gem_object *obj,
> + struct igt_spinner *spin,
> + u32 *rpcs)
> +{
> + struct i915_request *rq = NULL;
> + u32 s_mask, s_shift;
> + unsigned int cnt;
> + u32 *buf, val;
> + long ret;
> +
> + ret = emit_rpcs_query(obj, ctx, engine, &rq);
> + if (ret)
> + return ret;
> +
> + if (spin)
> + igt_spinner_end(spin);
> +
> + ret = i915_request_wait(rq, I915_WAIT_LOCKED, MAX_SCHEDULE_TIMEOUT);
> + if (ret <= 0)
> + return ret < 0 ? ret : -ETIME;
> +
> + i915_request_put(rq);
> +
> + buf = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(buf)) {
> + ret = PTR_ERR(buf);
> + return ret;
> + }
You can replace the get + request_wait + put with
i915_gem_obj_prepare_shmem_read. Yes the _shmem_ there is misleading.
> +
> + if (INTEL_GEN(i915) >= 11) {
> + s_mask = GEN11_RPCS_S_CNT_MASK;
> + s_shift = GEN11_RPCS_S_CNT_SHIFT;
> + } else {
> + s_mask = GEN8_RPCS_S_CNT_MASK;
> + s_shift = GEN8_RPCS_S_CNT_SHIFT;
> + }
> +
> + val = *buf;
> + cnt = (val & s_mask) >> s_shift;
> + *rpcs = val;
> +
> + i915_gem_object_unpin_map(obj);
> +
> + return cnt;
> +}
> +
> +static void __err_rpcs(u32 rpcs, unsigned int slices)
> +{
> + pr_info("RPCS=0x%x; %u%sx%u%s\n",
> + rpcs, slices,
> + (rpcs & GEN8_RPCS_S_CNT_ENABLE) ? "*" : "",
> + (rpcs & GEN8_RPCS_SS_CNT_MASK) >> GEN8_RPCS_SS_CNT_SHIFT,
> + (rpcs & GEN8_RPCS_SS_CNT_ENABLE) ? "*" : "");
> +}
> +
> +static int
> +__post_set(struct drm_i915_private *i915,
> + unsigned int flags,
> + struct i915_gem_context *ctx,
> + struct i915_gem_context *kctx,
> + struct intel_engine_cs *engine,
> + struct drm_i915_gem_object *obj,
> + unsigned int expected,
> + struct igt_spinner *spin)
> +{
> + unsigned int slices =
> + hweight32(intel_device_default_sseu(i915).slice_mask);
> + u32 rpcs = 0;
> + int ret = 0;
> +
> + if (flags & TEST_RESET) {
> + ret = i915_reset_engine(engine, "sseu");
> + if (ret)
> + goto out;
> + }
> +
> + ret = __read_slice_count(i915, ctx, engine, obj,
> + flags & TEST_RESET ? NULL : spin, &rpcs);
> + if (ret < 0) {
> + goto out;
> + } else if (ret != expected) {
> + pr_err("Context slice count %d is not %u!\n",
> + ret, expected);
Include stage + phase name (idle, busy, reset, etc) in the error message.
> + __err_rpcs(rpcs, ret);
> + ret = -EINVAL;
> + goto out;
> + } else {
> + ret = 0;
> + }
> +
> + ret = __read_slice_count(i915, kctx, engine, obj, NULL, &rpcs);
> + if (ret < 0) {
> + goto out;
> + } else if (ret != slices) {
> + pr_err("Kernel context slice count %d is not %u!\n",
> + ret, slices);
> + __err_rpcs(rpcs, ret);
> + ret = -EINVAL;
> + goto out;
> + } else {
> + ret = 0;
> + }
> +
> +out:
> + if (spin)
> + igt_spinner_end(spin);
> +
> + if (flags & TEST_IDLE) {
> + ret = i915_gem_wait_for_idle(i915,
> + I915_WAIT_LOCKED,
> + MAX_SCHEDULE_TIMEOUT);
> + if (ret)
> + return ret;
Do we want to go full idle (rpm) here? That shouldn't matter for ctx
images, so forget that.
Hmm, but we would like to kickstart the powercontext I guess. I wonder
if we can call __i915_gem_park directly...
> +
> + ret = __read_slice_count(i915, ctx, engine, obj, NULL, &rpcs);
> + if (ret < 0) {
> + return ret;
> + } else if (ret != expected) {
> + pr_err("Context slice count %d is not %u after idle!\n",
> + ret, expected);
> + __err_rpcs(rpcs, ret);
> + return -EINVAL;
> + } else {
> + ret = 0;
> + }
> + }
> +
> + return ret;
Ok, that should check across context switches and restoration from
reset. And reset should work so long as rpcs SRM as separate requests
from user batches.
> +
> +}
> +
> +static int
> +__sseu_test(struct drm_i915_private *i915,
> + unsigned int flags,
> + struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct drm_i915_gem_object *obj,
> + struct intel_sseu sseu)
> +{
> + struct igt_spinner *spin = NULL;
> + struct i915_gem_context *kctx;
> + int ret;
> +
> + kctx = kernel_context(i915);
> + if (IS_ERR(kctx))
> + return PTR_ERR(kctx);
> +
> + ret = __pre_set(i915, flags, ctx, engine, &spin);
__sseu_prepare & __sseu_finish
Just thinking that pre_set is a little generic and you'll wish you
called it something else next time you add a selftest.
> + if (ret)
> + goto out;
> +
> + ret = __i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
> + if (ret)
> + goto out;
> +
> + ret = __post_set(i915, flags, ctx, kctx, engine, obj,
> + hweight32(sseu.slice_mask), spin);
> +
> +out:
> + if (spin) {
> + igt_spinner_end(spin);
> + igt_spinner_fini(spin);
> + kfree(spin);
> + }
> +
> + kernel_context_close(kctx);
> +
> + return ret;
> +}
> +
> +static int __igt_ctx_sseu(struct drm_i915_private *i915, unsigned int flags)
> +{
> + struct intel_sseu default_sseu = intel_device_default_sseu(i915);
> + struct intel_engine_cs *engine = i915->engine[RCS];
> + struct drm_i915_gem_object *obj;
> + struct i915_gem_context *ctx;
> + struct intel_sseu pg_sseu;
> + struct drm_file *file;
> + int ret;
> +
> + if (INTEL_GEN(i915) < 9)
> + return 0;
> +
> + if (!INTEL_INFO(i915)->sseu.has_slice_pg)
> + return 0;
> +
> + if (hweight32(default_sseu.slice_mask) < 2)
> + return 0;
> +
> + /*
> + * Gen11 VME friendly power-gated configuration with half enabled
> + * sub-slices.
> + */
> + pg_sseu = default_sseu;
> + pg_sseu.slice_mask = 1;
> + pg_sseu.subslice_mask =
> + ~(~0 << (hweight32(default_sseu.subslice_mask) / 2));
> +
> + pr_info("SSE subtest flags=%x, def_slices=%u, pg_slices=%u\n",
> + flags, hweight32(default_sseu.slice_mask),
> + hweight32(pg_sseu.slice_mask));
> +
> + file = mock_file(i915);
> + if (IS_ERR(file))
> + return PTR_ERR(file);
> +
> + if (flags & TEST_RESET)
> + igt_global_reset_lock(i915);
> +
> + mutex_lock(&i915->drm.struct_mutex);
> +
> + ctx = i915_gem_create_context(i915, file->driver_priv);
> + if (IS_ERR(ctx)) {
> + ret = PTR_ERR(ctx);
> + goto out_unlock;
> + }
> +
> + obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
> + if (IS_ERR(obj)) {
> + ret = PTR_ERR(obj);
> + goto out_unlock;
> + }
> +
> + intel_runtime_pm_get(i915);
> +
> + /* First set the default mask. */
> + ret = __sseu_test(i915, flags, ctx, engine, obj, default_sseu);
> + if (ret)
> + goto out_fail;
> +
> + /* Then set a power-gated configuration. */
> + ret = __sseu_test(i915, flags, ctx, engine, obj, pg_sseu);
> + if (ret)
> + goto out_fail;
> +
> + /* Back to defaults. */
> + ret = __sseu_test(i915, flags, ctx, engine, obj, default_sseu);
> + if (ret)
> + goto out_fail;
> +
> + /* One last power-gated configuration for the road. */
> + ret = __sseu_test(i915, flags, ctx, engine, obj, pg_sseu);
> + if (ret)
> + goto out_fail;
> +
> +out_fail:
> + if (igt_flush_test(i915, I915_WAIT_LOCKED))
> + ret = -EIO;
> +
> + i915_gem_object_put(obj);
> +
> + intel_runtime_pm_put(i915);
> +
> +out_unlock:
> + mutex_unlock(&i915->drm.struct_mutex);
> +
> + if (flags & TEST_RESET)
> + igt_global_reset_unlock(i915);
> +
> + mock_file_free(i915, file);
> +
> + return ret;
> +}
> +
> +static int igt_ctx_sseu(void *arg)
> +{
> + return __igt_ctx_sseu(arg, 0);
> +}
> +
> +static int igt_ctx_sseu_idle(void *arg)
> +{
> + return __igt_ctx_sseu(arg, TEST_IDLE);
> +}
> +
> +static int igt_ctx_sseu_busy(void *arg)
> +{
> + return __igt_ctx_sseu(arg, TEST_BUSY);
> +}
> +
> +static int igt_ctx_sseu_busy_reset(void *arg)
> +{
> + return __igt_ctx_sseu(arg, TEST_BUSY | TEST_RESET);
> +}
> +
> +static int igt_ctx_sseu_busy_idle(void *arg)
> +{
> + return __igt_ctx_sseu(arg, TEST_BUSY | TEST_IDLE);
> +}
> +
> +static int igt_ctx_sseu_reset_idle(void *arg)
> +{
> + return __igt_ctx_sseu(arg, TEST_RESET | TEST_IDLE);
> +}
Looks ok. The only point I would like to reiterate is to pass down the
subtest names so that we can include them in the error messages for
easier comprehension.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev8)
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (6 preceding siblings ...)
2018-12-14 12:34 ` [PATCH 7/7] drm/i915/selftests: Context SSEU reconfiguration tests Tvrtko Ursulin
@ 2018-12-14 12:55 ` Patchwork
2018-12-14 12:58 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-12-14 12:55 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev8)
URL : https://patchwork.freedesktop.org/series/48194/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7bc81b868afe drm/i915/execlists: Move RPCS setup to context pin
5939874afc3d drm/i915: Record the sseu configuration per-context & engine
359b2f7b3643 drm/i915/perf: lock powergating configuration to default when active
db1043fd7760 drm/i915: Add timeline barrier support
62f6ae9d552a drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
-:47: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#47:
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)
-:499: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'user->min_eus_per_subslice !=
device->max_eus_per_subslice'
#499: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1171:
+ if ((user->min_eus_per_subslice !=
+ device->max_eus_per_subslice) ||
+ (user->max_eus_per_subslice !=
+ device->max_eus_per_subslice))
-:499: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'user->max_eus_per_subslice !=
device->max_eus_per_subslice'
#499: FILE: drivers/gpu/drm/i915/i915_gem_context.c:1171:
+ if ((user->min_eus_per_subslice !=
+ device->max_eus_per_subslice) ||
+ (user->max_eus_per_subslice !=
+ device->max_eus_per_subslice))
total: 0 errors, 1 warnings, 2 checks, 479 lines checked
393ecc46aec2 drm/i915/icl: Support co-existence between per-context SSEU and OA
b3cba63fa219 drm/i915/selftests: Context SSEU reconfiguration tests
-:222: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#222: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:784:
+int
-:402: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#402: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:964:
+ return -EINVAL;
+ } else {
-:409: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#409: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:971:
+
+}
total: 0 errors, 2 warnings, 1 checks, 563 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.SPARSE: warning for Per context dynamic (sub)slice power-gating (rev8)
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (7 preceding siblings ...)
2018-12-14 12:55 ` ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev8) Patchwork
@ 2018-12-14 12:58 ` Patchwork
2018-12-14 13:11 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-14 15:07 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-12-14 12:58 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev8)
URL : https://patchwork.freedesktop.org/series/48194/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/execlists: Move RPCS setup to context pin
Okay!
Commit: drm/i915: Record the sseu configuration per-context & engine
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3562:16: warning: expression using sizeof(void)
Commit: drm/i915/perf: lock powergating configuration to default when active
Okay!
Commit: drm/i915: Add timeline barrier support
Okay!
Commit: drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
+drivers/gpu/drm/i915/intel_lrc.c:2374:25: warning: expression using sizeof(void)
Commit: drm/i915/icl: Support co-existence between per-context SSEU and OA
Okay!
Commit: drm/i915/selftests: Context SSEU reconfiguration tests
+drivers/gpu/drm/i915/i915_gem_context.c:1049:1: warning: symbol '__i915_gem_context_reconfigure_sseu' was not declared. Should it be static?
+drivers/gpu/drm/i915/selftests/i915_gem_context.c:1223:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/i915_gem_context.c:1223:25: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/i915_gem_context.c:1223:25: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/i915_gem_context.c:1223:25: warning: expression using sizeof(void)
+./include/linux/slab.h:332:43: warning: dubious: x & !y
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev8)
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (8 preceding siblings ...)
2018-12-14 12:58 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-12-14 13:11 ` Patchwork
2018-12-14 15:07 ` ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-12-14 13:11 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev8)
URL : https://patchwork.freedesktop.org/series/48194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5317 -> Patchwork_11095
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48194/revisions/8/mbox/
Known issues
------------
Here are the changes found in Patchwork_11095 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: PASS -> FAIL [fdo#108767]
* {igt@runner@aborted}:
- fi-icl-y: NOTRUN -> FAIL [fdo#108070]
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-bsw-kefka: FAIL [fdo#108656] -> PASS
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
Participating hosts (49 -> 46)
------------------------------
Additional (2): fi-icl-y fi-byt-j1900
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-ctg-p8600 fi-pnv-d510
Build changes
-------------
* Linux: CI_DRM_5317 -> Patchwork_11095
CI_DRM_5317: 10c50ecb5eaa0176514e610d0c8bfd13babf88e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4747: ad821d1dc5d0eea4ac3a0e8e29c56c7f66191108 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11095: b3cba63fa219d779aea8de26f15d4d9e311a57e5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b3cba63fa219 drm/i915/selftests: Context SSEU reconfiguration tests
393ecc46aec2 drm/i915/icl: Support co-existence between per-context SSEU and OA
62f6ae9d552a drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)
db1043fd7760 drm/i915: Add timeline barrier support
359b2f7b3643 drm/i915/perf: lock powergating configuration to default when active
5939874afc3d drm/i915: Record the sseu configuration per-context & engine
7bc81b868afe drm/i915/execlists: Move RPCS setup to context pin
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11095/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* ✗ Fi.CI.IGT: failure for Per context dynamic (sub)slice power-gating (rev8)
2018-12-14 12:34 [PATCH 0/7] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
` (9 preceding siblings ...)
2018-12-14 13:11 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-12-14 15:07 ` Patchwork
10 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2018-12-14 15:07 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev8)
URL : https://patchwork.freedesktop.org/series/48194/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5317_full -> Patchwork_11095_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_11095_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11095_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11095_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: PASS -> FAIL
- shard-apl: PASS -> FAIL
- shard-iclb: PASS -> FAIL
- shard-glk: PASS -> FAIL
- shard-snb: PASS -> FAIL
- shard-hsw: PASS -> FAIL
- shard-kbl: PASS -> FAIL
#### Warnings ####
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-iclb: FAIL [fdo#108948] -> DMESG-FAIL
Known issues
------------
Here are the changes found in Patchwork_11095_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@i915_suspend@debugfs-reader:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-iclb: PASS -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +3
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-glk: PASS -> FAIL [fdo#103184]
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: NOTRUN -> FAIL [fdo#103184]
* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#107882]
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-kbl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166] +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724]
* igt@perf_pmu@rc6-runtime-pm:
- shard-kbl: PASS -> FAIL [fdo#105010]
* igt@pm_rpm@universal-planes:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#108654] / [fdo#108756]
* {igt@runner@aborted}:
- shard-iclb: NOTRUN -> FAIL [fdo#108654] / [fdo#108756]
#### Possible fixes ####
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-skl: FAIL [fdo#107815] / [fdo#108470] -> PASS
* igt@kms_color@pipe-a-ctm-max:
- shard-skl: FAIL [fdo#108147] -> PASS
* igt@kms_color@pipe-c-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-skl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-glk: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: FAIL -> PASS
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
- shard-skl: FAIL [fdo#108472] -> PASS
* igt@kms_fbcon_fbt@fbc:
- shard-skl: FAIL [fdo#103833] / [fdo#105682] -> PASS
* igt@kms_flip@flip-vs-modeset-vs-hang:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: FAIL [fdo#108134] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS +7
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-skl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- shard-skl: FAIL [fdo#107362] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-iclb: FAIL [fdo#103166] -> PASS
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS
* igt@pm_backlight@basic-brightness:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS +2
* igt@pm_rpm@fences-dpms:
- shard-iclb: INCOMPLETE [fdo#108840] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-apl: INCOMPLETE [fdo#103927] / [fdo#106886] -> DMESG-WARN [fdo#108784]
- shard-kbl: DMESG-WARN [fdo#108784] -> INCOMPLETE [fdo#103665] / [fdo#106886]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107361]: https://bugs.freedesktop.org/show_bug.cgi?id=107361
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108756]: https://bugs.freedesktop.org/show_bug.cgi?id=108756
[fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5317 -> Patchwork_11095
CI_DRM_5317: 10c50ecb5eaa0176514e610d0c8bfd13babf88e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4747: ad821d1dc5d0eea4ac3a0e8e29c56c7f66191108 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11095: b3cba63fa219d779aea8de26f15d4d9e311a57e5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11095/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread