[PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Mika Kuoppala]

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 +++++++++++++----------
 drivers/gpu/drm/i915/intel_lrc.c        | 10 +++++++---
 drivers/gpu/drm/i915/intel_lrc.h        | 19 ++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
 4 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 6f165f9ad2bf..f5960b3dc5d7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1305,37 +1305,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 	}
 
 	if (HAS_EXECLISTS(dev_priv)) {
-		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+		const u32 *hws = execlists->csb_status;
+		const u8 entries = execlists->csb_size;
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+				   I915_READ(RING_CSB_LO(engine, idx)),
 				   hws[idx * 2 + 1],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+				   I915_READ(RING_CSB_HI(engine, idx)));
 		}
 
 		rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1c9748f391fe..bd35ac3b7b77 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
-	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+	const unsigned int reset_value = execlists->csb_size - 1;
 
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -867,7 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	const u32 * const buf = execlists->csb_status;
-	u8 head, tail;
+	u8 head, tail, entries;
 
 	/*
 	 * Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -885,6 +885,8 @@ static void process_csb(struct intel_engine_cs *engine)
 	if (unlikely(head == tail))
 		return;
 
+	entries = execlists->csb_size;
+
 	/*
 	 * Hopefully paired with a wmb() in HW!
 	 *
@@ -900,7 +902,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == entries)
 			head = 0;
 
 		/*
@@ -2252,6 +2254,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
+	execlists->csb_size = GEN8_CSB_ENTRIES;
+
 	reset_csb_pointers(execlists);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..206b0da6fbcc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,9 +36,13 @@
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
+
+#define _RING_CSB_OFFSET(i)			((i) < 6 ? \
+						 (0x370 + (i) * 8) : \
+						 (0x3c0 + ((i) - 6) * 8))
+#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
+#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
+#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
 #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
 #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
@@ -55,10 +59,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1ae74e579386..64a54d8f9b2b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -332,6 +332,11 @@ struct intel_engine_execlists {
 	 */
 	u32 preempt_complete_status;
 
+	/**
+	 * @csb_size: context status buffer FIFO size
+	 */
+	u8 csb_size;
+
 	/**
 	 * @csb_head: context status buffer head
 	 */
-- 
2.17.1

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[PATCH 2/3] drm/i915/icl: Switch to using 12 deep CSB status FIFO

[Mika Kuoppala]

Now when we can support variable csb fifo sizes, disable legacy mode.
By disabling legacy we hope to get better hw testing coverage by
assuming everyone else have switched over.

v2: rebase

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bd35ac3b7b77..039e2a54b1fc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1659,17 +1659,9 @@ static void enable_execlists(struct intel_engine_cs *engine)
 
 	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 
-	/*
-	 * Make sure we're not enabling the new 12-deep CSB
-	 * FIFO as that requires a slightly updated handling
-	 * in the ctx switch irq. Since we're currently only
-	 * using only 2 elements of the enhanced execlists the
-	 * deeper FIFO it's not needed and it's not worth adding
-	 * more statements to the irq handler to support it.
-	 */
 	if (INTEL_GEN(dev_priv) >= 11)
 		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+			   _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
 	else
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
@@ -2254,7 +2246,10 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
-	execlists->csb_size = GEN8_CSB_ENTRIES;
+	if (INTEL_GEN(engine->i915) < 11)
+		execlists->csb_size = GEN8_CSB_ENTRIES;
+	else
+		execlists->csb_size = GEN11_CSB_ENTRIES;
 
 	reset_csb_pointers(execlists);
 
-- 
2.17.1

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[PATCH 3/3] drm/i915/icl: Introduce gen11 flush/invalidate

[Mika Kuoppala]

There are more pipe control levers to pull with icl.
Take them into use both for flushing and invalidating to
ensure completeness.

Doing so, avoid overloading the gen8 flush/invalidate
further and make a gen11 specific callback.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_gpu_commands.h |  2 +
 drivers/gpu/drm/i915/intel_lrc.c          | 61 ++++++++++++++++++++++-
 2 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h b/drivers/gpu/drm/i915/intel_gpu_commands.h
index 105e2a9e874a..62112e9da610 100644
--- a/drivers/gpu/drm/i915/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/intel_gpu_commands.h
@@ -195,6 +195,8 @@
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 039e2a54b1fc..d4c7dab9cdb4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2021,6 +2021,60 @@ static int gen8_emit_flush_render(struct i915_request *request,
 	return 0;
 }
 
+static int gen11_emit_flush_render(struct i915_request *request,
+				   u32 mode)
+{
+	struct intel_engine_cs *engine = request->engine;
+	const u32 scratch_addr =
+		i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
+	u32 *cs;
+
+	if (mode & EMIT_FLUSH) {
+		u32 flags = PIPE_CONTROL_CS_STALL;
+
+		flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
+		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+		cs = intel_ring_begin(request, 6);
+		if (IS_ERR(cs))
+			return PTR_ERR(cs);
+
+		cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+
+		intel_ring_advance(request, cs);
+	}
+
+	if (mode & EMIT_INVALIDATE) {
+		u32 flags = PIPE_CONTROL_CS_STALL;
+
+		flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_TLB_INVALIDATE;
+		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+
+		cs = intel_ring_begin(request, 6);
+		if (IS_ERR(cs))
+			return PTR_ERR(cs);
+
+		cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
+
+		intel_ring_advance(request, cs);
+	}
+
+	return 0;
+}
+
 /*
  * Reserve space for 2 NOOPs at the end of each request to be
  * used as a workaround for not being allowed to do lite
@@ -2268,7 +2322,12 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
 
 	/* Override some for render ring. */
 	engine->init_context = gen8_init_rcs_context;
-	engine->emit_flush = gen8_emit_flush_render;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		engine->emit_flush = gen11_emit_flush_render;
+	else
+		engine->emit_flush = gen8_emit_flush_render;
+
 	engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
 	engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
 
-- 
2.17.1

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Re: [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Chris Wilson]

Quoting Mika Kuoppala (2018-12-18 13:24:23)
> @@ -867,7 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
>         struct intel_engine_execlists * const execlists = &engine->execlists;
>         struct execlist_port *port = execlists->port;
>         const u32 * const buf = execlists->csb_status;
> -       u8 head, tail;
> +       u8 head, tail, entries;
>  
>         /*
>          * Note that csb_write, csb_status may be either in HWSP or mmio.
> @@ -885,6 +885,8 @@ static void process_csb(struct intel_engine_cs *engine)
>         if (unlikely(head == tail))
>                 return;
>  
> +       entries = execlists->csb_size;

Misplaced; as we certainly don't want it between the read and rmb.
So just go for const u8 entries = execlists->csb_size.
-Chris
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size
URL   : https://patchwork.freedesktop.org/series/54213/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c158aa2a2dad drm/i915: Prepare for larger CSB status FIFO size
-:133: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#133: FILE: drivers/gpu/drm/i915/intel_lrc.h:40:
+#define _RING_CSB_OFFSET(i)			((i) < 6 ? \
+						 (0x370 + (i) * 8) : \
+						 (0x3c0 + ((i) - 6) * 8))

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
8ab507eb3069 drm/i915/icl: Switch to using 12 deep CSB status FIFO
c801d4fe14d8 drm/i915/icl: Introduce gen11 flush/invalidate
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:198:
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
                                                		  ^

-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:199:
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
                                        			  ^

total: 0 errors, 0 warnings, 2 checks, 81 lines checked

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✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size
URL   : https://patchwork.freedesktop.org/series/54213/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5328 -> Patchwork_11114
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_11114 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11114, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54213/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11114:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-bsw-n3050:       PASS -> FAIL

  
#### Warnings ####

  * igt@kms_busy@basic-flip-a:
    - fi-kbl-7567u:       SKIP -> PASS +2

  
Known issues
------------

  Here are the changes found in Patchwork_11114 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        PASS -> DMESG-FAIL [fdo#108735]
    - fi-kbl-7560u:       PASS -> INCOMPLETE [fdo#108044]

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-skl-6700k2:      PASS -> INCOMPLETE [fdo#104108] / [fdo#105524] / [k.org#199541]

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       PASS -> FAIL [fdo#108767]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       PASS -> DMESG-WARN [fdo#102614]

  
#### Possible fixes ####

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105524]: https://bugs.freedesktop.org/show_bug.cgi?id=105524
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
  [fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [k.org#199541]: https://bugzilla.kernel.org/show_bug.cgi?id=199541


Participating hosts (51 -> 43)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-glk-j4005 fi-icl-y 


Build changes
-------------

    * Linux: CI_DRM_5328 -> Patchwork_11114

  CI_DRM_5328: 5af827aaf28d19d28880a61c528895b43bebec10 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11114: c801d4fe14d8ffc752f78d7222ad442a950a340b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c801d4fe14d8 drm/i915/icl: Introduce gen11 flush/invalidate
8ab507eb3069 drm/i915/icl: Switch to using 12 deep CSB status FIFO
c158aa2a2dad drm/i915: Prepare for larger CSB status FIFO size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11114/
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[PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Mika Kuoppala]

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 ++++++++++++----------
 drivers/gpu/drm/i915/intel_lrc.c        |  7 +++++--
 drivers/gpu/drm/i915/intel_lrc.h        | 26 ++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
 4 files changed, 42 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3dec31df123..d759ebb44cdc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1336,37 +1336,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 	}
 
 	if (HAS_EXECLISTS(dev_priv)) {
-		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+		const u32 *hws = execlists->csb_status;
+		const u8 entries = execlists->csb_size;
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+				   I915_READ(RING_CSB_LO(engine, idx)),
 				   hws[idx * 2 + 1],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+				   I915_READ(RING_CSB_HI(engine, idx)));
 		}
 
 		rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b05d0561f99a..986766c4df3b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
-	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+	const unsigned int reset_value = execlists->csb_size - 1;
 
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	const u32 * const buf = execlists->csb_status;
+	const u8 entries = execlists->csb_size;
 	u8 head, tail;
 
 	/*
@@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == entries)
 			head = 0;
 
 		/*
@@ -2252,6 +2253,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
+	execlists->csb_size = GEN8_CSB_ENTRIES;
+
 	reset_csb_pointers(execlists);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..c95f05f172d9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,9 +36,20 @@
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
+
+#define RING_CSB_0_5				0x370
+#define RING_CSB_6_12				0x3c0
+
+#define _RING_CSB_OFFSET(entry) ({					\
+	const int i = (entry);						\
+	i < 6 ?								\
+		RING_CSB_0_5 + i * 8 :					\
+		RING_CSB_6_12 + (i - 6) * 8;				\
+})
+
+#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
+#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
+#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
 #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
 #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
@@ -55,10 +66,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6b41b9ce5f5b..c3dfd0f59912 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -332,6 +332,11 @@ struct intel_engine_execlists {
 	 */
 	u32 preempt_complete_status;
 
+	/**
+	 * @csb_size: context status buffer FIFO size
+	 */
+	u8 csb_size;
+
 	/**
 	 * @csb_head: context status buffer head
 	 */
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev2)
URL   : https://patchwork.freedesktop.org/series/54213/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d97ce8e81683 drm/i915: Prepare for larger CSB status FIFO size
f97924e82a7c drm/i915/icl: Switch to using 12 deep CSB status FIFO
95173bd5251e drm/i915/icl: Introduce gen11 flush/invalidate
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:198:
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
                                                		  ^

-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:199:
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
                                        			  ^

total: 0 errors, 0 warnings, 2 checks, 81 lines checked

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Re: [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Chris Wilson]

Quoting Mika Kuoppala (2018-12-19 12:27:22)
> Make csb entry count variable in preparation for larger
> CSB status FIFO size found on gen11+ hardware.
> 
> v2: adapt to hwsp access only (Chris)
>     non continuous mmio (Daniele)
> v3: entries (Chris), fix macro for checkpatch
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> @@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
>         struct intel_engine_execlists * const execlists = &engine->execlists;
>         struct execlist_port *port = execlists->port;
>         const u32 * const buf = execlists->csb_status;
> +       const u8 entries = execlists->csb_size;
>         u8 head, tail;
>  
>         /*
> @@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
>                 unsigned int status;
>                 unsigned int count;
>  
> -               if (++head == GEN8_CSB_ENTRIES)
> +               if (++head == entries)

Fwiw, I would go with s/entries/num_entries/
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
 
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✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev2)
URL   : https://patchwork.freedesktop.org/series/54213/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5332 -> Patchwork_11123
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_11123 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11123, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54213/revisions/2/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11123:

### IGT changes ###

#### Possible regressions ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          PASS -> INCOMPLETE

  
Known issues
------------

  Here are the changes found in Patchwork_11123 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@amdgpu/amd_prime@amd-to-i915:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#107341]

  * {igt@runner@aborted}:
    - fi-icl-u2:          NOTRUN -> FAIL [fdo#108866]
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       DMESG-WARN [fdo#108965] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  
#### Warnings ####

  * igt@i915_selftest@live_contexts:
    - fi-icl-u2:          DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108866]: https://bugs.freedesktop.org/show_bug.cgi?id=108866
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965


Participating hosts (50 -> 45)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5332 -> Patchwork_11123

  CI_DRM_5332: 29cd50b134a44bab74bfc8b275d24a32e140196c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4750: f05c8c2739dce89185349703062784a7745cab14 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11123: 95173bd5251e554dd0628d076be01dc0d62f0be1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

95173bd5251e drm/i915/icl: Introduce gen11 flush/invalidate
f97924e82a7c drm/i915/icl: Switch to using 12 deep CSB status FIFO
d97ce8e81683 drm/i915: Prepare for larger CSB status FIFO size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11123/
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[PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Mika Kuoppala]

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch
v4: num_entries (Chris)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 ++++++++++++----------
 drivers/gpu/drm/i915/intel_lrc.c        |  7 +++++--
 drivers/gpu/drm/i915/intel_lrc.h        | 26 ++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
 4 files changed, 42 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3dec31df123..d759ebb44cdc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1336,37 +1336,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 	}
 
 	if (HAS_EXECLISTS(dev_priv)) {
-		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+		const u32 *hws = execlists->csb_status;
+		const u8 entries = execlists->csb_size;
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+				   I915_READ(RING_CSB_LO(engine, idx)),
 				   hws[idx * 2 + 1],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+				   I915_READ(RING_CSB_HI(engine, idx)));
 		}
 
 		rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b05d0561f99a..3594d489bd9f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
-	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+	const unsigned int reset_value = execlists->csb_size - 1;
 
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	const u32 * const buf = execlists->csb_status;
+	const u8 num_entries = execlists->csb_size;
 	u8 head, tail;
 
 	/*
@@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == num_entries)
 			head = 0;
 
 		/*
@@ -2252,6 +2253,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
+	execlists->csb_size = GEN8_CSB_ENTRIES;
+
 	reset_csb_pointers(execlists);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..c95f05f172d9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,9 +36,20 @@
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
+
+#define RING_CSB_0_5				0x370
+#define RING_CSB_6_12				0x3c0
+
+#define _RING_CSB_OFFSET(entry) ({					\
+	const int i = (entry);						\
+	i < 6 ?								\
+		RING_CSB_0_5 + i * 8 :					\
+		RING_CSB_6_12 + (i - 6) * 8;				\
+})
+
+#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
+#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
+#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
 #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
 #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
@@ -55,10 +66,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6b41b9ce5f5b..c3dfd0f59912 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -332,6 +332,11 @@ struct intel_engine_execlists {
 	 */
 	u32 preempt_complete_status;
 
+	/**
+	 * @csb_size: context status buffer FIFO size
+	 */
+	u8 csb_size;
+
 	/**
 	 * @csb_head: context status buffer head
 	 */
-- 
2.17.1

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Re: [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Mika Kuoppala]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> Make csb entry count variable in preparation for larger
> CSB status FIFO size found on gen11+ hardware.
>
> v2: adapt to hwsp access only (Chris)
>     non continuous mmio (Daniele)
> v3: entries (Chris), fix macro for checkpatch
> v4: num_entries (Chris)
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 23 ++++++++++++----------
>  drivers/gpu/drm/i915/intel_lrc.c        |  7 +++++--
>  drivers/gpu/drm/i915/intel_lrc.h        | 26 ++++++++++++++++++-------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
>  4 files changed, 42 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d3dec31df123..d759ebb44cdc 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1336,37 +1336,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
>  	}
>  
>  	if (HAS_EXECLISTS(dev_priv)) {
> -		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> +		const u32 *hws = execlists->csb_status;
> +		const u8 entries = execlists->csb_size;

Oh, I had a one job :O
-Mika

>  		unsigned int idx;
>  		u8 read, write;
>  
> -		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
> +		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
>  			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
> -			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
> +			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
> +			   entries);
>  
>  		read = execlists->csb_head;
>  		write = READ_ONCE(*execlists->csb_write);
>  
>  		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
>  			   read, write,
> -			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
> +			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
> +			   GEN11_CSB_WRITE_PTR_MASK,
>  			   yesno(test_bit(TASKLET_STATE_SCHED,
>  					  &engine->execlists.tasklet.state)),
>  			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
> -		if (read >= GEN8_CSB_ENTRIES)
> +		if (read >= entries)
>  			read = 0;
> -		if (write >= GEN8_CSB_ENTRIES)
> +		if (write >= entries)
>  			write = 0;
>  		if (read > write)
> -			write += GEN8_CSB_ENTRIES;
> +			write += entries;
>  		while (read < write) {
> -			idx = ++read % GEN8_CSB_ENTRIES;
> +			idx = ++read % entries;
>  			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
>  				   idx,
>  				   hws[idx * 2],
> -				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
> +				   I915_READ(RING_CSB_LO(engine, idx)),
>  				   hws[idx * 2 + 1],
> -				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
> +				   I915_READ(RING_CSB_HI(engine, idx)));
>  		}
>  
>  		rcu_read_lock();
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index b05d0561f99a..3594d489bd9f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
>  
>  static void reset_csb_pointers(struct intel_engine_execlists *execlists)
>  {
> -	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
> +	const unsigned int reset_value = execlists->csb_size - 1;
>  
>  	/*
>  	 * After a reset, the HW starts writing into CSB entry [0]. We
> @@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
>  	struct intel_engine_execlists * const execlists = &engine->execlists;
>  	struct execlist_port *port = execlists->port;
>  	const u32 * const buf = execlists->csb_status;
> +	const u8 num_entries = execlists->csb_size;
>  	u8 head, tail;
>  
>  	/*
> @@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
>  		unsigned int status;
>  		unsigned int count;
>  
> -		if (++head == GEN8_CSB_ENTRIES)
> +		if (++head == num_entries)
>  			head = 0;
>  
>  		/*
> @@ -2252,6 +2253,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
>  	execlists->csb_write =
>  		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
>  
> +	execlists->csb_size = GEN8_CSB_ENTRIES;
> +
>  	reset_csb_pointers(execlists);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index f5a5502ecf70..c95f05f172d9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -36,9 +36,20 @@
>  #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
>  #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
>  #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
> -#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
> -#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
> -#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
> +
> +#define RING_CSB_0_5				0x370
> +#define RING_CSB_6_12				0x3c0
> +
> +#define _RING_CSB_OFFSET(entry) ({					\
> +	const int i = (entry);						\
> +	i < 6 ?								\
> +		RING_CSB_0_5 + i * 8 :					\
> +		RING_CSB_6_12 + (i - 6) * 8;				\
> +})
> +
> +#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
> +#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
> +#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
>  #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
>  #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
>  #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
> @@ -55,10 +66,11 @@
>  #define GEN8_CSB_PTR_MASK 0x7
>  #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
>  #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
> -#define GEN8_CSB_WRITE_PTR(csb_status) \
> -	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
> -#define GEN8_CSB_READ_PTR(csb_status) \
> -	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
> +
> +#define GEN11_CSB_ENTRIES 12
> +#define GEN11_CSB_PTR_MASK 0xf
> +#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
> +#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
>  
>  enum {
>  	INTEL_CONTEXT_SCHEDULE_IN = 0,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 6b41b9ce5f5b..c3dfd0f59912 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -332,6 +332,11 @@ struct intel_engine_execlists {
>  	 */
>  	u32 preempt_complete_status;
>  
> +	/**
> +	 * @csb_size: context status buffer FIFO size
> +	 */
> +	u8 csb_size;
> +
>  	/**
>  	 * @csb_head: context status buffer head
>  	 */
> -- 
> 2.17.1
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[PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Mika Kuoppala]

Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.

v2: adapt to hwsp access only (Chris)
    non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch
v4: num_entries (Chris)
v5: consistency on num_entries

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 23 ++++++++++++----------
 drivers/gpu/drm/i915/intel_lrc.c        |  7 +++++--
 drivers/gpu/drm/i915/intel_lrc.h        | 26 ++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
 4 files changed, 42 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3dec31df123..673e7d753d4a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1336,37 +1336,40 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 	}
 
 	if (HAS_EXECLISTS(dev_priv)) {
-		const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+		const u32 *hws = execlists->csb_status;
+		const u8 num_entries = execlists->csb_size;
 		unsigned int idx;
 		u8 read, write;
 
-		drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+		drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
 			   I915_READ(RING_EXECLIST_STATUS_LO(engine)),
-			   I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+			   I915_READ(RING_EXECLIST_STATUS_HI(engine)),
+			   num_entries);
 
 		read = execlists->csb_head;
 		write = READ_ONCE(*execlists->csb_write);
 
 		drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
 			   read, write,
-			   GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+			   I915_READ(RING_CONTEXT_STATUS_PTR(engine)) &
+			   GEN11_CSB_WRITE_PTR_MASK,
 			   yesno(test_bit(TASKLET_STATE_SCHED,
 					  &engine->execlists.tasklet.state)),
 			   enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
-		if (read >= GEN8_CSB_ENTRIES)
+		if (read >= num_entries)
 			read = 0;
-		if (write >= GEN8_CSB_ENTRIES)
+		if (write >= num_entries)
 			write = 0;
 		if (read > write)
-			write += GEN8_CSB_ENTRIES;
+			write += num_entries;
 		while (read < write) {
-			idx = ++read % GEN8_CSB_ENTRIES;
+			idx = ++read % num_entries;
 			drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
 				   idx,
 				   hws[idx * 2],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+				   I915_READ(RING_CSB_LO(engine, idx)),
 				   hws[idx * 2 + 1],
-				   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+				   I915_READ(RING_CSB_HI(engine, idx)));
 		}
 
 		rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b05d0561f99a..3594d489bd9f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -760,7 +760,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
 
 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
 {
-	const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+	const unsigned int reset_value = execlists->csb_size - 1;
 
 	/*
 	 * After a reset, the HW starts writing into CSB entry [0]. We
@@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	const u32 * const buf = execlists->csb_status;
+	const u8 num_entries = execlists->csb_size;
 	u8 head, tail;
 
 	/*
@@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
 		unsigned int status;
 		unsigned int count;
 
-		if (++head == GEN8_CSB_ENTRIES)
+		if (++head == num_entries)
 			head = 0;
 
 		/*
@@ -2252,6 +2253,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	execlists->csb_write =
 		&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
 
+	execlists->csb_size = GEN8_CSB_ENTRIES;
+
 	reset_csb_pointers(execlists);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f5a5502ecf70..c95f05f172d9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,9 +36,20 @@
 #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
 #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
 #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
+
+#define RING_CSB_0_5				0x370
+#define RING_CSB_6_12				0x3c0
+
+#define _RING_CSB_OFFSET(entry) ({					\
+	const int i = (entry);						\
+	i < 6 ?								\
+		RING_CSB_0_5 + i * 8 :					\
+		RING_CSB_6_12 + (i - 6) * 8;				\
+})
+
+#define RING_CSB_OFFSET(engine, i)		((engine)->mmio_base + _RING_CSB_OFFSET(i))
+#define RING_CSB_LO(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i))
+#define RING_CSB_HI(engine, i)			_MMIO(RING_CSB_OFFSET(engine, i) + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
 #define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
 #define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
@@ -55,10 +66,11 @@
 #define GEN8_CSB_PTR_MASK 0x7
 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
-	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
 
 enum {
 	INTEL_CONTEXT_SCHEDULE_IN = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6b41b9ce5f5b..c3dfd0f59912 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -332,6 +332,11 @@ struct intel_engine_execlists {
 	 */
 	u32 preempt_complete_status;
 
+	/**
+	 * @csb_size: context status buffer FIFO size
+	 */
+	u8 csb_size;
+
 	/**
 	 * @csb_head: context status buffer head
 	 */
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev3)
URL   : https://patchwork.freedesktop.org/series/54213/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4bb9b3e03530 drm/i915: Prepare for larger CSB status FIFO size
052bef3b5275 drm/i915/icl: Switch to using 12 deep CSB status FIFO
b7be7041732e drm/i915/icl: Introduce gen11 flush/invalidate
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:198:
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
                                                		  ^

-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:199:
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
                                        			  ^

total: 0 errors, 0 warnings, 2 checks, 81 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev3)
URL   : https://patchwork.freedesktop.org/series/54213/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5332 -> Patchwork_11125
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54213/revisions/3/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11125 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@amdgpu/amd_prime@amd-to-i915:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#107341]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * {igt@runner@aborted}:
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       DMESG-WARN [fdo#108965] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#107362] -> PASS

  
#### Warnings ####

  * igt@i915_selftest@live_contexts:
    - fi-icl-u3:          DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965


Participating hosts (50 -> 45)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5332 -> Patchwork_11125

  CI_DRM_5332: 29cd50b134a44bab74bfc8b275d24a32e140196c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4750: f05c8c2739dce89185349703062784a7745cab14 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11125: b7be7041732eaf28ec6409982327a0a1956b7f01 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b7be7041732e drm/i915/icl: Introduce gen11 flush/invalidate
052bef3b5275 drm/i915/icl: Switch to using 12 deep CSB status FIFO
4bb9b3e03530 drm/i915: Prepare for larger CSB status FIFO size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11125/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)
URL   : https://patchwork.freedesktop.org/series/54213/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7854930e939b drm/i915: Prepare for larger CSB status FIFO size
7cbdc840c1d8 drm/i915/icl: Switch to using 12 deep CSB status FIFO
e050519e52a5 drm/i915/icl: Introduce gen11 flush/invalidate
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:198:
+#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
                                                		  ^

-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:199:
+#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
                                        			  ^

total: 0 errors, 0 warnings, 2 checks, 81 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)
URL   : https://patchwork.freedesktop.org/series/54213/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5333 -> Patchwork_11126
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/54213/revisions/4/mbox/

Known issues
------------

  Here are the changes found in Patchwork_11126 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       PASS -> DMESG-WARN [fdo#108965]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       PASS -> DMESG-WARN [fdo#102614]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * {igt@runner@aborted}:
    - fi-icl-y:           NOTRUN -> FAIL [fdo#108070]

  
#### Possible fixes ####

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        DMESG-FAIL [fdo#108735] -> PASS
    - fi-apl-guc:         DMESG-FAIL -> PASS
    - fi-kbl-7560u:       INCOMPLETE [fdo#108044] -> PASS

  * igt@kms_flip@basic-flip-vs-dpms:
    - fi-skl-6700hq:      DMESG-WARN [fdo#105998] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
#### Warnings ####

  * igt@i915_selftest@live_contexts:
    - fi-icl-u2:          INCOMPLETE [fdo#108315] -> DMESG-FAIL [fdo#108569]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
  [fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
  [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965


Participating hosts (49 -> 45)
------------------------------

  Additional (2): fi-icl-y fi-pnv-d510 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5333 -> Patchwork_11126

  CI_DRM_5333: c758693b615deff56e5e2098379b587486cfff8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4750: f05c8c2739dce89185349703062784a7745cab14 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11126: e050519e52a564a46744301e737f0040ba144ee2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e050519e52a5 drm/i915/icl: Introduce gen11 flush/invalidate
7cbdc840c1d8 drm/i915/icl: Switch to using 12 deep CSB status FIFO
7854930e939b drm/i915: Prepare for larger CSB status FIFO size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11126/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Prepare for larger CSB status FIFO size (rev4)
URL   : https://patchwork.freedesktop.org/series/54213/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5333_full -> Patchwork_11126_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_11126_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11126_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11126_full:

### IGT changes ###

#### Possible regressions ####

  * igt@debugfs_test@read_all_entries:
    - shard-iclb:         PASS -> INCOMPLETE

  
#### Warnings ####

  * igt@kms_cursor_crc@cursor-128x42-offscreen:
    - shard-apl:          SKIP -> PASS +92

  * igt@perf_pmu@rc6:
    - shard-kbl:          SKIP -> PASS

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-snb:          PASS -> SKIP

  
Known issues
------------

  Here are the changes found in Patchwork_11126_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-skl:          PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-skl:          PASS -> TIMEOUT [fdo#108039]

  * igt@i915_suspend@shrink:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#108784]

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-snb:          NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-apl:          SKIP -> DMESG-WARN [fdo#107956] +1

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] +13

  * igt@kms_busy@extended-pageflip-hang-newfb-render-c:
    - shard-glk:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#107956]

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
    - shard-glk:          PASS -> FAIL [fdo#108145]

  * igt@kms_color@pipe-b-degamma:
    - shard-apl:          PASS -> FAIL [fdo#104782]

  * igt@kms_color@pipe-c-gamma:
    - shard-skl:          NOTRUN -> FAIL [fdo#104782] / [fdo#108228]

  * igt@kms_cursor_crc@cursor-128x128-random:
    - shard-skl:          NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-128x42-sliding:
    - shard-apl:          PASS -> FAIL [fdo#103232] +5
    - shard-glk:          PASS -> FAIL [fdo#103232] +2

  * igt@kms_cursor_crc@cursor-256x256-dpms:
    - shard-apl:          SKIP -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x256-offscreen:
    - shard-skl:          PASS -> FAIL [fdo#103232]

  * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled:
    - shard-iclb:         PASS -> WARN [fdo#108336] +1

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          PASS -> FAIL [fdo#105363]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-apl:          SKIP -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-glk:          PASS -> FAIL [fdo#103167] +5

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#107724] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-iclb:         PASS -> FAIL [fdo#105683]

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885]
    - shard-apl:          PASS -> FAIL [fdo#103166]

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-apl:          PASS -> FAIL [fdo#108948]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          SKIP -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815]

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +6

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-skl:          PASS -> INCOMPLETE [fdo#104108]

  * igt@perf_pmu@rc6-runtime-pm:
    - shard-apl:          PASS -> FAIL [fdo#105010]

  * {igt@runner@aborted}:
    - shard-snb:          NOTRUN -> FAIL [fdo#108929]

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          DMESG-WARN [fdo#103558] -> PASS

  * igt@kms_atomic_transition@1x-modeset-transitions-fencing:
    - shard-skl:          FAIL [fdo#108470] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_chv_cursor_fail@pipe-b-64x64-right-edge:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +5

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          FAIL [fdo#105454] / [fdo#106509] -> PASS

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-iclb:         FAIL [fdo#103355] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
    - shard-iclb:         WARN [fdo#108336] -> PASS +3

  * igt@kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled:
    - shard-skl:          FAIL [fdo#107791] -> PASS

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-glk:          FAIL [fdo#103060] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> PASS +3

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
    - shard-skl:          FAIL [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          FAIL [fdo#103167] -> PASS +5

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +3

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         DMESG-FAIL [fdo#103166] / [fdo#107724] -> PASS +1
    - shard-skl:          INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - shard-glk:          FAIL [fdo#103166] -> PASS +3

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-iclb:         FAIL [fdo#103166] -> PASS +2

  * igt@kms_psr@sprite_mmap_gtt:
    - shard-iclb:         DMESG-WARN [fdo#107724] -> PASS +24

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          DMESG-WARN [fdo#105604] -> PASS

  * igt@pm_rpm@cursor-dpms:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS

  
#### Warnings ####

  * igt@kms_ccs@pipe-c-crc-primary-basic:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#107725]

  * igt@kms_cursor_crc@cursor-64x21-onscreen:
    - shard-iclb:         FAIL [fdo#103232] -> DMESG-WARN [fdo#107724] / [fdo#108336] +1

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-iclb:         DMESG-FAIL [fdo#103232] / [fdo#107724] -> FAIL [fdo#103232]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         DMESG-FAIL [fdo#107724] -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-iclb:         FAIL [fdo#103167] -> DMESG-WARN [fdo#107724] / [fdo#108336]

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-iclb:         DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#108948]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
  [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
  [fdo#108929]: https://bugs.freedesktop.org/show_bug.cgi?id=108929
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948


Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5333 -> Patchwork_11126

  CI_DRM_5333: c758693b615deff56e5e2098379b587486cfff8a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4750: f05c8c2739dce89185349703062784a7745cab14 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11126: e050519e52a564a46744301e737f0040ba144ee2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11126/
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