[U-Boot] [PATCH v2 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver

[U-Boot] [PATCH v2 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver

[Lars Povlsen]

This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based
SOCs, and enables it on the supported platforms.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This version adress comments from Daniel Schwierzeck
<daniel.schwierzeck@gmail.com> and Linus Walleij
<linus.walleij@linaro.org>.

This is based off the u-boot-mips repository.

v2 changes:
 - Extended the DT bindings documentation
 - Eliminated the need for the "mscc,sgpio-bitcount" property.
 - Using dev_read_u32_default() instead of fdtdec_get_int()
 - Using map_physmem()
 - Added MAINTAINERS entry for driver

Lars Povlsen (6):
  mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
  mips: mscc_sgpio: Add DT bindings documentation
  mips: luton: DT: Enable use of serial gpio
  mips: luton: Enable use of serial gpio for LED
  mips: ocelot: DT: Enable use of serial gpio
  mips: ocelot: Enable use of serial gpio for LED

 MAINTAINERS                                  |   1 +
 arch/mips/dts/luton_pcb090.dts               |  21 ++
 arch/mips/dts/luton_pcb091.dts               |  27 ++
 arch/mips/dts/mscc,luton.dtsi                |  20 ++
 arch/mips/dts/mscc,ocelot.dtsi               |  23 ++
 arch/mips/dts/ocelot_pcb120.dts              |  76 +++++
 arch/mips/dts/ocelot_pcb123.dts              |  25 ++
 board/mscc/luton/luton.c                     |   6 +
 board/mscc/ocelot/ocelot.c                   |   6 +
 configs/mscc_luton_defconfig                 |   3 +
 configs/mscc_ocelot_defconfig                |   3 +
 doc/device-tree-bindings/gpio/mscc_sgpio.txt |  45 +++
 drivers/gpio/Kconfig                         |  11 +
 drivers/gpio/Makefile                        |   1 +
 drivers/gpio/mscc_sgpio.c                    | 274 +++++++++++++++++++
 15 files changed, 542 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
 create mode 100644 drivers/gpio/mscc_sgpio.c

-- 
2.19.2

[U-Boot] [PATCH v2 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)

[Lars Povlsen]

This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 MAINTAINERS               |   1 +
 drivers/gpio/Kconfig      |  11 ++
 drivers/gpio/Makefile     |   1 +
 drivers/gpio/mscc_sgpio.c | 274 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 287 insertions(+)
 create mode 100644 drivers/gpio/mscc_sgpio.c

diff --git a/MAINTAINERS b/MAINTAINERS
index ae825014bd..494962e9b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -523,6 +523,7 @@ F:	arch/mips/dts/mscc*
 F:	arch/mips/dts/ocelot*
 F:	board/mscc/
 F:	configs/mscc*
+F:	drivers/gpio/mscc_sgpio.c
 F:	include/configs/vcoreiii.h
 
 MIPS JZ4780
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60623..aa55ff43c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
 	  Support controlling the GPIO used for SPI bitbang by software. Can
 	  be used by the VCoreIII SoCs, but it was mainly useful for Luton.
 
+config MSCC_SGPIO
+	bool "Microsemi Serial GPIO driver"
+	depends on DM_GPIO && SOC_VCOREIII
+	help
+	  Support for the VCoreIII SoC serial GPIO device. By using a
+          serial interface, the SIO controller significantly extends
+          the number of available GPIOs with a minimum number of
+          additional pins on the device. The primary purpose of the
+          SIO controller is to connect control signals from SFP
+          modules and to act as an LED controller.
+
 config MSM_GPIO
 	bool "Qualcomm GPIO driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1537..be2b3c792f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
 obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)	+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 0000000000..134d36066c
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author: <lars.povlsen@microchip.com>
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <clk.h>
+
+#define MSCC_SGPIOS_PER_BANK	32
+#define MSCC_SGPIO_BANK_DEPTH	4
+
+enum {
+	REG_INPUT_DATA,
+	REG_PORT_CONFIG,
+	REG_PORT_ENABLE,
+	REG_SIO_CONFIG,
+	REG_SIO_CLOCK,
+	MAXREG
+};
+
+struct mscc_sgpio_bf {
+	u8 beg;
+	u8 end;
+};
+
+struct mscc_sgpio_props {
+	u8 regoff[MAXREG];
+	struct mscc_sgpio_bf auto_repeat;
+	struct mscc_sgpio_bf port_width;
+	struct mscc_sgpio_bf clk_freq;
+	struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)		GENMASK((bf).end, (bf).beg)
+#define __F(bf, x)	(__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x)	(((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p)		BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)		__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p)		__M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)		__F(p->props->clk_freq, x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p)		__M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)	__F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)	__X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+	.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+	.auto_repeat = { 5, 5 },
+	.port_width  = { 2, 3 },
+	.clk_freq    = { 0, 11 },
+	.bit_source  = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+	.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+	.auto_repeat = { 10, 10 },
+	.port_width  = {  7, 8  },
+	.clk_freq    = {  8, 19 },
+	.bit_source  = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+	u32 bitcount;
+	u32 ports;
+	u32 clock;
+	u32 mode[MSCC_SGPIOS_PER_BANK];
+	u32 __iomem *regs;
+	const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	return readl(reg);
+}
+
+static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
+				u32 val, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	writel(val, reg);
+}
+
+static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
+			     u32 rno, u32 off, u32 clear, u32 set)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	clrsetbits_le32(reg, clear, set);
+}
+
+static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+
+	priv->mode[port] |= BIT(bit);
+
+	return 0;
+}
+
+static int mscc_sgpio_direction_output(struct udevice *dev,
+				       unsigned int gpio, int value)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 mask = 3 << (3 * bit);
+
+	debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
+	      port, bit, mask, value);
+
+	value = (value & 3) << (3 * bit);
+	sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
+	clrbits_le32(&priv->mode[port], BIT(bit));
+
+	return 0;
+}
+
+static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 val = priv->mode[port] & BIT(bit);
+
+	if (val)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int mscc_sgpio_set_value(struct udevice *dev,
+				unsigned int gpio, int value)
+{
+	return mscc_sgpio_direction_output(dev, gpio, value);
+}
+
+static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	int ret;
+
+	if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
+		ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
+	} else {
+		u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
+
+		ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
+		ret = !!(ret & (3 << (3 * bit)));
+	}
+
+	debug("get: gpio %d, port %d, bit %d, value %d\n",
+	      gpio, port, bit, ret);
+	return ret;
+}
+
+static int mscc_sgpio_get_count(struct udevice *dev)
+{
+	struct ofnode_phandle_args args;
+	int count = 0, i = 0, ret;
+
+	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
+	while (ret != -ENOENT) {
+		count += args.args[2];
+		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+						 ++i, &args);
+	}
+	return count;
+}
+
+static int mscc_sgpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	int err, div_clock = 0, port;
+	u32 val;
+	struct clk clk;
+
+	err = clk_get_by_index(dev, 0, &clk);
+	if (!err) {
+		err = clk_get_rate(&clk);
+		if (!IS_ERR_VALUE(err))
+			div_clock = err;
+	} else {
+		debug("mscc_sgpio: failed to get clock\n");
+		return err;
+	}
+
+	priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
+	priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
+	priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
+					   12500000);
+	if (priv->clock <= 0 || priv->clock > div_clock) {
+		printf("mscc_sgpio: Invalid frequency %d\n", priv->clock);
+		return -EINVAL;
+	}
+
+	uc_priv->gpio_count = mscc_sgpio_get_count(dev);
+	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+						   uc_priv->gpio_count);
+	if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
+	    (4 * MSCC_SGPIOS_PER_BANK)) {
+		printf("mscc_sgpio: gpio count %d\n", uc_priv->gpio_count);
+		return -EINVAL;
+	}
+	priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
+				      MSCC_SGPIOS_PER_BANK);
+	debug("probe: gpios = %d, bit-count = %d\n",
+	      uc_priv->gpio_count, priv->bitcount);
+
+	priv->regs = (u32 __iomem *)map_physmem(devfdt_get_addr(dev),
+						0x100,
+						MAP_NOCACHE);
+	uc_priv->bank_name = "sgpio";
+
+	sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
+			 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
+			 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
+			 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
+	val = div_clock / priv->clock;
+	debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
+	      div_clock / 1000, priv->clock / 1000, val);
+	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
+			 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
+			 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
+
+	for (port = 0; port < 32; port++)
+		sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
+	sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
+
+	debug("probe: sgpio regs = %p\n", priv->regs);
+
+	return 0;
+}
+
+static const struct dm_gpio_ops mscc_sgpio_ops = {
+	.direction_input	= mscc_sgpio_direction_input,
+	.direction_output	= mscc_sgpio_direction_output,
+	.get_function		= mscc_sgpio_get_function,
+	.get_value		= mscc_sgpio_get_value,
+	.set_value		= mscc_sgpio_set_value,
+};
+
+static const struct udevice_id mscc_sgpio_ids[] = {
+	{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
+	{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_mscc_sgpio) = {
+	.name			= "mscc-sgpio",
+	.id			= UCLASS_GPIO,
+	.of_match		= mscc_sgpio_ids,
+	.ops			= &mscc_sgpio_ops,
+	.probe			= mscc_sgpio_probe,
+	.priv_auto_alloc_size	= sizeof(struct mscc_sgpio_priv),
+};
-- 
2.19.2

[U-Boot] [PATCH v2 2/6] mips: mscc_sgpio: Add DT bindings documentation

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This add device tree binding documentation for the MSCC serial GPIO
driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
---
 doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45 ++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt

diff --git a/doc/device-tree-bindings/gpio/mscc_sgpio.txt b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
new file mode 100644
index 0000000000..2db2d277a5
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
@@ -0,0 +1,45 @@
+Microsemi Corporation (MSCC) Serial GPIO driver
+
+The MSCC serial GPIO extends the number or GPIO's on the system by
+means of 4 dedicated pins: one input, one output, one clock and one
+strobe pin. By attaching a number of (external) shift registers, the
+effective GPIO count can be extended by up to 128 GPIO's per
+controller.
+
+Required properties:
+- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
+- clock: Reference clock used to generate clock divider setting. See
+  mscc,sgpio-frequency property.
+- reg : Physical base address and length of the controller's registers.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters:
+  - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
+  and count.
+
+Optional properties:
+- ngpios: Set the number of GPIO's actually used.
+- mscc,sgpio-frequency: The frequency at which the serial bitstream is
+  generated and sampled. Default: 12500000 (Hz).
+- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
+  the serialized gpio stream. One 'port' will transport from 1 to 4
+  gpio bits. Default: 0xFFFFFFFF.
+
+Typically the pinctrl-0 and pinctrl-names properties will also be
+present to enable the use of the SIO CLK, LD, DI and DO for some
+regular GPIO pins.
+
+Example:
+
+sgpio: gpio at 10700f8 {
+       compatible = "mscc,ocelot-sgpio";
+       pinctrl-0 = <&sgpio_pins>;
+       pinctrl-names = "default";
+       reg = <0x10700f8 0x100>;
+       gpio-controller;
+       #gpio-cells = <2>;
+       gpio-ranges = <&sgpio 0 0 64>;
+       mscc,sgpio-frequency = <12500>;
+       mscc,sgpio-ports = <0x000FFFFF>;
+};
-- 
2.19.2

[U-Boot] [PATCH v2 3/6] mips: luton: DT: Enable use of serial gpio

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
---
 arch/mips/dts/luton_pcb090.dts | 21 +++++++++++++++++++++
 arch/mips/dts/luton_pcb091.dts | 27 +++++++++++++++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 20 ++++++++++++++++++++
 3 files changed, 68 insertions(+)

diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index a3f8926ad9..951d8da1be 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -18,6 +18,27 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status_green {
+			label = "pcb090:green:status";
+			gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb090:red:status";
+			gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	gpio-ranges = <&sgpio 0 0 96>;
 };
 
 &uart0 {
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index 74f9274c21..bf638b2bc7 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -18,6 +18,33 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		top_dimmer {
+			label = "pcb091:top:dimmer";
+			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		status_green {
+			label = "pcb091:green:status";
+			gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb091:red:status";
+			gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0xFFF000FF>;
 };
 
 &uart0 {
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 6a4ad2a5be..87e27c6de5 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -25,6 +25,11 @@
 		serial0 = &uart0;
 	};
 
+	sys_clk: sys-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
 	ahb_clk: ahb-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -57,11 +62,26 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 32>;
 
+			sgpio_pins: sgpio-pins {
+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+				function = "sio";
+			};
 			uart_pins: uart-pins {
 				pins = "GPIO_30", "GPIO_31";
 				function = "uart";
 			};
+		};
 
+		sgpio: gpio at 70130 {
+			compatible = "mscc,luton-sgpio";
+			status = "disabled";
+			clocks = <&sys_clk>;
+			pinctrl-0 = <&sgpio_pins>;
+			pinctrl-names = "default";
+			reg = <0x0070130 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&sgpio 0 0 64>;
 		};
 
 		gpio_spi_bitbang: gpio at 10000064 {
-- 
2.19.2

[U-Boot] [PATCH v2 4/6] mips: luton: Enable use of serial gpio for LED

[Lars Povlsen]

This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'luton' SoC.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 board/mscc/luton/luton.c     | 6 ++++++
 configs/mscc_luton_defconfig | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index b509b6beb3..807c717e33 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +28,11 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
 	return 0;
 }
 
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 03922f5379..0b3eb3865c 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -46,6 +46,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-- 
2.19.2

[U-Boot] [PATCH v2 5/6] mips: ocelot: DT: Enable use of serial gpio

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
---
 arch/mips/dts/mscc,ocelot.dtsi  | 23 ++++++++++
 arch/mips/dts/ocelot_pcb120.dts | 76 +++++++++++++++++++++++++++++++++
 arch/mips/dts/ocelot_pcb123.dts | 25 +++++++++++
 3 files changed, 124 insertions(+)

diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 87b4736285..2592003103 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -37,6 +37,12 @@
 		clock-frequency = <500000000>;
 	};
 
+	sys_clk: sys-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
+
 	ahb_clk: ahb-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -118,6 +124,11 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 22>;
 
+			sgpio_pins: sgpio-pins {
+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+				function = "sg0";
+			};
+
 			uart_pins: uart-pins {
 				pins = "GPIO_6", "GPIO_7";
 				function = "uart";
@@ -148,5 +159,17 @@
 				function = "si";
 			};
 		};
+
+		sgpio: gpio at 10700f8 {
+			compatible = "mscc,ocelot-sgpio";
+			status = "disabled";
+			clocks = <&sys_clk>;
+			pinctrl-0 = <&sgpio_pins>;
+			pinctrl-names = "default";
+			reg = <0x10700f8 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&sgpio 0 0 64>;
+		};
 	};
 };
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 47d305a614..658719e684 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -9,4 +9,80 @@
 / {
 	model = "Ocelot PCB120 Reference Board";
 	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		poe_green {
+			label = "pcb120:green:poe";
+			gpios = <&sgpio 44 1>; /* p12.1 */
+			default-state = "off";
+		};
+
+		poe_red {
+			label = "pcb120:red:poe";
+			gpios = <&sgpio 12 1>; /* p12.0 */
+			default-state = "off";
+		};
+
+		alarm_green {
+			label = "pcb120:green:alarm";
+			gpios = <&sgpio 45 1>; /* p13.1 */
+			default-state = "off";
+		};
+
+		alarm_red {
+			label = "pcb120:red:alarm";
+			gpios = <&sgpio 13 1>; /* p13.0 */
+			default-state = "off";
+		};
+
+		dc_a_green {
+			label = "pcb120:green:dc_a";
+			gpios = <&sgpio 46 1>; /* p14.1 */
+			default-state = "off";
+		};
+
+		dc_a_red {
+			label = "pcb120:red:dc_a";
+			gpios = <&sgpio 14 1>; /* p14.0 */
+			default-state = "off";
+		};
+
+		dc_b_green {
+			label = "pcb120:green:dc_b";
+			gpios = <&sgpio 47 1>; /* p15.1 */
+			default-state = "off";
+		};
+
+		dc_b_red {
+			label = "pcb120:red:dc_b";
+			gpios = <&sgpio 15 1>; /* p15.0 */
+			default-state = "off";
+		};
+
+		status_green {
+			label = "pcb120:green:status";
+			gpios = <&sgpio 48 1>; /* p16.1 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb120:red:alarm";
+			gpios = <&sgpio 16 1>; /* p16.0 */
+			default-state = "off";
+		};
+
+	};
+
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0x000FFFFF>;
 };
+
diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
index 17d8d326ce..c4cb7a1194 100644
--- a/arch/mips/dts/ocelot_pcb123.dts
+++ b/arch/mips/dts/ocelot_pcb123.dts
@@ -9,4 +9,29 @@
 / {
 	model = "Ocelot PCB123 Reference Board";
 	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status_green {
+			label = "pcb123:green:status";
+			gpios = <&sgpio 43 1>; /* p11.1 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb123:red:status";
+			gpios = <&sgpio 11 1>; /* p11.0 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0x00FFFFFF>;
 };
-- 
2.19.2

[U-Boot] [PATCH v2 6/6] mips: ocelot: Enable use of serial gpio for LED

[Lars Povlsen]

This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 board/mscc/ocelot/ocelot.c    | 6 ++++++
 configs/mscc_ocelot_defconfig | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index a557cacd1b..a05c308669 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -9,6 +9,7 @@
 #include <asm/types.h>
 #include <environment.h>
 #include <spi.h>
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,6 +57,11 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
 	return 0;
 }
 
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 66451000d9..fb6a5bdc31 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -48,6 +48,9 @@ CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_SPI_NAND=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-- 
2.19.2

[U-Boot] [PATCH v2 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)

[Daniel Schwierzeck]

Am Do., 27. Dez. 2018 um 12:51 Uhr schrieb Lars Povlsen
<lars.povlsen@microchip.com>:
>
> This add support for the the MSCC serial GPIO driver in MSCC
> VCoreIII-based SOCs.
>
> By using a serial interface, the SIO controller significantly extends
> the number of available GPIOs with a minimum number of additional pins
> on the device. The primary purpose of the SIO controller is to connect
> control signals from SFP modules and to act as an LED controller.
>
> This adds the base driver.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> ---
>  MAINTAINERS               |   1 +
>  drivers/gpio/Kconfig      |  11 ++
>  drivers/gpio/Makefile     |   1 +
>  drivers/gpio/mscc_sgpio.c | 274 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 287 insertions(+)
>  create mode 100644 drivers/gpio/mscc_sgpio.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ae825014bd..494962e9b3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -523,6 +523,7 @@ F:  arch/mips/dts/mscc*
>  F:     arch/mips/dts/ocelot*
>  F:     board/mscc/
>  F:     configs/mscc*
> +F:     drivers/gpio/mscc_sgpio.c
>  F:     include/configs/vcoreiii.h
>
>  MIPS JZ4780
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index c8c6c60623..aa55ff43c4 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
>           Support controlling the GPIO used for SPI bitbang by software. Can
>           be used by the VCoreIII SoCs, but it was mainly useful for Luton.
>
> +config MSCC_SGPIO
> +       bool "Microsemi Serial GPIO driver"
> +       depends on DM_GPIO && SOC_VCOREIII
> +       help
> +         Support for the VCoreIII SoC serial GPIO device. By using a
> +          serial interface, the SIO controller significantly extends
> +          the number of available GPIOs with a minimum number of
> +          additional pins on the device. The primary purpose of the
> +          SIO controller is to connect control signals from SFP
> +          modules and to act as an LED controller.
> +
>  config MSM_GPIO
>         bool "Qualcomm GPIO driver"
>         depends on DM_GPIO
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 61feda1537..be2b3c792f 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO)     += pcf8575_gpio.o
>  obj-$(CONFIG_PM8916_GPIO)      += pm8916_gpio.o
>  obj-$(CONFIG_MT7621_GPIO)      += mt7621_gpio.o
>  obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)    += gpio-mscc-bitbang-spi.o
> +obj-$(CONFIG_MSCC_SGPIO)       += mscc_sgpio.o
> diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
> new file mode 100644
> index 0000000000..134d36066c
> --- /dev/null
> +++ b/drivers/gpio/mscc_sgpio.c
> @@ -0,0 +1,274 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Microsemi SoCs serial gpio driver
> + *
> + * Author: <lars.povlsen@microchip.com>
> + *
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <clk.h>
> +
> +#define MSCC_SGPIOS_PER_BANK   32
> +#define MSCC_SGPIO_BANK_DEPTH  4
> +
> +enum {
> +       REG_INPUT_DATA,
> +       REG_PORT_CONFIG,
> +       REG_PORT_ENABLE,
> +       REG_SIO_CONFIG,
> +       REG_SIO_CLOCK,
> +       MAXREG
> +};
> +
> +struct mscc_sgpio_bf {
> +       u8 beg;
> +       u8 end;
> +};
> +
> +struct mscc_sgpio_props {
> +       u8 regoff[MAXREG];
> +       struct mscc_sgpio_bf auto_repeat;
> +       struct mscc_sgpio_bf port_width;
> +       struct mscc_sgpio_bf clk_freq;
> +       struct mscc_sgpio_bf bit_source;
> +};
> +
> +#define __M(bf)                GENMASK((bf).end, (bf).beg)
> +#define __F(bf, x)     (__M(bf) & ((x) << (bf).beg))
> +#define __X(bf, x)     (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
> +
> +#define MSCC_M_CFG_SIO_AUTO_REPEAT(p)          BIT(p->props->auto_repeat.beg)
> +#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)                __F(p->props->port_width, x)
> +#define MSCC_M_CFG_SIO_PORT_WIDTH(p)           __M(p->props->port_width)
> +#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)                __F(p->props->clk_freq, x)
> +#define MSCC_M_CLOCK_SIO_CLK_FREQ(p)           __M(p->props->clk_freq)
> +#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)       __F(p->props->bit_source, x)
> +#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)       __X(p->props->bit_source, x)
> +
> +const struct mscc_sgpio_props props_luton = {
> +       .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
> +       .auto_repeat = { 5, 5 },
> +       .port_width  = { 2, 3 },
> +       .clk_freq    = { 0, 11 },
> +       .bit_source  = { 0, 11 },
> +};
> +
> +const struct mscc_sgpio_props props_ocelot = {
> +       .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
> +       .auto_repeat = { 10, 10 },
> +       .port_width  = {  7, 8  },
> +       .clk_freq    = {  8, 19 },
> +       .bit_source  = { 12, 23 },
> +};
> +
> +struct mscc_sgpio_priv {
> +       u32 bitcount;
> +       u32 ports;
> +       u32 clock;
> +       u32 mode[MSCC_SGPIOS_PER_BANK];
> +       u32 __iomem *regs;
> +       const struct mscc_sgpio_props *props;
> +};
> +
> +static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
> +{
> +       u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
> +
> +       return readl(reg);
> +}
> +
> +static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
> +                               u32 val, u32 rno, u32 off)
> +{
> +       u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
> +
> +       writel(val, reg);
> +}
> +
> +static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
> +                            u32 rno, u32 off, u32 clear, u32 set)
> +{
> +       u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
> +
> +       clrsetbits_le32(reg, clear, set);
> +}
> +
> +static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
> +{
> +       struct mscc_sgpio_priv *priv = dev_get_priv(dev);
> +
> +       u32 port = gpio % MSCC_SGPIOS_PER_BANK;
> +       u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
> +
> +       priv->mode[port] |= BIT(bit);
> +
> +       return 0;
> +}
> +
> +static int mscc_sgpio_direction_output(struct udevice *dev,
> +                                      unsigned int gpio, int value)
> +{
> +       struct mscc_sgpio_priv *priv = dev_get_priv(dev);
> +       u32 port = gpio % MSCC_SGPIOS_PER_BANK;
> +       u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
> +       u32 mask = 3 << (3 * bit);
> +
> +       debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
> +             port, bit, mask, value);
> +
> +       value = (value & 3) << (3 * bit);
> +       sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
> +                        MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
> +                        MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
> +       clrbits_le32(&priv->mode[port], BIT(bit));
> +
> +       return 0;
> +}
> +
> +static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
> +{
> +       struct mscc_sgpio_priv *priv = dev_get_priv(dev);
> +       u32 port = gpio % MSCC_SGPIOS_PER_BANK;
> +       u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
> +       u32 val = priv->mode[port] & BIT(bit);
> +
> +       if (val)
> +               return GPIOF_INPUT;
> +       else
> +               return GPIOF_OUTPUT;
> +}
> +
> +static int mscc_sgpio_set_value(struct udevice *dev,
> +                               unsigned int gpio, int value)
> +{
> +       return mscc_sgpio_direction_output(dev, gpio, value);
> +}
> +
> +static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
> +{
> +       struct mscc_sgpio_priv *priv = dev_get_priv(dev);
> +       u32 port = gpio % MSCC_SGPIOS_PER_BANK;
> +       u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
> +       int ret;
> +
> +       if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
> +               ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
> +       } else {
> +               u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
> +
> +               ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
> +               ret = !!(ret & (3 << (3 * bit)));
> +       }
> +
> +       debug("get: gpio %d, port %d, bit %d, value %d\n",
> +             gpio, port, bit, ret);
> +       return ret;
> +}
> +
> +static int mscc_sgpio_get_count(struct udevice *dev)
> +{
> +       struct ofnode_phandle_args args;
> +       int count = 0, i = 0, ret;
> +
> +       ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
> +       while (ret != -ENOENT) {
> +               count += args.args[2];
> +               ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
> +                                                ++i, &args);
> +       }
> +       return count;
> +}
> +
> +static int mscc_sgpio_probe(struct udevice *dev)
> +{
> +       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
> +       struct mscc_sgpio_priv *priv = dev_get_priv(dev);
> +       int err, div_clock = 0, port;
> +       u32 val;
> +       struct clk clk;
> +
> +       err = clk_get_by_index(dev, 0, &clk);
> +       if (!err) {
> +               err = clk_get_rate(&clk);
> +               if (!IS_ERR_VALUE(err))
> +                       div_clock = err;

shouldn't the probe fail without a clock?

> +       } else {
> +               debug("mscc_sgpio: failed to get clock\n");
> +               return err;
> +       }
> +
> +       priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
> +       priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
> +       priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
> +                                          12500000);
> +       if (priv->clock <= 0 || priv->clock > div_clock) {
> +               printf("mscc_sgpio: Invalid frequency %d\n", priv->clock);
> +               return -EINVAL;
> +       }
> +
> +       uc_priv->gpio_count = mscc_sgpio_get_count(dev);
> +       uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
> +                                                  uc_priv->gpio_count);
> +       if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
> +           (4 * MSCC_SGPIOS_PER_BANK)) {
> +               printf("mscc_sgpio: gpio count %d\n", uc_priv->gpio_count);
> +               return -EINVAL;
> +       }
> +       priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
> +                                     MSCC_SGPIOS_PER_BANK);
> +       debug("probe: gpios = %d, bit-count = %d\n",
> +             uc_priv->gpio_count, priv->bitcount);
> +
> +       priv->regs = (u32 __iomem *)map_physmem(devfdt_get_addr(dev),
> +                                               0x100,
> +                                               MAP_NOCACHE);

there is a wrapper dev_remap_addr() for this

> +       uc_priv->bank_name = "sgpio";
> +
> +       sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
> +                        MSCC_M_CFG_SIO_PORT_WIDTH(priv),
> +                        MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
> +                        MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
> +       val = div_clock / priv->clock;
> +       debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
> +             div_clock / 1000, priv->clock / 1000, val);
> +       sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
> +                        MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
> +                        MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
> +
> +       for (port = 0; port < 32; port++)
> +               sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
> +       sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
> +
> +       debug("probe: sgpio regs = %p\n", priv->regs);
> +
> +       return 0;
> +}
> +
> +static const struct dm_gpio_ops mscc_sgpio_ops = {
> +       .direction_input        = mscc_sgpio_direction_input,
> +       .direction_output       = mscc_sgpio_direction_output,
> +       .get_function           = mscc_sgpio_get_function,
> +       .get_value              = mscc_sgpio_get_value,
> +       .set_value              = mscc_sgpio_set_value,
> +};
> +
> +static const struct udevice_id mscc_sgpio_ids[] = {
> +       { .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
> +       { .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(gpio_mscc_sgpio) = {
> +       .name                   = "mscc-sgpio",
> +       .id                     = UCLASS_GPIO,
> +       .of_match               = mscc_sgpio_ids,
> +       .ops                    = &mscc_sgpio_ops,
> +       .probe                  = mscc_sgpio_probe,
> +       .priv_auto_alloc_size   = sizeof(struct mscc_sgpio_priv),
> +};
> --
> 2.19.2
>


-- 
- Daniel

[U-Boot] [PATCH v3 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver

[Lars Povlsen]

This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based
SOCs, and enables it on the supported platforms.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This version address comments from Daniel Schwierzeck
<daniel.schwierzeck@gmail.com> and Linus Walleij
<linus.walleij@linaro.org>.

This is based off the u-boot-mips repository.

v3 changes:
 - Fail driver load if clk_get_rate() fails
 - Use dev_remap_addr() instead of map_physmem()
 - Use dev_err instead of printf
 - (DT doc) ngpios: Refer to gpio.txt

v2 changes:
 - Extended the DT bindings documentation
 - Eliminated the need for the "mscc,sgpio-bitcount" property.
 - Using dev_read_u32_default() instead of fdtdec_get_int()
 - Using map_physmem()
 - Added MAINTAINERS entry for driver

Lars Povlsen (6):
  mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
  mips: mscc_sgpio: Add DT bindings documentation
  mips: luton: DT: Enable use of serial gpio
  mips: luton: Enable use of serial gpio for LED
  mips: ocelot: DT: Enable use of serial gpio
  mips: ocelot: Enable use of serial gpio for LED

 MAINTAINERS                                  |   1 +
 arch/mips/dts/luton_pcb090.dts               |  21 ++
 arch/mips/dts/luton_pcb091.dts               |  27 ++
 arch/mips/dts/mscc,luton.dtsi                |  20 ++
 arch/mips/dts/mscc,ocelot.dtsi               |  23 ++
 arch/mips/dts/ocelot_pcb120.dts              |  76 +++++
 arch/mips/dts/ocelot_pcb123.dts              |  25 ++
 board/mscc/luton/luton.c                     |   6 +
 board/mscc/ocelot/ocelot.c                   |   6 +
 configs/mscc_luton_defconfig                 |   3 +
 configs/mscc_ocelot_defconfig                |   3 +
 doc/device-tree-bindings/gpio/mscc_sgpio.txt |  45 +++
 drivers/gpio/Kconfig                         |  11 +
 drivers/gpio/Makefile                        |   1 +
 drivers/gpio/mscc_sgpio.c                    | 275 +++++++++++++++++++
 15 files changed, 543 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
 create mode 100644 drivers/gpio/mscc_sgpio.c

-- 
2.19.2

[U-Boot] [PATCH v3 1/6] mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)

[Lars Povlsen]

This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 MAINTAINERS               |   1 +
 drivers/gpio/Kconfig      |  11 ++
 drivers/gpio/Makefile     |   1 +
 drivers/gpio/mscc_sgpio.c | 275 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 288 insertions(+)
 create mode 100644 drivers/gpio/mscc_sgpio.c

diff --git a/MAINTAINERS b/MAINTAINERS
index ae825014bd..494962e9b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -523,6 +523,7 @@ F:	arch/mips/dts/mscc*
 F:	arch/mips/dts/ocelot*
 F:	board/mscc/
 F:	configs/mscc*
+F:	drivers/gpio/mscc_sgpio.c
 F:	include/configs/vcoreiii.h
 
 MIPS JZ4780
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60623..aa55ff43c4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -106,6 +106,17 @@ config MSCC_BITBANG_SPI_GPIO
 	  Support controlling the GPIO used for SPI bitbang by software. Can
 	  be used by the VCoreIII SoCs, but it was mainly useful for Luton.
 
+config MSCC_SGPIO
+	bool "Microsemi Serial GPIO driver"
+	depends on DM_GPIO && SOC_VCOREIII
+	help
+	  Support for the VCoreIII SoC serial GPIO device. By using a
+          serial interface, the SIO controller significantly extends
+          the number of available GPIOs with a minimum number of
+          additional pins on the device. The primary purpose of the
+          SIO controller is to connect control signals from SFP
+          modules and to act as an LED controller.
+
 config MSM_GPIO
 	bool "Qualcomm GPIO driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1537..be2b3c792f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
 obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)	+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 0000000000..c899454ec4
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author: <lars.povlsen@microchip.com>
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <clk.h>
+
+#define MSCC_SGPIOS_PER_BANK	32
+#define MSCC_SGPIO_BANK_DEPTH	4
+
+enum {
+	REG_INPUT_DATA,
+	REG_PORT_CONFIG,
+	REG_PORT_ENABLE,
+	REG_SIO_CONFIG,
+	REG_SIO_CLOCK,
+	MAXREG
+};
+
+struct mscc_sgpio_bf {
+	u8 beg;
+	u8 end;
+};
+
+struct mscc_sgpio_props {
+	u8 regoff[MAXREG];
+	struct mscc_sgpio_bf auto_repeat;
+	struct mscc_sgpio_bf port_width;
+	struct mscc_sgpio_bf clk_freq;
+	struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)		GENMASK((bf).end, (bf).beg)
+#define __F(bf, x)	(__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x)	(((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p)		BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)		__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p)		__M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)		__F(p->props->clk_freq, x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p)		__M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)	__F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)	__X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+	.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+	.auto_repeat = { 5, 5 },
+	.port_width  = { 2, 3 },
+	.clk_freq    = { 0, 11 },
+	.bit_source  = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+	.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+	.auto_repeat = { 10, 10 },
+	.port_width  = {  7, 8  },
+	.clk_freq    = {  8, 19 },
+	.bit_source  = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+	u32 bitcount;
+	u32 ports;
+	u32 clock;
+	u32 mode[MSCC_SGPIOS_PER_BANK];
+	u32 __iomem *regs;
+	const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	return readl(reg);
+}
+
+static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
+				u32 val, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	writel(val, reg);
+}
+
+static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
+			     u32 rno, u32 off, u32 clear, u32 set)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	clrsetbits_le32(reg, clear, set);
+}
+
+static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+
+	priv->mode[port] |= BIT(bit);
+
+	return 0;
+}
+
+static int mscc_sgpio_direction_output(struct udevice *dev,
+				       unsigned int gpio, int value)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 mask = 3 << (3 * bit);
+
+	debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
+	      port, bit, mask, value);
+
+	value = (value & 3) << (3 * bit);
+	sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
+	clrbits_le32(&priv->mode[port], BIT(bit));
+
+	return 0;
+}
+
+static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 val = priv->mode[port] & BIT(bit);
+
+	if (val)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int mscc_sgpio_set_value(struct udevice *dev,
+				unsigned int gpio, int value)
+{
+	return mscc_sgpio_direction_output(dev, gpio, value);
+}
+
+static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	int ret;
+
+	if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
+		ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
+	} else {
+		u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
+
+		ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
+		ret = !!(ret & (3 << (3 * bit)));
+	}
+
+	debug("get: gpio %d, port %d, bit %d, value %d\n",
+	      gpio, port, bit, ret);
+	return ret;
+}
+
+static int mscc_sgpio_get_count(struct udevice *dev)
+{
+	struct ofnode_phandle_args args;
+	int count = 0, i = 0, ret;
+
+	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
+	while (ret != -ENOENT) {
+		count += args.args[2];
+		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+						 ++i, &args);
+	}
+	return count;
+}
+
+static int mscc_sgpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	int err, div_clock = 0, port;
+	u32 val;
+	struct clk clk;
+
+	err = clk_get_by_index(dev, 0, &clk);
+	if (!err) {
+		err = clk_get_rate(&clk);
+		if (IS_ERR_VALUE(err)) {
+			dev_err(dev, "Invalid clk rate\n");
+			return -EINVAL;
+		}
+		div_clock = err;
+	} else {
+		dev_err(dev, "Failed to get clock\n");
+		return err;
+	}
+
+	priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
+	priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
+	priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
+					   12500000);
+	if (priv->clock <= 0 || priv->clock > div_clock) {
+		dev_err(dev, "Invalid frequency %d\n", priv->clock);
+		return -EINVAL;
+	}
+
+	uc_priv->gpio_count = mscc_sgpio_get_count(dev);
+	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+						   uc_priv->gpio_count);
+	if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
+	    (4 * MSCC_SGPIOS_PER_BANK)) {
+		dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
+		return -EINVAL;
+	}
+	priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
+				      MSCC_SGPIOS_PER_BANK);
+	debug("probe: gpios = %d, bit-count = %d\n",
+	      uc_priv->gpio_count, priv->bitcount);
+
+	priv->regs = (u32 __iomem *)dev_read_addr(dev);
+	uc_priv->bank_name = "sgpio";
+
+	sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
+			 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
+			 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
+			 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
+	val = div_clock / priv->clock;
+	debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
+	      div_clock / 1000, priv->clock / 1000, val);
+	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
+			 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
+			 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
+
+	for (port = 0; port < 32; port++)
+		sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
+	sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
+
+	debug("probe: sgpio regs = %p\n", priv->regs);
+
+	return 0;
+}
+
+static const struct dm_gpio_ops mscc_sgpio_ops = {
+	.direction_input	= mscc_sgpio_direction_input,
+	.direction_output	= mscc_sgpio_direction_output,
+	.get_function		= mscc_sgpio_get_function,
+	.get_value		= mscc_sgpio_get_value,
+	.set_value		= mscc_sgpio_set_value,
+};
+
+static const struct udevice_id mscc_sgpio_ids[] = {
+	{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
+	{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_mscc_sgpio) = {
+	.name			= "mscc-sgpio",
+	.id			= UCLASS_GPIO,
+	.of_match		= mscc_sgpio_ids,
+	.ops			= &mscc_sgpio_ops,
+	.probe			= mscc_sgpio_probe,
+	.priv_auto_alloc_size	= sizeof(struct mscc_sgpio_priv),
+};
-- 
2.19.2

[U-Boot] [PATCH v3 2/6] mips: mscc_sgpio: Add DT bindings documentation

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This add device tree binding documentation for the MSCC serial GPIO
driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 doc/device-tree-bindings/gpio/mscc_sgpio.txt | 45 ++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt

diff --git a/doc/device-tree-bindings/gpio/mscc_sgpio.txt b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
new file mode 100644
index 0000000000..3d344d64ac
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/mscc_sgpio.txt
@@ -0,0 +1,45 @@
+Microsemi Corporation (MSCC) Serial GPIO driver
+
+The MSCC serial GPIO extends the number or GPIO's on the system by
+means of 4 dedicated pins: one input, one output, one clock and one
+strobe pin. By attaching a number of (external) shift registers, the
+effective GPIO count can be extended by up to 128 GPIO's per
+controller.
+
+Required properties:
+- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
+- clock: Reference clock used to generate clock divider setting. See
+  mscc,sgpio-frequency property.
+- reg : Physical base address and length of the controller's registers.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters:
+  - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
+  and count.
+
+Optional properties:
+- ngpios: See gpio.txt
+- mscc,sgpio-frequency: The frequency at which the serial bitstream is
+  generated and sampled. Default: 12500000 (Hz).
+- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
+  the serialized gpio stream. One 'port' will transport from 1 to 4
+  gpio bits. Default: 0xFFFFFFFF.
+
+Typically the pinctrl-0 and pinctrl-names properties will also be
+present to enable the use of the SIO CLK, LD, DI and DO for some
+regular GPIO pins.
+
+Example:
+
+sgpio: gpio at 10700f8 {
+       compatible = "mscc,ocelot-sgpio";
+       pinctrl-0 = <&sgpio_pins>;
+       pinctrl-names = "default";
+       reg = <0x10700f8 0x100>;
+       gpio-controller;
+       #gpio-cells = <2>;
+       gpio-ranges = <&sgpio 0 0 64>;
+       mscc,sgpio-frequency = <12500>;
+       mscc,sgpio-ports = <0x000FFFFF>;
+};
-- 
2.19.2

[U-Boot] [PATCH v3 3/6] mips: luton: DT: Enable use of serial gpio

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This enables the use of the MSCC serial GPIO driver, and add gpio-leds
nodes to the 'luton' pcb090 and pcb091 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
---
 arch/mips/dts/luton_pcb090.dts | 21 +++++++++++++++++++++
 arch/mips/dts/luton_pcb091.dts | 27 +++++++++++++++++++++++++++
 arch/mips/dts/mscc,luton.dtsi  | 20 ++++++++++++++++++++
 3 files changed, 68 insertions(+)

diff --git a/arch/mips/dts/luton_pcb090.dts b/arch/mips/dts/luton_pcb090.dts
index a3f8926ad9..951d8da1be 100644
--- a/arch/mips/dts/luton_pcb090.dts
+++ b/arch/mips/dts/luton_pcb090.dts
@@ -18,6 +18,27 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status_green {
+			label = "pcb090:green:status";
+			gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb090:red:status";
+			gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	gpio-ranges = <&sgpio 0 0 96>;
 };
 
 &uart0 {
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
index 74f9274c21..bf638b2bc7 100644
--- a/arch/mips/dts/luton_pcb091.dts
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -18,6 +18,33 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		top_dimmer {
+			label = "pcb091:top:dimmer";
+			gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+
+		status_green {
+			label = "pcb091:green:status";
+			gpios = <&sgpio 26 GPIO_ACTIVE_HIGH>; /* p26.0 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb091:red:status";
+			gpios = <&sgpio 58 GPIO_ACTIVE_HIGH>; /* p26.1 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0xFFF000FF>;
 };
 
 &uart0 {
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
index 6a4ad2a5be..87e27c6de5 100644
--- a/arch/mips/dts/mscc,luton.dtsi
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -25,6 +25,11 @@
 		serial0 = &uart0;
 	};
 
+	sys_clk: sys-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
 	ahb_clk: ahb-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -57,11 +62,26 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 32>;
 
+			sgpio_pins: sgpio-pins {
+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+				function = "sio";
+			};
 			uart_pins: uart-pins {
 				pins = "GPIO_30", "GPIO_31";
 				function = "uart";
 			};
+		};
 
+		sgpio: gpio at 70130 {
+			compatible = "mscc,luton-sgpio";
+			status = "disabled";
+			clocks = <&sys_clk>;
+			pinctrl-0 = <&sgpio_pins>;
+			pinctrl-names = "default";
+			reg = <0x0070130 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&sgpio 0 0 64>;
 		};
 
 		gpio_spi_bitbang: gpio at 10000064 {
-- 
2.19.2

[U-Boot] [PATCH v3 4/6] mips: luton: Enable use of serial gpio for LED

[Lars Povlsen]

This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'luton' SoC.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 board/mscc/luton/luton.c     | 6 ++++++
 configs/mscc_luton_defconfig | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
index b509b6beb3..807c717e33 100644
--- a/board/mscc/luton/luton.c
+++ b/board/mscc/luton/luton.c
@@ -5,6 +5,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +28,11 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
 	return 0;
 }
 
diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
index 03922f5379..0b3eb3865c 100644
--- a/configs/mscc_luton_defconfig
+++ b/configs/mscc_luton_defconfig
@@ -46,6 +46,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-- 
2.19.2

[U-Boot] [PATCH v3 5/6] mips: ocelot: DT: Enable use of serial gpio

[Lars Povlsen]

From: Lars Povlsen <lars.povlsen@microsemi.com>

This enables the use of the MSCC serial GPIO driver on the MSCC
VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and
pcb120 DT.

Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
---
 arch/mips/dts/mscc,ocelot.dtsi  | 23 ++++++++++
 arch/mips/dts/ocelot_pcb120.dts | 76 +++++++++++++++++++++++++++++++++
 arch/mips/dts/ocelot_pcb123.dts | 25 +++++++++++
 3 files changed, 124 insertions(+)

diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 87b4736285..2592003103 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -37,6 +37,12 @@
 		clock-frequency = <500000000>;
 	};
 
+	sys_clk: sys-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
+
 	ahb_clk: ahb-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -118,6 +124,11 @@
 			#gpio-cells = <2>;
 			gpio-ranges = <&gpio 0 0 22>;
 
+			sgpio_pins: sgpio-pins {
+				pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+				function = "sg0";
+			};
+
 			uart_pins: uart-pins {
 				pins = "GPIO_6", "GPIO_7";
 				function = "uart";
@@ -148,5 +159,17 @@
 				function = "si";
 			};
 		};
+
+		sgpio: gpio at 10700f8 {
+			compatible = "mscc,ocelot-sgpio";
+			status = "disabled";
+			clocks = <&sys_clk>;
+			pinctrl-0 = <&sgpio_pins>;
+			pinctrl-names = "default";
+			reg = <0x10700f8 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&sgpio 0 0 64>;
+		};
 	};
 };
diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
index 47d305a614..658719e684 100644
--- a/arch/mips/dts/ocelot_pcb120.dts
+++ b/arch/mips/dts/ocelot_pcb120.dts
@@ -9,4 +9,80 @@
 / {
 	model = "Ocelot PCB120 Reference Board";
 	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		poe_green {
+			label = "pcb120:green:poe";
+			gpios = <&sgpio 44 1>; /* p12.1 */
+			default-state = "off";
+		};
+
+		poe_red {
+			label = "pcb120:red:poe";
+			gpios = <&sgpio 12 1>; /* p12.0 */
+			default-state = "off";
+		};
+
+		alarm_green {
+			label = "pcb120:green:alarm";
+			gpios = <&sgpio 45 1>; /* p13.1 */
+			default-state = "off";
+		};
+
+		alarm_red {
+			label = "pcb120:red:alarm";
+			gpios = <&sgpio 13 1>; /* p13.0 */
+			default-state = "off";
+		};
+
+		dc_a_green {
+			label = "pcb120:green:dc_a";
+			gpios = <&sgpio 46 1>; /* p14.1 */
+			default-state = "off";
+		};
+
+		dc_a_red {
+			label = "pcb120:red:dc_a";
+			gpios = <&sgpio 14 1>; /* p14.0 */
+			default-state = "off";
+		};
+
+		dc_b_green {
+			label = "pcb120:green:dc_b";
+			gpios = <&sgpio 47 1>; /* p15.1 */
+			default-state = "off";
+		};
+
+		dc_b_red {
+			label = "pcb120:red:dc_b";
+			gpios = <&sgpio 15 1>; /* p15.0 */
+			default-state = "off";
+		};
+
+		status_green {
+			label = "pcb120:green:status";
+			gpios = <&sgpio 48 1>; /* p16.1 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb120:red:alarm";
+			gpios = <&sgpio 16 1>; /* p16.0 */
+			default-state = "off";
+		};
+
+	};
+
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0x000FFFFF>;
 };
+
diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
index 17d8d326ce..c4cb7a1194 100644
--- a/arch/mips/dts/ocelot_pcb123.dts
+++ b/arch/mips/dts/ocelot_pcb123.dts
@@ -9,4 +9,29 @@
 / {
 	model = "Ocelot PCB123 Reference Board";
 	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		status_green {
+			label = "pcb123:green:status";
+			gpios = <&sgpio 43 1>; /* p11.1 */
+			default-state = "on";
+		};
+
+		status_red {
+			label = "pcb123:red:status";
+			gpios = <&sgpio 11 1>; /* p11.0 */
+			default-state = "off";
+		};
+	};
+};
+
+&sgpio {
+	status = "okay";
+	mscc,sgpio-ports = <0x00FFFFFF>;
 };
-- 
2.19.2

[U-Boot] [PATCH v3 6/6] mips: ocelot: Enable use of serial gpio for LED

[Lars Povlsen]

This enables the use of the MSCC serial GPIO driver to control the
LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
 board/mscc/ocelot/ocelot.c    | 6 ++++++
 configs/mscc_ocelot_defconfig | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index a557cacd1b..a05c308669 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -9,6 +9,7 @@
 #include <asm/types.h>
 #include <environment.h>
 #include <spi.h>
+#include <led.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,6 +57,11 @@ int board_early_init_r(void)
 
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
 	return 0;
 }
 
diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index 66451000d9..fb6a5bdc31 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -48,6 +48,9 @@ CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_MTD=y
 CONFIG_MTD_SPI_NAND=y
+CONFIG_MSCC_SGPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
-- 
2.19.2

[U-Boot] [PATCH v3 0/6] mips: mscc: gpio: Add MSCC serial GPIO driver

[Daniel Schwierzeck]

Am 02.01.19 um 09:52 schrieb Lars Povlsen:
> This patch series add the GPIO device (SIO) in the MSCC VCoreIII-based
> SOCs, and enables it on the supported platforms.
> 
> By using a serial interface, the SIO controller significantly extends
> the number of available GPIOs with a minimum number of additional pins
> on the device. The primary purpose of the SIO controller is to connect
> control signals from SFP modules and to act as an LED controller.
> 
> This version address comments from Daniel Schwierzeck
> <daniel.schwierzeck@gmail.com> and Linus Walleij
> <linus.walleij@linaro.org>.
> 
> This is based off the u-boot-mips repository.
> 
> v3 changes:
>  - Fail driver load if clk_get_rate() fails
>  - Use dev_remap_addr() instead of map_physmem()
>  - Use dev_err instead of printf
>  - (DT doc) ngpios: Refer to gpio.txt
> 
> v2 changes:
>  - Extended the DT bindings documentation
>  - Eliminated the need for the "mscc,sgpio-bitcount" property.
>  - Using dev_read_u32_default() instead of fdtdec_get_int()
>  - Using map_physmem()
>  - Added MAINTAINERS entry for driver
> 
> Lars Povlsen (6):
>   mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
>   mips: mscc_sgpio: Add DT bindings documentation
>   mips: luton: DT: Enable use of serial gpio
>   mips: luton: Enable use of serial gpio for LED
>   mips: ocelot: DT: Enable use of serial gpio
>   mips: ocelot: Enable use of serial gpio for LED
> 
>  MAINTAINERS                                  |   1 +
>  arch/mips/dts/luton_pcb090.dts               |  21 ++
>  arch/mips/dts/luton_pcb091.dts               |  27 ++
>  arch/mips/dts/mscc,luton.dtsi                |  20 ++
>  arch/mips/dts/mscc,ocelot.dtsi               |  23 ++
>  arch/mips/dts/ocelot_pcb120.dts              |  76 +++++
>  arch/mips/dts/ocelot_pcb123.dts              |  25 ++
>  board/mscc/luton/luton.c                     |   6 +
>  board/mscc/ocelot/ocelot.c                   |   6 +
>  configs/mscc_luton_defconfig                 |   3 +
>  configs/mscc_ocelot_defconfig                |   3 +
>  doc/device-tree-bindings/gpio/mscc_sgpio.txt |  45 +++
>  drivers/gpio/Kconfig                         |  11 +
>  drivers/gpio/Makefile                        |   1 +
>  drivers/gpio/mscc_sgpio.c                    | 275 +++++++++++++++++++
>  15 files changed, 543 insertions(+)
>  create mode 100644 doc/device-tree-bindings/gpio/mscc_sgpio.txt
>  create mode 100644 drivers/gpio/mscc_sgpio.c
> 

series applied to u-boot-mips/next, thanks.

-- 
- Daniel