[linux dev-4.19 v1 0/4] dd NPCM7xx ADC patch to dev-4.19

[linux dev-4.19 v1 0/4] dd NPCM7xx ADC patch to dev-4.19

[Tomer Maimon]

Add NPCM7xx ADC patch to dev-4.19.

please add the NPCM7xx ADC patch set after adding 
the following patch set:
https://patchwork.ozlabs.org/cover/1014101/

Tomer Maimon (4):
  dt-binding: iio: add NPCM ADC documentation
  iio: adc: add NPCM ADC driver
  dts: npcm7xx: Modify NPCM7xx device tree
  arm: configs: add NPCM7xx ADC and MMIO configuration

 .../bindings/iio/adc/nuvoton,npcm-adc.txt          |  35 +++
 arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi      | 182 +++++++----
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts          | 157 +++++++---
 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi        |   4 +-
 arch/arm/boot/dts/nuvoton-npcm750.dtsi             |   1 +
 arch/arm/configs/npcm7xx_defconfig                 |   5 +
 drivers/iio/adc/Kconfig                            |  10 +
 drivers/iio/adc/Makefile                           |   1 +
 drivers/iio/adc/npcm_adc.c                         | 336 +++++++++++++++++++++
 9 files changed, 627 insertions(+), 104 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
 create mode 100644 drivers/iio/adc/npcm_adc.c

-- 
2.14.1

[linux dev-4.19 v1 1/4] dt-binding: iio: add NPCM ADC documentation

[Tomer Maimon]

Added device tree binding documentation for Nuvoton BMC
NPCM Analog-to-Digital Converter(ADC).

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 .../bindings/iio/adc/nuvoton,npcm-adc.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt

diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
new file mode 100644
index 000000000000..6f0843d837cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Analog to Digital Converter (ADC)
+
+The NPCM ADC is a 10-bit converter for eight channel inputs.
+
+Required properties:
+- compatible	: "nuvoton,npcm750-adc" for the NPCM7XX BMC.
+- reg			: specifies physical base address and size of the registers.
+- interrupts	: Contain the ADC interrupt with flags for falling edge.
+
+Optional properties:
+- clocks		: phandle of ADC reference clock, in case the clock is not
+				  added the ADC will use the default ADC sample rate.
+- vref-supply	: The regulator supply ADC reference voltage, in case the
+				  vref-supply is not added the ADC will use internal voltage
+				  reference.
+
+Required Node in the NPCM7xx BMC:
+An additional register is present in the NPCM7xx SOC which is
+assumed to be in the same device tree, with and marked as
+compatible with "nuvoton,npcm750-rst".
+
+Example:
+
+adc: adc@f000c000 {
+	compatible = "nuvoton,npcm750-adc";
+	reg = <0xf000c000 0x8>;
+	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clk NPCM7XX_CLK_ADC>;
+};
+
+rst: rst@f0801000 {
+	compatible = "nuvoton,npcm750-rst", "syscon",
+	"simple-mfd";
+	reg = <0xf0801000 0x6C>;
+};
-- 
2.14.1

[linux dev-4.19 v1 2/4] iio: adc: add NPCM ADC driver

[Tomer Maimon]

Add Nuvoton NPCM BMC Analog-to-Digital Converter(ADC) driver.

The NPCM ADC is a 10-bit converter for eight channel inputs.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/iio/adc/Kconfig    |  10 ++
 drivers/iio/adc/Makefile   |   1 +
 drivers/iio/adc/npcm_adc.c | 336 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 347 insertions(+)
 create mode 100644 drivers/iio/adc/npcm_adc.c

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 4a754921fb6f..c261e12bdc01 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -545,6 +545,16 @@ config NAU7802
 	  To compile this driver as a module, choose M here: the
 	  module will be called nau7802.
 
+config NPCM_ADC
+	tristate "Nuvoton NPCM ADC driver"
+	depends on ARCH_NPCM || COMPILE_TEST
+	depends on HAS_IOMEM
+	help
+	  Say yes here to build support for Nuvoton NPCM ADC.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called npcm_adc.
+
 config PALMAS_GPADC
 	tristate "TI Palmas General Purpose ADC"
 	depends on MFD_PALMAS
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 03db7b578f9c..68c7aa898c62 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
 obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
 obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o
 obj-$(CONFIG_NAU7802) += nau7802.o
+obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
 obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
 obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
 obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o
diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c
new file mode 100644
index 000000000000..4f7851472997
--- /dev/null
+++ b/drivers/iio/adc/npcm_adc.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2016-2018 Nuvoton Technology corporation.
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/io.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+
+struct npcm_adc {
+	u32 vref_mv;
+	bool int_status;
+	u32 adc_sample_hz;
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *adc_clk;
+	wait_queue_head_t wq;
+	struct regulator *vref;
+	struct regmap *rst_regmap;
+};
+
+/* NPCM7xx reset module */
+#define IPSRST1_OFFSET		0x020
+#define IPSRST1_ADC_RST		BIT(27)
+
+/* ADC registers */
+#define NPCM_ADCCON	 0x00
+#define NPCM_ADCDATA	 0x04
+
+/* ADCCON Register Bits */
+#define NPCM_ADCCON_ADC_INT_EN		BIT(21)
+#define NPCM_ADCCON_REFSEL		BIT(19)
+#define NPCM_ADCCON_ADC_INT_ST		BIT(18)
+#define NPCM_ADCCON_ADC_EN		BIT(17)
+#define NPCM_ADCCON_ADC_RST		BIT(16)
+#define NPCM_ADCCON_ADC_CONV		BIT(13)
+
+#define NPCM_ADCCON_CH_MASK		GENMASK(27, 24)
+#define NPCM_ADCCON_CH(x)		((x) << 24)
+#define NPCM_ADCCON_DIV_SHIFT		1
+#define NPCM_ADCCON_DIV_MASK		GENMASK(8, 1)
+#define NPCM_ADC_DATA_MASK(x)		((x) & GENMASK(9, 0))
+
+#define NPCM_ADC_ENABLE		(NPCM_ADCCON_ADC_EN | NPCM_ADCCON_ADC_INT_EN)
+
+/* ADC General Definition */
+#define NPCM_RESOLUTION_BITS		10
+#define ADC_DEFAULT_SAMPLE_RATE		12500000
+#define INT_VREF_MV			2000
+
+#define NPCM_ADC_CHAN(ch) {					\
+	.type = IIO_VOLTAGE,					\
+	.indexed = 1,						\
+	.channel = ch,						\
+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
+}
+
+static const struct iio_chan_spec npcm_adc_iio_channels[] = {
+	NPCM_ADC_CHAN(0),
+	NPCM_ADC_CHAN(1),
+	NPCM_ADC_CHAN(2),
+	NPCM_ADC_CHAN(3),
+	NPCM_ADC_CHAN(4),
+	NPCM_ADC_CHAN(5),
+	NPCM_ADC_CHAN(6),
+	NPCM_ADC_CHAN(7),
+};
+
+static irqreturn_t npcm_adc_isr(int irq, void *data)
+{
+	u32 regtemp = 0;
+	struct iio_dev *indio_dev = data;
+	struct npcm_adc *info = iio_priv(indio_dev);
+
+	regtemp = ioread32(info->regs + NPCM_ADCCON);
+	if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
+		iowrite32(regtemp, info->regs + NPCM_ADCCON);
+		wake_up_interruptible(&info->wq);
+		info->int_status = true;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
+{
+	int ret;
+	u32 regtemp = 0;
+
+	/* Select ADC channal */
+	regtemp = ioread32(info->regs + NPCM_ADCCON);
+	regtemp &= ~NPCM_ADCCON_CH_MASK;
+	iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
+		  NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
+
+	info->int_status = false;
+	ret = wait_event_interruptible_timeout(info->wq, info->int_status,
+					       msecs_to_jiffies(10));
+	if (ret == 0) {
+		regtemp = ioread32(info->regs + NPCM_ADCCON);
+		if ((regtemp & NPCM_ADCCON_ADC_CONV) && info->rst_regmap) {
+			/* if conversion failed - reset ADC module */
+			regmap_write(info->rst_regmap, IPSRST1_OFFSET,
+				     IPSRST1_ADC_RST);
+			msleep(100);
+			regmap_write(info->rst_regmap, IPSRST1_OFFSET, 0x0);
+			msleep(100);
+
+			/* Enable ADC and start conversion Module */
+			iowrite32(NPCM_ADC_ENABLE | NPCM_ADCCON_ADC_CONV,
+				  info->regs + NPCM_ADCCON);
+			dev_err(info->dev, "RESET ADC Complete\n");
+		}
+		return -ETIMEDOUT;
+	}
+	if (ret < 0)
+		return ret;
+
+	*val = NPCM_ADC_DATA_MASK(ioread32(info->regs + NPCM_ADCDATA));
+
+	return 0;
+}
+
+static int npcm_adc_read_raw(struct iio_dev *indio_dev,
+			     struct iio_chan_spec const *chan, int *val,
+			     int *val2, long mask)
+{
+	int ret;
+	struct npcm_adc *info = iio_priv(indio_dev);
+
+	switch (mask) {
+	case IIO_CHAN_INFO_RAW:
+		mutex_lock(&indio_dev->mlock);
+		ret = npcm_adc_read(info, val, chan->channel);
+		if (ret) {
+			dev_err(info->dev, "NPCM ADC read failed\n");
+			mutex_unlock(&indio_dev->mlock);
+			return ret;
+		}
+		mutex_unlock(&indio_dev->mlock);
+		return IIO_VAL_INT;
+	case IIO_CHAN_INFO_SCALE:
+		*val = info->vref_mv;
+		*val2 = NPCM_RESOLUTION_BITS;
+		return IIO_VAL_FRACTIONAL_LOG2;
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		*val = info->adc_sample_hz;
+		return IIO_VAL_INT;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct iio_info npcm_adc_iio_info = {
+	.read_raw = &npcm_adc_read_raw,
+};
+
+static const struct of_device_id npcm_adc_match[] = {
+	{ .compatible = "nuvoton,npcm750-adc", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, npcm_adc_match);
+
+static int npcm_adc_probe(struct platform_device *pdev)
+{
+	int ret;
+	int irq;
+	u32 div;
+	u32 reg_con;
+	struct resource *res;
+	struct npcm_adc *info;
+	struct iio_dev *indio_dev;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+
+	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
+	if (!indio_dev)
+		return -ENOMEM;
+	info = iio_priv(indio_dev);
+
+	info->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	info->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(info->regs))
+		return PTR_ERR(info->regs);
+
+	info->adc_clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(info->adc_clk)) {
+		dev_warn(&pdev->dev, "ADC clock failed: can't read clk, Assuming ADC clock Rate 12.5MHz\n");
+		info->adc_sample_hz = ADC_DEFAULT_SAMPLE_RATE;
+	} else {
+		/* calculate ADC clock sample rate */
+		reg_con = ioread32(info->regs + NPCM_ADCCON);
+		div = reg_con & NPCM_ADCCON_DIV_MASK;
+		div = div >> NPCM_ADCCON_DIV_SHIFT;
+		info->adc_sample_hz = clk_get_rate(info->adc_clk) /
+			((div + 1) * 2);
+	}
+
+	if (of_device_is_compatible(np, "nuvoton,npcm750-adc")) {
+		info->rst_regmap = syscon_regmap_lookup_by_compatible
+			("nuvoton,npcm750-rst");
+		if (IS_ERR(info->rst_regmap)) {
+			dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-rst\n");
+			ret = PTR_ERR(info->rst_regmap);
+			goto err_disable_clk;
+		}
+	}
+
+	reg_con = ioread32(info->regs + NPCM_ADCCON);
+	info->vref = devm_regulator_get_optional(&pdev->dev, "vref");
+	if (!IS_ERR(info->vref)) {
+		ret = regulator_enable(info->vref);
+		if (ret) {
+			dev_err(&pdev->dev, "Can't enable ADC reference voltage\n");
+			goto err_disable_clk;
+		}
+
+		ret = regulator_get_voltage(info->vref);
+		if (ret < 0)
+			goto err_disable_vref_reg;
+
+		info->vref_mv = ret / 1000;
+		iowrite32(reg_con & ~NPCM_ADCCON_REFSEL,
+			  info->regs + NPCM_ADCCON);
+	} else {
+		/* Any other error indicates that the regulator does exist */
+		if (PTR_ERR(info->vref) != -ENODEV) {
+			goto err_disable_clk;
+			return PTR_ERR(info->vref);
+		}
+
+		/* Use internal reference */
+		info->vref_mv = INT_VREF_MV;
+		iowrite32(reg_con | NPCM_ADCCON_REFSEL,
+			  info->regs + NPCM_ADCCON);
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq <= 0) {
+		dev_err(dev, "failed getting interrupt resource\n");
+		ret = -EINVAL;
+		goto err_disable_vref_reg;
+	}
+
+	ret = devm_request_irq(&pdev->dev, irq, npcm_adc_isr, 0,
+			       "NPCM_ADC", indio_dev);
+	if (ret < 0) {
+		dev_err(dev, "failed requesting interrupt\n");
+		goto err_disable_vref_reg;
+	}
+
+	init_waitqueue_head(&info->wq);
+
+	platform_set_drvdata(pdev, indio_dev);
+	indio_dev->name = dev_name(&pdev->dev);
+	indio_dev->dev.parent = &pdev->dev;
+	indio_dev->info = &npcm_adc_iio_info;
+	indio_dev->modes = INDIO_DIRECT_MODE;
+	indio_dev->channels = npcm_adc_iio_channels;
+	indio_dev->num_channels = ARRAY_SIZE(npcm_adc_iio_channels);
+
+	ret = iio_device_register(indio_dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Couldn't register the device.\n");
+		goto err_disable_vref_reg;
+	}
+
+	reg_con = ioread32(info->regs + NPCM_ADCCON);
+	reg_con |= NPCM_ADC_ENABLE;
+
+	/* Enable the ADC Module */
+	iowrite32(reg_con, info->regs + NPCM_ADCCON);
+
+	/* Start ADC conversion */
+	iowrite32(reg_con | NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON);
+
+	pr_info("NPCM ADC driver probed, sample Rate %dHz\n",
+		info->adc_sample_hz);
+
+	return 0;
+
+err_disable_vref_reg:
+	if (!IS_ERR(info->vref))
+		regulator_disable(info->vref);
+err_disable_clk:
+	clk_disable_unprepare(info->adc_clk);
+
+	return ret;
+}
+
+static int npcm_adc_remove(struct platform_device *pdev)
+{
+	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+	struct npcm_adc *info = iio_priv(indio_dev);
+	u32 regtemp = 0;
+
+	regtemp = ioread32(info->regs + NPCM_ADCCON);
+
+	/* Disable the ADC Module */
+	iowrite32(regtemp & ~NPCM_ADCCON_ADC_EN, info->regs + NPCM_ADCCON);
+
+	iio_device_unregister(indio_dev);
+	clk_disable_unprepare(info->adc_clk);
+	if (!IS_ERR(info->vref))
+		regulator_disable(info->vref);
+
+	return 0;
+}
+
+static struct platform_driver npcm_adc_driver = {
+	.probe		= npcm_adc_probe,
+	.remove		= npcm_adc_remove,
+	.driver		= {
+		.name	= "npcm_adc",
+		.of_match_table = npcm_adc_match,
+	},
+};
+
+module_platform_driver(npcm_adc_driver);
+
+MODULE_DESCRIPTION("Nuvoton NPCM ADC Sensor Driver");
+MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.14.1

[linux dev-4.19 v1 3/4] dts: npcm7xx: Modify NPCM7xx device tree

[Tomer Maimon]

Modify NPCM7xx device tree FIU, ADC, RST, VCD and SPI nodes
Add regulator and HGPIO pins nodes.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 182 +++++++++++++++++---------
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts     | 157 ++++++++++++++++------
 arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi   |   4 +-
 arch/arm/boot/dts/nuvoton-npcm750.dtsi        |   1 +
 4 files changed, 240 insertions(+), 104 deletions(-)

diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index afe0d3cb516d..73ec9649204b 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -5,6 +5,7 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <1>;
@@ -74,7 +75,7 @@
 		rst: rst@f0801000 {
 			compatible = "nuvoton,npcm750-rst", "syscon",
 			"simple-mfd";
-			reg = <0x801000 0x1000>;
+			reg = <0x801000 0x6C>;
 		};
 
 		scu: scu@3fe000 {
@@ -144,6 +145,7 @@
 			pinctrl-0 = <&r1_pins
 			             &r1err_pins
 				     &r1md_pins>;
+			status = "disabled";
 		};
 
 		ehci1:usb@f0806000 {
@@ -213,39 +215,39 @@
 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		spi0: spi@fb000000 {
-			compatible = "nuvoton,npcm750-spi";
+		fiu0: fiu@fb000000 {
+			compatible = "nuvoton,npcm750-fiu";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
 			reg-names = "control", "memory";
-			chip-max-address-map = <0x8000000>;
 			clocks = <&clk NPCM7XX_CLK_AHB>;
 			clock-names = "clk_ahb";
-			spi-nor@0 {
-					compatible = "jedec,spi-nor";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					reg = <0>;
-			};
+			status = "disabled";
 		};
-		spi3: spi@c0000000 {
-			compatible = "nuvoton,npcm750-spi";
+
+		fiu3: fiu@c0000000 {
+			compatible = "nuvoton,npcm750-fiu";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>;
 			reg-names = "control", "memory";
-			chip-max-address-map = <0x8000000>;
 			clocks = <&clk NPCM7XX_CLK_AHB>;
 			clock-names = "clk_ahb";
 			pinctrl-names = "default";
-			pinctrl-0 = <&spi3_pins &spi3quad_pins>;
-			spi-nor@0 {
-					compatible = "jedec,spi-nor";
-					#address-cells = <1>;
-					#size-cells = <1>;
-					reg = <0>;
-			};
+			pinctrl-0 = <&spi3_pins>;
+			status = "disabled";
+		};
+
+		fiux: fiu@fb001000 {
+			compatible = "nuvoton,npcm750-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfb001000 0x1000>, <0xf8000000 0x2000000>;
+			reg-names = "control", "memory";
+			clocks = <&clk NPCM7XX_CLK_AHB>;
+			clock-names = "clk_ahb";
+			status = "disabled";
 		};
 
 		pci_rc: axi-pcie@e1000000 {
@@ -271,17 +273,18 @@
 		vcd: vcd@f0810000 {
 			compatible = "nuvoton,npcm750-vcd";
 			reg = <0xf0810000 0x10000>;
-			phy-memory = <0x3e200000 0x600000>;
-			de-mode = /bits/ 8 <1>;
-			interrupts = <0 22 4>;
+			mem-addr = <0x3e200000>;
+			mem-size = <0x600000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
 		ece: ece@f0820000 {
 			compatible = "nuvoton,npcm750-ece";
 			reg = <0xf0820000 0x2000>;
-			phy-memory = <0x3e800000 0x600000>;
-			interrupts = <0 24 4>;
+			mem-addr = <0x3e800000>;
+			mem-size = <0x600000>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
@@ -352,13 +355,30 @@
 				};
 			};
 
-			pspi: pspi@0 {
+			spi0: spi@200000 {
+				compatible = "nuvoton,npcm750-pspi";
+				reg = <0x200000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi1_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM7XX_CLK_APB5>;
+				clock-names = "clk_apb5";
+				status = "disabled";
+			};
+
+			spi1: spi@201000 {
 				compatible = "nuvoton,npcm750-pspi";
-				reg = <0x200000 0x2000>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-						<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x201000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi2_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk NPCM7XX_CLK_APB5>;
 				clock-names = "clk_apb5";
+				status = "disabled";
 			};
 
 			timer0: timer@8000 {
@@ -438,10 +458,10 @@
 
 			adc: adc@c000 {
 				compatible = "nuvoton,npcm750-adc";
-				reg = <0xc000 0x1000>;
+				reg = <0xc000 0x8>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk NPCM7XX_CLK_ADC>;
-				clock-names = "clk_adc";
-				vref = <2048>;
+				status = "disabled";
 			};
 
 			otp:otp@189000 {
@@ -453,7 +473,7 @@
 				clock-names = "clk_apb4";
 			};
 
-			pwm_fan:pwm-fan-controller@103000 {	
+			pwm_fan:pwm-fan-controller@103000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "nuvoton,npcm750-pwm-fan";
@@ -487,9 +507,9 @@
 				status = "disabled";
 			};
 
-			i2c0: i2c-bus@80000 {
+			i2c0: i2c@80000 {
 				reg = <0x80000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
@@ -498,9 +518,9 @@
 				status = "disabled";
 			};
 
-			i2c1: i2c-bus@81000 {
+			i2c1: i2c@81000 {
 				reg = <0x81000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
@@ -509,9 +529,9 @@
 				status = "disabled";
 			};
 
-			i2c2: i2c-bus@82000 {
+			i2c2: i2c@82000 {
 				reg = <0x82000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
@@ -520,9 +540,9 @@
 				status = "disabled";
 			};
 
-			i2c3: i2c-bus@83000 {
+			i2c3: i2c@83000 {
 				reg = <0x83000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,9 +551,9 @@
 				status = "disabled";
 			};
 
-			i2c4: i2c-bus@84000 {
+			i2c4: i2c@84000 {
 				reg = <0x84000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -542,9 +562,9 @@
 				status = "disabled";
 			};
 
-			i2c5: i2c-bus@85000 {
+			i2c5: i2c@85000 {
 				reg = <0x85000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -553,9 +573,9 @@
 				status = "disabled";
 			};
 
-			i2c6: i2c-bus@86000 {
+			i2c6: i2c@86000 {
 				reg = <0x86000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -564,9 +584,9 @@
 				status = "disabled";
 			};
 
-			i2c7: i2c-bus@87000 {
+			i2c7: i2c@87000 {
 				reg = <0x87000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -575,9 +595,9 @@
 				status = "disabled";
 			};
 
-			i2c8: i2c-bus@88000 {
+			i2c8: i2c@88000 {
 				reg = <0x88000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -586,9 +606,9 @@
 				status = "disabled";
 			};
 
-			i2c9: i2c-bus@89000 {
+			i2c9: i2c@89000 {
 				reg = <0x89000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -597,9 +617,9 @@
 				status = "disabled";
 			};
 
-			i2c10: i2c-bus@8a000 {
+			i2c10: i2c@8a000 {
 				reg = <0x8a000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -608,9 +628,9 @@
 				status = "disabled";
 			};
 
-			i2c11: i2c-bus@8b000 {
+			i2c11: i2c@8b000 {
 				reg = <0x8b000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -619,9 +639,9 @@
 				status = "disabled";
 			};
 
-			i2c12: i2c-bus@8c000 {
+			i2c12: i2c@8c000 {
 				reg = <0x8c000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -630,9 +650,9 @@
 				status = "disabled";
 			};
 
-			i2c13: i2c-bus@8d000 {
+			i2c13: i2c@8d000 {
 				reg = <0x8d000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -641,9 +661,9 @@
 				status = "disabled";
 			};
 
-			i2c14: i2c-bus@8e000 {
+			i2c14: i2c@8e000 {
 				reg = <0x8e000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
@@ -652,9 +672,9 @@
 				status = "disabled";
 			};
 
-			i2c15: i2c-bus@8f000 {
+			i2c15: i2c@8f000 {
 				reg = <0x8f000 0x1000>;
-				compatible = "nuvoton,npcm750-i2c-bus";
+				compatible = "nuvoton,npcm750-i2c";
 				clocks = <&clk NPCM7XX_CLK_APB2>;
 				bus-frequency = <100000>;
 				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -1202,5 +1222,37 @@
 			groups = "clkreq";
 			function = "clkreq";
 		};
+		hgpio0_pins: hgpio0-pins {
+			groups = "hgpio0";
+			function = "hgpio0";
+		};
+		hgpio1_pins: hgpio1-pins {
+			groups = "hgpio1";
+			function = "hgpio1";
+		};
+		hgpio2_pins: hgpio2-pins {
+			groups = "hgpio2";
+			function = "hgpio2";
+		};
+		hgpio3_pins: hgpio3-pins {
+			groups = "hgpio3";
+			function = "hgpio3";
+		};
+		hgpio4_pins: hgpio4-pins {
+			groups = "hgpio4";
+			function = "hgpio4";
+		};
+		hgpio5_pins: hgpio5-pins {
+			groups = "hgpio5";
+			function = "hgpio5";
+		};
+		hgpio6_pins: hgpio6-pins {
+			groups = "hgpio6";
+			function = "hgpio6";
+		};
+		hgpio7_pins: hgpio7-pins {
+			groups = "hgpio7";
+			function = "hgpio7";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 8c568b380706..f135f9ba9b2b 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -46,6 +46,11 @@
 		i2c13 = &i2c13;
 		i2c14 = &i2c14;
 		i2c15 = &i2c15;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
 	};
 
 	chosen {
@@ -56,6 +61,27 @@
 		reg = <0 0x40000000>;
 	};
 
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_vref1_2: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vref_1_2v";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+		reg_vref3_3: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "vref_3_3v";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+
 	ahb {
 	        gmac0: eth@f0802000 {
 			phy-mode = "rgmii-id";
@@ -135,8 +161,14 @@
 			status = "okay";
 		};
 
-		spi0: spi@fb000000 {
+		fiu0: fiu@fb000000 {
+			status = "okay";
 			spi-nor@0 {
+				compatible = "jedec,spi-nor";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				spi-rx-bus-width = <2>;
+				reg = <0>;
 				partitions@80000000 {
 					compatible = "fixed-partitions";
 					#address-cells = <1>;
@@ -188,8 +220,15 @@
 			};
 		};
 
-		spi3: spi@c0000000 {
-				spi-nor@0 {
+		fiu3: fiu@c0000000 {
+			pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+			status = "okay";
+			spi-nor@0 {
+				compatible = "jedec,spi-nor";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				spi-rx-bus-width = <2>;
+				reg = <0>;
 				partitions@A0000000 {
 					compatible = "fixed-partitions";
 					#address-cells = <1>;
@@ -206,6 +245,17 @@
 			};
 		};
 
+		fiux: fiu@fb001000 {
+			status = "okay";
+			spix-mode;
+			spi-nor@0 {
+				compatible = "m25p80-nonjedec";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0>;
+			};
+		};
+
 		sdhci0: sdhci@f0842000 {
 			status = "okay";
 		};
@@ -252,6 +302,10 @@
 				status = "okay";
 			};
 
+			adc: adc@c000 {
+				status = "okay";
+			};
+
 			otp:otp@189000 {
 				status = "okay";
 			};
@@ -278,7 +332,7 @@
 			};
 
 			/* lm75 on SVB */
-			i2c0: i2c-bus@80000 {
+			i2c0: i2c@80000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
@@ -292,7 +346,7 @@
 			};
 
 			/* lm75 on EB */
-			i2c1: i2c-bus@81000 {
+			i2c1: i2c@81000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
@@ -306,7 +360,7 @@
 			};
 
 			/* tmp100 on EB */
-			i2c2: i2c-bus@82000 {
+			i2c2: i2c@82000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
@@ -320,7 +374,7 @@
 			};
 
 			/* tmp100 on SVB */
-			i2c6: i2c-bus@86000 {
+			i2c6: i2c@86000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
@@ -332,70 +386,70 @@
 					status = "okay";
 				};
 			};
-			i2c3: i2c-bus@83000 {
+			i2c3: i2c@83000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
 				status = "okay";
 			};
 
-			i2c4: i2c-bus@84000 {
+			i2c4: i2c@84000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
 				status = "disabled";
 			};
 
-			i2c5: i2c-bus@85000 {
+			i2c5: i2c@85000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c7: i2c-bus@87000 {
+			i2c7: i2c@87000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c8: i2c-bus@88000 {
+			i2c8: i2c@88000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c9: i2c-bus@89000 {
+			i2c9: i2c@89000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c10: i2c-bus@8a000 {
+			i2c10: i2c@8a000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c11: i2c-bus@8b000 {
+			i2c11: i2c@8b000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c14: i2c-bus@8e000 {
+			i2c14: i2c@8e000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
-				status = "disabled";
+				status = "okay";
 			};
 
-			i2c15: i2c-bus@8f000 {
+			i2c15: i2c@8f000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				bus-frequency = <100000>;
@@ -446,16 +500,45 @@
 				};
 			};
 
-			/* example for future pspi binding */
-			/*
-			pspi: pspi@0 {
-				pinctrl-names = "default";
-				pinctrl-0 = <&pspi1_pins &pspi2_pins 
-					&gpio20o_pins &gpio203o_pins>;
-				cs-gpios = <&gpio 20 1>, <&gpio 203 1>;
+			spi0: spi@200000 {
+				cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 				status = "okay";
+				Flash@0 {
+					compatible = "winbond,w25q128", "jedec,spi-nor";
+					reg = <0x0>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					spi-max-frequency = <5000000>;
+					partition@0 {
+						label = "spi_spare1";
+						reg = <0x0000000 0x800000>;
+					};
+					partition@1 {
+						label = "spi_spare2";
+						reg = <0x800000 0x0>;
+					};
+				};
+			};
+
+			spi1: spi@201000 {
+				cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+				status = "okay";
+				Flash@0 {
+					compatible = "winbond,w25q128fw", "jedec,spi-nor";
+					reg = <0x0>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					spi-max-frequency = <5000000>;
+					partition@0 {
+						label = "spi_spare1";
+						reg = <0x0000000 0x800000>;
+					};
+					partition@1 {
+						label = "spi_spare2";
+						reg = <0x800000 0x0>;
+					};
+				};
 			};
-			*/
 		};
 	};
 
@@ -480,7 +563,7 @@
 				&gpio82_pins
 				&gpio83_pins
 				&lpc_pins
-				&gpio132o_pins
+				&gpio132_pins
 				&gpio133_pins
 				&gpio134_pins
 				&gpio135_pins
@@ -514,10 +597,10 @@
 
 &gcr {
 	serial_port_mux: mux-controller {
-	compatible = "mmio-mux";
-	#mux-control-cells = <1>;
+		compatible = "mmio-mux";
+		#mux-control-cells = <1>;
 
-	mux-reg-masks = <0x38 0x07>;
-	idle-states = <2>; /* Serial port mode 3 (takeover) */
+		mux-reg-masks = <0x38 0x07>;
+		idle-states = <2>; /* Serial port mode 3 (takeover) */
 	};
 };
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi
index b9675fbce4e6..abe6a3402a59 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi
@@ -1107,10 +1107,10 @@
 			bias-disable;
 			input-enable;
 		};
-		gpio132o_pins: gpio132o-pins {
+		gpio132_pins: gpio132-pins {
 			pins = "GPIO132/SMB10SCL";
 			bias-disable;
-			output-high;
+			input-enable;
 		};
 		gpio133_pins: gpio133-pins {
 			pins = "GPIO133/SMB10SDA";
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 421a4ed54bad..4ce748f14763 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -73,6 +73,7 @@
 			pinctrl-0 = <&r2_pins
 			             &r2err_pins
 				     &r2md_pins>;
+			status = "disabled";
 		};
 
 		udc0:udc@f0830000 {
-- 
2.14.1

[linux dev-4.19 v1 4/4] arm: configs: add NPCM7xx ADC and MMIO configuration

[Tomer Maimon]

Add ADC and MMIO configuration to NPCM7xx (Poleg) BMC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 arch/arm/configs/npcm7xx_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/configs/npcm7xx_defconfig b/arch/arm/configs/npcm7xx_defconfig
index f3cefe303a21..15d345a8c99b 100644
--- a/arch/arm/configs/npcm7xx_defconfig
+++ b/arch/arm/configs/npcm7xx_defconfig
@@ -67,6 +67,8 @@ CONFIG_SENSORS_LM75=y
 CONFIG_SENSORS_NPCM7XX=y
 CONFIG_SENSORS_TMP102=y
 CONFIG_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_USB_HIDDEV=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -81,6 +83,9 @@ CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_IIO=y
+CONFIG_NPCM_ADC=y
+CONFIG_IIO_MUX=y
+CONFIG_MUX_MMIO=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-- 
2.14.1