* [PATCH 0/6] drm/i915: start splitting off runtime device info
@ 2018-12-31 14:56 Jani Nikula
2018-12-31 14:56 ` [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct Jani Nikula
` (10 more replies)
0 siblings, 11 replies; 26+ messages in thread
From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The mkwrite_device_info removal series [1] seems to have stalled. I'm
trying to nudge things forward a bit with this series. This isn't near
as complete as Tvrtko's work, but does some of the prep work I wanted,
specifically using INTEL_INFO() and RUNTIME_INFO() to access the
fields. There are obviously conflicts, but mostly I think this should
make the rest of Tvrtko's work easier, not harder.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/52381/
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Jani Nikula (6):
drm/i915: start moving runtime device info to a separate struct
drm/i915/reg: abstract display_mmio_offset access
drm/i915: pass dev_priv to intel_device_info_runtime_init()
drm/i915: always use INTEL_INFO() to access device info
drm/i915: drop intel_device_info_dump()
drm/i915: rename dev_priv info to __info to avoid usage
drivers/gpu/drm/i915/i915_debugfs.c | 26 +--
drivers/gpu/drm/i915/i915_drv.c | 26 +--
drivers/gpu/drm/i915/i915_drv.h | 104 ++++++-----
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 4 +-
drivers/gpu/drm/i915/i915_query.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 200 +++++++++++-----------
drivers/gpu/drm/i915/intel_device_info.c | 80 ++++-----
drivers/gpu/drm/i915/intel_device_info.h | 29 ++--
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_display.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 6 +-
drivers/gpu/drm/i915/intel_workarounds.c | 6 +-
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +-
21 files changed, 267 insertions(+), 270 deletions(-)
--
2.11.0
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^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 9:27 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access Jani Nikula ` (9 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula First move the low hanging fruit, the fields that are only initialized runtime. Use RUNTIME_INFO() exclusively to access the fields. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++----- drivers/gpu/drm/i915/i915_drv.c | 16 +++--- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++- drivers/gpu/drm/i915/i915_gpu_error.h | 1 + drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_query.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 60 +++++++++++------------ drivers/gpu/drm/i915/intel_device_info.h | 25 ++++++---- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_display.h | 6 +-- drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/intel_lrc.c | 14 +++--- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 4 +- drivers/gpu/drm/i915/intel_workarounds.c | 6 +-- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 6 +-- drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +- 20 files changed, 107 insertions(+), 94 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b89abbba4604..193823048f96 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data) seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); intel_device_info_dump_flags(info, &p); - intel_device_info_dump_runtime(info, &p); + intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); intel_driver_caps_print(&dev_priv->caps, &p); kernel_param_lock(THIS_MODULE); @@ -3157,7 +3157,7 @@ static int i915_engine_info(struct seq_file *m, void *unused) seq_printf(m, "Global active requests: %d\n", dev_priv->gt.active_requests); seq_printf(m, "CS timestamp frequency: %u kHz\n", - dev_priv->info.cs_timestamp_frequency_khz); + RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); p = drm_seq_file_printer(m); for_each_engine(engine, dev_priv, id) @@ -3173,7 +3173,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_printer p = drm_seq_file_printer(m); - intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p); + intel_device_info_dump_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); return 0; } @@ -4209,7 +4209,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { #define SS_MAX 6 - const struct intel_device_info *info = INTEL_INFO(dev_priv); + const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; int s, ss; @@ -4265,7 +4265,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { #define SS_MAX 3 - const struct intel_device_info *info = INTEL_INFO(dev_priv); + const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; int s, ss; @@ -4293,7 +4293,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, if (IS_GEN9_BC(dev_priv)) sseu->subslice_mask[s] = - INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; + RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; @@ -4327,10 +4327,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, if (sseu->slice_mask) { sseu->eu_per_subslice = - INTEL_INFO(dev_priv)->sseu.eu_per_subslice; + RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice; for (s = 0; s < fls(sseu->slice_mask); s++) { sseu->subslice_mask[s] = - INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; + RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; } sseu->eu_total = sseu->eu_per_subslice * sseu_subslice_total(sseu); @@ -4338,7 +4338,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, /* subtract fused off EU(s) from enabled slice(s) */ for (s = 0; s < fls(sseu->slice_mask); s++) { u8 subslice_7eu = - INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; + RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s]; sseu->eu_total -= hweight8(subslice_7eu); } @@ -4391,14 +4391,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused) return -ENODEV; seq_puts(m, "SSEU Device Info\n"); - i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); + i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu); seq_puts(m, "SSEU Device Status\n"); memset(&sseu, 0, sizeof(sseu)); - sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices; - sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices; + sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices; + sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices; sseu.max_eus_per_subslice = - INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice; + RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice; intel_runtime_pm_get(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index dcb935338c63..f884b9a138cd 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -358,12 +358,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = i915_cmd_parser_get_version(dev_priv); break; case I915_PARAM_SUBSLICE_TOTAL: - value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); + value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu); if (!value) return -ENODEV; break; case I915_PARAM_EU_TOTAL: - value = INTEL_INFO(dev_priv)->sseu.eu_total; + value = RUNTIME_INFO(dev_priv)->sseu.eu_total; if (!value) return -ENODEV; break; @@ -380,7 +380,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = HAS_POOLED_EU(dev_priv); break; case I915_PARAM_MIN_EU_IN_POOL: - value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; + value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool; break; case I915_PARAM_HUC_STATUS: value = intel_huc_check_status(&dev_priv->huc); @@ -430,17 +430,17 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = intel_engines_has_context_isolation(dev_priv); break; case I915_PARAM_SLICE_MASK: - value = INTEL_INFO(dev_priv)->sseu.slice_mask; + value = RUNTIME_INFO(dev_priv)->sseu.slice_mask; if (!value) return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: - value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0]; + value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]; if (!value) return -ENODEV; break; case I915_PARAM_CS_TIMESTAMP_FREQUENCY: - value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; + value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz; break; case I915_PARAM_MMAP_GTT_COHERENT: value = INTEL_INFO(dev_priv)->has_coherent_ggtt; @@ -1637,7 +1637,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) struct drm_printer p = drm_debug_printer("i915 device info:"); intel_device_info_dump(&dev_priv->info, &p); - intel_device_info_dump_runtime(&dev_priv->info, &p); + intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); } if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) @@ -1674,7 +1674,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) /* Setup the write-once "constant" device info */ device_info = mkwrite_device_info(i915); memcpy(device_info, match_info, sizeof(*device_info)); - device_info->device_id = pdev->device; + RUNTIME_INFO(i915)->device_id = pdev->device; BUILD_BUG_ON(INTEL_MAX_PLATFORMS > BITS_PER_TYPE(device_info->platform_mask)); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3053b0505dde..4534beeed6f9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1432,6 +1432,7 @@ struct drm_i915_private { struct kmem_cache *priorities; const struct intel_device_info info; + struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ struct intel_driver_caps caps; /** @@ -2198,10 +2199,11 @@ intel_info(const struct drm_i915_private *dev_priv) } #define INTEL_INFO(dev_priv) intel_info((dev_priv)) +#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) +#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) #define REVID_FOREVER 0xff #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 2bd7991ec9af..6238a06b6d4e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -594,13 +594,14 @@ static void print_error_obj(struct drm_i915_error_state_buf *m, static void err_print_capabilities(struct drm_i915_error_state_buf *m, const struct intel_device_info *info, + const struct intel_runtime_info *runtime, const struct intel_driver_caps *caps) { struct drm_printer p = i915_error_printer(m); intel_device_info_dump_flags(info, &p); intel_driver_caps_print(caps, &p); - intel_device_info_dump_topology(&info->sseu, &p); + intel_device_info_dump_topology(&runtime->sseu, &p); } static void err_print_params(struct drm_i915_error_state_buf *m, @@ -844,7 +845,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, if (error->display) intel_display_print_error_state(m, error->display); - err_print_capabilities(m, &error->device_info, &error->driver_caps); + err_print_capabilities(m, &error->device_info, &error->runtime_info, + &error->driver_caps); err_print_params(m, &error->params); err_print_uc(m, &error->uc); } @@ -1824,6 +1826,9 @@ static void capture_gen_state(struct i915_gpu_state *error) memcpy(&error->device_info, INTEL_INFO(i915), sizeof(error->device_info)); + memcpy(&error->runtime_info, + RUNTIME_INFO(i915), + sizeof(error->runtime_info)); error->driver_caps = i915->caps; } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index ff2652bbb0b0..6d9f45468ac1 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -45,6 +45,7 @@ struct i915_gpu_state { u32 reset_count; u32 suspend_count; struct intel_device_info device_info; + struct intel_runtime_info runtime_info; struct intel_driver_caps driver_caps; struct i915_params params; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 4288c0e02f0c..289b90065d27 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2646,7 +2646,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent) { return div64_u64(1000000000ULL * (2ULL << exponent), - 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz); + 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); } /** @@ -3471,7 +3471,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock); oa_sample_rate_hard_limit = 1000 * - (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); + (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); mutex_init(&dev_priv->perf.metrics_lock); diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 6fc4b8eeab42..95a343934cbd 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -13,7 +13,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) { - const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct drm_i915_query_topology_info topo; u32 slice_length, subslice_length, eu_length, total_length; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index a1dfb00aa16d..ffc5d75aa690 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -104,7 +104,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); } -void intel_device_info_dump_runtime(const struct intel_device_info *info, +void intel_device_info_dump_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { sseu_dump(&info->sseu, p); @@ -164,7 +164,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu) static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) { - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u8 s_en; u32 ss_en, ss_en_mask; u8 eu_en; @@ -203,7 +203,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) { - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; const u32 fuse2 = I915_READ(GEN8_FUSE2); int s, ss; const int eu_mask = 0xff; @@ -280,7 +280,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) { - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 fuse; fuse = I915_READ(CHV_FUSE_GT); @@ -334,7 +334,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); - struct sseu_dev_info *sseu = &info->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; int s, ss; u32 fuse2, eu_disable, subslice_mask; const u8 eu_mask = 0xff; @@ -437,7 +437,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) { - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; int s, ss; u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ @@ -519,8 +519,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) { - struct intel_device_info *info = mkwrite_device_info(dev_priv); - struct sseu_dev_info *sseu = &info->sseu; + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 fuse1; int s, ss; @@ -528,9 +527,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) * There isn't a register to tell us how many slices/subslices. We * work off the PCI-ids here. */ - switch (info->gt) { + switch (INTEL_INFO(dev_priv)->gt) { default: - MISSING_CASE(info->gt); + MISSING_CASE(INTEL_INFO(dev_priv)->gt); /* fall through */ case 1: sseu->slice_mask = BIT(0); @@ -743,25 +742,26 @@ void intel_device_info_runtime_init(struct intel_device_info *info) { struct drm_i915_private *dev_priv = container_of(info, struct drm_i915_private, info); + struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); enum pipe pipe; if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) - info->num_scalers[pipe] = 2; + runtime->num_scalers[pipe] = 2; } else if (IS_GEN(dev_priv, 9)) { - info->num_scalers[PIPE_A] = 2; - info->num_scalers[PIPE_B] = 2; - info->num_scalers[PIPE_C] = 1; + runtime->num_scalers[PIPE_A] = 2; + runtime->num_scalers[PIPE_B] = 2; + runtime->num_scalers[PIPE_C] = 1; } BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); if (IS_GEN(dev_priv, 11)) for_each_pipe(dev_priv, pipe) - info->num_sprites[pipe] = 6; + runtime->num_sprites[pipe] = 6; else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) for_each_pipe(dev_priv, pipe) - info->num_sprites[pipe] = 3; + runtime->num_sprites[pipe] = 3; else if (IS_BROXTON(dev_priv)) { /* * Skylake and Broxton currently don't expose the topmost plane as its @@ -772,15 +772,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info) * down the line. */ - info->num_sprites[PIPE_A] = 2; - info->num_sprites[PIPE_B] = 2; - info->num_sprites[PIPE_C] = 1; + runtime->num_sprites[PIPE_A] = 2; + runtime->num_sprites[PIPE_B] = 2; + runtime->num_sprites[PIPE_C] = 1; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { for_each_pipe(dev_priv, pipe) - info->num_sprites[pipe] = 2; + runtime->num_sprites[pipe] = 2; } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { for_each_pipe(dev_priv, pipe) - info->num_sprites[pipe] = 1; + runtime->num_sprites[pipe] = 1; } if (i915_modparams.disable_display) { @@ -864,7 +864,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) } /* Initialize command stream timestamp frequency */ - info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); + runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); } void intel_driver_caps_print(const struct intel_driver_caps *caps, @@ -893,16 +893,16 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); - info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; - info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> - GEN11_GT_VEBOX_DISABLE_SHIFT; + RUNTIME_INFO(dev_priv)->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; + RUNTIME_INFO(dev_priv)->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> + GEN11_GT_VEBOX_DISABLE_SHIFT; - DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable); + DRM_DEBUG_DRIVER("vdbox enable: %04x\n", RUNTIME_INFO(dev_priv)->vdbox_enable); for (i = 0; i < I915_MAX_VCS; i++) { if (!HAS_ENGINE(dev_priv, _VCS(i))) continue; - if (!(BIT(i) & info->vdbox_enable)) { + if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vdbox_enable)) { info->ring_mask &= ~ENGINE_MASK(_VCS(i)); DRM_DEBUG_DRIVER("vcs%u fused off\n", i); continue; @@ -913,15 +913,15 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) * hooked up to an SFC (Scaler & Format Converter) unit. */ if (logical_vdbox++ % 2 == 0) - info->vdbox_sfc_access |= BIT(i); + RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); } - DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable); + DRM_DEBUG_DRIVER("vebox enable: %04x\n", RUNTIME_INFO(dev_priv)->vebox_enable); for (i = 0; i < I915_MAX_VECS; i++) { if (!HAS_ENGINE(dev_priv, _VECS(i))) continue; - if (!(BIT(i) & info->vebox_enable)) { + if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vebox_enable)) { info->ring_mask &= ~ENGINE_MASK(_VECS(i)); DRM_DEBUG_DRIVER("vecs%u fused off\n", i); } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index dd34f974a857..fa81ee15dfa1 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -152,12 +152,10 @@ struct sseu_dev_info { typedef u8 intel_ring_mask_t; struct intel_device_info { - u16 device_id; u16 gen_mask; u8 gen; u8 gt; /* GT number, 0 if undefined */ - u8 num_rings; intel_ring_mask_t ring_mask; /* Rings supported by the HW */ enum intel_platform platform; @@ -169,8 +167,6 @@ struct intel_device_info { u32 display_mmio_offset; u8 num_pipes; - u8 num_sprites[I915_MAX_PIPES]; - u8 num_scalers[I915_MAX_PIPES]; #define DEFINE_FLAG(name) u8 name:1 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); @@ -189,6 +185,20 @@ struct intel_device_info { int trans_offsets[I915_MAX_TRANSCODERS]; int cursor_offsets[I915_MAX_PIPES]; + struct color_luts { + u16 degamma_lut_size; + u16 gamma_lut_size; + } color; +}; + +struct intel_runtime_info { + u16 device_id; + + u8 num_sprites[I915_MAX_PIPES]; + u8 num_scalers[I915_MAX_PIPES]; + + u8 num_rings; + /* Slice/subslice/EU info */ struct sseu_dev_info sseu; @@ -200,11 +210,6 @@ struct intel_device_info { /* Media engine access to SFC per instance */ u8 vdbox_sfc_access; - - struct color_luts { - u16 degamma_lut_size; - u16 gamma_lut_size; - } color; }; struct intel_driver_caps { @@ -266,7 +271,7 @@ void intel_device_info_dump(const struct intel_device_info *info, struct drm_printer *p); void intel_device_info_dump_flags(const struct intel_device_info *info, struct drm_printer *p); -void intel_device_info_dump_runtime(const struct intel_device_info *info, +void intel_device_info_dump_runtime(const struct intel_runtime_info *info, struct drm_printer *p); void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, struct drm_printer *p); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f0b480fba980..3df7db706d47 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14060,7 +14060,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); int i; - crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; + crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe]; if (!crtc->num_scalers) return; diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 4262452963b3..c7c068662288 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h @@ -121,7 +121,7 @@ enum i9xx_plane_id { }; #define plane_name(p) ((p) + 'A') -#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') +#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') /* * Per-pipe plane identifier. @@ -311,12 +311,12 @@ struct intel_link_m_n { #define for_each_universal_plane(__dev_priv, __pipe, __p) \ for ((__p) = 0; \ - (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ + (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ (__p)++) #define for_each_sprite(__dev_priv, __p, __s) \ for ((__s) = 0; \ - (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ + (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ (__s)++) #define for_each_port_masked(__port, __ports_mask) \ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 1462bb49f420..0200e5e20168 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -393,7 +393,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv) goto cleanup; } - device_info->num_rings = hweight32(mask); + RUNTIME_INFO(dev_priv)->num_rings = hweight32(mask); i915_check_and_clear_faults(dev_priv); @@ -783,7 +783,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) { - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 mcr_s_ss_select; u32 slice = fls(sseu->slice_mask); u32 subslice = fls(sseu->subslice_mask[slice]); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index ff08e5d600d4..6c98fb7cebf2 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2312,9 +2312,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) static u32 make_rpcs(struct drm_i915_private *dev_priv) { - bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg; - u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); - u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); + bool subslice_pg = RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg; + u8 slices = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); + u8 subslices = hweight8(RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]); u32 rpcs = 0; /* @@ -2362,7 +2362,7 @@ make_rpcs(struct drm_i915_private *dev_priv) * must make an explicit request through RPCS for full * enablement. */ - if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { + if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) { u32 mask, val = slices; if (INTEL_GEN(dev_priv) >= 11) { @@ -2390,17 +2390,17 @@ make_rpcs(struct drm_i915_private *dev_priv) rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; } - if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { + if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) { u32 val; - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice << + val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); val &= GEN8_RPCS_EU_MIN_MASK; rpcs |= val; - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice << + val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); val &= GEN8_RPCS_EU_MAX_MASK; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a6ffb8b975a..83b01cde8113 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7274,7 +7274,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); - switch (INTEL_INFO(dev_priv)->sseu.eu_total) { + switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) { case 8: /* (2 * 4) config */ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index fc1e29305951..87d3d3690d8a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1605,7 +1605,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) struct intel_engine_cs *engine = rq->engine; enum intel_engine_id id; const int num_rings = - IS_HSW_GT1(i915) ? INTEL_INFO(i915)->num_rings - 1 : 0; + IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_rings - 1 : 0; bool force_restore = false; int len; u32 *cs; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 32606d795af3..b6939856046d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -95,11 +95,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) #define instdone_slice_mask(dev_priv__) \ (IS_GEN(dev_priv__, 7) ? \ - 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) + 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) #define instdone_subslice_mask(dev_priv__) \ (IS_GEN(dev_priv__, 7) ? \ - 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) + 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ for ((slice__) = 0, (subslice__) = 0; \ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 5800f0ce2c57..e5e5c6e9ed28 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1934,7 +1934,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { - u8 vdbox_sfc_access = INTEL_INFO(dev_priv)->vdbox_sfc_access; + u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit; i915_reg_t sfc_usage; @@ -2002,7 +2002,7 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, static void gen11_unlock_sfc(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { - u8 vdbox_sfc_access = INTEL_INFO(dev_priv)->vdbox_sfc_access; + u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; i915_reg_t sfc_forced_lock; u32 sfc_forced_lock_bit; diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 7a8618065491..480c53a2ecb5 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -366,7 +366,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine) * Only consider slices where one, and only one, subslice has 7 * EUs */ - if (!is_power_of_2(INTEL_INFO(i915)->sseu.subslice_7eu[i])) + if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) continue; /* @@ -375,7 +375,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine) * * -> 0 <= ss <= 3; */ - ss = ffs(INTEL_INFO(i915)->sseu.subslice_7eu[i]) - 1; + ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; vals[i] = 3 - ss; } @@ -743,7 +743,7 @@ static void cfl_gt_workarounds_init(struct drm_i915_private *i915) static void wa_init_mcr(struct drm_i915_private *dev_priv) { - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct i915_wa_list *wal = &dev_priv->gt_wa_list; u32 mcr_slice_subslice_mask; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 7d82043aff10..d00cdf3c2939 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg) ncontexts++; } pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n", - ncontexts, INTEL_INFO(i915)->num_rings, ndwords); + ncontexts, RUNTIME_INFO(i915)->num_rings, ndwords); dw = 0; list_for_each_entry(obj, &objects, st_link) { @@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg) } } pr_info("Submitted %lu dwords (across %u engines)\n", - ndwords, INTEL_INFO(i915)->num_rings); + ndwords, RUNTIME_INFO(i915)->num_rings); dw = 0; list_for_each_entry(obj, &objects, st_link) { @@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg) count += this; } pr_info("Checked %lu scratch offsets across %d engines\n", - count, INTEL_INFO(i915)->num_rings); + count, RUNTIME_INFO(i915)->num_rings); out_rpm: intel_runtime_pm_put(i915); diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c index ca461e3a5f27..00caaa00f02f 100644 --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c @@ -522,7 +522,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n", count, flags, - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext); + RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext); return 0; } @@ -550,7 +550,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n", count, flags, - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext); + RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext); return 0; } -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct 2018-12-31 14:56 ` [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct Jani Nikula @ 2019-01-02 9:27 ` Tvrtko Ursulin 2019-01-02 10:21 ` Jani Nikula 0 siblings, 1 reply; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 9:27 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > First move the low hanging fruit, the fields that are only initialized > runtime. Use RUNTIME_INFO() exclusively to access the fields. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++----- > drivers/gpu/drm/i915/i915_drv.c | 16 +++--- > drivers/gpu/drm/i915/i915_drv.h | 4 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++- > drivers/gpu/drm/i915/i915_gpu_error.h | 1 + > drivers/gpu/drm/i915/i915_perf.c | 4 +- > drivers/gpu/drm/i915/i915_query.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 60 +++++++++++------------ > drivers/gpu/drm/i915/intel_device_info.h | 25 ++++++---- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_display.h | 6 +-- > drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/intel_lrc.c | 14 +++--- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > drivers/gpu/drm/i915/intel_uncore.c | 4 +- > drivers/gpu/drm/i915/intel_workarounds.c | 6 +-- > drivers/gpu/drm/i915/selftests/i915_gem_context.c | 6 +-- > drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +- > 20 files changed, 107 insertions(+), 94 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index b89abbba4604..193823048f96 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -48,7 +48,7 @@ static int i915_capabilities(struct seq_file *m, void *data) > seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); > > intel_device_info_dump_flags(info, &p); > - intel_device_info_dump_runtime(info, &p); > + intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); > intel_driver_caps_print(&dev_priv->caps, &p); > > kernel_param_lock(THIS_MODULE); > @@ -3157,7 +3157,7 @@ static int i915_engine_info(struct seq_file *m, void *unused) > seq_printf(m, "Global active requests: %d\n", > dev_priv->gt.active_requests); > seq_printf(m, "CS timestamp frequency: %u kHz\n", > - dev_priv->info.cs_timestamp_frequency_khz); > + RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); > > p = drm_seq_file_printer(m); > for_each_engine(engine, dev_priv, id) > @@ -3173,7 +3173,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > struct drm_printer p = drm_seq_file_printer(m); > > - intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p); > + intel_device_info_dump_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); > > return 0; > } > @@ -4209,7 +4209,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, > struct sseu_dev_info *sseu) > { > #define SS_MAX 6 > - const struct intel_device_info *info = INTEL_INFO(dev_priv); > + const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; > int s, ss; > > @@ -4265,7 +4265,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, > struct sseu_dev_info *sseu) > { > #define SS_MAX 3 > - const struct intel_device_info *info = INTEL_INFO(dev_priv); > + const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; > int s, ss; > > @@ -4293,7 +4293,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, > > if (IS_GEN9_BC(dev_priv)) > sseu->subslice_mask[s] = > - INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; > + RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; > > for (ss = 0; ss < info->sseu.max_subslices; ss++) { > unsigned int eu_cnt; > @@ -4327,10 +4327,10 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, > > if (sseu->slice_mask) { > sseu->eu_per_subslice = > - INTEL_INFO(dev_priv)->sseu.eu_per_subslice; > + RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice; > for (s = 0; s < fls(sseu->slice_mask); s++) { > sseu->subslice_mask[s] = > - INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; > + RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; > } > sseu->eu_total = sseu->eu_per_subslice * > sseu_subslice_total(sseu); > @@ -4338,7 +4338,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, > /* subtract fused off EU(s) from enabled slice(s) */ > for (s = 0; s < fls(sseu->slice_mask); s++) { > u8 subslice_7eu = > - INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; > + RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s]; > > sseu->eu_total -= hweight8(subslice_7eu); > } > @@ -4391,14 +4391,14 @@ static int i915_sseu_status(struct seq_file *m, void *unused) > return -ENODEV; > > seq_puts(m, "SSEU Device Info\n"); > - i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); > + i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu); > > seq_puts(m, "SSEU Device Status\n"); > memset(&sseu, 0, sizeof(sseu)); > - sseu.max_slices = INTEL_INFO(dev_priv)->sseu.max_slices; > - sseu.max_subslices = INTEL_INFO(dev_priv)->sseu.max_subslices; > + sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices; > + sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices; > sseu.max_eus_per_subslice = > - INTEL_INFO(dev_priv)->sseu.max_eus_per_subslice; > + RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice; > > intel_runtime_pm_get(dev_priv); > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index dcb935338c63..f884b9a138cd 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -358,12 +358,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, > value = i915_cmd_parser_get_version(dev_priv); > break; > case I915_PARAM_SUBSLICE_TOTAL: > - value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu); > + value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu); > if (!value) > return -ENODEV; > break; > case I915_PARAM_EU_TOTAL: > - value = INTEL_INFO(dev_priv)->sseu.eu_total; > + value = RUNTIME_INFO(dev_priv)->sseu.eu_total; > if (!value) > return -ENODEV; > break; > @@ -380,7 +380,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, > value = HAS_POOLED_EU(dev_priv); > break; > case I915_PARAM_MIN_EU_IN_POOL: > - value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool; > + value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool; > break; > case I915_PARAM_HUC_STATUS: > value = intel_huc_check_status(&dev_priv->huc); > @@ -430,17 +430,17 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, > value = intel_engines_has_context_isolation(dev_priv); > break; > case I915_PARAM_SLICE_MASK: > - value = INTEL_INFO(dev_priv)->sseu.slice_mask; > + value = RUNTIME_INFO(dev_priv)->sseu.slice_mask; > if (!value) > return -ENODEV; > break; > case I915_PARAM_SUBSLICE_MASK: > - value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0]; > + value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]; > if (!value) > return -ENODEV; > break; > case I915_PARAM_CS_TIMESTAMP_FREQUENCY: > - value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; > + value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz; > break; > case I915_PARAM_MMAP_GTT_COHERENT: > value = INTEL_INFO(dev_priv)->has_coherent_ggtt; > @@ -1637,7 +1637,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) > struct drm_printer p = drm_debug_printer("i915 device info:"); > > intel_device_info_dump(&dev_priv->info, &p); > - intel_device_info_dump_runtime(&dev_priv->info, &p); > + intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); > } > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) > @@ -1674,7 +1674,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) > /* Setup the write-once "constant" device info */ > device_info = mkwrite_device_info(i915); > memcpy(device_info, match_info, sizeof(*device_info)); > - device_info->device_id = pdev->device; > + RUNTIME_INFO(i915)->device_id = pdev->device; > > BUILD_BUG_ON(INTEL_MAX_PLATFORMS > > BITS_PER_TYPE(device_info->platform_mask)); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 3053b0505dde..4534beeed6f9 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1432,6 +1432,7 @@ struct drm_i915_private { > struct kmem_cache *priorities; > > const struct intel_device_info info; > + struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ > struct intel_driver_caps caps; > > /** > @@ -2198,10 +2199,11 @@ intel_info(const struct drm_i915_private *dev_priv) > } > > #define INTEL_INFO(dev_priv) intel_info((dev_priv)) > +#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) Do we want to keep the const trick like with INTEL_INFO in order to make accidental modifications harder? Argument is different there than with static info. > #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) > > #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) > -#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) > +#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) > > #define REVID_FOREVER 0xff > #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 2bd7991ec9af..6238a06b6d4e 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -594,13 +594,14 @@ static void print_error_obj(struct drm_i915_error_state_buf *m, > > static void err_print_capabilities(struct drm_i915_error_state_buf *m, > const struct intel_device_info *info, > + const struct intel_runtime_info *runtime, > const struct intel_driver_caps *caps) > { > struct drm_printer p = i915_error_printer(m); > > intel_device_info_dump_flags(info, &p); If I am not missing something here we now miss the runtime flags being dumped. A bit later: Ah ok, you haven't yet added any flags to runtime info in this patch. > intel_driver_caps_print(caps, &p); > - intel_device_info_dump_topology(&info->sseu, &p); > + intel_device_info_dump_topology(&runtime->sseu, &p); > } > > static void err_print_params(struct drm_i915_error_state_buf *m, > @@ -844,7 +845,8 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, > if (error->display) > intel_display_print_error_state(m, error->display); > > - err_print_capabilities(m, &error->device_info, &error->driver_caps); > + err_print_capabilities(m, &error->device_info, &error->runtime_info, > + &error->driver_caps); > err_print_params(m, &error->params); > err_print_uc(m, &error->uc); > } > @@ -1824,6 +1826,9 @@ static void capture_gen_state(struct i915_gpu_state *error) > memcpy(&error->device_info, > INTEL_INFO(i915), > sizeof(error->device_info)); > + memcpy(&error->runtime_info, > + RUNTIME_INFO(i915), > + sizeof(error->runtime_info)); > error->driver_caps = i915->caps; > } > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h > index ff2652bbb0b0..6d9f45468ac1 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.h > +++ b/drivers/gpu/drm/i915/i915_gpu_error.h > @@ -45,6 +45,7 @@ struct i915_gpu_state { > u32 reset_count; > u32 suspend_count; > struct intel_device_info device_info; > + struct intel_runtime_info runtime_info; > struct intel_driver_caps driver_caps; > struct i915_params params; > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 4288c0e02f0c..289b90065d27 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -2646,7 +2646,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, > static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent) > { > return div64_u64(1000000000ULL * (2ULL << exponent), > - 1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz); > + 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz); > } > > /** > @@ -3471,7 +3471,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock); > > oa_sample_rate_hard_limit = 1000 * > - (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); > + (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2); > dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); > > mutex_init(&dev_priv->perf.metrics_lock); > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > index 6fc4b8eeab42..95a343934cbd 100644 > --- a/drivers/gpu/drm/i915/i915_query.c > +++ b/drivers/gpu/drm/i915/i915_query.c > @@ -13,7 +13,7 @@ > static int query_topology_info(struct drm_i915_private *dev_priv, > struct drm_i915_query_item *query_item) > { > - const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > struct drm_i915_query_topology_info topo; > u32 slice_length, subslice_length, eu_length, total_length; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index a1dfb00aa16d..ffc5d75aa690 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -104,7 +104,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) > drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); > } > > -void intel_device_info_dump_runtime(const struct intel_device_info *info, > +void intel_device_info_dump_runtime(const struct intel_runtime_info *info, > struct drm_printer *p) > { > sseu_dump(&info->sseu, p); > @@ -164,7 +164,7 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu) > > static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > { > - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u8 s_en; > u32 ss_en, ss_en_mask; > u8 eu_en; > @@ -203,7 +203,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > > static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > { > - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > const u32 fuse2 = I915_READ(GEN8_FUSE2); > int s, ss; > const int eu_mask = 0xff; > @@ -280,7 +280,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > > static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > { > - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 fuse; > > fuse = I915_READ(CHV_FUSE_GT); > @@ -334,7 +334,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct intel_device_info *info = mkwrite_device_info(dev_priv); > - struct sseu_dev_info *sseu = &info->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > int s, ss; > u32 fuse2, eu_disable, subslice_mask; > const u8 eu_mask = 0xff; > @@ -437,7 +437,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > > static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > { > - struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > int s, ss; > u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ > > @@ -519,8 +519,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > > static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > { > - struct intel_device_info *info = mkwrite_device_info(dev_priv); > - struct sseu_dev_info *sseu = &info->sseu; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 fuse1; > int s, ss; > > @@ -528,9 +527,9 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > * There isn't a register to tell us how many slices/subslices. We > * work off the PCI-ids here. > */ > - switch (info->gt) { > + switch (INTEL_INFO(dev_priv)->gt) { > default: > - MISSING_CASE(info->gt); > + MISSING_CASE(INTEL_INFO(dev_priv)->gt); > /* fall through */ > case 1: > sseu->slice_mask = BIT(0); > @@ -743,25 +742,26 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > { > struct drm_i915_private *dev_priv = > container_of(info, struct drm_i915_private, info); > + struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); > enum pipe pipe; > > if (INTEL_GEN(dev_priv) >= 10) { > for_each_pipe(dev_priv, pipe) > - info->num_scalers[pipe] = 2; > + runtime->num_scalers[pipe] = 2; > } else if (IS_GEN(dev_priv, 9)) { > - info->num_scalers[PIPE_A] = 2; > - info->num_scalers[PIPE_B] = 2; > - info->num_scalers[PIPE_C] = 1; > + runtime->num_scalers[PIPE_A] = 2; > + runtime->num_scalers[PIPE_B] = 2; > + runtime->num_scalers[PIPE_C] = 1; > } > > BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); > > if (IS_GEN(dev_priv, 11)) > for_each_pipe(dev_priv, pipe) > - info->num_sprites[pipe] = 6; > + runtime->num_sprites[pipe] = 6; > else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) > for_each_pipe(dev_priv, pipe) > - info->num_sprites[pipe] = 3; > + runtime->num_sprites[pipe] = 3; > else if (IS_BROXTON(dev_priv)) { > /* > * Skylake and Broxton currently don't expose the topmost plane as its > @@ -772,15 +772,15 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > * down the line. > */ > > - info->num_sprites[PIPE_A] = 2; > - info->num_sprites[PIPE_B] = 2; > - info->num_sprites[PIPE_C] = 1; > + runtime->num_sprites[PIPE_A] = 2; > + runtime->num_sprites[PIPE_B] = 2; > + runtime->num_sprites[PIPE_C] = 1; > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > for_each_pipe(dev_priv, pipe) > - info->num_sprites[pipe] = 2; > + runtime->num_sprites[pipe] = 2; > } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { > for_each_pipe(dev_priv, pipe) > - info->num_sprites[pipe] = 1; > + runtime->num_sprites[pipe] = 1; > } > > if (i915_modparams.disable_display) { > @@ -864,7 +864,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > } > > /* Initialize command stream timestamp frequency */ > - info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); > + runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); > } > > void intel_driver_caps_print(const struct intel_driver_caps *caps, > @@ -893,16 +893,16 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > > media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); > > - info->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > - info->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> > - GEN11_GT_VEBOX_DISABLE_SHIFT; > + RUNTIME_INFO(dev_priv)->vdbox_enable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > + RUNTIME_INFO(dev_priv)->vebox_enable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> > + GEN11_GT_VEBOX_DISABLE_SHIFT; > > - DRM_DEBUG_DRIVER("vdbox enable: %04x\n", info->vdbox_enable); > + DRM_DEBUG_DRIVER("vdbox enable: %04x\n", RUNTIME_INFO(dev_priv)->vdbox_enable); > for (i = 0; i < I915_MAX_VCS; i++) { > if (!HAS_ENGINE(dev_priv, _VCS(i))) > continue; > > - if (!(BIT(i) & info->vdbox_enable)) { > + if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vdbox_enable)) { > info->ring_mask &= ~ENGINE_MASK(_VCS(i)); > DRM_DEBUG_DRIVER("vcs%u fused off\n", i); > continue; > @@ -913,15 +913,15 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > * hooked up to an SFC (Scaler & Format Converter) unit. > */ > if (logical_vdbox++ % 2 == 0) > - info->vdbox_sfc_access |= BIT(i); > + RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); > } > > - DRM_DEBUG_DRIVER("vebox enable: %04x\n", info->vebox_enable); > + DRM_DEBUG_DRIVER("vebox enable: %04x\n", RUNTIME_INFO(dev_priv)->vebox_enable); > for (i = 0; i < I915_MAX_VECS; i++) { > if (!HAS_ENGINE(dev_priv, _VECS(i))) > continue; > > - if (!(BIT(i) & info->vebox_enable)) { > + if (!(BIT(i) & RUNTIME_INFO(dev_priv)->vebox_enable)) { > info->ring_mask &= ~ENGINE_MASK(_VECS(i)); > DRM_DEBUG_DRIVER("vecs%u fused off\n", i); > } > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index dd34f974a857..fa81ee15dfa1 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -152,12 +152,10 @@ struct sseu_dev_info { > typedef u8 intel_ring_mask_t; > > struct intel_device_info { > - u16 device_id; > u16 gen_mask; > > u8 gen; > u8 gt; /* GT number, 0 if undefined */ > - u8 num_rings; > intel_ring_mask_t ring_mask; /* Rings supported by the HW */ > > enum intel_platform platform; > @@ -169,8 +167,6 @@ struct intel_device_info { > u32 display_mmio_offset; > > u8 num_pipes; > - u8 num_sprites[I915_MAX_PIPES]; > - u8 num_scalers[I915_MAX_PIPES]; > > #define DEFINE_FLAG(name) u8 name:1 > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); > @@ -189,6 +185,20 @@ struct intel_device_info { > int trans_offsets[I915_MAX_TRANSCODERS]; > int cursor_offsets[I915_MAX_PIPES]; > > + struct color_luts { > + u16 degamma_lut_size; > + u16 gamma_lut_size; > + } color; > +}; > + > +struct intel_runtime_info { > + u16 device_id; > + > + u8 num_sprites[I915_MAX_PIPES]; > + u8 num_scalers[I915_MAX_PIPES]; > + > + u8 num_rings; > + > /* Slice/subslice/EU info */ > struct sseu_dev_info sseu; > > @@ -200,11 +210,6 @@ struct intel_device_info { > > /* Media engine access to SFC per instance */ > u8 vdbox_sfc_access; > - > - struct color_luts { > - u16 degamma_lut_size; > - u16 gamma_lut_size; > - } color; > }; > > struct intel_driver_caps { > @@ -266,7 +271,7 @@ void intel_device_info_dump(const struct intel_device_info *info, > struct drm_printer *p); > void intel_device_info_dump_flags(const struct intel_device_info *info, > struct drm_printer *p); > -void intel_device_info_dump_runtime(const struct intel_device_info *info, > +void intel_device_info_dump_runtime(const struct intel_runtime_info *info, > struct drm_printer *p); > void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, > struct drm_printer *p); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f0b480fba980..3df7db706d47 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -14060,7 +14060,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > int i; > > - crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; > + crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe]; > if (!crtc->num_scalers) > return; > > diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h > index 4262452963b3..c7c068662288 100644 > --- a/drivers/gpu/drm/i915/intel_display.h > +++ b/drivers/gpu/drm/i915/intel_display.h > @@ -121,7 +121,7 @@ enum i9xx_plane_id { > }; > > #define plane_name(p) ((p) + 'A') > -#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') > +#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') > > /* > * Per-pipe plane identifier. > @@ -311,12 +311,12 @@ struct intel_link_m_n { > > #define for_each_universal_plane(__dev_priv, __pipe, __p) \ > for ((__p) = 0; \ > - (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ > + (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ > (__p)++) > > #define for_each_sprite(__dev_priv, __p, __s) \ > for ((__s) = 0; \ > - (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ > + (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ > (__s)++) > > #define for_each_port_masked(__port, __ports_mask) \ > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 1462bb49f420..0200e5e20168 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -393,7 +393,7 @@ int intel_engines_init_mmio(struct drm_i915_private *dev_priv) > goto cleanup; > } > > - device_info->num_rings = hweight32(mask); > + RUNTIME_INFO(dev_priv)->num_rings = hweight32(mask); > > i915_check_and_clear_faults(dev_priv); > > @@ -783,7 +783,7 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) > > u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) > { > - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 mcr_s_ss_select; > u32 slice = fls(sseu->slice_mask); > u32 subslice = fls(sseu->subslice_mask[slice]); > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index ff08e5d600d4..6c98fb7cebf2 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -2312,9 +2312,9 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) > static u32 > make_rpcs(struct drm_i915_private *dev_priv) > { > - bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg; > - u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); > - u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); > + bool subslice_pg = RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg; > + u8 slices = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); > + u8 subslices = hweight8(RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]); > u32 rpcs = 0; > > /* > @@ -2362,7 +2362,7 @@ make_rpcs(struct drm_i915_private *dev_priv) > * must make an explicit request through RPCS for full > * enablement. > */ > - if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { > + if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) { > u32 mask, val = slices; > > if (INTEL_GEN(dev_priv) >= 11) { > @@ -2390,17 +2390,17 @@ make_rpcs(struct drm_i915_private *dev_priv) > rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; > } > > - if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { > + if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) { > u32 val; > > - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice << > + val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << > GEN8_RPCS_EU_MIN_SHIFT; > GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); > val &= GEN8_RPCS_EU_MIN_MASK; > > rpcs |= val; > > - val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice << > + val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << > GEN8_RPCS_EU_MAX_SHIFT; > GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); > val &= GEN8_RPCS_EU_MAX_MASK; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2a6ffb8b975a..83b01cde8113 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7274,7 +7274,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) > > val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); > > - switch (INTEL_INFO(dev_priv)->sseu.eu_total) { > + switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) { > case 8: > /* (2 * 4) config */ > rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index fc1e29305951..87d3d3690d8a 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1605,7 +1605,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > struct intel_engine_cs *engine = rq->engine; > enum intel_engine_id id; > const int num_rings = > - IS_HSW_GT1(i915) ? INTEL_INFO(i915)->num_rings - 1 : 0; > + IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_rings - 1 : 0; > bool force_restore = false; > int len; > u32 *cs; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 32606d795af3..b6939856046d 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -95,11 +95,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) > > #define instdone_slice_mask(dev_priv__) \ > (IS_GEN(dev_priv__, 7) ? \ > - 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) > + 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) > > #define instdone_subslice_mask(dev_priv__) \ > (IS_GEN(dev_priv__, 7) ? \ > - 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) > + 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) > > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ > for ((slice__) = 0, (subslice__) = 0; \ > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 5800f0ce2c57..e5e5c6e9ed28 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1934,7 +1934,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, > static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, > struct intel_engine_cs *engine) > { > - u8 vdbox_sfc_access = INTEL_INFO(dev_priv)->vdbox_sfc_access; > + u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; > i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; > u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit; > i915_reg_t sfc_usage; > @@ -2002,7 +2002,7 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv, > static void gen11_unlock_sfc(struct drm_i915_private *dev_priv, > struct intel_engine_cs *engine) > { > - u8 vdbox_sfc_access = INTEL_INFO(dev_priv)->vdbox_sfc_access; > + u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; > i915_reg_t sfc_forced_lock; > u32 sfc_forced_lock_bit; > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index 7a8618065491..480c53a2ecb5 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -366,7 +366,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine) > * Only consider slices where one, and only one, subslice has 7 > * EUs > */ > - if (!is_power_of_2(INTEL_INFO(i915)->sseu.subslice_7eu[i])) > + if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) > continue; > > /* > @@ -375,7 +375,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine) > * > * -> 0 <= ss <= 3; > */ > - ss = ffs(INTEL_INFO(i915)->sseu.subslice_7eu[i]) - 1; > + ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; > vals[i] = 3 - ss; > } > > @@ -743,7 +743,7 @@ static void cfl_gt_workarounds_init(struct drm_i915_private *i915) > > static void wa_init_mcr(struct drm_i915_private *dev_priv) > { > - const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > struct i915_wa_list *wal = &dev_priv->gt_wa_list; > u32 mcr_slice_subslice_mask; > > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > index 7d82043aff10..d00cdf3c2939 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > @@ -627,7 +627,7 @@ static int igt_ctx_exec(void *arg) > ncontexts++; > } > pr_info("Submitted %lu contexts (across %u engines), filling %lu dwords\n", > - ncontexts, INTEL_INFO(i915)->num_rings, ndwords); > + ncontexts, RUNTIME_INFO(i915)->num_rings, ndwords); > > dw = 0; > list_for_each_entry(obj, &objects, st_link) { > @@ -732,7 +732,7 @@ static int igt_ctx_readonly(void *arg) > } > } > pr_info("Submitted %lu dwords (across %u engines)\n", > - ndwords, INTEL_INFO(i915)->num_rings); > + ndwords, RUNTIME_INFO(i915)->num_rings); > > dw = 0; > list_for_each_entry(obj, &objects, st_link) { > @@ -1064,7 +1064,7 @@ static int igt_vm_isolation(void *arg) > count += this; > } > pr_info("Checked %lu scratch offsets across %d engines\n", > - count, INTEL_INFO(i915)->num_rings); > + count, RUNTIME_INFO(i915)->num_rings); > > out_rpm: > intel_runtime_pm_put(i915); > diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c > index ca461e3a5f27..00caaa00f02f 100644 > --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c > +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c > @@ -522,7 +522,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) > > pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n", > count, flags, > - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext); > + RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext); > return 0; > } > > @@ -550,7 +550,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) > > pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n", > count, flags, > - INTEL_INFO(smoke->i915)->num_rings, smoke->ncontext); > + RUNTIME_INFO(smoke->i915)->num_rings, smoke->ncontext); > return 0; > } > > Looks okay to me. The only thing which worries me is that one day we end up with too little in static vs runtime and decide having two separate sources of info is only a hassle. (Like if the DCE/LTO path either does not happen, or ends up not needing this completely.) I suppose it is worth exploring and we can always go back easily if all else fails. I at least want to have another go at the subplatform/devid centralization. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct 2019-01-02 9:27 ` Tvrtko Ursulin @ 2019-01-02 10:21 ` Jani Nikula 0 siblings, 0 replies; 26+ messages in thread From: Jani Nikula @ 2019-01-02 10:21 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 31/12/2018 14:56, Jani Nikula wrote: >> @@ -2198,10 +2199,11 @@ intel_info(const struct drm_i915_private *dev_priv) >> } >> >> #define INTEL_INFO(dev_priv) intel_info((dev_priv)) >> +#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) > > Do we want to keep the const trick like with INTEL_INFO in order to make > accidental modifications harder? Argument is different there than with > static info. I did think about it, but I don't want to repeat mkwrite_device_info(). I understand we have three classes of data: 1) immutable 2) immutable after one-time runtime init 3) mutable Currently we mix all of them, the intention here is to split out 1 from 2&3, the latter two remaining conflated. I'd like to see how this pans out before worrying about the difference between 2&3. >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c >> index 2bd7991ec9af..6238a06b6d4e 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >> @@ -594,13 +594,14 @@ static void print_error_obj(struct drm_i915_error_state_buf *m, >> >> static void err_print_capabilities(struct drm_i915_error_state_buf *m, >> const struct intel_device_info *info, >> + const struct intel_runtime_info *runtime, >> const struct intel_driver_caps *caps) >> { >> struct drm_printer p = i915_error_printer(m); >> >> intel_device_info_dump_flags(info, &p); > > If I am not missing something here we now miss the runtime flags being > dumped. > > A bit later: Ah ok, you haven't yet added any flags to runtime info in > this patch. *grin* Like I said, not as complete as your series. > Looks okay to me. > > The only thing which worries me is that one day we end up with too > little in static vs runtime and decide having two separate sources of > info is only a hassle. (Like if the DCE/LTO path either does not happen, > or ends up not needing this completely.) > > I suppose it is worth exploring and we can always go back easily if all > else fails. I at least want to have another go at the subplatform/devid > centralization. > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula 2018-12-31 14:56 ` [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 9:37 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() Jani Nikula ` (8 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Add a macro wrapper for display_mmio_offset access in register definitions. Prep work for reducing direct dev_priv->info usage. No functional changes. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 188 ++++++++++++++++++++-------------------- 1 file changed, 95 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 02af9b5add34..de1c9d495808 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -139,6 +139,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); } +#define VLV_DISPLAY_BASE 0x180000 +#define VLV_MIPI_BASE VLV_DISPLAY_BASE +#define BXT_MIPI_BASE 0x60000 + +#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) + /* * Given the first two numbers __a and __b of arbitrarily many evenly spaced * numbers, pick the 0-based __index'th value. @@ -181,13 +187,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) */ #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ - dev_priv->info.display_mmio_offset) + DISPLAY_MMIO_BASE(dev_priv)) #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ - dev_priv->info.display_mmio_offset) + DISPLAY_MMIO_BASE(dev_priv)) #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ - dev_priv->info.display_mmio_offset) + DISPLAY_MMIO_BASE(dev_priv)) #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ @@ -2614,10 +2620,6 @@ enum i915_power_well_id { #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) -#define VLV_DISPLAY_BASE 0x180000 -#define VLV_MIPI_BASE VLV_DISPLAY_BASE -#define BXT_MIPI_BASE 0x60000 - #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) #define SCPD0 _MMIO(0x209c) /* 915+ only */ @@ -3174,9 +3176,9 @@ enum i915_power_well_id { /* * Clock control & power management */ -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) +#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) +#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) +#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) #define VGA0 _MMIO(0x6000) @@ -3273,9 +3275,9 @@ enum i915_power_well_id { #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) +#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) +#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) +#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) /* @@ -3347,7 +3349,7 @@ enum i915_power_well_id { #define DSTATE_PLL_D3_OFF (1 << 3) #define DSTATE_GFX_CLOCK_GATING (1 << 1) #define DSTATE_DOT_CLOCK_GATING (1 << 0) -#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) +#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ @@ -3487,7 +3489,7 @@ enum i915_power_well_id { #define _PALETTE_A 0xa000 #define _PALETTE_B 0xa800 #define _CHV_PALETTE_C 0xc000 -#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \ +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ _PICK((pipe), _PALETTE_A, \ _PALETTE_B, _CHV_PALETTE_C) + \ (i) * 4) @@ -4320,7 +4322,7 @@ enum { /* Hotplug control (945+ only) */ -#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) +#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) #define PORTB_HOTPLUG_INT_EN (1 << 29) #define PORTC_HOTPLUG_INT_EN (1 << 28) #define PORTD_HOTPLUG_INT_EN (1 << 27) @@ -4350,7 +4352,7 @@ enum { #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) -#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) +#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) /* * HDMI/DP bits are g4x+ * @@ -4432,7 +4434,7 @@ enum { #define PORT_DFT_I9XX _MMIO(0x61150) #define DC_BALANCE_RESET (1 << 25) -#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) +#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) #define DC_BALANCE_RESET_VLV (1 << 31) #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ @@ -4717,7 +4719,7 @@ enum { #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 /* Panel fitting */ -#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) +#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) #define PFIT_ENABLE (1 << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 @@ -4735,7 +4737,7 @@ enum { #define PFIT_SCALING_PROGRAMMED (1 << 26) #define PFIT_SCALING_PILLAR (2 << 26) #define PFIT_SCALING_LETTER (3 << 26) -#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) +#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) /* Pre-965 */ #define PFIT_VERT_SCALE_SHIFT 20 #define PFIT_VERT_SCALE_MASK 0xfff00000 @@ -4747,25 +4749,25 @@ enum { #define PFIT_HORIZ_SCALE_SHIFT_965 0 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff -#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) +#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) +#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) +#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ _VLV_BLC_PWM_CTL2_B) -#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) -#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) +#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) +#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ _VLV_BLC_PWM_CTL_B) -#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) -#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) +#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) +#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ _VLV_BLC_HIST_CTL_B) /* Backlight control */ -#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ +#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ #define BLM_PWM_ENABLE (1 << 31) #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ #define BLM_PIPE_SELECT (1 << 29) @@ -4788,7 +4790,7 @@ enum { #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) #define BLM_PHASE_IN_INCR_SHIFT (0) #define BLM_PHASE_IN_INCR_MASK (0xff << 0) -#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) +#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. @@ -4810,7 +4812,7 @@ enum { #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ -#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) +#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) #define BLM_HISTOGRAM_ENABLE (1 << 31) /* New registers for PCH-split platforms. Safe where new bits show up, the @@ -5434,47 +5436,47 @@ enum { * is 20 bytes in each direction, hence the 5 fixed * data registers */ -#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) -#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) -#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) -#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) -#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) -#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) - -#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) -#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) -#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) -#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) -#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) -#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) - -#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) -#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) -#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) -#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) -#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) -#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) - -#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) -#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) -#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) -#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) -#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) -#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) - -#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410) -#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414) -#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418) -#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c) -#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420) -#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424) - -#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510) -#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514) -#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518) -#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c) -#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520) -#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524) +#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) +#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) +#define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) +#define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) +#define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) +#define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) + +#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) +#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) +#define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) +#define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) +#define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) +#define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) + +#define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) +#define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) +#define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) +#define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) +#define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) +#define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) + +#define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) +#define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) +#define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) +#define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) +#define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) +#define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) + +#define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) +#define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) +#define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) +#define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) +#define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) +#define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) + +#define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) +#define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) +#define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) +#define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) +#define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) +#define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ @@ -5750,7 +5752,7 @@ enum { #define DPINVGTT_STATUS_MASK 0xff #define DPINVGTT_STATUS_MASK_CHV 0xfff -#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) +#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) #define DSPARB_CSTART_MASK (0x7f << 7) #define DSPARB_CSTART_SHIFT 7 #define DSPARB_BSTART_MASK (0x7f) @@ -5785,7 +5787,7 @@ enum { #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) /* pnv/gen4/g4x/vlv/chv */ -#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) +#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) #define DSPFW_SR_SHIFT 23 #define DSPFW_SR_MASK (0x1ff << 23) #define DSPFW_CURSORB_SHIFT 16 @@ -5796,7 +5798,7 @@ enum { #define DSPFW_PLANEA_SHIFT 0 #define DSPFW_PLANEA_MASK (0x7f << 0) #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ -#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) +#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ #define DSPFW_FBC_SR_SHIFT 28 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ @@ -5812,7 +5814,7 @@ enum { #define DSPFW_SPRITEA_SHIFT 0 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ -#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) +#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) #define DSPFW_HPLL_SR_EN (1 << 31) #define PINEVIEW_SELF_REFRESH_EN (1 << 30) #define DSPFW_CURSOR_SR_SHIFT 24 @@ -6228,35 +6230,35 @@ enum { * [10:1f] all * [30:32] all */ -#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) -#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) -#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) +#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) +#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) +#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) /* Pipe B */ -#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) -#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) -#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) +#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) +#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) +#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) #define _PIPEBFRAMEHIGH 0x71040 #define _PIPEBFRAMEPIXEL 0x71044 -#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) -#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) +#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) +#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) /* Display B control */ -#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) +#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) #define DISPPLANE_ALPHA_TRANS_DISABLE 0 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) -#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) -#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) -#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) -#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) -#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) -#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) -#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) +#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) +#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) +#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) +#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) +#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) +#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) +#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) +#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) /* ICL DSI 0 and 1 */ #define _PIPEDSI0CONF 0x7b008 @@ -8808,7 +8810,7 @@ enum { #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) /* Audio */ -#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) +#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) #define INTEL_AUDIO_DEVCL 0x808629FB #define INTEL_AUDIO_DEVBLC 0x80862801 #define INTEL_AUDIO_DEVCTG 0x80862802 -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access 2018-12-31 14:56 ` [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access Jani Nikula @ 2019-01-02 9:37 ` Tvrtko Ursulin 0 siblings, 0 replies; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 9:37 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > Add a macro wrapper for display_mmio_offset access in register > definitions. Prep work for reducing direct dev_priv->info usage. No > functional changes. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 188 ++++++++++++++++++++-------------------- > 1 file changed, 95 insertions(+), 93 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 02af9b5add34..de1c9d495808 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -139,6 +139,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); > } > > +#define VLV_DISPLAY_BASE 0x180000 > +#define VLV_MIPI_BASE VLV_DISPLAY_BASE > +#define BXT_MIPI_BASE 0x60000 > + > +#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) > + > /* > * Given the first two numbers __a and __b of arbitrarily many evenly spaced > * numbers, pick the 0-based __index'th value. > @@ -181,13 +187,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > */ > #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ > dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ > - dev_priv->info.display_mmio_offset) > + DISPLAY_MMIO_BASE(dev_priv)) > #define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ > dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ > - dev_priv->info.display_mmio_offset) > + DISPLAY_MMIO_BASE(dev_priv)) > #define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ > dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ > - dev_priv->info.display_mmio_offset) > + DISPLAY_MMIO_BASE(dev_priv)) > > #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) > #define _MASKED_FIELD(mask, value) ({ \ > @@ -2614,10 +2620,6 @@ enum i915_power_well_id { > > #define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) > > -#define VLV_DISPLAY_BASE 0x180000 > -#define VLV_MIPI_BASE VLV_DISPLAY_BASE > -#define BXT_MIPI_BASE 0x60000 > - > #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) > #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) > #define SCPD0 _MMIO(0x209c) /* 915+ only */ > @@ -3174,9 +3176,9 @@ enum i915_power_well_id { > /* > * Clock control & power management > */ > -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) > -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) > -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) > +#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) > +#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) > +#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) > #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) > > #define VGA0 _MMIO(0x6000) > @@ -3273,9 +3275,9 @@ enum i915_power_well_id { > #define SDVO_MULTIPLIER_SHIFT_HIRES 4 > #define SDVO_MULTIPLIER_SHIFT_VGA 0 > > -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) > -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) > -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) > +#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) > +#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) > +#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) > #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) > > /* > @@ -3347,7 +3349,7 @@ enum i915_power_well_id { > #define DSTATE_PLL_D3_OFF (1 << 3) > #define DSTATE_GFX_CLOCK_GATING (1 << 1) > #define DSTATE_DOT_CLOCK_GATING (1 << 0) > -#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200) > +#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ > @@ -3487,7 +3489,7 @@ enum i915_power_well_id { > #define _PALETTE_A 0xa000 > #define _PALETTE_B 0xa800 > #define _CHV_PALETTE_C 0xc000 > -#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \ > +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ > _PICK((pipe), _PALETTE_A, \ > _PALETTE_B, _CHV_PALETTE_C) + \ > (i) * 4) > @@ -4320,7 +4322,7 @@ enum { > > > /* Hotplug control (945+ only) */ > -#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110) > +#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) > #define PORTB_HOTPLUG_INT_EN (1 << 29) > #define PORTC_HOTPLUG_INT_EN (1 << 28) > #define PORTD_HOTPLUG_INT_EN (1 << 27) > @@ -4350,7 +4352,7 @@ enum { > #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) > #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) > > -#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114) > +#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) > /* > * HDMI/DP bits are g4x+ > * > @@ -4432,7 +4434,7 @@ enum { > > #define PORT_DFT_I9XX _MMIO(0x61150) > #define DC_BALANCE_RESET (1 << 25) > -#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154) > +#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) > #define DC_BALANCE_RESET_VLV (1 << 31) > #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) > #define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ > @@ -4717,7 +4719,7 @@ enum { > #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 > > /* Panel fitting */ > -#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230) > +#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) > #define PFIT_ENABLE (1 << 31) > #define PFIT_PIPE_MASK (3 << 29) > #define PFIT_PIPE_SHIFT 29 > @@ -4735,7 +4737,7 @@ enum { > #define PFIT_SCALING_PROGRAMMED (1 << 26) > #define PFIT_SCALING_PILLAR (2 << 26) > #define PFIT_SCALING_LETTER (3 << 26) > -#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234) > +#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) > /* Pre-965 */ > #define PFIT_VERT_SCALE_SHIFT 20 > #define PFIT_VERT_SCALE_MASK 0xfff00000 > @@ -4747,25 +4749,25 @@ enum { > #define PFIT_HORIZ_SCALE_SHIFT_965 0 > #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff > > -#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238) > +#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) > > -#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) > -#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) > +#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) > +#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) > #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ > _VLV_BLC_PWM_CTL2_B) > > -#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) > -#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) > +#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) > +#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) > #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ > _VLV_BLC_PWM_CTL_B) > > -#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) > -#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) > +#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) > +#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) > #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ > _VLV_BLC_HIST_CTL_B) > > /* Backlight control */ > -#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ > +#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ > #define BLM_PWM_ENABLE (1 << 31) > #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ > #define BLM_PIPE_SELECT (1 << 29) > @@ -4788,7 +4790,7 @@ enum { > #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) > #define BLM_PHASE_IN_INCR_SHIFT (0) > #define BLM_PHASE_IN_INCR_MASK (0xff << 0) > -#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) > +#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) > /* > * This is the most significant 15 bits of the number of backlight cycles in a > * complete cycle of the modulated backlight control. > @@ -4810,7 +4812,7 @@ enum { > #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) > #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ > > -#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260) > +#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) > #define BLM_HISTOGRAM_ENABLE (1 << 31) > > /* New registers for PCH-split platforms. Safe where new bits show up, the > @@ -5434,47 +5436,47 @@ enum { > * is 20 bytes in each direction, hence the 5 fixed > * data registers > */ > -#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) > -#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) > -#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) > -#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) > -#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) > -#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) > - > -#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) > -#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) > -#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) > -#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) > -#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) > -#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) > - > -#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) > -#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) > -#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) > -#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) > -#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) > -#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) > - > -#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) > -#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) > -#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) > -#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) > -#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) > -#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) > - > -#define _DPE_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64410) > -#define _DPE_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64414) > -#define _DPE_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64418) > -#define _DPE_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6441c) > -#define _DPE_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64420) > -#define _DPE_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64424) > - > -#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510) > -#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514) > -#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518) > -#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c) > -#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520) > -#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524) > +#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) > +#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) > +#define _DPA_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64018) > +#define _DPA_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6401c) > +#define _DPA_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64020) > +#define _DPA_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64024) > + > +#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) > +#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) > +#define _DPB_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64118) > +#define _DPB_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6411c) > +#define _DPB_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64120) > +#define _DPB_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64124) > + > +#define _DPC_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64210) > +#define _DPC_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64214) > +#define _DPC_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64218) > +#define _DPC_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6421c) > +#define _DPC_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64220) > +#define _DPC_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64224) > + > +#define _DPD_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64310) > +#define _DPD_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64314) > +#define _DPD_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64318) > +#define _DPD_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6431c) > +#define _DPD_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64320) > +#define _DPD_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64324) > + > +#define _DPE_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64410) > +#define _DPE_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64414) > +#define _DPE_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64418) > +#define _DPE_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6441c) > +#define _DPE_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64420) > +#define _DPE_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64424) > + > +#define _DPF_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64510) > +#define _DPF_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64514) > +#define _DPF_AUX_CH_DATA2 (DISPLAY_MMIO_BASE(dev_priv) + 0x64518) > +#define _DPF_AUX_CH_DATA3 (DISPLAY_MMIO_BASE(dev_priv) + 0x6451c) > +#define _DPF_AUX_CH_DATA4 (DISPLAY_MMIO_BASE(dev_priv) + 0x64520) > +#define _DPF_AUX_CH_DATA5 (DISPLAY_MMIO_BASE(dev_priv) + 0x64524) Observation only - this block looks could be computed something like: _DPx_AUX_CH_DATAn(x, n) ... 0x64014 + (x - 'A') * 0x100 + n * 4 ... You'll know if that is at all feasible. > > #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) > #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ > @@ -5750,7 +5752,7 @@ enum { > #define DPINVGTT_STATUS_MASK 0xff > #define DPINVGTT_STATUS_MASK_CHV 0xfff > > -#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030) > +#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) > #define DSPARB_CSTART_MASK (0x7f << 7) > #define DSPARB_CSTART_SHIFT 7 > #define DSPARB_BSTART_MASK (0x7f) > @@ -5785,7 +5787,7 @@ enum { > #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) > > /* pnv/gen4/g4x/vlv/chv */ > -#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034) > +#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) > #define DSPFW_SR_SHIFT 23 > #define DSPFW_SR_MASK (0x1ff << 23) > #define DSPFW_CURSORB_SHIFT 16 > @@ -5796,7 +5798,7 @@ enum { > #define DSPFW_PLANEA_SHIFT 0 > #define DSPFW_PLANEA_MASK (0x7f << 0) > #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ > -#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038) > +#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) > #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ > #define DSPFW_FBC_SR_SHIFT 28 > #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ > @@ -5812,7 +5814,7 @@ enum { > #define DSPFW_SPRITEA_SHIFT 0 > #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ > #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ > -#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c) > +#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) > #define DSPFW_HPLL_SR_EN (1 << 31) > #define PINEVIEW_SELF_REFRESH_EN (1 << 30) > #define DSPFW_CURSOR_SR_SHIFT 24 > @@ -6228,35 +6230,35 @@ enum { > * [10:1f] all > * [30:32] all > */ > -#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) > -#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) > -#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) > +#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) > +#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) > +#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) > #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) > > /* Pipe B */ > -#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) > -#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) > -#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) > +#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) > +#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) > +#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) > #define _PIPEBFRAMEHIGH 0x71040 > #define _PIPEBFRAMEPIXEL 0x71044 > -#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040) > -#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044) > +#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) > +#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) > > > /* Display B control */ > -#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) > +#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) > #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) > #define DISPPLANE_ALPHA_TRANS_DISABLE 0 > #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 > #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) > -#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) > -#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) > -#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) > -#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) > -#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) > -#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) > -#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) > -#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) > +#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) > +#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) > +#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) > +#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) > +#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) > +#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) > +#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) > +#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) > > /* ICL DSI 0 and 1 */ > #define _PIPEDSI0CONF 0x7b008 > @@ -8808,7 +8810,7 @@ enum { > #define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) > > /* Audio */ > -#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020) > +#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) > #define INTEL_AUDIO_DEVCL 0x808629FB > #define INTEL_AUDIO_DEVBLC 0x80862801 > #define INTEL_AUDIO_DEVCTG 0x80862802 > Looks completely mechanical - no mistakes spotted. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula 2018-12-31 14:56 ` [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct Jani Nikula 2018-12-31 14:56 ` [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 9:38 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info Jani Nikula ` (7 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula With the static/runtime device info split, this makes more sense. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 5 ++--- drivers/gpu/drm/i915/intel_device_info.h | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index f884b9a138cd..261932ee6837 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1374,7 +1374,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) if (i915_inject_load_failure()) return -ENODEV; - intel_device_info_runtime_init(mkwrite_device_info(dev_priv)); + intel_device_info_runtime_init(dev_priv); if (HAS_PPGTT(dev_priv)) { if (intel_vgpu_active(dev_priv) && diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ffc5d75aa690..f35e8cff4b99 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -738,10 +738,9 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) * - after the PCH has been detected, * - before the first usage of the fields it can tweak. */ -void intel_device_info_runtime_init(struct intel_device_info *info) +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = - container_of(info, struct drm_i915_private, info); + struct intel_device_info *info = mkwrite_device_info(dev_priv); struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); enum pipe pipe; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index fa81ee15dfa1..f0e6d374d4ec 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -266,7 +266,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, const char *intel_platform_name(enum intel_platform platform); -void intel_device_info_runtime_init(struct intel_device_info *info); +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); void intel_device_info_dump(const struct intel_device_info *info, struct drm_printer *p); void intel_device_info_dump_flags(const struct intel_device_info *info, -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() 2018-12-31 14:56 ` [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() Jani Nikula @ 2019-01-02 9:38 ` Tvrtko Ursulin 0 siblings, 0 replies; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 9:38 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > With the static/runtime device info split, this makes more sense. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 5 ++--- > drivers/gpu/drm/i915/intel_device_info.h | 2 +- > 3 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index f884b9a138cd..261932ee6837 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1374,7 +1374,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) > if (i915_inject_load_failure()) > return -ENODEV; > > - intel_device_info_runtime_init(mkwrite_device_info(dev_priv)); > + intel_device_info_runtime_init(dev_priv); > > if (HAS_PPGTT(dev_priv)) { > if (intel_vgpu_active(dev_priv) && > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index ffc5d75aa690..f35e8cff4b99 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -738,10 +738,9 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > * - after the PCH has been detected, > * - before the first usage of the fields it can tweak. > */ > -void intel_device_info_runtime_init(struct intel_device_info *info) > +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = > - container_of(info, struct drm_i915_private, info); > + struct intel_device_info *info = mkwrite_device_info(dev_priv); > struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); > enum pipe pipe; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index fa81ee15dfa1..f0e6d374d4ec 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -266,7 +266,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, > > const char *intel_platform_name(enum intel_platform platform); > > -void intel_device_info_runtime_init(struct intel_device_info *info); > +void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); > void intel_device_info_dump(const struct intel_device_info *info, > struct drm_printer *p); > void intel_device_info_dump_flags(const struct intel_device_info *info, > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (2 preceding siblings ...) 2018-12-31 14:56 ` [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 9:58 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 5/6] drm/i915: drop intel_device_info_dump() Jani Nikula ` (6 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Hide the way device info is stored, in preparation of making device info a pointer to the const rodata in i915_pci.c. No functional changes. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 90 ++++++++++++++++++------------------- drivers/gpu/drm/i915/i915_reg.h | 12 ++--- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 4 files changed, 53 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 261932ee6837..8d7a3a852c10 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1636,7 +1636,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) if (drm_debug & DRM_UT_DRIVER) { struct drm_printer p = drm_debug_printer("i915 device info:"); - intel_device_info_dump(&dev_priv->info, &p); + intel_device_info_dump(INTEL_INFO(dev_priv), &p); intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4534beeed6f9..ce8d7a97e26b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2202,7 +2202,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) +#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) #define REVID_FOREVER 0xff @@ -2215,11 +2215,11 @@ intel_info(const struct drm_i915_private *dev_priv) /* Returns true if Gen is in inclusive range [Start, End] */ #define IS_GEN_RANGE(dev_priv, s, e) \ - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) #define IS_GEN(dev_priv, n) \ (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ - (dev_priv)->info.gen == (n)) + INTEL_INFO(dev_priv)->gen == (n)) /* * Return true if revision is in range [since,until] inclusive. @@ -2229,7 +2229,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p)) #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) @@ -2251,7 +2251,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ - (dev_priv)->info.gt == 1) + INTEL_INFO(dev_priv)->gt == 1) #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) @@ -2263,7 +2263,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ @@ -2274,13 +2274,13 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xf) == 0xe) #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ - (dev_priv)->info.gt == 3) + INTEL_INFO(dev_priv)->gt == 3) #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ - (dev_priv)->info.gt == 3) + INTEL_INFO(dev_priv)->gt == 3) #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ - (dev_priv)->info.gt == 1) + INTEL_INFO(dev_priv)->gt == 1) /* ULX machines are also considered ULT. */ #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ INTEL_DEVID(dev_priv) == 0x0A1E) @@ -2303,21 +2303,21 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \ INTEL_DEVID(dev_priv) == 0x87C0) #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (dev_priv)->info.gt == 2) + INTEL_INFO(dev_priv)->gt == 2) #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (dev_priv)->info.gt == 3) + INTEL_INFO(dev_priv)->gt == 3) #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ - (dev_priv)->info.gt == 4) + INTEL_INFO(dev_priv)->gt == 4) #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ - (dev_priv)->info.gt == 2) + INTEL_INFO(dev_priv)->gt == 2) #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ - (dev_priv)->info.gt == 3) + INTEL_INFO(dev_priv)->gt == 3) #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ - (dev_priv)->info.gt == 2) + INTEL_INFO(dev_priv)->gt == 2) #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ - (dev_priv)->info.gt == 3) + INTEL_INFO(dev_priv)->gt == 3) #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) @@ -2390,27 +2390,27 @@ intel_info(const struct drm_i915_private *dev_priv) #define ALL_ENGINES (~0) #define HAS_ENGINE(dev_priv, id) \ - (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) + (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) -#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) +#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ - ((dev_priv)->info.has_logical_ring_contexts) + (INTEL_INFO(dev_priv)->has_logical_ring_contexts) #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ - ((dev_priv)->info.has_logical_ring_elsq) + (INTEL_INFO(dev_priv)->has_logical_ring_elsq) #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ - ((dev_priv)->info.has_logical_ring_preemption) + (INTEL_INFO(dev_priv)->has_logical_ring_preemption) #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) @@ -2424,12 +2424,12 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ GEM_BUG_ON((sizes) == 0); \ - ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ + ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ }) -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay) +#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ - ((dev_priv)->info.display.overlay_needs_physical) + (INTEL_INFO(dev_priv)->display.overlay_needs_physical) /* Early gen2 have a totally busted CS tlb and require pinned batches. */ #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) @@ -2450,39 +2450,39 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv) -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug) +#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) -#define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc) +#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst) +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) -#define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi) -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) -#define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr) +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) -#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) -#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) +#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) +#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ -#define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr) +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) -#define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc) +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) /* * For now, anything with a GuC requires uCode loading, and then supports * command submission once loaded. But these are logically independent * properties, so we have separate macros to test them. */ -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc) +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct) #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) @@ -2495,7 +2495,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv) #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv) -#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) +#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) #define INTEL_PCH_DEVICE_ID_MASK 0xff80 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 @@ -2535,12 +2535,12 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display) +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch_display) #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) /* DPF == dynamic parity feature */ -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 2 : HAS_L3_DPF(dev_priv)) @@ -3302,7 +3302,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } static inline struct intel_device_info * mkwrite_device_info(struct drm_i915_private *dev_priv) { - return (struct intel_device_info *)&dev_priv->info; + return (struct intel_device_info *)INTEL_INFO(dev_priv); } /* modesetting */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index de1c9d495808..44958d994bfa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -185,14 +185,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) * Device info offset array based helpers for groups of registers with unevenly * spaced base offsets. */ -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ + INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv)) -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ +#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \ + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv)) -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ +#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ DISPLAY_MMIO_BASE(dev_priv)) #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e5e5c6e9ed28..fff468f17d2d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2361,7 +2361,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) bool intel_has_reset_engine(struct drm_i915_private *dev_priv) { - return (dev_priv->info.has_reset_engine && + return (INTEL_INFO(dev_priv)->has_reset_engine && i915_modparams.reset >= 2); } -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info 2018-12-31 14:56 ` [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info Jani Nikula @ 2019-01-02 9:58 ` Tvrtko Ursulin 0 siblings, 0 replies; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 9:58 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > Hide the way device info is stored, in preparation of making device info > a pointer to the const rodata in i915_pci.c. No functional changes. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 90 ++++++++++++++++++------------------- > drivers/gpu/drm/i915/i915_reg.h | 12 ++--- > drivers/gpu/drm/i915/intel_uncore.c | 2 +- > 4 files changed, 53 insertions(+), 53 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 261932ee6837..8d7a3a852c10 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1636,7 +1636,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) > if (drm_debug & DRM_UT_DRIVER) { > struct drm_printer p = drm_debug_printer("i915 device info:"); > > - intel_device_info_dump(&dev_priv->info, &p); > + intel_device_info_dump(INTEL_INFO(dev_priv), &p); > intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); > } > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4534beeed6f9..ce8d7a97e26b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2202,7 +2202,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) > #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) > > -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) > +#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) > #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) > > #define REVID_FOREVER 0xff > @@ -2215,11 +2215,11 @@ intel_info(const struct drm_i915_private *dev_priv) > > /* Returns true if Gen is in inclusive range [Start, End] */ > #define IS_GEN_RANGE(dev_priv, s, e) \ > - (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > + (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) > > #define IS_GEN(dev_priv, n) \ > (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ > - (dev_priv)->info.gen == (n)) > + INTEL_INFO(dev_priv)->gen == (n)) > > /* > * Return true if revision is in range [since,until] inclusive. > @@ -2229,7 +2229,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_REVID(p, since, until) \ > (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) > > -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) > +#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p)) > > #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) > #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) > @@ -2251,7 +2251,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) > #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) > #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ > - (dev_priv)->info.gt == 1) > + INTEL_INFO(dev_priv)->gt == 1) > #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) > #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) > #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) > @@ -2263,7 +2263,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) > #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) > #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) > -#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) > +#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ > @@ -2274,13 +2274,13 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xf) == 0xe) > #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ > - (dev_priv)->info.gt == 3) > + INTEL_INFO(dev_priv)->gt == 3) > #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) > #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ > - (dev_priv)->info.gt == 3) > + INTEL_INFO(dev_priv)->gt == 3) > #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ > - (dev_priv)->info.gt == 1) > + INTEL_INFO(dev_priv)->gt == 1) > /* ULX machines are also considered ULT. */ > #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ > INTEL_DEVID(dev_priv) == 0x0A1E) > @@ -2303,21 +2303,21 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \ > INTEL_DEVID(dev_priv) == 0x87C0) > #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ > - (dev_priv)->info.gt == 2) > + INTEL_INFO(dev_priv)->gt == 2) > #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ > - (dev_priv)->info.gt == 3) > + INTEL_INFO(dev_priv)->gt == 3) > #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ > - (dev_priv)->info.gt == 4) > + INTEL_INFO(dev_priv)->gt == 4) > #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ > - (dev_priv)->info.gt == 2) > + INTEL_INFO(dev_priv)->gt == 2) > #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ > - (dev_priv)->info.gt == 3) > + INTEL_INFO(dev_priv)->gt == 3) > #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) > #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ > - (dev_priv)->info.gt == 2) > + INTEL_INFO(dev_priv)->gt == 2) > #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ > - (dev_priv)->info.gt == 3) > + INTEL_INFO(dev_priv)->gt == 3) > #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) > > @@ -2390,27 +2390,27 @@ intel_info(const struct drm_i915_private *dev_priv) > #define ALL_ENGINES (~0) > > #define HAS_ENGINE(dev_priv, id) \ > - (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) > + (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) > > #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) > #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) > #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) > #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) > > -#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) > -#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) > +#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > +#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) > #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) > #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ > IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) > > -#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) > +#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) > > #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ > - ((dev_priv)->info.has_logical_ring_contexts) > + (INTEL_INFO(dev_priv)->has_logical_ring_contexts) > #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ > - ((dev_priv)->info.has_logical_ring_elsq) > + (INTEL_INFO(dev_priv)->has_logical_ring_elsq) > #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ > - ((dev_priv)->info.has_logical_ring_preemption) > + (INTEL_INFO(dev_priv)->has_logical_ring_preemption) > > #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) > > @@ -2424,12 +2424,12 @@ intel_info(const struct drm_i915_private *dev_priv) > > #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ > GEM_BUG_ON((sizes) == 0); \ > - ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ > + ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ > }) > > -#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay) > +#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) > #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ > - ((dev_priv)->info.display.overlay_needs_physical) > + (INTEL_INFO(dev_priv)->display.overlay_needs_physical) > > /* Early gen2 have a totally busted CS tlb and require pinned batches. */ > #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) > @@ -2450,39 +2450,39 @@ intel_info(const struct drm_i915_private *dev_priv) > #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ > !(IS_I915G(dev_priv) || \ > IS_I915GM(dev_priv))) > -#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv) > -#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug) > +#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) > +#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) > > #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) > -#define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc) > +#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) > #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) > > #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) > > -#define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst) > +#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) > > -#define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi) > -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) > -#define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr) > +#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > +#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) > +#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > > -#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) > -#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) > +#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > +#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) > #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ > > -#define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr) > +#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) > > -#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) > -#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) > +#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) > +#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) > > -#define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc) > +#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) > > /* > * For now, anything with a GuC requires uCode loading, and then supports > * command submission once loaded. But these are logically independent > * properties, so we have separate macros to test them. > */ > -#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) > -#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) > +#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc) > +#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct) > #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) > #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) > > @@ -2495,7 +2495,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv) > #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv) > > -#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) > +#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) > > #define INTEL_PCH_DEVICE_ID_MASK 0xff80 > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > @@ -2535,12 +2535,12 @@ intel_info(const struct drm_i915_private *dev_priv) > #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) > #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) > > -#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display) > +#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch_display) > > #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) > > /* DPF == dynamic parity feature */ > -#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) > +#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) > #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ > 2 : HAS_L3_DPF(dev_priv)) > > @@ -3302,7 +3302,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } > static inline struct intel_device_info * > mkwrite_device_info(struct drm_i915_private *dev_priv) > { > - return (struct intel_device_info *)&dev_priv->info; > + return (struct intel_device_info *)INTEL_INFO(dev_priv); > } > > /* modesetting */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index de1c9d495808..44958d994bfa 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -185,14 +185,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > * Device info offset array based helpers for groups of registers with unevenly > * spaced base offsets. > */ > -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ > - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ > +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ > + INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ > DISPLAY_MMIO_BASE(dev_priv)) > -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ > - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ > +#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \ > + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ > DISPLAY_MMIO_BASE(dev_priv)) > -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \ > - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ > +#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ > + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ > DISPLAY_MMIO_BASE(dev_priv)) > > #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index e5e5c6e9ed28..fff468f17d2d 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -2361,7 +2361,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) > > bool intel_has_reset_engine(struct drm_i915_private *dev_priv) > { > - return (dev_priv->info.has_reset_engine && > + return (INTEL_INFO(dev_priv)->has_reset_engine && > i915_modparams.reset >= 2); > } > > Looks OK. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Have you tried renaming the dev info member to see you got all of them? Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 5/6] drm/i915: drop intel_device_info_dump() 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (3 preceding siblings ...) 2018-12-31 14:56 ` [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 10:02 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage Jani Nikula ` (5 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula The debugfs, error state and regular dmesg logging dump needs seem to be different. Remove the generic dump function only used for the welcome message. This may be added back later when better abstractions are identified, but at the moment this seems to be the simplest considering the device info rework in progress. No longer rely on device info being a substruct of dev_priv. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 8 +++++++- drivers/gpu/drm/i915/intel_device_info.c | 15 --------------- drivers/gpu/drm/i915/intel_device_info.h | 2 -- 3 files changed, 7 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8d7a3a852c10..fe01d090f9bb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1636,7 +1636,13 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) if (drm_debug & DRM_UT_DRIVER) { struct drm_printer p = drm_debug_printer("i915 device info:"); - intel_device_info_dump(INTEL_INFO(dev_priv), &p); + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", + INTEL_DEVID(dev_priv), + INTEL_REVID(dev_priv), + intel_platform_name(INTEL_INFO(dev_priv)->platform), + INTEL_GEN(dev_priv)); + + intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); } diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index f35e8cff4b99..e0ce0c9791fc 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -113,21 +113,6 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, info->cs_timestamp_frequency_khz); } -void intel_device_info_dump(const struct intel_device_info *info, - struct drm_printer *p) -{ - struct drm_i915_private *dev_priv = - container_of(info, struct drm_i915_private, info); - - drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", - INTEL_DEVID(dev_priv), - INTEL_REVID(dev_priv), - intel_platform_name(info->platform), - info->gen); - - intel_device_info_dump_flags(info, p); -} - void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) { diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index f0e6d374d4ec..76735869e32d 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -267,8 +267,6 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, const char *intel_platform_name(enum intel_platform platform); void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); -void intel_device_info_dump(const struct intel_device_info *info, - struct drm_printer *p); void intel_device_info_dump_flags(const struct intel_device_info *info, struct drm_printer *p); void intel_device_info_dump_runtime(const struct intel_runtime_info *info, -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] drm/i915: drop intel_device_info_dump() 2018-12-31 14:56 ` [PATCH 5/6] drm/i915: drop intel_device_info_dump() Jani Nikula @ 2019-01-02 10:02 ` Tvrtko Ursulin 2019-01-02 10:42 ` Jani Nikula 0 siblings, 1 reply; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 10:02 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > The debugfs, error state and regular dmesg logging dump needs seem to be > different. Remove the generic dump function only used for the welcome > message. This may be added back later when better abstractions are > identified, but at the moment this seems to be the simplest considering > the device info rework in progress. No longer rely on device info being > a substruct of dev_priv. Why not just make intel_device_info_dump take dev_priv? Regards, Tvrtko > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 8 +++++++- > drivers/gpu/drm/i915/intel_device_info.c | 15 --------------- > drivers/gpu/drm/i915/intel_device_info.h | 2 -- > 3 files changed, 7 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 8d7a3a852c10..fe01d090f9bb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1636,7 +1636,13 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) > if (drm_debug & DRM_UT_DRIVER) { > struct drm_printer p = drm_debug_printer("i915 device info:"); > > - intel_device_info_dump(INTEL_INFO(dev_priv), &p); > + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", > + INTEL_DEVID(dev_priv), > + INTEL_REVID(dev_priv), > + intel_platform_name(INTEL_INFO(dev_priv)->platform), > + INTEL_GEN(dev_priv)); > + > + intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); > intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); > } > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index f35e8cff4b99..e0ce0c9791fc 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -113,21 +113,6 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, > info->cs_timestamp_frequency_khz); > } > > -void intel_device_info_dump(const struct intel_device_info *info, > - struct drm_printer *p) > -{ > - struct drm_i915_private *dev_priv = > - container_of(info, struct drm_i915_private, info); > - > - drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", > - INTEL_DEVID(dev_priv), > - INTEL_REVID(dev_priv), > - intel_platform_name(info->platform), > - info->gen); > - > - intel_device_info_dump_flags(info, p); > -} > - > void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, > struct drm_printer *p) > { > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index f0e6d374d4ec..76735869e32d 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -267,8 +267,6 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, > const char *intel_platform_name(enum intel_platform platform); > > void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); > -void intel_device_info_dump(const struct intel_device_info *info, > - struct drm_printer *p); > void intel_device_info_dump_flags(const struct intel_device_info *info, > struct drm_printer *p); > void intel_device_info_dump_runtime(const struct intel_runtime_info *info, > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] drm/i915: drop intel_device_info_dump() 2019-01-02 10:02 ` Tvrtko Ursulin @ 2019-01-02 10:42 ` Jani Nikula 2019-01-02 11:09 ` Tvrtko Ursulin 0 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2019-01-02 10:42 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 31/12/2018 14:56, Jani Nikula wrote: >> The debugfs, error state and regular dmesg logging dump needs seem to be >> different. Remove the generic dump function only used for the welcome >> message. This may be added back later when better abstractions are >> identified, but at the moment this seems to be the simplest considering >> the device info rework in progress. No longer rely on device info being >> a substruct of dev_priv. > > Why not just make intel_device_info_dump take dev_priv? I'm thinking the device info dumpers will need some refactoring in the future anyway to best suit all the needs of dmesg logging, debugfs, and error state dumping. The last one especially wants to use data copied to the error state instead of drm_i915_private. I admittedly took the easy way out here, and removed the function altogether because there's currently only one user. I didn't want to change now, and then change again later. BR, Jani. > > Regards, > > Tvrtko > >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.c | 8 +++++++- >> drivers/gpu/drm/i915/intel_device_info.c | 15 --------------- >> drivers/gpu/drm/i915/intel_device_info.h | 2 -- >> 3 files changed, 7 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> index 8d7a3a852c10..fe01d090f9bb 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -1636,7 +1636,13 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) >> if (drm_debug & DRM_UT_DRIVER) { >> struct drm_printer p = drm_debug_printer("i915 device info:"); >> >> - intel_device_info_dump(INTEL_INFO(dev_priv), &p); >> + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", >> + INTEL_DEVID(dev_priv), >> + INTEL_REVID(dev_priv), >> + intel_platform_name(INTEL_INFO(dev_priv)->platform), >> + INTEL_GEN(dev_priv)); >> + >> + intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); >> intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); >> } >> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c >> index f35e8cff4b99..e0ce0c9791fc 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -113,21 +113,6 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, >> info->cs_timestamp_frequency_khz); >> } >> >> -void intel_device_info_dump(const struct intel_device_info *info, >> - struct drm_printer *p) >> -{ >> - struct drm_i915_private *dev_priv = >> - container_of(info, struct drm_i915_private, info); >> - >> - drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", >> - INTEL_DEVID(dev_priv), >> - INTEL_REVID(dev_priv), >> - intel_platform_name(info->platform), >> - info->gen); >> - >> - intel_device_info_dump_flags(info, p); >> -} >> - >> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, >> struct drm_printer *p) >> { >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h >> index f0e6d374d4ec..76735869e32d 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.h >> +++ b/drivers/gpu/drm/i915/intel_device_info.h >> @@ -267,8 +267,6 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, >> const char *intel_platform_name(enum intel_platform platform); >> >> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); >> -void intel_device_info_dump(const struct intel_device_info *info, >> - struct drm_printer *p); >> void intel_device_info_dump_flags(const struct intel_device_info *info, >> struct drm_printer *p); >> void intel_device_info_dump_runtime(const struct intel_runtime_info *info, >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 5/6] drm/i915: drop intel_device_info_dump() 2019-01-02 10:42 ` Jani Nikula @ 2019-01-02 11:09 ` Tvrtko Ursulin 0 siblings, 0 replies; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 11:09 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 02/01/2019 10:42, Jani Nikula wrote: > On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: >> On 31/12/2018 14:56, Jani Nikula wrote: >>> The debugfs, error state and regular dmesg logging dump needs seem to be >>> different. Remove the generic dump function only used for the welcome >>> message. This may be added back later when better abstractions are >>> identified, but at the moment this seems to be the simplest considering >>> the device info rework in progress. No longer rely on device info being >>> a substruct of dev_priv. >> >> Why not just make intel_device_info_dump take dev_priv? > > I'm thinking the device info dumpers will need some refactoring in the > future anyway to best suit all the needs of dmesg logging, debugfs, and > error state dumping. The last one especially wants to use data copied to > the error state instead of drm_i915_private. > > I admittedly took the easy way out here, and removed the function > altogether because there's currently only one user. I didn't want to > change now, and then change again later. Okay, makes sense. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > BR, > Jani. > >> >> Regards, >> >> Tvrtko >> >>> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_drv.c | 8 +++++++- >>> drivers/gpu/drm/i915/intel_device_info.c | 15 --------------- >>> drivers/gpu/drm/i915/intel_device_info.h | 2 -- >>> 3 files changed, 7 insertions(+), 18 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >>> index 8d7a3a852c10..fe01d090f9bb 100644 >>> --- a/drivers/gpu/drm/i915/i915_drv.c >>> +++ b/drivers/gpu/drm/i915/i915_drv.c >>> @@ -1636,7 +1636,13 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) >>> if (drm_debug & DRM_UT_DRIVER) { >>> struct drm_printer p = drm_debug_printer("i915 device info:"); >>> >>> - intel_device_info_dump(INTEL_INFO(dev_priv), &p); >>> + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", >>> + INTEL_DEVID(dev_priv), >>> + INTEL_REVID(dev_priv), >>> + intel_platform_name(INTEL_INFO(dev_priv)->platform), >>> + INTEL_GEN(dev_priv)); >>> + >>> + intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p); >>> intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p); >>> } >>> >>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c >>> index f35e8cff4b99..e0ce0c9791fc 100644 >>> --- a/drivers/gpu/drm/i915/intel_device_info.c >>> +++ b/drivers/gpu/drm/i915/intel_device_info.c >>> @@ -113,21 +113,6 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, >>> info->cs_timestamp_frequency_khz); >>> } >>> >>> -void intel_device_info_dump(const struct intel_device_info *info, >>> - struct drm_printer *p) >>> -{ >>> - struct drm_i915_private *dev_priv = >>> - container_of(info, struct drm_i915_private, info); >>> - >>> - drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", >>> - INTEL_DEVID(dev_priv), >>> - INTEL_REVID(dev_priv), >>> - intel_platform_name(info->platform), >>> - info->gen); >>> - >>> - intel_device_info_dump_flags(info, p); >>> -} >>> - >>> void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, >>> struct drm_printer *p) >>> { >>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h >>> index f0e6d374d4ec..76735869e32d 100644 >>> --- a/drivers/gpu/drm/i915/intel_device_info.h >>> +++ b/drivers/gpu/drm/i915/intel_device_info.h >>> @@ -267,8 +267,6 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, >>> const char *intel_platform_name(enum intel_platform platform); >>> >>> void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); >>> -void intel_device_info_dump(const struct intel_device_info *info, >>> - struct drm_printer *p); >>> void intel_device_info_dump_flags(const struct intel_device_info *info, >>> struct drm_printer *p); >>> void intel_device_info_dump_runtime(const struct intel_runtime_info *info, >>> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (4 preceding siblings ...) 2018-12-31 14:56 ` [PATCH 5/6] drm/i915: drop intel_device_info_dump() Jani Nikula @ 2018-12-31 14:56 ` Jani Nikula 2019-01-02 10:04 ` Tvrtko Ursulin 2018-12-31 15:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: start splitting off runtime device info Patchwork ` (4 subsequent siblings) 10 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2018-12-31 14:56 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Encourage use of INTEL_INFO() to access dev_priv->info to not accumulate more direct users of ->info, making further changes easier. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ce8d7a97e26b..18e67aaef764 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1431,7 +1431,7 @@ struct drm_i915_private { struct kmem_cache *dependencies; struct kmem_cache *priorities; - const struct intel_device_info info; + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ struct intel_driver_caps caps; @@ -2192,13 +2192,7 @@ static inline unsigned int i915_sg_segment_size(void) return size; } -static inline const struct intel_device_info * -intel_info(const struct drm_i915_private *dev_priv) -{ - return &dev_priv->info; -} - -#define INTEL_INFO(dev_priv) intel_info((dev_priv)) +#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage 2018-12-31 14:56 ` [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage Jani Nikula @ 2019-01-02 10:04 ` Tvrtko Ursulin 2019-01-02 10:44 ` Jani Nikula 0 siblings, 1 reply; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 10:04 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 31/12/2018 14:56, Jani Nikula wrote: > Encourage use of INTEL_INFO() to access dev_priv->info to not accumulate > more direct users of ->info, making further changes easier. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index ce8d7a97e26b..18e67aaef764 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1431,7 +1431,7 @@ struct drm_i915_private { > struct kmem_cache *dependencies; > struct kmem_cache *priorities; > > - const struct intel_device_info info; > + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ > struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ > struct intel_driver_caps caps; > > @@ -2192,13 +2192,7 @@ static inline unsigned int i915_sg_segment_size(void) > return size; > } > > -static inline const struct intel_device_info * > -intel_info(const struct drm_i915_private *dev_priv) > -{ > - return &dev_priv->info; > -} > - What was this helper for, who remembers? :) Regards, Tvrtko > -#define INTEL_INFO(dev_priv) intel_info((dev_priv)) > +#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) > #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) > #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage 2019-01-02 10:04 ` Tvrtko Ursulin @ 2019-01-02 10:44 ` Jani Nikula 2019-01-02 11:10 ` Tvrtko Ursulin 0 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2019-01-02 10:44 UTC (permalink / raw) To: Tvrtko Ursulin, intel-gfx On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 31/12/2018 14:56, Jani Nikula wrote: >> Encourage use of INTEL_INFO() to access dev_priv->info to not accumulate >> more direct users of ->info, making further changes easier. >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 10 ++-------- >> 1 file changed, 2 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index ce8d7a97e26b..18e67aaef764 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1431,7 +1431,7 @@ struct drm_i915_private { >> struct kmem_cache *dependencies; >> struct kmem_cache *priorities; >> >> - const struct intel_device_info info; >> + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ >> struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ >> struct intel_driver_caps caps; >> >> @@ -2192,13 +2192,7 @@ static inline unsigned int i915_sg_segment_size(void) >> return size; >> } >> >> -static inline const struct intel_device_info * >> -intel_info(const struct drm_i915_private *dev_priv) >> -{ >> - return &dev_priv->info; >> -} >> - > > What was this helper for, who remembers? :) Didn't dig through the git logs, but I presume it's a leftover from the days we were migrating to subclassing drm_device in drm_i915_private... BR, Jani. > > Regards, > > Tvrtko > >> -#define INTEL_INFO(dev_priv) intel_info((dev_priv)) >> +#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) >> #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) >> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) >> >> > -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage 2019-01-02 10:44 ` Jani Nikula @ 2019-01-02 11:10 ` Tvrtko Ursulin 0 siblings, 0 replies; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 11:10 UTC (permalink / raw) To: Jani Nikula, intel-gfx On 02/01/2019 10:44, Jani Nikula wrote: > On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: >> On 31/12/2018 14:56, Jani Nikula wrote: >>> Encourage use of INTEL_INFO() to access dev_priv->info to not accumulate >>> more direct users of ->info, making further changes easier. >>> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_drv.h | 10 ++-------- >>> 1 file changed, 2 insertions(+), 8 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >>> index ce8d7a97e26b..18e67aaef764 100644 >>> --- a/drivers/gpu/drm/i915/i915_drv.h >>> +++ b/drivers/gpu/drm/i915/i915_drv.h >>> @@ -1431,7 +1431,7 @@ struct drm_i915_private { >>> struct kmem_cache *dependencies; >>> struct kmem_cache *priorities; >>> >>> - const struct intel_device_info info; >>> + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ >>> struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ >>> struct intel_driver_caps caps; >>> >>> @@ -2192,13 +2192,7 @@ static inline unsigned int i915_sg_segment_size(void) >>> return size; >>> } >>> >>> -static inline const struct intel_device_info * >>> -intel_info(const struct drm_i915_private *dev_priv) >>> -{ >>> - return &dev_priv->info; >>> -} >>> - >> >> What was this helper for, who remembers? :) > > Didn't dig through the git logs, but I presume it's a leftover from the > days we were migrating to subclassing drm_device in drm_i915_private... Hm yeah, could be. So the last one: Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > > BR, > Jani. > > >> >> Regards, >> >> Tvrtko >> >>> -#define INTEL_INFO(dev_priv) intel_info((dev_priv)) >>> +#define INTEL_INFO(dev_priv) (&(dev_priv)->__info) >>> #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) >>> #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) >>> >>> >> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: start splitting off runtime device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (5 preceding siblings ...) 2018-12-31 14:56 ` [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage Jani Nikula @ 2018-12-31 15:07 ` Patchwork 2018-12-31 15:10 ` ✗ Fi.CI.SPARSE: " Patchwork ` (3 subsequent siblings) 10 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2018-12-31 15:07 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: start splitting off runtime device info URL : https://patchwork.freedesktop.org/series/54589/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0973736519c3 drm/i915: start moving runtime device info to a separate struct -:565: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #565: FILE: drivers/gpu/drm/i915/intel_display.h:124: +#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') total: 0 errors, 0 warnings, 1 checks, 648 lines checked fb252e952052 drm/i915/reg: abstract display_mmio_offset access f8478d51f1f6 drm/i915: pass dev_priv to intel_device_info_runtime_init() 90a4d812a923 drm/i915: always use INTEL_INFO() to access device info -:280: WARNING:LONG_LINE: line over 100 characters #280: FILE: drivers/gpu/drm/i915/i915_reg.h:192: + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ -:285: WARNING:LONG_LINE: line over 100 characters #285: FILE: drivers/gpu/drm/i915/i915_reg.h:195: + INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ total: 0 errors, 2 warnings, 0 checks, 258 lines checked 0e6d7586940e drm/i915: drop intel_device_info_dump() a8ce6166b2c2 drm/i915: rename dev_priv info to __info to avoid usage _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: start splitting off runtime device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (6 preceding siblings ...) 2018-12-31 15:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: start splitting off runtime device info Patchwork @ 2018-12-31 15:10 ` Patchwork 2018-12-31 15:43 ` ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 10 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2018-12-31 15:10 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: start splitting off runtime device info URL : https://patchwork.freedesktop.org/series/54589/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: start moving runtime device info to a separate struct -drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3551:16: warning: expression using sizeof(void) Commit: drm/i915/reg: abstract display_mmio_offset access Okay! Commit: drm/i915: pass dev_priv to intel_device_info_runtime_init() Okay! Commit: drm/i915: always use INTEL_INFO() to access device info Okay! Commit: drm/i915: drop intel_device_info_dump() Okay! Commit: drm/i915: rename dev_priv info to __info to avoid usage -drivers/gpu/drm/i915/selftests/../i915_drv.h:3551:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3545:16: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: start splitting off runtime device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (7 preceding siblings ...) 2018-12-31 15:10 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-12-31 15:43 ` Patchwork 2018-12-31 17:53 ` ✓ Fi.CI.IGT: " Patchwork 2019-01-01 10:31 ` [PATCH 0/6] " Chris Wilson 10 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2018-12-31 15:43 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: start splitting off runtime device info URL : https://patchwork.freedesktop.org/series/54589/ State : success == Summary == CI Bug Log - changes from CI_DRM_5352 -> Patchwork_11172 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/54589/revisions/1/mbox/ Known issues ------------ Here are the changes found in Patchwork_11172 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] #### Possible fixes #### * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS #### Warnings #### * igt@i915_selftest@live_contexts: - fi-icl-u3: INCOMPLETE [fdo#108315] -> DMESG-FAIL [fdo#108569] - fi-icl-u2: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315] [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 Participating hosts (53 -> 47) ------------------------------ Missing (6): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_5352 -> Patchwork_11172 CI_DRM_5352: 7d18b164a5395c1e9f4cc01ed7d88e315cb65cd4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4755: 0ba18cf75cafb51d1e72557528de4a1be640a85c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11172: a8ce6166b2c2c97b0ad2d77878f218a72d3b4a43 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a8ce6166b2c2 drm/i915: rename dev_priv info to __info to avoid usage 0e6d7586940e drm/i915: drop intel_device_info_dump() 90a4d812a923 drm/i915: always use INTEL_INFO() to access device info f8478d51f1f6 drm/i915: pass dev_priv to intel_device_info_runtime_init() fb252e952052 drm/i915/reg: abstract display_mmio_offset access 0973736519c3 drm/i915: start moving runtime device info to a separate struct == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11172/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: start splitting off runtime device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (8 preceding siblings ...) 2018-12-31 15:43 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-12-31 17:53 ` Patchwork 2019-01-01 10:31 ` [PATCH 0/6] " Chris Wilson 10 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2018-12-31 17:53 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915: start splitting off runtime device info URL : https://patchwork.freedesktop.org/series/54589/ State : success == Summary == CI Bug Log - changes from CI_DRM_5352_full -> Patchwork_11172_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_11172_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@bcs0-s3: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@gem_exec_schedule@pi-ringfull-bsd: - shard-skl: NOTRUN -> FAIL [fdo#103158] * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-skl: NOTRUN -> TIMEOUT [fdo#108039] * igt@i915_suspend@shrink: - shard-snb: NOTRUN -> DMESG-WARN [fdo#108784] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-b-crc-primary-rotation-180: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_concurrent@pipe-b: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +9 * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled: - shard-iclb: PASS -> WARN [fdo#108336] +3 * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled: - shard-iclb: NOTRUN -> WARN [fdo#108336] +1 * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-skl: PASS -> FAIL [fdo#107791] * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#107882] +1 * igt@kms_flip@dpms-vs-vblank-race: - shard-apl: PASS -> FAIL [fdo#103060] * igt@kms_flip_tiling@flip-x-tiled: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +4 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-render: - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +4 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#107724] +2 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] / [fdo#108336] +3 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu: - shard-skl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_rotation_crc@primary-rotation-90: - shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-b-ts-continuation-modeset-hang: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +5 * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@pm_backlight@fade_with_suspend: - shard-skl: NOTRUN -> FAIL [fdo#107847] #### Possible fixes #### * igt@kms_atomic_transition@plane-toggle-modeset-transition: - shard-iclb: DMESG-WARN [fdo#107724] -> PASS +3 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-iclb: DMESG-WARN [fdo#107956] -> PASS * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: INCOMPLETE [fdo#107713] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: DMESG-FAIL [fdo#107724] -> PASS +1 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-apl: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: - shard-iclb: FAIL [fdo#103167] -> PASS +6 * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt: - shard-iclb: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: FAIL [fdo#103166] -> PASS * igt@kms_plane@plane-position-covered-pipe-c-planes: - shard-apl: FAIL [fdo#103166] -> PASS * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-iclb: FAIL [fdo#103166] -> PASS * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: DMESG-WARN [fdo#105604] -> PASS - shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS * igt@kms_vblank@pipe-b-ts-continuation-suspend: - shard-iclb: FAIL [fdo#104894] -> PASS * igt@kms_vblank@pipe-c-query-busy: - shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +16 * igt@pm_rpm@legacy-planes: - shard-iclb: INCOMPLETE [fdo#108840] -> PASS #### Warnings #### * igt@i915_suspend@shrink: - shard-skl: INCOMPLETE [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#108784] - shard-glk: INCOMPLETE [fdo#103359] / [fdo#106886] / [k.org#198133] -> DMESG-WARN [fdo#108784] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-snb: INCOMPLETE [fdo#105411] -> DMESG-FAIL [fdo#107469] * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-iclb: FAIL [fdo#103166] -> DMESG-WARN [fdo#107724] / [fdo#108336] [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103925]: https://bugs.freedesktop.org/show_bug.cgi?id=103925 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894 [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604 [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538 [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885 [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886 [fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791 [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815 [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847 [fdo#107882]: https://bugs.freedesktop.org/show_bug.cgi?id=107882 [fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886 [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956 [fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336 [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784 [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (7 -> 7) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_5352 -> Patchwork_11172 CI_DRM_5352: 7d18b164a5395c1e9f4cc01ed7d88e315cb65cd4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4755: 0ba18cf75cafb51d1e72557528de4a1be640a85c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_11172: a8ce6166b2c2c97b0ad2d77878f218a72d3b4a43 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11172/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/6] drm/i915: start splitting off runtime device info 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula ` (9 preceding siblings ...) 2018-12-31 17:53 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-01-01 10:31 ` Chris Wilson 2019-01-02 9:13 ` Jani Nikula 10 siblings, 1 reply; 26+ messages in thread From: Chris Wilson @ 2019-01-01 10:31 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula Quoting Jani Nikula (2018-12-31 14:56:40) > The mkwrite_device_info removal series [1] seems to have stalled. I'm > trying to nudge things forward a bit with this series. This isn't near > as complete as Tvrtko's work, but does some of the prep work I wanted, > specifically using INTEL_INFO() and RUNTIME_INFO() to access the > fields. There are obviously conflicts, but mostly I think this should > make the rest of Tvrtko's work easier, not harder. > > BR, > Jani. > > > [1] https://patchwork.freedesktop.org/series/52381/ > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > > > Jani Nikula (6): > drm/i915: start moving runtime device info to a separate struct > drm/i915/reg: abstract display_mmio_offset access > drm/i915: pass dev_priv to intel_device_info_runtime_init() > drm/i915: always use INTEL_INFO() to access device info > drm/i915: drop intel_device_info_dump() > drm/i915: rename dev_priv info to __info to avoid usage Looked ok, and didn't see anything odd compared to my own attempts. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/6] drm/i915: start splitting off runtime device info 2019-01-01 10:31 ` [PATCH 0/6] " Chris Wilson @ 2019-01-02 9:13 ` Jani Nikula 2019-01-02 10:17 ` Tvrtko Ursulin 0 siblings, 1 reply; 26+ messages in thread From: Jani Nikula @ 2019-01-02 9:13 UTC (permalink / raw) To: Chris Wilson, intel-gfx, Ursulin, Tvrtko On Tue, 01 Jan 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Quoting Jani Nikula (2018-12-31 14:56:40) >> The mkwrite_device_info removal series [1] seems to have stalled. I'm >> trying to nudge things forward a bit with this series. This isn't near >> as complete as Tvrtko's work, but does some of the prep work I wanted, >> specifically using INTEL_INFO() and RUNTIME_INFO() to access the >> fields. There are obviously conflicts, but mostly I think this should >> make the rest of Tvrtko's work easier, not harder. >> >> BR, >> Jani. >> >> >> [1] https://patchwork.freedesktop.org/series/52381/ >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> >> >> Jani Nikula (6): >> drm/i915: start moving runtime device info to a separate struct >> drm/i915/reg: abstract display_mmio_offset access >> drm/i915: pass dev_priv to intel_device_info_runtime_init() >> drm/i915: always use INTEL_INFO() to access device info >> drm/i915: drop intel_device_info_dump() >> drm/i915: rename dev_priv info to __info to avoid usage > > Looked ok, and didn't see anything odd compared to my own attempts. > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Thanks for the review. Tvrtko, I'd still like to get your ack before I go ahead and push these. Also, do you think you'll have time in the near future to pick up your series, or shall I? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/6] drm/i915: start splitting off runtime device info 2019-01-02 9:13 ` Jani Nikula @ 2019-01-02 10:17 ` Tvrtko Ursulin 2019-01-02 11:19 ` Jani Nikula 0 siblings, 1 reply; 26+ messages in thread From: Tvrtko Ursulin @ 2019-01-02 10:17 UTC (permalink / raw) To: Jani Nikula, Chris Wilson, intel-gfx, Ursulin, Tvrtko On 02/01/2019 09:13, Jani Nikula wrote: > On Tue, 01 Jan 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: >> Quoting Jani Nikula (2018-12-31 14:56:40) >>> The mkwrite_device_info removal series [1] seems to have stalled. I'm >>> trying to nudge things forward a bit with this series. This isn't near >>> as complete as Tvrtko's work, but does some of the prep work I wanted, >>> specifically using INTEL_INFO() and RUNTIME_INFO() to access the >>> fields. There are obviously conflicts, but mostly I think this should >>> make the rest of Tvrtko's work easier, not harder. >>> >>> BR, >>> Jani. >>> >>> >>> [1] https://patchwork.freedesktop.org/series/52381/ >>> >>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >>> >>> >>> Jani Nikula (6): >>> drm/i915: start moving runtime device info to a separate struct >>> drm/i915/reg: abstract display_mmio_offset access >>> drm/i915: pass dev_priv to intel_device_info_runtime_init() >>> drm/i915: always use INTEL_INFO() to access device info >>> drm/i915: drop intel_device_info_dump() >>> drm/i915: rename dev_priv info to __info to avoid usage >> >> Looked ok, and didn't see anything odd compared to my own attempts. >> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > Thanks for the review. > > Tvrtko, I'd still like to get your ack before I go ahead and push > these. Also, do you think you'll have time in the near future to pick up > your series, or shall I? I missed Chris had already reviewed it. Yeah, series looks fine to me. With regards to the second part, after your work what I think would be left from mine is: * move some more fields/flags to runtime info * subplatform/devid consolidation * looking at how to wean selftests off modifying the gen field * maybe introducting INTEL_SSEU to avoid many RUNTIME_INFO(...)->sseu If you are in a hurry and have time you can take over, or if you are just in a hurry I might be able to do within a week or two. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 0/6] drm/i915: start splitting off runtime device info 2019-01-02 10:17 ` Tvrtko Ursulin @ 2019-01-02 11:19 ` Jani Nikula 0 siblings, 0 replies; 26+ messages in thread From: Jani Nikula @ 2019-01-02 11:19 UTC (permalink / raw) To: Tvrtko Ursulin, Chris Wilson, intel-gfx, Ursulin, Tvrtko On Wed, 02 Jan 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 02/01/2019 09:13, Jani Nikula wrote: >> On Tue, 01 Jan 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote: >>> Quoting Jani Nikula (2018-12-31 14:56:40) >>>> The mkwrite_device_info removal series [1] seems to have stalled. I'm >>>> trying to nudge things forward a bit with this series. This isn't near >>>> as complete as Tvrtko's work, but does some of the prep work I wanted, >>>> specifically using INTEL_INFO() and RUNTIME_INFO() to access the >>>> fields. There are obviously conflicts, but mostly I think this should >>>> make the rest of Tvrtko's work easier, not harder. >>>> >>>> BR, >>>> Jani. >>>> >>>> >>>> [1] https://patchwork.freedesktop.org/series/52381/ >>>> >>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >>>> >>>> >>>> Jani Nikula (6): >>>> drm/i915: start moving runtime device info to a separate struct >>>> drm/i915/reg: abstract display_mmio_offset access >>>> drm/i915: pass dev_priv to intel_device_info_runtime_init() >>>> drm/i915: always use INTEL_INFO() to access device info >>>> drm/i915: drop intel_device_info_dump() >>>> drm/i915: rename dev_priv info to __info to avoid usage >>> >>> Looked ok, and didn't see anything odd compared to my own attempts. >>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> >> >> Thanks for the review. >> >> Tvrtko, I'd still like to get your ack before I go ahead and push >> these. Also, do you think you'll have time in the near future to pick up >> your series, or shall I? > > I missed Chris had already reviewed it. Yeah, series looks fine to me. Thanks for your reviews too, pushed the series. > With regards to the second part, after your work what I think would be > left from mine is: > > * move some more fields/flags to runtime info > * subplatform/devid consolidation > * looking at how to wean selftests off modifying the gen field Once we make dev_priv->info a pointer to the static const structs, I think the selftests can make a copy, and point dev_priv->info at that instead, and go wild. There might be a slight chicken and egg issue to deal with in the patch series ordering though to keep it clean. > * maybe introducting INTEL_SSEU to avoid many RUNTIME_INFO(...)->sseu > > If you are in a hurry and have time you can take over, or if you are > just in a hurry I might be able to do within a week or two. I'll eyeball it a bit, and let you know if I do anything to avoid duplicating the effort. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-01-02 11:19 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-12-31 14:56 [PATCH 0/6] drm/i915: start splitting off runtime device info Jani Nikula 2018-12-31 14:56 ` [PATCH 1/6] drm/i915: start moving runtime device info to a separate struct Jani Nikula 2019-01-02 9:27 ` Tvrtko Ursulin 2019-01-02 10:21 ` Jani Nikula 2018-12-31 14:56 ` [PATCH 2/6] drm/i915/reg: abstract display_mmio_offset access Jani Nikula 2019-01-02 9:37 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 3/6] drm/i915: pass dev_priv to intel_device_info_runtime_init() Jani Nikula 2019-01-02 9:38 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 4/6] drm/i915: always use INTEL_INFO() to access device info Jani Nikula 2019-01-02 9:58 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 5/6] drm/i915: drop intel_device_info_dump() Jani Nikula 2019-01-02 10:02 ` Tvrtko Ursulin 2019-01-02 10:42 ` Jani Nikula 2019-01-02 11:09 ` Tvrtko Ursulin 2018-12-31 14:56 ` [PATCH 6/6] drm/i915: rename dev_priv info to __info to avoid usage Jani Nikula 2019-01-02 10:04 ` Tvrtko Ursulin 2019-01-02 10:44 ` Jani Nikula 2019-01-02 11:10 ` Tvrtko Ursulin 2018-12-31 15:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: start splitting off runtime device info Patchwork 2018-12-31 15:10 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-12-31 15:43 ` ✓ Fi.CI.BAT: success " Patchwork 2018-12-31 17:53 ` ✓ Fi.CI.IGT: " Patchwork 2019-01-01 10:31 ` [PATCH 0/6] " Chris Wilson 2019-01-02 9:13 ` Jani Nikula 2019-01-02 10:17 ` Tvrtko Ursulin 2019-01-02 11:19 ` Jani Nikula
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